January 2009 - U-Boot

[U-Boot] [PATCH] IXP425: Fixing timer code Part 1/1
by Stefan Althoefer 04 Jan '09

04 Jan '09

[PATCH] IXP425: Fixing timer code The non-interrupted timer code is inaccurate. I found that the timing error of udelay() is caused by to much looping overhead. The actual timing routine was called repeatedly for each microsecond. When I used bigger slices it became more accurate. Some IXP425 ports have this line in their config file: #define CONFIG_SYS_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ With this patch, this is nonsense. Instead you should use: #ifdef CONFIG_USE_IRQ /* Interrupt driven timer wants system tick here */ #define CONFIG_SYS_HZ 1000 #else /* The code in cpu/ixp/timer.c needs timer clock tick in HZ */ #define CONFIG_SYS_HZ 66666666 #endif The patch is against "latest" u-boot git-repository Please (still) be patient if style of submission or patches are offending. Signed-off-by: Stefan Althoefer <stefan.althoefer(a)web.de> ---- diff -uprN u-boot-orig//cpu/ixp/timer.c u-boot/cpu/ixp/timer.c --- u-boot-orig//cpu/ixp/timer.c 2008-12-02 17:25:31.000000000 +0100 +++ u-boot/cpu/ixp/timer.c 2008-12-02 22:27:22.000000000 +0100 @@ -46,6 +46,8 @@ void ixp425_udelay(unsigned long usec) */ unsigned long usecs = CONFIG_SYS_HZ/1000000L & ~IXP425_OST_RELOAD_MASK; + usecs *= usec; + *IXP425_OSST = IXP425_OSST_TIMER_1_PEND; usecs |= IXP425_OST_ONE_SHOT | IXP425_OST_ENABLE; *IXP425_OSRT1 = usecs; @@ -54,7 +56,13 @@ void ixp425_udelay(unsigned long usec) void udelay (unsigned long usec) { - while (usec--) ixp425_udelay(1); + /* ipx425_udelay has big overhead, so call it in bigger slices */ + while (usec>1000){ + ixp425_udelay(1000); + usec -= 1000; + } + /* and now the rest */ + ixp425_udelay(usec); } static ulong reload_constant = 0xfffffff0;

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[U-Boot] [PATCH 3/4] usb : OMAP3 : Enabling TI OMAP3 MUSB Host controller driver hook up to USB core layer
by Thomas Abraham 04 Jan '09

04 Jan '09

This patch enables TI OMAP3 MUSB Host controller driver hook up to USB core layer. Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- include/usb.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/usb.h b/include/usb.h index cd6f37a..19876f2 100644 --- a/include/usb.h +++ b/include/usb.h @@ -183,7 +183,7 @@ struct usb_device { #if defined(CONFIG_USB_UHCI) || defined(CONFIG_USB_OHCI) || \ defined(CONFI_USB_EHCI) || defined(CONFIG_USB_OHCI_NEW) || \ defined(CONFIG_USB_SL811HS) || defined(CONFIG_USB_ISP116X_HCD) || \ - defined(CONFIG_USB_R8A66597_HCD) + defined(CONFIG_USB_R8A66597_HCD) || defined(CONFIG_USB_OMAP3530) int usb_lowlevel_init(void); int usb_lowlevel_stop(void); -- 1.5.6

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[U-Boot] [PATCH 1/4] usb : OMAP3 : Adding TI OMAP3 platform specific USB support
by Thomas Abraham 04 Jan '09

04 Jan '09

Adding TI OMAP3 platform specific USB functionality for enabling and disabling of Mentor USB OTG controller module. This functionality will be used by the Mentor USB Host controller driver. Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- drivers/usb/Makefile | 1 + drivers/usb/omap3530_usb.c | 66 ++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/omap3530_usb.h | 49 ++++++++++++++++++++++++++++++++ 3 files changed, 116 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/omap3530_usb.c create mode 100644 drivers/usb/omap3530_usb.h diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index d93be2b..d256d07 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -34,6 +34,7 @@ COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811_usb.o COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o +COBJS-$(CONFIG_USB_OMAP3530) += omap3530_usb.o # device ifdef CONFIG_USB_DEVICE diff --git a/drivers/usb/omap3530_usb.c b/drivers/usb/omap3530_usb.c new file mode 100644 index 0000000..0a1e3bf --- /dev/null +++ b/drivers/usb/omap3530_usb.c @@ -0,0 +1,66 @@ +/* + * TI's OMAP3530 platform specific USB functions. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#include <common.h> + +#include "omap3530_usb.h" +#include <asm/arch/cpu.h> +#include <asm/arch/sys_proto.h> +#include <asm/io.h> + +/* MUSB platform configuration */ +struct musb_config musb_cfg = { + (struct musb_regs *)MENTOR_USB0_BASE, + OMAP3530_USB_TIMEOUT, + 0 +}; + +/* MUSB module register overlay */ +struct omap3530_usb_regs *regs; + +/* + * This function performs OMAP3530 platform specific initialization for Mentor + * USB OTG controller. + */ +int musb_platform_init(void) +{ + regs = (struct omap3530_usb_regs *)OMAP3530_USB0_BASE; + /* Disable force standby */ + sr32((void *)&regs->forcestdby, 0 , 1 , 0); + /* Set configuration for clock and interface clock to be always on */ + writel(0x1008, &regs->sysconfig); + /* Configure the PHY as PHY interface is 12-pin, 8-bit SDR ULPI */ + sr32((void *)&regs->interfsel, 0, 1, 1); + return 0; +} + +/* + * This function performs OMAP3530 platform specific deinitialization for + * Mentor USB OTG controller. + */ +void musb_platform_deinit(void) +{ + /* MUSB soft-reset */ + writel(2, &regs->sysconfig); +} + diff --git a/drivers/usb/omap3530_usb.h b/drivers/usb/omap3530_usb.h new file mode 100644 index 0000000..10bc3e3 --- /dev/null +++ b/drivers/usb/omap3530_usb.h @@ -0,0 +1,49 @@ +/* + * TI's OMAP3530 platform specific USB functions. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#ifndef __OMAP3530_MUSB_H__ +#define __OMAP3530_MUSB_H__ + +#include "musb_core.h" + +/* Base address of OMAP3530 usb0 wrapper */ +#define OMAP3530_USB0_BASE 0x480AB400 +/* Base address of OMAP3530 musb core */ +#define MENTOR_USB0_BASE 0x480AB000 +/* Timeout for OMAP3530 USB module */ +#define OMAP3530_USB_TIMEOUT 0x3FFFFFF + +/* + * OMAP3530 platform USB register overlay. + */ +struct omap3530_usb_regs { + u32 revision; + u32 sysconfig; + u32 sysstatus; + u32 interfsel; + u32 simenable; + u32 forcestdby; +}; + +#endif /* __OMAP3530_MUSB_H__ */ + -- 1.5.6

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[U-Boot] [PATCH 0/4] usb : OMAP3 : Adding USB MSC and Keyboard support for OMAP3530 EVM platform
by Thomas Abraham 04 Jan '09

04 Jan '09

This patch series adds USB MSC and USB Keyboard support for TI's OMAP3530 EVM platform. The first three patches are applicable to other OMAP3 platforms as well. - [PATCH 1/4] usb : OMAP3 : Adding TI OMAP3 platform specific USB support - [PATCH 2/4] usb : OMAP3 : Enable Mentor USB OTG module interface clock - [PATCH 3/4] usb : OMAP3 : Enabling TI OMAP3 MUSB Host controller driver hook up to USB core layer - [PATCH 4/4] usb : OMAP3 : Enabling USB MSC and Keyboard support for TI OMAP3530 EVM platform Note: This patch series depends on the following patches. - [U-Boot] [RFC PATCH V2 0/2] Prepare USB layer to support ehci core - [U-Boot] [USB PATCH] USB change speed - [U-Boot] [PATCH] usb : usb_kbd : Populating 'priv' member of USB keyboard device_t structure - [U-Boot] [PATCH v3 1/5] usb : musb : Adding host controller driver for Mentor USB controller

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[U-Boot] [PATCH v3 5/5] usb : musb : Enabling USB MSC support for DM6446 (TI DaVinci) platform
by Thomas Abraham 04 Jan '09

04 Jan '09

Enabling USB MSC support for DM6446 (TI DaVinci) platform in the configuration file. Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- include/configs/davinci_dvevm.h | 18 ++++++++++++++++++ 1 files changed, 18 insertions(+), 0 deletions(-) diff --git a/include/configs/davinci_dvevm.h b/include/configs/davinci_dvevm.h index 6885b2c..cbf8df4 100644 --- a/include/configs/davinci_dvevm.h +++ b/include/configs/davinci_dvevm.h @@ -172,6 +172,8 @@ #define CONFIG_SYS_LONGHELP #define CONFIG_CRC32_VERIFY #define CONFIG_MX_CYCLIC +#define CONFIG_MUSB_HCD +#define CONFIG_USB_DAVINCI /*===================*/ /* Linux Information */ /*===================*/ @@ -204,6 +206,22 @@ #else #error "Either CONFIG_SYS_USE_NAND or CONFIG_SYS_USE_NOR _MUST_ be defined !!!" #endif +/*==========================*/ +/* USB MSC support (if any) */ +/*==========================*/ +#ifdef CONFIG_USB_DAVINCI +#define CONFIG_CMD_USB +#ifdef CONFIG_MUSB_HCD +#define CONFIG_USB_STORAGE +#define CONFIG_CMD_STORAGE +#define CONFIG_CMD_FAT +#define CONFIG_DOS_PARTITION +#endif +#ifdef CONFIG_USB_KEYBOARD +#define CONFIG_SYS_USB_EVENT_POLL +#define CONFIG_PREBOOT "usb start" +#endif +#endif /*=======================*/ /* KGDB support (if any) */ /*=======================*/ -- 1.5.6

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[U-Boot] [PATCH v3 2/5] usb : musb : Adding USB VBUS enable functionality for DM644x DVEVM
by Thomas Abraham 04 Jan '09

04 Jan '09

Adding USB VBUS enable functionality for DM644x DVEVM (TI DaVinci) platform. Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- board/davinci/dvevm/dvevm.c | 23 +++++++++++++++++++++++ 1 files changed, 23 insertions(+), 0 deletions(-) diff --git a/board/davinci/dvevm/dvevm.c b/board/davinci/dvevm/dvevm.c index abf60b3..5dd081c 100644 --- a/board/davinci/dvevm/dvevm.c +++ b/board/davinci/dvevm/dvevm.c @@ -101,3 +101,26 @@ int misc_init_r(void) return(0); } + +#ifdef CONFIG_USB_DAVINCI + +/* IO Expander I2C address and USB VBUS enable mask */ +#define IOEXP_I2C_ADDR 0x3A +#define IOEXP_VBUSEN_MASK 1 + +/* + * This function enables USB VBUS by writting to IO expander using I2C. + * Note that the I2C is already initialized at this stage. This + * function is used by davinci specific USB wrapper code. + */ +void enable_vbus(void) +{ + uchar data; /* IO Expander data to enable VBUS */ + + /* Write to IO expander to enable VBUS */ + i2c_read(IOEXP_I2C_ADDR, 0, 0, &data, 1); + data &= ~IOEXP_VBUSEN_MASK; + i2c_write(IOEXP_I2C_ADDR, 0, 0, &data, 1); +} +#endif + -- 1.5.6

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[U-Boot] [PATCH v3 1/5] usb : musb : Adding host controller driver for Mentor USB controller
by Thomas Abraham 04 Jan '09

04 Jan '09

Adding Mentor USB core functionality and Mentor USB Host controller functionality for Mentor USB OTG controller (musbhdrc). Signed-off-by: Ravi Babu <ravibabu(a)ti.com> Signed-off-by: Swaminathan S <swami.iyer(a)ti.com> Signed-off-by: Thomas Abraham <t-abraham(a)ti.com> Signed-off-by: Ajay Kumar Gupta <ajay.gupta(a)ti.com> --- drivers/usb/Makefile | 1 + drivers/usb/musb_core.c | 141 +++++++++ drivers/usb/musb_core.h | 317 +++++++++++++++++++ drivers/usb/musb_hcd.c | 792 +++++++++++++++++++++++++++++++++++++++++++++++ drivers/usb/musb_hcd.h | 51 +++ 5 files changed, 1302 insertions(+), 0 deletions(-) create mode 100644 drivers/usb/musb_core.c create mode 100644 drivers/usb/musb_core.h create mode 100644 drivers/usb/musb_hcd.c create mode 100644 drivers/usb/musb_hcd.h diff --git a/drivers/usb/Makefile b/drivers/usb/Makefile index 6ba154b..94eea70 100644 --- a/drivers/usb/Makefile +++ b/drivers/usb/Makefile @@ -35,6 +35,7 @@ COBJS-$(CONFIG_USB_ISP116X_HCD) += isp116x-hcd.o COBJS-$(CONFIG_USB_R8A66597_HCD) += r8a66597-hcd.o COBJS-$(CONFIG_USB_SL811HS) += sl811_usb.o COBJS-$(CONFIG_USB_EHCI_FSL) += usb_ehci_fsl.o +COBJS-$(CONFIG_MUSB_HCD) += musb_hcd.o musb_core.o # device ifdef CONFIG_USB_DEVICE diff --git a/drivers/usb/musb_core.c b/drivers/usb/musb_core.c new file mode 100644 index 0000000..ec57fc8 --- /dev/null +++ b/drivers/usb/musb_core.c @@ -0,0 +1,141 @@ +/* + * Mentor USB OTG Core functionality common for both Host and Device + * functionality. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#include <common.h> + +#include "musb_core.h" +struct musb_regs *musbr; + +/* + * program the mentor core to start (enable interrupts, dma, etc.) + */ +void musb_start(void) +{ + u8 devctl; + + /* disable all interrupts */ + writew(0, &musbr->intrtxe); + writew(0, &musbr->intrrxe); + writeb(0, &musbr->intrusbe); + writeb(0, &musbr->testmode); + + /* put into basic highspeed mode and start session */ + writeb(MUSB_POWER_HSENAB, &musbr->power); +#if defined(CONFIG_MUSB_HCD) + devctl = readb(&musbr->devctl); + writeb(devctl | MUSB_DEVCTL_SESSION, &musbr->devctl); +#endif +} + +/* + * This function configures the endpoint configuration. The musb hcd or musb + * device implementation can use this function to configure the endpoints + * and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints + * should not be more than the available FIFO size. + * + * epinfo - Pointer to EP configuration table + * cnt - Number of entries in the EP conf table. + */ +void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) +{ + u16 csr; + u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */ + u32 fifosize; + u8 idx; + + while (cnt--) { + /* prepare fifosize to write to register */ + fifosize = epinfo->epsize >> 3; + idx = ffs(fifosize) - 1; + + writeb(epinfo->epnum, &musbr->index); + if (epinfo->epdir) { + /* Configure fifo size and fifo base address */ + writeb(idx, &musbr->txfifosz); + writew(fifoaddr >> 3, &musbr->txfifoadd); +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); +#endif + /* Flush fifo if required */ + if (csr & MUSB_TXCSR_TXPKTRDY) + writew(csr | MUSB_TXCSR_FLUSHFIFO, + &musbr->txcsr); + } else { + /* Configure fifo size and fifo base address */ + writeb(idx, &musbr->rxfifosz); + writew(fifoaddr >> 3, &musbr->rxfifoadd); +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = readw(&musbr->rxcsr); + writew(csr | MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); +#endif + /* Flush fifo if required */ + if (csr & MUSB_RXCSR_RXPKTRDY) + writew(csr | MUSB_RXCSR_FLUSHFIFO, + &musbr->rxcsr); + } + fifoaddr += epinfo->epsize; + epinfo++; + } +} + +/* + * This function writes data to endpoint fifo + * + * ep - endpoint number + * length - number of bytes to write to FIFO + * fifo_data - Pointer to data buffer that contains the data to write + */ +void write_fifo(u8 ep, u32 length, void *fifo_data) +{ + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + writeb(ep, &musbr->index); + + /* write the data to the fifo */ + while (length--) + writeb(*data++, &musbr->fifox[ep]); +} + +/* + * This function reads data from endpoint fifo + * + * ep - endpoint number + * length - number of bytes to read from FIFO + * fifo_data - pointer to data buffer into which data is read + */ +void read_fifo(u8 ep, u32 length, void *fifo_data) +{ + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + writeb(ep, &musbr->index); + + /* read the data to the fifo */ + while (length--) + *data++ = readb(&musbr->fifox[ep]); +} diff --git a/drivers/usb/musb_core.h b/drivers/usb/musb_core.h new file mode 100644 index 0000000..9f5ebe7 --- /dev/null +++ b/drivers/usb/musb_core.h @@ -0,0 +1,317 @@ +/****************************************************************** + * Copyright 2008 Mentor Graphics Corporation + * Copyright (C) 2008 by Texas Instruments + * + * This file is part of the Inventra Controller Driver for Linux. + * + * The Inventra Controller Driver for Linux is free software; you + * can redistribute it and/or modify it under the terms of the GNU + * General Public License version 2 as published by the Free Software + * Foundation. + * + * The Inventra Controller Driver for Linux is distributed in + * the hope that it will be useful, but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with The Inventra Controller Driver for Linux ; if not, + * write to the Free Software Foundation, Inc., 59 Temple Place, + * Suite 330, Boston, MA 02111-1307 USA + * + * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION + * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE + * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS + * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. + * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT + * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR + * GRAPHICS SUPPORT CUSTOMER. + ******************************************************************/ + +#ifndef __MUSB_HDRC_DEFS_H__ +#define __MUSB_HDRC_DEFS_H__ + +#include <usb.h> +#include <usb_defs.h> +#include <asm/io.h> + +#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ + +/* Mentor USB core register overlay structure */ +struct musb_regs { + /* common registers */ + u8 faddr; + u8 power; + u16 intrtx; + u16 intrrx; + u16 intrtxe; + u16 intrrxe; + u8 intrusb; + u8 intrusbe; + u16 frame; + u8 index; + u8 testmode; + /* indexed registers */ + u16 txmaxp; + u16 txcsr; + u16 rxmaxp; + u16 rxcsr; + u16 rxcount; + u8 txtype; + u8 txinterval; + u8 rxtype; + u8 rxinterval; + u8 reserved0; + u8 fifosize; + /* fifo */ + u32 fifox[16]; + /* OTG, dynamic FIFO, version & vendor registers */ + u8 devctl; + u8 reserved1; + u8 txfifosz; + u8 rxfifosz; + u16 txfifoadd; + u16 rxfifoadd; + u32 vcontrol; + u16 hwvers; + u16 reserved2[5]; + u8 epinfo; + u8 raminfo; + u8 linkinfo; + u8 vplen; + u8 hseof1; + u8 fseof1; + u8 lseof1; + u8 reserved3; + /* target address registers */ + struct musb_tar_regs { + u8 txfuncaddr; + u8 reserved0; + u8 txhubaddr; + u8 txhubport; + u8 rxfuncaddr; + u8 reserved1; + u8 rxhubaddr; + u8 rxhubport; + } tar[16]; +} __attribute((aligned(32))); + +/* + * MUSB Register bits + */ + +/* POWER */ +#define MUSB_POWER_ISOUPDATE 0x80 +#define MUSB_POWER_SOFTCONN 0x40 +#define MUSB_POWER_HSENAB 0x20 +#define MUSB_POWER_HSMODE 0x10 +#define MUSB_POWER_RESET 0x08 +#define MUSB_POWER_RESUME 0x04 +#define MUSB_POWER_SUSPENDM 0x02 +#define MUSB_POWER_ENSUSPEND 0x01 +#define MUSB_POWER_HSMODE_SHIFT 4 + +/* INTRUSB */ +#define MUSB_INTR_SUSPEND 0x01 +#define MUSB_INTR_RESUME 0x02 +#define MUSB_INTR_RESET 0x04 +#define MUSB_INTR_BABBLE 0x04 +#define MUSB_INTR_SOF 0x08 +#define MUSB_INTR_CONNECT 0x10 +#define MUSB_INTR_DISCONNECT 0x20 +#define MUSB_INTR_SESSREQ 0x40 +#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ + +/* DEVCTL */ +#define MUSB_DEVCTL_BDEVICE 0x80 +#define MUSB_DEVCTL_FSDEV 0x40 +#define MUSB_DEVCTL_LSDEV 0x20 +#define MUSB_DEVCTL_VBUS 0x18 +#define MUSB_DEVCTL_VBUS_SHIFT 3 +#define MUSB_DEVCTL_HM 0x04 +#define MUSB_DEVCTL_HR 0x02 +#define MUSB_DEVCTL_SESSION 0x01 + +/* TESTMODE */ +#define MUSB_TEST_FORCE_HOST 0x80 +#define MUSB_TEST_FIFO_ACCESS 0x40 +#define MUSB_TEST_FORCE_FS 0x20 +#define MUSB_TEST_FORCE_HS 0x10 +#define MUSB_TEST_PACKET 0x08 +#define MUSB_TEST_K 0x04 +#define MUSB_TEST_J 0x02 +#define MUSB_TEST_SE0_NAK 0x01 + +/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ +#define MUSB_FIFOSZ_DPB 0x10 +/* Allocation size (8, 16, 32, ... 4096) */ +#define MUSB_FIFOSZ_SIZE 0x0f + +/* CSR0 */ +#define MUSB_CSR0_FLUSHFIFO 0x0100 +#define MUSB_CSR0_TXPKTRDY 0x0002 +#define MUSB_CSR0_RXPKTRDY 0x0001 + +/* CSR0 in Peripheral mode */ +#define MUSB_CSR0_P_SVDSETUPEND 0x0080 +#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 +#define MUSB_CSR0_P_SENDSTALL 0x0020 +#define MUSB_CSR0_P_SETUPEND 0x0010 +#define MUSB_CSR0_P_DATAEND 0x0008 +#define MUSB_CSR0_P_SENTSTALL 0x0004 + +/* CSR0 in Host mode */ +#define MUSB_CSR0_H_DIS_PING 0x0800 +#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ +#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ +#define MUSB_CSR0_H_NAKTIMEOUT 0x0080 +#define MUSB_CSR0_H_STATUSPKT 0x0040 +#define MUSB_CSR0_H_REQPKT 0x0020 +#define MUSB_CSR0_H_ERROR 0x0010 +#define MUSB_CSR0_H_SETUPPKT 0x0008 +#define MUSB_CSR0_H_RXSTALL 0x0004 + +/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_CSR0_P_WZC_BITS \ + (MUSB_CSR0_P_SENTSTALL) +#define MUSB_CSR0_H_WZC_BITS \ + (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ + | MUSB_CSR0_RXPKTRDY) + +/* TxType/RxType */ +#define MUSB_TYPE_SPEED 0xc0 +#define MUSB_TYPE_SPEED_SHIFT 6 +#define MUSB_TYPE_SPEED_HIGH 1 +#define MUSB_TYPE_SPEED_FULL 2 +#define MUSB_TYPE_SPEED_LOW 3 +#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_SHIFT 4 +#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_BULK 2 +#define MUSB_TYPE_PROTO_INTR 3 + +/* CONFIGDATA */ +#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ +#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ +#define MUSB_CONFIGDATA_BIGENDIAN 0x20 +#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ +#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ +#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ +#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ +#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ + +/* TXCSR in Peripheral and Host mode */ +#define MUSB_TXCSR_AUTOSET 0x8000 +#define MUSB_TXCSR_MODE 0x2000 +#define MUSB_TXCSR_DMAENAB 0x1000 +#define MUSB_TXCSR_FRCDATATOG 0x0800 +#define MUSB_TXCSR_DMAMODE 0x0400 +#define MUSB_TXCSR_CLRDATATOG 0x0040 +#define MUSB_TXCSR_FLUSHFIFO 0x0008 +#define MUSB_TXCSR_FIFONOTEMPTY 0x0002 +#define MUSB_TXCSR_TXPKTRDY 0x0001 + +/* TXCSR in Peripheral mode */ +#define MUSB_TXCSR_P_ISO 0x4000 +#define MUSB_TXCSR_P_INCOMPTX 0x0080 +#define MUSB_TXCSR_P_SENTSTALL 0x0020 +#define MUSB_TXCSR_P_SENDSTALL 0x0010 +#define MUSB_TXCSR_P_UNDERRUN 0x0004 + +/* TXCSR in Host mode */ +#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 +#define MUSB_TXCSR_H_DATATOGGLE 0x0100 +#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 +#define MUSB_TXCSR_H_RXSTALL 0x0020 +#define MUSB_TXCSR_H_ERROR 0x0004 +#define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 + +/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_TXCSR_P_WZC_BITS \ + (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ + | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) +#define MUSB_TXCSR_H_WZC_BITS \ + (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ + | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) + +/* RXCSR in Peripheral and Host mode */ +#define MUSB_RXCSR_AUTOCLEAR 0x8000 +#define MUSB_RXCSR_DMAENAB 0x2000 +#define MUSB_RXCSR_DISNYET 0x1000 +#define MUSB_RXCSR_PID_ERR 0x1000 +#define MUSB_RXCSR_DMAMODE 0x0800 +#define MUSB_RXCSR_INCOMPRX 0x0100 +#define MUSB_RXCSR_CLRDATATOG 0x0080 +#define MUSB_RXCSR_FLUSHFIFO 0x0010 +#define MUSB_RXCSR_DATAERROR 0x0008 +#define MUSB_RXCSR_FIFOFULL 0x0002 +#define MUSB_RXCSR_RXPKTRDY 0x0001 + +/* RXCSR in Peripheral mode */ +#define MUSB_RXCSR_P_ISO 0x4000 +#define MUSB_RXCSR_P_SENTSTALL 0x0040 +#define MUSB_RXCSR_P_SENDSTALL 0x0020 +#define MUSB_RXCSR_P_OVERRUN 0x0004 + +/* RXCSR in Host mode */ +#define MUSB_RXCSR_H_AUTOREQ 0x4000 +#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 +#define MUSB_RXCSR_H_DATATOGGLE 0x0200 +#define MUSB_RXCSR_H_RXSTALL 0x0040 +#define MUSB_RXCSR_H_REQPKT 0x0020 +#define MUSB_RXCSR_H_ERROR 0x0004 +#define MUSB_S_RXCSR_H_DATATOGGLE 9 + +/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_RXCSR_P_WZC_BITS \ + (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ + | MUSB_RXCSR_RXPKTRDY) +#define MUSB_RXCSR_H_WZC_BITS \ + (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ + | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) + +/* HUBADDR */ +#define MUSB_HUBADDR_MULTI_TT 0x80 + +/* Endpoint configuration information. Note: The value of endpoint fifo size + * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other + * values are not supported + */ +struct musb_epinfo { + u8 epnum; /* endpoint number */ + u8 epdir; /* endpoint direction */ + u16 epsize; /* endpoint FIFO size */ +}; + +/* + * Platform specific MUSB configuration. Any platform using the musb + * functionality should create one instance of this structure in the + * platform specific file. + */ +struct musb_config { + struct musb_regs *regs; + u32 timeout; + u8 musb_speed; +}; + +/* externally defined data */ +extern struct musb_config musb_cfg; +extern struct musb_regs *musbr; + +/* exported functions */ +extern void musb_start(void); +extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); +extern void write_fifo(u8 ep, u32 length, void *fifo_data); +extern void read_fifo(u8 ep, u32 length, void *fifo_data); + +/* extern functions */ +extern inline void musb_writew(u32 offset, u16 value); +extern inline void musb_writeb(u32 offset, u8 value); +extern inline u16 musb_readw(u32 offset); +extern inline u8 musb_readb(u32 offset); + +#endif /* __MUSB_HDRC_DEFS_H__ */ + diff --git a/drivers/usb/musb_hcd.c b/drivers/usb/musb_hcd.c new file mode 100644 index 0000000..352a0d4 --- /dev/null +++ b/drivers/usb/musb_hcd.c @@ -0,0 +1,792 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#include <common.h> +#include "musb_hcd.h" + +/* MSC control transfers */ +#define USB_MSC_BBB_RESET 0xFF +#define USB_MSC_BBB_GET_MAX_LUN 0xFE + +/* Endpoint configuration information */ +static struct musb_epinfo epinfo[3] = { + {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ + {MUSB_BULK_EP, 0, 512}, /* EP1 - Bluk In - 512 Bytes */ + {MUSB_INTR_EP, 0, 64} /* EP2 - Interrupt IN - 64 Bytes */ +}; + +/* + * This function writes the data toggle value. + */ +static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) +{ + u16 toggle = usb_gettoggle(dev, ep, dir_out); + u16 csr; + + if (dir_out) { + if (!toggle) + writew(MUSB_TXCSR_CLRDATATOG, &musbr->txcsr); + else { + csr = readw(&musbr->txcsr); + csr |= MUSB_TXCSR_H_WR_DATATOGGLE; + writew(csr, &musbr->txcsr); + csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); + writew(csr, &musbr->txcsr); + } + } else { + if (!toggle) + writew(MUSB_RXCSR_CLRDATATOG, &musbr->rxcsr); + else { + csr = readw(&musbr->rxcsr); + csr |= MUSB_RXCSR_H_WR_DATATOGGLE; + writew(csr, &musbr->rxcsr); + csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); + writew(csr, &musbr->rxcsr); + } + } +} + +/* + * This function checks if RxStall has occured on the endpoint. If a RxStall + * has occured, the RxStall is cleared and 1 is returned. If RxStall has + * not occured, 0 is returned. + */ +static u8 check_stall(u8 ep, u8 dir_out) +{ + u16 csr; + + /* For endpoint 0 */ + if (!ep) { + csr = readw(&musbr->txcsr); + if (csr & MUSB_CSR0_H_RXSTALL) { + csr &= ~MUSB_CSR0_H_RXSTALL; + writew(csr, &musbr->txcsr); + return 1; + } + } else { /* For non-ep0 */ + if (dir_out) { /* is it tx ep */ + csr = readw(&musbr->txcsr); + if (csr & MUSB_TXCSR_H_RXSTALL) { + csr &= ~MUSB_TXCSR_H_RXSTALL; + writew(csr, &musbr->txcsr); + return 1; + } + } else { /* is it rx ep */ + csr = readw(&musbr->rxcsr); + if (csr & MUSB_RXCSR_H_RXSTALL) { + csr &= ~MUSB_RXCSR_H_RXSTALL; + writew(csr, &musbr->rxcsr); + return 1; + } + } + } + return 0; +} + +/* + * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout + * error and -2 for stall. + */ +static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) +{ + u16 csr; + int result = 1; + + while (result > 0) { + csr = readw(&musbr->txcsr); + if (csr & MUSB_CSR0_H_ERROR) { + csr &= ~MUSB_CSR0_H_ERROR; + writew(csr, &musbr->txcsr); + dev->status = USB_ST_CRC_ERR; + result = -1; + break; + } + + switch (bit_mask) { + case MUSB_CSR0_TXPKTRDY: + if (!(csr & MUSB_CSR0_TXPKTRDY)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + + case MUSB_CSR0_RXPKTRDY: + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + if (csr & MUSB_CSR0_RXPKTRDY) + result = 0; + break; + + case MUSB_CSR0_H_REQPKT: + if (!(csr & MUSB_CSR0_H_REQPKT)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + } + } + return result; +} + +/* + * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 1)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = readw(&musbr->txcsr); + if (csr & MUSB_TXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (csr & MUSB_TXCSR_TXPKTRDY); + return 1; +} + +/* + * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 0)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = readw(&musbr->rxcsr); + if (csr & MUSB_RXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (!(csr & MUSB_RXCSR_RXPKTRDY)); + return 1; +} + +/* + * This function performs the setup phase of the control transfer + */ +static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) +{ + int result; + u16 csr; + + /* write the control request to ep0 fifo */ + write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); + + /* enable transfer of setup packet */ + csr = readw(&musbr->txcsr); + csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); + writew(csr, &musbr->txcsr); + + /* wait until the setup packet is transmitted */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + dev->act_len = 0; + return result; +} + +/* + * This function handles the control transfer in data phase + */ +static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 rxlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *rxbuff = (u8 *)buffer; + u8 rxedlength; + int result; + + while (rxlen < len) { + /* Determine the next read length */ + nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); + + /* Set the ReqPkt bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_CSR0_H_REQPKT, &musbr->txcsr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); + if (result < 0) + return result; + + /* Actual number of bytes received by usb */ + rxedlength = readb(&musbr->rxcount); + + /* Read the data from the RxFIFO */ + read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); + + /* Clear the RxPktRdy Bit */ + csr = readw(&musbr->txcsr); + csr &= ~MUSB_CSR0_RXPKTRDY; + writew(csr, &musbr->txcsr); + + /* short packet? */ + if (rxedlength != nextlen) { + dev->act_len += rxedlength; + break; + } + rxlen += nextlen; + dev->act_len = rxlen; + } + return 0; +} + +/* + * This function handles the control transfer out data phase + */ +static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *txbuff = (u8 *)buffer; + int result = 0; + + while (txlen < len) { + /* Determine the next write length */ + nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); + + /* Load the data to send in FIFO */ + write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); + + /* Set TXPKTRDY bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY, + &musbr->txcsr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + if (result < 0) + break; + + txlen += nextlen; + dev->act_len = txlen; + } + return result; +} + +/* + * This function handles the control transfer out status phase + */ +static int ctrlreq_out_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit */ + csr = readw(&musbr->txcsr); + csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | + MUSB_CSR0_H_STATUSPKT); + writew(csr, &musbr->txcsr); + + /* Wait until TXPKTRDY bit is cleared */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + return result; +} + +/* + * This function handles the control transfer in status phase + */ +static int ctrlreq_in_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit and ReqPkt bit */ + csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; + writew(csr, &musbr->txcsr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); + + /* clear StatusPkt bit and RxPktRdy bit */ + csr = readw(&musbr->txcsr); + csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); + writew(csr, &musbr->txcsr); + return result; +} + +/* + * determines the speed of the device (High/Full/Slow) + */ +static u8 get_dev_speed(struct usb_device *dev) +{ + return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : + ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : + MUSB_TYPE_SPEED_FULL); +} + +/* + * configure the hub address and the port address. + */ +static void config_hub_port(struct usb_device *dev, u8 ep) +{ + u8 chid; + u8 hub; + + /* Find out the nearest parent which is high speed */ + while (dev->parent->parent != NULL) + if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) + dev = dev->parent; + else + break; + + /* determine the port address at that hub */ + hub = dev->parent->devnum; + for (chid = 0; chid < USB_MAXCHILDREN; chid++) + if (dev->parent->children[chid] == dev) + break; + + /* configure the hub address and the port address */ + writeb(hub, &musbr->tar[ep].txhubaddr); + writeb((chid + 1), &musbr->tar[ep].txhubport); + writeb(hub, &musbr->tar[ep].rxhubaddr); + writeb((chid + 1), &musbr->tar[ep].rxhubport); +} + +/* + * do a control transfer + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int devnum = usb_pipedevice(pipe); + u16 csr; + u8 devspeed; + + /* select control endpoint */ + writeb(MUSB_CONTROL_EP, &musbr->index); + csr = readw(&musbr->txcsr); + + /* target addr and (for multipoint) hub addr/port */ + writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].txfuncaddr); + writeb(devnum, &musbr->tar[MUSB_CONTROL_EP].rxfuncaddr); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + config_hub_port(dev, MUSB_CONTROL_EP); + writeb(devspeed << 6, &musbr->txtype); + } else { + writeb(musb_cfg.musb_speed << 6, &musbr->txtype); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubaddr); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].txhubport); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubaddr); + writeb(0, &musbr->tar[MUSB_CONTROL_EP].rxhubport); + } + + /* Control transfer setup phase */ + if (ctrlreq_setup_phase(dev, setup) < 0) + return 0; + + switch (setup->request) { + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_GET_STATUS: + case USB_MSC_BBB_GET_MAX_LUN: + /* control transfer in-data-phase */ + if (ctrlreq_in_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer out-status-phase */ + if (ctrlreq_out_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_INTERFACE: + case USB_REQ_CLEAR_FEATURE: + case USB_MSC_BBB_RESET: + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_DESCRIPTOR: + /* control transfer out data phase */ + if (ctrlreq_out_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + default: + /* unhandled control transfer */ + return -1; + } + + dev->status = 0; + dev->act_len = len; + return len; +} + +/* + * do a bulk transfer + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int devnum = usb_pipedevice(pipe); + u8 type; + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 devspeed; + + /* select bulk endpoint */ + writeb(MUSB_BULK_EP, &musbr->index); + + /* write the address of the device */ + if (dir_out) + writeb(devnum, &musbr->tar[MUSB_BULK_EP].txfuncaddr); + else + writeb(devnum, &musbr->tar[MUSB_BULK_EP].rxfuncaddr); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + /* + * MUSB is in high speed and the destination device is full + * speed device. So configure the hub address and port + * address registers. + */ + config_hub_port(dev, MUSB_BULK_EP); + } else { + if (dir_out) { + writeb(0, &musbr->tar[MUSB_BULK_EP].txhubaddr); + writeb(0, &musbr->tar[MUSB_BULK_EP].txhubport); + } else { + writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubaddr); + writeb(0, &musbr->tar[MUSB_BULK_EP].rxhubport); + } + devspeed = musb_cfg.musb_speed; + } + + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + if (dir_out) { /* bulk-out transfer */ + /* Program the TxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + writeb(type, &musbr->txtype); + + /* Write maximum packet size to the TxMaxp register */ + writew(dev->epmaxpacketout[ep], &musbr->txmaxp); + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? + (len-txlen) : dev->epmaxpacketout[ep]; + + /* Write the data to the FIFO */ + write_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Set the TxPktRdy bit */ + csr = readw(&musbr->txcsr); + writew(csr | MUSB_TXCSR_TXPKTRDY, &musbr->txcsr); + + /* Wait until the TxPktRdy bit is cleared */ + if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { + readw(&musbr->txcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + dev->act_len = txlen; + return 0; + } + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = readw(&musbr->txcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + } else { /* bulk-in transfer */ + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + /* Program the RxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + writeb(type, &musbr->rxtype); + + /* Write the maximum packet size to the RxMaxp register */ + writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? + (len-txlen) : dev->epmaxpacketin[ep]; + + /* Set the ReqPkt bit */ + writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); + + /* Wait until the RxPktRdy bit is set */ + if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + dev->act_len = txlen; + return 0; + } + + /* Read the data from the FIFO */ + read_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Clear the RxPktRdy bit */ + csr = readw(&musbr->rxcsr); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + } + + /* bulk transfer is complete */ + dev->status = 0; + dev->act_len = len; + return 0; +} + +/* + * This function initializes the usb controller module. + */ +int usb_lowlevel_init(void) +{ + u8 power; + u32 timeout; + + if (musb_platform_init() == -1) + return -1; + + /* Configure all the endpoint FIFO's and start usb controller */ + musbr = musb_cfg.regs; + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + musb_start(); + + /* + * Wait until musb is enabled in host mode with a timeout. There + * should be a usb device connected. + */ + timeout = musb_cfg.timeout; + while (timeout--) + if (readb(&musbr->devctl) & MUSB_DEVCTL_HM) + break; + + /* if musb core is not in host mode, then return */ + if (!timeout) + return -1; + + /* start usb bus reset */ + power = readb(&musbr->power); + writeb(power | MUSB_POWER_RESET, &musbr->power); + + /* After initiating a usb reset, wait for about 20ms to 30ms */ + udelay(30000); + + /* stop usb bus reset */ + power = readb(&musbr->power); + power &= ~MUSB_POWER_RESET; + writeb(power, &musbr->power); + + /* Determine if the connected device is a high/full/low speed device */ + musb_cfg.musb_speed = (readb(&musbr->power) & MUSB_POWER_HSMODE) ? + MUSB_TYPE_SPEED_HIGH : + ((readb(&musbr->devctl) & MUSB_DEVCTL_FSDEV) ? + MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); + return 0; +} + +/* + * This function stops the operation of the davinci usb module. + */ +int usb_lowlevel_stop(void) +{ + /* Reset the USB module */ + musb_platform_deinit(); + writeb(0, &musbr->devctl); + return 0; +} + +/* + * This function supports usb interrupt transfers. Currently, usb interrupt + * transfers are not supported. + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len, int interval) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int devnum = usb_pipedevice(pipe); + u8 type; + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 devspeed; + + /* select interrupt endpoint */ + writeb(MUSB_INTR_EP, &musbr->index); + + /* write the address of the device */ + if (dir_out) + writeb(devnum, &musbr->tar[MUSB_INTR_EP].txfuncaddr); + else + writeb(devnum, &musbr->tar[MUSB_INTR_EP].rxfuncaddr); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + /* + * MUSB is in high speed and the destination device is full + * speed device. So configure the hub address and port + * address registers. + */ + config_hub_port(dev, MUSB_INTR_EP); + } else { + if (dir_out) { + writeb(0, &musbr->tar[MUSB_INTR_EP].txhubaddr); + writeb(0, &musbr->tar[MUSB_INTR_EP].txhubport); + } else { + writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubaddr); + writeb(0, &musbr->tar[MUSB_INTR_EP].rxhubport); + } + devspeed = musb_cfg.musb_speed; + } + + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + if (!dir_out) { /* intrrupt-in transfer */ + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + writeb(interval, &musbr->rxinterval); + + /* Program the RxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_INTR << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); + writeb(type, &musbr->rxtype); + + /* Write the maximum packet size to the RxMaxp register */ + writew(dev->epmaxpacketin[ep], &musbr->rxmaxp); + + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? + (len-txlen) : dev->epmaxpacketin[ep]; + + /* Set the ReqPkt bit */ + writew(MUSB_RXCSR_H_REQPKT, &musbr->rxcsr); + + /* Wait until the RxPktRdy bit is set */ + if (!wait_until_rxep_ready(dev, MUSB_INTR_EP)) { + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + dev->act_len = txlen; + return 0; + } + + /* Read the data from the FIFO */ + read_fifo(MUSB_INTR_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Clear the RxPktRdy bit */ + csr = readw(&musbr->rxcsr); + csr &= ~MUSB_RXCSR_RXPKTRDY; + writew(csr, &musbr->rxcsr); + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = readw(&musbr->rxcsr); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + } + + /* interrupt transfer is complete */ + dev->irq_status = 0; + dev->irq_act_len = len; + dev->irq_handle(dev); + dev->status = 0; + dev->act_len = len; + return 0; +} + + +#ifdef CONFIG_SYS_USB_EVENT_POLL +/* + * This function polls for USB keyboard data. + */ +void usb_event_poll() +{ + device_t *dev; + struct usb_device *usb_kbd_dev; + struct usb_interface_descriptor *iface; + struct usb_endpoint_descriptor *ep; + int pipe; + int maxp; + + /* Get the pointer to USB Keyboard device pointer */ + dev = device_get_by_name("usbkbd"); + usb_kbd_dev = (struct usb_device *)dev->priv; + iface = &usb_kbd_dev->config.if_desc[0]; + ep = &iface->ep_desc[0]; + pipe = usb_rcvintpipe(usb_kbd_dev, ep->bEndpointAddress); + + /* Submit a interrupt transfer request */ + maxp = usb_maxpacket(usb_kbd_dev, pipe); + usb_submit_int_msg(usb_kbd_dev, pipe, &new[0], + maxp > 8 ? 8 : maxp, ep->bInterval); +} +#endif /* CONFIG_SYS_USB_EVENT_POLL */ diff --git a/drivers/usb/musb_hcd.h b/drivers/usb/musb_hcd.h new file mode 100644 index 0000000..bb83311 --- /dev/null +++ b/drivers/usb/musb_hcd.h @@ -0,0 +1,51 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham(a)ti.com, Texas Instruments + */ + +#ifndef __MUSB_HCD_H__ +#define __MUSB_HCD_H__ + +#include "musb_core.h" +#ifdef CONFIG_USB_KEYBOARD +#include <devices.h> +extern unsigned char new[]; +#endif + +/* This defines the endpoint number used for control transfers */ +#define MUSB_CONTROL_EP 0 + +/* This defines the endpoint number used for bulk transfer */ +#define MUSB_BULK_EP 1 + +/* This defines the endpoint number used for interrupt transfer */ +#define MUSB_INTR_EP 2 + +/* Determine the operating speed of MUSB core */ +#define musb_ishighspeed() \ + ((readb(&musbr->power) & MUSB_POWER_HSMODE) \ + >> MUSB_POWER_HSMODE_SHIFT) + +/* extern functions */ +extern int musb_platform_init(void); +extern void musb_platform_deinit(void); + +#endif /* __MUSB_HCD_H__ */ -- 1.5.6

1 0

[U-Boot] [RFC] Build errors in u-boot mainline and daily builds
by Remy Bohmer 03 Jan '09

03 Jan '09

Hello All, I started a server to do only daily builds of all U-boot board configurations. (currently on a old slow box, but it works, it takes about 2 hours to build all boards for ARM only) The primary goal was to find early compile regressions in the u-boot-USB tree that I maintain, before pushing patches to mainline. To find a regression compared to u-boot mainline, the u-boot mainline (master branch) also needs to build, so I build that tree also daily from now. Currently I only build for ARM based boards, but there is no limit on architectures, if I have all the cross-compilers. I use the Denx ELDK for ARM as cross-compile toolchain. First, I discovered some build failures of which the logging is listed below. What can we do about these errors? Are these boards still maintained? Should these be fixed? Who wants to fix them? I currently run the 'MAKEALL arm' script to build all these boards, so either the boards should be fixed, or if no longer maintained removed (at least from the MAKEALL script) Further, is there any interest to make the daily build results public? * Is it appreciated if I post the build results in a daily post to the mailinglist, _if_ there is a build failure? (No news is good news) What format is preferred? * Or is it preferred to post the results on a website? * Or ... Working it up from here to make it public will take me some time, so I will only do that if there is any serious interest. Kind Regards, Remy Here are the build errors of last night build: ------------------------------------------------------------ Building U-boot: * branch: master * src-dir: /home/remy/nightbuild/git/u-boot ------------------------------------------------------------ Configuring for m501sk board... cpu/arm920t/at91rm9200/libat91rm9200.a(lowlevel_init.o): In function `SMRDATA': /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `MC_PUIA_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `MC_PUP_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `MC_PUER_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `MC_ASR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `MC_AASR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `EBI_CFGR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SMC_CSR0_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `PLLAR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `PLLBR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `MCKR_VAL' cpu/arm920t/at91rm9200/libat91rm9200.a(lowlevel_init.o): In function `SMRDATA1': /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `PIOC_ASR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `PIOC_BSR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `PIOC_PDR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `EBI_CSA_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRC_CR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRC_MR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRC_MR_VAL1' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRC_MR_VAL2' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM1' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRC_TR_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRC_MR_VAL3' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM' /home/remy/nightbuild/git/u-boot/cpu/arm920t/at91rm9200/lowlevel_init.S:132: undefined reference to `SDRAM_VAL' make: *** [/home/remy/nightbuild/scratch/build/u-boot] Error 1 Configuring for actux4 board... actux4.c: In function 'board_init': actux4.c:83: warning: left shift count >= width of type actux4.c:83: warning: left shift count >= width of type text data bss dec hex filename 222576 6692 550812 780080 be730 /home/remy/nightbuild/scratch/build/u-boot Configuring for ixdp425 board... make[1]: *** No rule to make target `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/IxNpeMicrocode.o', needed by `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a'. Stop. make: *** [/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a] Error 2 Configuring for ixdpg425 board... make[1]: *** No rule to make target `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/IxNpeMicrocode.o', needed by `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a'. Stop. make: *** [/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a] Error 2 Configuring for pdnb3 board... make[1]: *** No rule to make target `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/IxNpeMicrocode.o', needed by `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a'. Stop. make: *** [/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a] Error 2 ... on SCPU board variant Configuring for pdnb3 board... make[1]: *** No rule to make target `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/IxNpeMicrocode.o', needed by `/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a'. Stop. make: *** [/home/remy/nightbuild/scratch/build/cpu/ixp/npe/libnpe.a] Error 2

5 7

[U-Boot] [PATCH] V2 NAND_SPL support for phycore imx31
by Maxim Artamonov 02 Jan '09

02 Jan '09

V2 NAND_SPL support for phycore imx31 Changelog: * Added bad block verify and skip; * Correct code to codestyle; * Added few comments; Signed-off-by: Maxim Artamonov <scn1874 at yandex.ru> --- MAKEALL | 1 + Makefile | 9 ++- board/imx31_phycore/config.mk | 10 ++ board/imx31_phycore/lowlevel_init.S | 27 ++++- board/imx31_phycore/u-boot-nand.lds | 62 ++++++++++ cpu/arm1136/start.S | 36 +++++-- include/asm-arm/arch-mx31/mx31-regs.h | 96 ++++++++++++++++ include/configs/imx31_phycore.h | 59 ++++++++-- nand_spl/board/imx31_phycore/Makefile | 95 +++++++++++++++ nand_spl/board/imx31_phycore/config.mk | 33 ++++++ nand_spl/board/imx31_phycore/u-boot.lds | 65 +++++++++++ nand_spl/nand_boot_mx31.c | 190 +++++++++++++++++++++++++++++++ 12 files changed, 661 insertions(+), 22 deletions(-) create mode 100644 board/imx31_phycore/u-boot-nand.lds create mode 100644 nand_spl/board/imx31_phycore/Makefile create mode 100644 nand_spl/board/imx31_phycore/config.mk create mode 100644 nand_spl/board/imx31_phycore/u-boot.lds create mode 100644 nand_spl/nand_boot_mx31.c diff --git a/MAKEALL b/MAKEALL index 9ccb9ac..1f639a8 100755 --- a/MAKEALL +++ b/MAKEALL @@ -522,6 +522,7 @@ LIST_ARM11=" \ apollon \ imx31_litekit \ imx31_phycore \ + imx31_phycore_nand \ mx31ads \ smdk6400 \ " diff --git a/Makefile b/Makefile index 58b8331..7519dfe 100644 --- a/Makefile +++ b/Makefile @@ -353,7 +353,7 @@ $(NAND_SPL): $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C nand_spl/board/$(BOARDDIR) all $(U_BOOT_NAND): $(NAND_SPL) $(obj)u-boot.bin $(obj)include/autoconf.mk - cat $(obj)nand_spl/u-boot-spl-16k.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin + cat $(obj)nand_spl/u-boot-spl-aligned.bin $(obj)u-boot.bin > $(obj)u-boot-nand.bin $(ONENAND_IPL): $(VERSION_FILE) $(obj)include/autoconf.mk $(MAKE) -C onenand_ipl/board/$(BOARDDIR) all @@ -2805,6 +2805,13 @@ imx31_litekit_config : unconfig imx31_phycore_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +imx31_phycore_nand_config : unconfig + @mkdir -p $(obj)include $(obj)board/imx31_phycore + @mkdir -p $(obj)nand_spl/board/imx31_phycore + @echo "#define CONFIG_NAND_U_BOOT" > $(obj)include/config.h + @$(MKCONFIG) -n $@ -a imx31_phycore arm arm1136 imx31_phycore NULL mx31 + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk + mx31ads_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads freescale mx31 diff --git a/board/imx31_phycore/config.mk b/board/imx31_phycore/config.mk index d34dc02..412defc 100644 --- a/board/imx31_phycore/config.mk +++ b/board/imx31_phycore/config.mk @@ -1 +1,11 @@ +# +# (C) Copyright 2008 +# was changed by Maxim Artamonov, <scn1874 at yandex.ru> +# + +ifndef CONFIG_NAND_SPL TEXT_BASE = 0x87f00000 +else +TEXT_BASE = 0x87ec0000 +endif + diff --git a/board/imx31_phycore/lowlevel_init.S b/board/imx31_phycore/lowlevel_init.S index c5d6eb0..afae317 100644 --- a/board/imx31_phycore/lowlevel_init.S +++ b/board/imx31_phycore/lowlevel_init.S @@ -1,5 +1,7 @@ /* - * + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> * * See file CREDITS for list of people who contributed to this @@ -43,6 +45,20 @@ bcs 1b .endm +#ifdef CONFIG_NAND_SPL +/* somewhat macro to reduce bin size for CONFIG_NAND_SPL*/ +.macro FILLREGS begreg, val, count, step + ldr r2, =\begreg + ldr r3, =\val + ldr r4, =\count +2: + str r3, [r2] + add r2, r2, #\step + subs r4, r4, #1 + bcs 2b +.endm +#endif + .globl lowlevel_init lowlevel_init: @@ -60,10 +76,18 @@ lowlevel_init: REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(0x43) | PLL_MFI(12) | PLL_MFN(1) +#ifdef CONFIG_NAND_SPL + FILLREGS 0x43FAC26C, 0, 0x3, 0x4 +#else REG 0x43FAC26C, 0 /* SDCLK */ REG 0x43FAC270, 0 /* CAS */ REG 0x43FAC274, 0 /* RAS */ +#endif /* CONFIG_NAND_SPL */ REG 0x43FAC27C, 0x1000 /* CS2 (CSD0) */ + +#ifdef CONFIG_NAND_SPL + FILLREGS 0x43FAC284, 0, 0x17, 0x4 +#else REG 0x43FAC284, 0 /* DQM3 */ REG 0x43FAC288, 0 /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ REG 0x43FAC28C, 0 @@ -87,6 +111,7 @@ lowlevel_init: REG 0x43FAC2D4, 0 REG 0x43FAC2D8, 0 REG 0x43FAC2DC, 0 +#endif /* CONFIG_NAND_SPL */ REG 0xB8001010, 0x00000004 REG 0xB8001004, 0x006ac73a REG 0xB8001000, 0x92100000 diff --git a/board/imx31_phycore/u-boot-nand.lds b/board/imx31_phycore/u-boot-nand.lds new file mode 100644 index 0000000..bd09a8d --- /dev/null +++ b/board/imx31_phycore/u-boot-nand.lds @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/arm1136/start.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/cpu/arm1136/start.S b/cpu/arm1136/start.S index 51b664d..596efe9 100644 --- a/cpu/arm1136/start.S +++ b/cpu/arm1136/start.S @@ -1,6 +1,9 @@ /* * armboot - Startup Code for OMP2420/ARM1136 CPU-core * + * + * Copyright (c) 2008 Maxim Artamonov, <scn1874 at yandex.ru> + * * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> * * Copyright (c) 2001 Marius Gr�ger <mag(a)sysgo.de> @@ -32,6 +35,15 @@ #include <version.h> .globl _start _start: b reset +#ifdef CONFIG_NAND_SPL + nop + nop + nop + nop + nop + nop + nop +#else #ifdef CONFIG_ONENAND_IPL ldr pc, _hang ldr pc, _hang @@ -68,6 +80,7 @@ _irq: .word irq _fiq: .word fiq _pad: .word 0x12345678 /* now 16*4=64 */ #endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ .global _end_vect _end_vect: @@ -156,9 +169,9 @@ relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ cmp r0, r1 /* don't reloc during debug */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) beq stack_setup -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL && !CONFIG_NAND_SPL*/ ldr r2, _armboot_start ldr r3, _bss_start @@ -175,7 +188,7 @@ copy_loop: /* Set up the stack */ stack_setup: ldr r0, _TEXT_BASE /* upper 128 KiB: relocated uboot */ -#ifdef CONFIG_ONENAND_IPL +#if defined(CONFIG_ONENAND_IPL) || defined (CONFIG_NAND_SPL) sub sp, r0, #128 /* leave 32 words for abort-stack */ #else sub r0, r0, #CFG_MALLOC_LEN /* malloc area */ @@ -184,14 +197,14 @@ stack_setup: sub r0, r0, #(CONFIG_STACKSIZE_IRQ+CONFIG_STACKSIZE_FIQ) #endif sub sp, r0, #12 /* leave 3 words for abort-stack */ -#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_ONENAND_IPL || CONFIG_NAND_SPL*/ clear_bss: ldr r0, _bss_start /* find start of bss segment */ ldr r1, _bss_end /* stop here */ mov r2, #0x00000000 /* clear */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) clbss_l:str r2, [r0] /* clear loop... */ add r0, r0, #4 cmp r0, r1 @@ -200,12 +213,15 @@ clbss_l:str r2, [r0] /* clear loop... */ ldr pc, _start_armboot +#ifdef CONFIG_NAND_SPL +_start_armboot: .word nand_boot +#else #ifdef CONFIG_ONENAND_IPL _start_armboot: .word start_oneboot #else _start_armboot: .word start_armboot -#endif - +#endif /* CONFIG_ONENAND_IPL */ +#endif /* CONFIG_NAND_SPL */ /* ************************************************************************* @@ -244,7 +260,7 @@ cpu_init_crit: mov lr, ip /* restore link */ mov pc, lr /* back to my caller */ -#ifndef CONFIG_ONENAND_IPL +#if !defined(CONFIG_ONENAND_IPL) && !defined(CONFIG_NAND_SPL) /* ************************************************************************* * @@ -357,11 +373,12 @@ cpu_init_crit: .macro get_fiq_stack @ setup FIQ stack ldr sp, FIQ_STACK_START .endm -#endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_ONENAND_IPL && !CONFIG_NAND_SPL*/ /* * exception handlers */ +#ifndef CONFIG_NAND_SPL #ifdef CONFIG_ONENAND_IPL .align 5 do_hang: @@ -436,3 +453,4 @@ arm1136_cache_flush: mcr p15, 0, r1, c7, c5, 0 @ invalidate I cache mov pc, lr @ back to caller #endif /* CONFIG_ONENAND_IPL */ +#endif /* !CONFIG_NAND_SPL*/ diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index b04a718..78825f5 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -168,4 +168,100 @@ #define CS5_BASE 0xB6000000 #define PCMCIA_MEM_BASE 0xC0000000 +/* + * NAND controller + */ +#define NFC_BASE_ADDR 0xB8000000 + +/* + * Addresses for NFC registers + */ +#define NFC_BUF_SIZE (*((volatile u16 *)(NFC_BASE_ADDR + 0xE00))) +#define NFC_BUF_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE04))) +#define NFC_FLASH_ADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE06))) +#define NFC_FLASH_CMD (*((volatile u16 *)(NFC_BASE_ADDR + 0xE08))) +#define NFC_CONFIG (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0A))) +#define NFC_ECC_STATUS_RESULT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0C))) +#define NFC_RSLTMAIN_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE0E))) +#define NFC_RSLTSPARE_AREA (*((volatile u16 *)(NFC_BASE_ADDR + 0xE10))) +#define NFC_WRPROT (*((volatile u16 *)(NFC_BASE_ADDR + 0xE12))) +#define NFC_UNLOCKSTART_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE14))) +#define NFC_UNLOCKEND_BLKADDR (*((volatile u16 *)(NFC_BASE_ADDR + 0xE16))) +#define NFC_NF_WRPRST (*((volatile u16 *)(NFC_BASE_ADDR + 0xE18))) +#define NFC_CONFIG1 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1A))) +#define NFC_CONFIG2 (*((volatile u16 *)(NFC_BASE_ADDR + 0xE1C))) + +/* + * Addresses for NFC RAM BUFFER Main area 0 + */ +#define MAIN_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x000) +#define MAIN_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x200) +#define MAIN_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x400) +#define MAIN_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x600) + +/* + * Addresses for NFC SPARE BUFFER Spare area 0 + */ +#define SPARE_AREA0 (volatile u16 *)(NFC_BASE_ADDR + 0x800) +#define SPARE_AREA1 (volatile u16 *)(NFC_BASE_ADDR + 0x810) +#define SPARE_AREA2 (volatile u16 *)(NFC_BASE_ADDR + 0x820) +#define SPARE_AREA3 (volatile u16 *)(NFC_BASE_ADDR + 0x830) + +/* + * Set INT to 0, FCMD to 1, rest to 0 in NFC_CONFIG2 Register for Command + * operation + */ +#define NFC_CMD 0x1 + +/* + * Set INT to 0, FADD to 1, rest to 0 in NFC_CONFIG2 Register for Address + * operation + */ +#define NFC_ADDR 0x2 + +/* + * Set INT to 0, FDI to 1, rest to 0 in NFC_CONFIG2 Register for Input + * operation + */ +#define NFC_INPUT 0x4 + +/* + * Set INT to 0, FDO to 001, rest to 0 in NFC_CONFIG2 Register for Data + * Output operation + */ +#define NFC_OUTPUT 0x8 + +/* + * Set INT to 0, FD0 to 010, rest to 0 in NFC_CONFIG2 Register for Read ID + * operation + */ +#define NFC_ID 0x10 + +/* + * Set INT to 0, FDO to 100, rest to 0 in NFC_CONFIG2 Register for Read + * Status operation + */ +#define NFC_STATUS 0x20 + +/* + * Set INT to 1, rest to 0 in NFC_CONFIG2 Register for Read Status + * operation + */ +#define NFC_INT 0x8000 + +#define NFC_SP_EN (1 << 2) +#define NFC_ECC_EN (1 << 3) +#define NFC_INT_MSK (1 << 4) +#define NFC_BIG (1 << 5) +#define NFC_RST (1 << 6) +#define NFC_CE (1 << 7) +#define NFC_ONE_CYCLE (1 << 8) + +/* + * NFMS bit in RCSR register for pagesize of nandflash + */ +#define NFMS (*((volatile u32 *)CCM_RCSR)) +#define NFMS_BIT 30 + #endif /* __ASM_ARCH_MX31_REGS_H */ + diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index 1540203..946fd19 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -1,4 +1,7 @@ /* + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * * (C) Copyright 2004 * Texas Instruments. * Richard Woodruff <r-woodruff2(a)ti.com> @@ -34,6 +37,11 @@ #define CONFIG_MX31_HCLK_FREQ 26000000 #define CONFIG_MX31_CLK32 32000 +#if defined(CONFIG_NAND_U_BOOT) && !defined(CONFIG_NAND_SPL) +#define CONFIG_SKIP_LOWLEVEL_INIT +#define CONFIG_SKIP_RELOCATE_UBOOT +#endif + #define CONFIG_DISPLAY_CPUINFO #define CONFIG_DISPLAY_BOARDINFO @@ -85,26 +93,30 @@ #define CONFIG_BOOTDELAY 3 -#define MTDPARTS_DEFAULT "mtdparts=physmap-flash.0:128k(uboot)ro,1536k(kernel),-(root)" +#define MTDPARTS_DEFAULT "mtdparts=phys_mapped_flash.0:128k(uboot)ro,128k(env),1792k(kernel),-(root)" #define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 192.168.23.168 -#define CONFIG_SERVERIP 192.168.23.2 +#define CONFIG_IPADDR 192.168.3.11 +#define CONFIG_SERVERIP 192.168.3.10 #define CONFIG_EXTRA_ENV_SETTINGS \ - "bootargs_base=setenv bootargs console=ttySMX0,115200\0" \ - "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ - "bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock2 rootfstype=jffs2" \ - "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)" \ + "jffs2=root-pcm037.jffs2\0" \ + "uimage=uImage-pcm037\0" \ + "nfsrootfs=/nfsroot\0" \ "bootcmd=run bootcmd_net\0" \ + "mtdids=nor0=phys_mapped_flash\0" \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bootargs_mtd=setenv bootargs $(bootargs) $(mtdparts)\0" \ + "bootargs_flash=setenv bootargs $(bootargs) root=/dev/mtdblock3 rootfstype=jffs2\0" \ "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 $(uimage); bootm\0" \ - "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0x80000000\0" \ + "bootcmd_flash=run bootargs_base bootargs_mtd bootargs_flash; bootm 0xa0040000\0" \ + "bootcmd_netflash=run bootargs_base bootargs_mtd bootargs_flash; tftpboot 0x80000000 $(uimage); bootm\0" \ "unlock=yes\0" \ "mtdparts=" MTDPARTS_DEFAULT "\0" \ "prg_uboot=tftpboot 0x80000000 $(uboot); protect off 0xa0000000 +0x20000; erase 0xa0000000 +0x20000; cp.b 0x80000000 0xa0000000 $(filesize)\0" \ - "prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x180000; cp.b 0x80000000 0xa0040000 $(filesize)\0" \ - "prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa01c0000 0xa1ffffff; cp.b 0x80000000 0xa01c0000 $(filesize)\0" - + "prg_kernel=tftpboot 0x80000000 $(uimage); erase 0xa0040000 +0x1C0000; cp.b 0x80000000 0xa0040000 $(filesize)\0" \ + "prg_jffs2=tftpboot 0x80000000 $(jffs2); erase 0xa0200000 0xa1ffffff; cp.b 0x80000000 0xa0200000 $(filesize)\0" #define CONFIG_DRIVER_SMC911X 1 #define CONFIG_DRIVER_SMC911X_BASE 0xa8000000 @@ -172,6 +184,31 @@ #define CFG_FLASH_ERASE_TOUT (100*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (100*CFG_HZ) /* Timeout for Flash Write */ +/*----------------------------------------------------------------------- + * NAND flash + */ + +#define NAND_MAX_CHIPS 1 +#define CFG_MAX_NAND_DEVICE 1 +#define CFG_NAND_BASE 0x40000000 + +/* + * Because of small buffer size of NFC in iMX31, SPL has to fit into 2kB. + */ + +/*CFG_NAND_U_BOOT_OFFS and CFG_NAND_U_BOOT_SIZE must be align to full pages*/ +#define CFG_NAND_U_BOOT_OFFS 0x800 +#define CFG_NAND_U_BOOT_SIZE 0x30000 +#define CFG_NAND_U_BOOT_DST 0x87f00000 /* Load big U-Boot to this addr */ +#define CFG_NAND_U_BOOT_START CFG_NAND_U_BOOT_DST /* Start big U-Boot from */ +#define CFG_NAND_SPL_DST CFG_NAND_U_BOOT_DST-0x40000 /* Relocate NAND_SPL to this adress*/ + +#define CFG_NAND_PAGE_SIZE 0x200 +#define CFG_NAND_BLOCK_SIZE 0x4000 +#define CFG_NAND_PAGE_COUNT 0x20 +/*for NAND_SPL*/ +#define CFG_NAND_CHIP_SIZE 0x4000000 + /* * JFFS2 partitions */ diff --git a/nand_spl/board/imx31_phycore/Makefile b/nand_spl/board/imx31_phycore/Makefile new file mode 100644 index 0000000..0aabea3 --- /dev/null +++ b/nand_spl/board/imx31_phycore/Makefile @@ -0,0 +1,95 @@ +# +# (C) Copyright 2008 +# Maxim Artamonov, <scn1874 at yandex.ru> +# +# (C) Copyright 2006-2007 +# Stefan Roese, DENX Software Engineering, sr(a)denx.de. +# +# (C) Copyright 2008 +# Guennadi Liakhovetki, DENX Software Engineering, <lg(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +CONFIG_NAND_SPL = y + +include $(TOPDIR)/config.mk +include $(TOPDIR)/nand_spl/board/$(BOARDDIR)/config.mk + +LDSCRIPT= $(TOPDIR)/nand_spl/board/$(BOARDDIR)/u-boot.lds +LDFLAGS = -Bstatic -T $(LDSCRIPT) -Ttext $(TEXT_BASE) $(PLATFORM_LDFLAGS) +AFLAGS += -DCONFIG_NAND_SPL +CFLAGS += -DCONFIG_NAND_SPL + +SOBJS = start.o lowlevel_init.o +COBJS = nand_boot_mx31.o + +SRCS := $(addprefix $(obj),$(SOBJS:.o=.S) $(COBJS:.o=.c)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +__OBJS := $(SOBJS) $(COBJS) +LNDIR := $(OBJTREE)/nand_spl/board/$(BOARDDIR) + +nandobj := $(OBJTREE)/nand_spl/ + +ALL = $(nandobj)u-boot-spl $(nandobj)u-boot-spl.bin $(nandobj)u-boot-spl-aligned.bin + +all: $(obj).depend $(ALL) + +$(nandobj)u-boot-spl-aligned.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} --pad-to=$(PAD_TO) -O binary $< $@ + +$(nandobj)u-boot-spl.bin: $(nandobj)u-boot-spl + $(OBJCOPY) ${OBJCFLAGS} -O binary $< $@ + +$(nandobj)u-boot-spl: $(OBJS) + cd $(LNDIR) && $(LD) $(LDFLAGS) $(__OBJS) \ + -Map $(nandobj)u-boot-spl.map \ + -o $(nandobj)u-boot-spl + +# create symbolic links for common files + +# from cpu directory +$(obj)start.S: + @rm -f $@ + @ln -s $(TOPDIR)/cpu/arm1136/start.S $@ + +# from board directory +$(obj)lowlevel_init.S: + @rm -f $@ + @ln -s $(TOPDIR)/board/imx31_phycore/lowlevel_init.S $@ + +# from nand_spl directory +$(obj)nand_boot_mx31.c: + @rm -f $@ + @ln -s $(TOPDIR)/nand_spl/nand_boot_mx31.c $@ + +######################################################################### + +$(obj)%.o: $(obj)%.S + $(CC) $(AFLAGS) -c -o $@ $< + +$(obj)%.o: $(obj)%.c + $(CC) $(CFLAGS) -c -o $@ $< + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/nand_spl/board/imx31_phycore/config.mk b/nand_spl/board/imx31_phycore/config.mk new file mode 100644 index 0000000..4c271c5 --- /dev/null +++ b/nand_spl/board/imx31_phycore/config.mk @@ -0,0 +1,33 @@ +# +# (C) Copyright 2008 +# Maxim Artamonov, <scn1874 at yandex.ru> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +# phyCORE-i.MX31 - PHYTEC’s phyCORE Single Board Computer module + +# TEXT_BASE for SPL: = CFG_NAND_U_BOOT_DST-0x40000 is set in board/imx31_phycore/config.mk + +# PAD_TO used to generate a 2kByte binary needed for the combined image +# -> PAD_TO = TEXT_BASE + 2048 +PAD_TO := $(shell expr $$[$(TEXT_BASE) + 2048]) + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff --git a/nand_spl/board/imx31_phycore/u-boot.lds b/nand_spl/board/imx31_phycore/u-boot.lds new file mode 100644 index 0000000..d25abf8 --- /dev/null +++ b/nand_spl/board/imx31_phycore/u-boot.lds @@ -0,0 +1,65 @@ +/* + * + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * January 2004 - Changed to support H4 device + * Copyright (c) 2004 Texas Instruments + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + start.o (.text) + lowlevel_init.o (.text) + nand_boot_mx31.o (.text) + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss : { *(.bss) } + _end = .; +} diff --git a/nand_spl/nand_boot_mx31.c b/nand_spl/nand_boot_mx31.c new file mode 100644 index 0000000..1cd7232 --- /dev/null +++ b/nand_spl/nand_boot_mx31.c @@ -0,0 +1,190 @@ +/* + * (C) Copyright 2008 + * Maxim Artamonov, <scn1874 at yandex.ru> + * + * (C) Copyright 2006-2008 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> +#include <nand.h> +#include <asm-arm/arch/mx31-regs.h> + +static void mx31_wait_ready(void) +{ + while (1) + if (NFC_CONFIG2 & NFC_INT){ + NFC_CONFIG2 = NFC_CONFIG2 & (~NFC_INT);/*int flag reset*/ + break; + } +} + +static void mx31_nand_init(void) +{ + /*unlocking RAM Buff*/ + NFC_CONFIG = 0x2; + + /*hardware ECC checking and correct*/ + NFC_CONFIG1 = NFC_ECC_EN; +} + +static void mx31_nand_command(unsigned short command) +{ + NFC_FLASH_CMD = command; + NFC_CONFIG2 = NFC_CMD; + mx31_wait_ready(); +} + +static void mx31_nand_page_address(unsigned int page_address) +{ + unsigned int page_count; + + NFC_FLASH_ADDR = 0x00; + NFC_CONFIG2 = NFC_ADDR; + mx31_wait_ready(); + + /*code only for 2kb flash*/ + if (CFG_NAND_PAGE_SIZE == 0x800){ + NFC_FLASH_ADDR = 0x00; + NFC_CONFIG2 = NFC_ADDR; + mx31_wait_ready(); + }; + + page_count = CFG_NAND_CHIP_SIZE / CFG_NAND_PAGE_SIZE; + + if (page_address <= page_count){ + page_count--;/* transform 0x01000000 to 0x00ffffff */ + do{ + NFC_FLASH_ADDR = (unsigned short)(page_address & 0xff); + NFC_CONFIG2 = NFC_ADDR; + mx31_wait_ready(); + page_address = page_address >> 8; + page_count = page_count >> 8; + }while (page_count); + } +} + +static void mx31_nand_data_output(void) +{ + NFC_CONFIG1 = NFC_ECC_EN; + NFC_BUF_ADDR = 0; /* read in first 0 buffer*/ + NFC_CONFIG2 = NFC_OUTPUT; + mx31_wait_ready(); +} + +static int mx31_nand_check_ecc(void) +{ + unsigned short ecc_status_registr; + + ecc_status_registr = NFC_ECC_STATUS_RESULT; + + if (ecc_status_registr != 0) + return 1;/*error*/ + return 0; +} + +static int mx31_read_page(unsigned int page_address, unsigned char *buf) +{ + int i; + volatile u32 *p1, *p2, a; + + mx31_nand_init (); + NFC_BUF_ADDR = 0; /* read in first 0 buffer*/ + mx31_nand_command (NAND_CMD_READ0); + mx31_nand_page_address (page_address); + + if (CFG_NAND_CHIP_SIZE >= 0x08000000) + mx31_nand_command (NAND_CMD_READSTART); + + mx31_nand_data_output ();/*fill the main buffer 0*/ + + if (mx31_nand_check_ecc ()) + while (1){ + break;}; /*!!!!!*/ + + p1 = (u32 *)MAIN_AREA0; + p2 = (u32 *)buf; + + /*main copy loop from NAND-buffer to SDRAM memory*/ + for (i=0; i < (CFG_NAND_PAGE_SIZE / 4); i++){ + *p2 = *p1; + p1++; + p2++; + } + + p1 = (u32 *)SPARE_AREA0; + + /*it is hardware specific code for 8-bit 512kB NAND-flash spare area*/ + p1++; + a = *p1; + a = (a & 0x0000ff00) >> 8; + + if (a != 0xff) /*bad block marker verify*/ + return 1;/*potential bad block*/ + + return 0; +} + +static int nand_load(unsigned int from, unsigned int size, unsigned char *buf) +{ + int i, bb; + + mx31_nand_init (); + + /*conver from to page number*/ + from = from / CFG_NAND_PAGE_SIZE; + + i = 0; + + while (i < (size/CFG_NAND_PAGE_SIZE)){ + + if ((from*CFG_NAND_PAGE_SIZE) >= CFG_NAND_CHIP_SIZE) + return 2;/*memory segment violation*/ + + bb = mx31_read_page (from, buf); + + /*checking first page of each block*/ + /*if this page has bb marker, then skip whole block*/ + if ((!(from % CFG_NAND_PAGE_COUNT)) && bb){ + from = from + CFG_NAND_PAGE_COUNT; + } + else{ + i++; + from++; + buf = buf + CFG_NAND_PAGE_SIZE; + } + } + return 0; +} + +/* + * The main entry for NAND booting. It's necessary that SDRAM is already + * configured and available since this code loads the main U-Boot image + * from NAND into SDRAM and starts it from there. + */ +void nand_boot(void) +{ + __attribute__((noreturn)) void (*uboot)(void); + + /*CFG_NAND_U_BOOT_OFFS and CFG_NAND_U_BOOT_SIZE must*/ + /* be align to full pages*/ + nand_load (CFG_NAND_U_BOOT_OFFS, CFG_NAND_U_BOOT_SIZE, \ + (uchar *)CFG_NAND_U_BOOT_DST); + + uboot = (void *)CFG_NAND_U_BOOT_START; + uboot (); +} -- 1.5.2.4

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[U-Boot] Problem while using u-boot for Omap 2430 sdp
by Vijay Kolhal 02 Jan '09

02 Jan '09

Dear Sir / Madam, I have tried using u-boot code for Omap 2430 sdp. after using command, make ARCH=arm CROSS_COMPILE=arm-none-linux-gnueabi- I am able to create boot image u-boot.bin and it also Run in Nor flash of board. But when i instered on puts(); statement or printf(); statement in icache_enable() function of cpu\arm1136\cpu.c file, Though it gets compile well and it create u-boot.bin image file, It doesnt get execute on Omap 2430 board. Currently i am debugging this issue but anyone of you know it in advance then please direct me for the same. Thanks and in advacne for any of your helf. Vijay V. Kolhal. Lnt Infotech Ltd., Mahape, New Mumbai, Email :- vijay.kolhal(a)lntinfotech.com vvk2200(a)gmail.com Cell No. :- 9920048840 Larsen & Toubro Infotech Ltd. www.Lntinfotech.com This Document is classified as: L&T Infotech Proprietary L&T Infotech Confidential L&T Infotech Internal Use Only L&T Infotech General Business This Email may contain confidential or privileged information for the intended recipient (s) If you are not the intended recipient, please do not use or disseminate the information, notify the sender and delete it from your system. ______________________________________________________________________

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