January 2009 - U-Boot

[U-Boot] [PATCH] USB: Add config option to call ehci_hcd_init() again after EHCI reset
by Stefan Roese 21 Jan '09

21 Jan '09

This patch adds the config option CONFIG_EHCI_HCD_INIT_AFTER_RESET to call ehci_hcd_init() again after ehci_reset() is executed. This is needed for the upcoming VCT EHCI support which needs to re-init the hcd part again after the EHCI CMD_RESET is executed. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/usb/usb_ehci_core.c | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-) diff --git a/drivers/usb/usb_ehci_core.c b/drivers/usb/usb_ehci_core.c index 28962fa..2f38f33 100644 --- a/drivers/usb/usb_ehci_core.c +++ b/drivers/usb/usb_ehci_core.c @@ -691,6 +691,11 @@ int usb_lowlevel_init(void) if (ehci_reset() != 0) return -1; +#if defined(CONFIG_EHCI_HCD_INIT_AFTER_RESET) + if (ehci_hcd_init() != 0) + return -1; +#endif + /* Set head of reclaim list */ memset(&qh_list, 0, sizeof(qh_list)); qh_list.qh_link = cpu_to_hc32((uint32_t)&qh_list | QH_LINK_TYPE_QH); -- 1.6.1

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[U-Boot] [PATCH] USB: Fix speed detection on EHCI cntr with root hub transaction translators
by Stefan Roese 21 Jan '09

21 Jan '09

This patch fixes an issue that the speed of USB devices was not detected correctly on some EHCI controllers. This will be used on the upcoming VCT EHCI support. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/usb/usb_ehci_core.c | 17 ++++++++++++++++- 1 files changed, 16 insertions(+), 1 deletions(-) diff --git a/drivers/usb/usb_ehci_core.c b/drivers/usb/usb_ehci_core.c index 9736707..28962fa 100644 --- a/drivers/usb/usb_ehci_core.c +++ b/drivers/usb/usb_ehci_core.c @@ -546,7 +546,22 @@ ehci_submit_root(struct usb_device *dev, unsigned long pipe, void *buffer, } if (reg & EHCI_PS_PP) tmpbuf[1] |= USB_PORT_STAT_POWER >> 8; - tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + + if (ehci_is_TDI()) { + switch ((reg >> 26) & 3) { + case 0: + break; + case 1: + tmpbuf[1] |= USB_PORT_STAT_LOW_SPEED >> 8; + break; + case 2: + default: + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + break; + } + } else { + tmpbuf[1] |= USB_PORT_STAT_HIGH_SPEED >> 8; + } if (reg & EHCI_PS_CSC) tmpbuf[2] |= USB_PORT_STAT_C_CONNECTION; -- 1.6.1

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[U-Boot] Trouble booting custom MPC8265 board with u-boot 1-3.2
by Jyotshna Cherukuri 21 Jan '09

21 Jan '09

Hi, I am trying to get custom MPC8265 board up and runnning with u-boot 1.3.2 and I am using Codewarrior USB TAP debugger to debug u-boot code using a custom initialization file. The board gives me a prompt when the debugger is on and when I turn off the debugger I don't see anything on the serial console. My u-boot configuarations and initilization file both match each other but I don't know why its not booting all by itself. Also my board doesn't have any BCSR registers and so I programmed HRCW into first byes of FLASH SIMM but I don't know whether the board is fetching it on reset. Could any one please let me know to how we can find out if HRCW is fetched from FLASH on RESET. If so which registers I have to look at ? Any help is greatly appreciated . Thanks in advance Regards Jyotshna

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[U-Boot] Fw: TFTP fails when using network switch
by Loren A. Linden Levy 21 Jan '09

21 Jan '09

Hi Everyone, I am having an interesting problem with am m5282Lite Dev Kit. I had done all of the previous development work by connection the card directly to a spare ethernet card in my PC via a cross-over cable. This worked just fine and the tftp download was very fast. Now I have run a long Ethernet cable and can download the uClinux using u-boot, but the hub is 10Mbit. I get some "bad len" errors but eventually (seems to take a long time) the download completes and uClinux boots. I then tried to hook up a spare 100MBit switch i had running one Ethernet cable to the pC (tftp server) and one to the coldfire board (now using regular network cable) but the tftp just times out. The funny thing is i seem to be able to ping the coldfire from the PC side but not the PC from the coldfire side. Does anyone have an idea of what is wrong? Thanks in advance! Alex -- -- --------------------------------------------- Loren A. Linden Levy Department of Physics 390 UCB University of Colorado Boulder, CO 80309-0390 Tel: 303-735-6146 (CU) / +049 040 8998 4789 (DESY) Fax: 303-492-3352 (CU) / +049 040 8998 4034 (DESY) Cell: 303-332-2768 (U.S.) / +049 (0)151 5496 1831 (Germany) Email: Loren.Lindenlevy(a)colorado.edu url: http://up.colorado.edu/~lindenle _____________________________________________ --------------------------------------------- This email has been cryptographically signed. Search for "lindenle" at pgp.mit.edu to obtain my public key which can be used to verify the authenticity of this message. _____________________________________________ --------------------------------------------- -- -- --------------------------------------------- Loren A. Linden Levy Department of Physics 390 UCB University of Colorado Boulder, CO 80309-0390 Tel: 303-735-6146 (CU) / +049 040 8998 4789 (DESY) Fax: 303-492-3352 (CU) / +049 040 8998 4034 (DESY) Cell: 303-332-2768 (U.S.) / +049 (0)151 5496 1831 (Germany) Email: Loren.Lindenlevy(a)colorado.edu url: http://up.colorado.edu/~lindenle _____________________________________________ --------------------------------------------- This email has been cryptographically signed. Search for "lindenle" at pgp.mit.edu to obtain my public key which can be used to verify the authenticity of this message. _____________________________________________ ---------------------------------------------

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[U-Boot] u-boot-v2
by John Jeffers 21 Jan '09

21 Jan '09

Hi If I use for u-boot-v2 #ln -s arm cross_arch #ln -s /opt/arm-v5te-linux-gnueabi/gcc-4.1.2-glibc-2.5-binutils-2.17-kernel-2.6.18/arm-v5te-linux-gnueabi/bin \ cross_compile During make menuconfig the arm is not picked up as the architecture. I appear to get sandbox. Obviously I am not telling the menuconfig to use my architecture. Perhap the /board is more appropriate.' Regards John For u-boot-v2 we are instructed: U-Boot uses the Linux kernel's build system. It consists of two parts: the makefile infrastructure (kbuild), plus a configuration system (kconfig). So building U-Boot is very similar to building the Linux kernel. For the examples below, we use the User Mode U-Boot implementation, which is a port of U-Boot to the Linux userspace. This makes it possible to test drive the code without having real hardware. So for this test scenario, ARCH=sandbox is the valid architecture selection. This currently only works on ia32 hosts and partly on x86-64. Selection of the architecture and the cross compiler can be done in two ways. You can either specify it using the environment variables ARCH and CROSS_COMPILE, or you can create the soft links cross_arch and cross_compile pointing to your architecture and compiler. For ARCH=sandbox we do not need a cross compiler so it is sufficient to specify the architecture: # ln -s sandbox cross_arch In order to configure the various aspects of U-Boot, start the U-Boot configuration system: # make menuconfig

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[U-Boot] question about U-Boot's cpu/ppc4xx/44x_spd_ddr2.c
by carolyn.j.smith＠tektronix.com 21 Jan '09

21 Jan '09

I have a question about some of the code in U-Boot's cpu/ppc4xx/44x_spd_ddr2.c, in particular the program_codt function and these lines of code: mfsdram(SDRAM_CODT, codt); codt |= (SDRAM_CODT_IO_NMODE & (~SDRAM_CODT_DQS_SINGLE_END & ~SDRAM_CODT_CKSE_SINGLE_END & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END)); What is the intention of this code? As far as I can tell, all it is doing is or'ing SDRAM_CODT_IO_NMODE (= 0x00000001) into the codt variable and the & (~SDRAM_CODT_DQS_SINGLE_END & ~SDRAM_CODT_CKSE_SINGLE_END & ~SDRAM_CODT_FEEBBACK_RCV_SINGLE_END & ~SDRAM_CODT_FEEBBACK_DRV_SINGLE_END) part of it has no real effect. Was the intention to turn on the SDRAM_CODT_IO_NMODE bit and turn off the SDRAM_CODT_DQS_SINGLE_END, SDRAM_CODT_CKSE_SINGLE_END, SDRAM_CODT_FEEBBACK_RCV_SINGLE_END and SDRAM_CODT_FEEBBACK_DRV_SINGLE_END bits in which case the code should be something like this? codt |= SDRAM_CODT_IO_NMODE; codt &= ~(SDRAM_CODT_DQS_SINGLE_END | SDRAM_CODT_CKSE_SINGLE_END | SDRAM_CODT_FEEBBACK_RCV_SINGLE_END | SDRAM_CODT_FEEBBACK_DRV_SINGLE_END); Also the 460EX manual I have (revision 1.16 - November 17, 2008) shows bits 29 and 30 of the CODT register as Reserved (in which case they shouldn't be modified) while U-Boot has them as #define SDRAM_CODT_FEEBBACK_RCV_SINGLE_END 0x00000004 #define SDRAM_CODT_FEEBBACK_DRV_SINGLE_END 0x00000002 Do I have an out-of-date manual or are they reserved only for the 460EX and not for other processors using this code? Thanks, Carolyn

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[U-Boot] NAND is detected as 0 MiB
by Adan Scotney 21 Jan '09

21 Jan '09

Hi, I am trying to update some (for the most part very ugly) code from a source tree based on u-boot 1.1.6 which I have been given to a more up to date version (I am trying to get 2008.10 to work for now, and I am hoping that when it does, keeping in line with the main tree will be a bit easier). I have managed to get 2008.10 to run, but I simply get this on the serial output: U-Boot 2008.10 (Jan 9 2009 - 10:57:15) DRAM: 64 MB manufacture ID = 191lx device ID = 9051lx Flash: 4 MB NAND: 0 MiB And then, it reboots and does the same thing again. Clearly the NAND driver isn't working properly, so does anybody have any ideas about specific things I should check? I have included the source below in case anybody can spot something obviously wrong with it. Many thanks, Adan #include <common.h> #include <asm/io.h> #ifdef CONFIG_CMD_NAND #include <nand.h> /* * hardware specific access to control-lines */ #define MASK_CLE 0x10 #define MASK_ALE 0x18 static void pollux_hwcontrol(struct mtd_info *mtd, int cmd, unsigned int ctrl) { struct nand_chip *chip = mtd->priv; void __iomem* addr = chip->IO_ADDR_W; if (cmd == NAND_CMD_NONE) return; if(ctrl & NAND_CLE) addr += MASK_CLE; else if(ctrl & NAND_ALE) addr += MASK_ALE; writeb(cmd, addr); } void board_nand_init(struct nand_chip *nand) { /* set up nand chip data structure */ nand->IO_ADDR_R = nand->IO_ADDR_W = (void *)0xAC000000; nand->cmd_ctrl = pollux_hwcontrol; nand->dev_ready = NULL; /* use software ECC for now */ nand->ecc.mode = NAND_ECC_SOFT; nand->options = NAND_SAMSUNG_LP_OPTIONS|NAND_NO_AUTOINCR; nand->chip_delay = 18; } #endif

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[U-Boot] nand erase cleanmarker and jffs2
by Derek Ou 20 Jan '09

20 Jan '09

Dear all, What is the use of "nand erase clean"? According to the source code, it erases the NAND block and also writes the jffs2 cleanmarker to OOB session. Is this necessary to write a jffs2 file system? I didn't run into any Linux file system problem when I erased a NAND partitaion without clean flag and wrote the jffs2 file system there. Currently, I only have a "jffs2_scan_inode_node() CRC failed on ..." message and I think it's not related to how I erased the partition. Am I right? By the way, the Linux tool seems to indicate that the size of cleanmarker should be 12 bytes. But it seems to be only 8 bytes from our board/u-boot. Which one is correct? Many thanks. Derek

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[U-Boot] u-boot compiler optimization barrier, board_init_f
by Suresh Bhaskaran 20 Jan '09

20 Jan '09

Does anyone know what I have to do "differently" for the "compiler optimization barrier" for GCC >= 3.4 in board_init_f? I am suspecting some difference here in why my compilation with ELDK4.1.1 of uboot v 1.3.4 is failing. I have it working with ELDK 3.1, but it is failing ELDK 4.1.1. It works a little better if I turn compiler optimization flags off. (but still fails) Thanks in advance. The relevant code snippet follows: Suresh Bhaskaran void board_init_f(ulong bootflag) { DECLARE_GLOBAL_DATA_PTR; int count =0; gd_t gd_data, *id; bd_t *bd; init_fnc_t **init_fnc_ptr; ulong addr, addr_sp, len = (ulong)&uboot_end - CFG_MONITOR_BASE; /* Pointer is writable since we allocated a register for it. */ gd = &gd_data; /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); memset ((void *)gd, 0, sizeof (gd_t)); for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr)() != 0) { puts(" error at "); putc(count+'0'); printf("fnc at %p\n", *init_fnc_ptr); hang (); } count++; }

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[U-Boot] [PATCH] nand read.jffs2 (nand_legacy) in common/cmd_nand.c
by Schlaegl Manfred jun. 20 Jan '09

20 Jan '09

Hi! Error with CONFIG_NAND_LEGACY in common/cmd_nand.c: With current code "nand read.jffs2s" (read and skip bad blocks) is always interpreted as "nand read.jffs2" (read and fill bad blocks with 0xff). This is because ".jffs2" is tested before ".jffs2s" and only the first two characters are compared. Correction: Test for ".jffs2s" first and compare the first 7 characters. diff --git a/common/cmd_nand.c b/common/cmd_nand.c index 0a366d3..ba1b27f 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -854,13 +854,12 @@ int do_nand (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) (u_char *) addr); } return ret; - } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) - cmd |= NANDRW_JFFS2; /* skip bad blocks */ - else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 2)) { + } else if (cmdtail && !strncmp (cmdtail, ".jffs2s", 7)) { cmd |= NANDRW_JFFS2; /* skip bad blocks (on read too) */ if (cmd & NANDRW_READ) cmd |= NANDRW_JFFS2_SKIP; /* skip bad blocks (on read too) */ - } + } else if (cmdtail && !strncmp (cmdtail, ".jffs2", 2)) + cmd |= NANDRW_JFFS2; /* skip bad blocks */ #ifdef SXNI855T /* need ".e" same as ".j" for compatibility with older units */ else if (cmdtail && !strcmp (cmdtail, ".e")) Signed-off-by: Manfred Schlaegl jun. <manfred.schlaegl(a)gmx.at>

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