September 2008 - U-Boot

[U-Boot] Handling different ethernhet phys on the same system.
by vb 26 Sep '08

26 Sep '08

Hello Ben, I am trying to port u-boot on a system which deploys two different types of ethernet PHYs, and don't see a good way of doing it with the current sw structure. There are concurrent implementations for supporting different PHYs, and it looks like quite often bringing in a new etherent controller brings in a duplicate PHY driver code. OTOH it is always presumed that the same kind of phy is used on all ports. I want to modify this scheme, but I don't want to go too far on a tangent, as we here plan to integrate our changes back into the master repository one of those days. Here is what I suggest doing: we introduce a concept of 'phy bus' - an MDIO bus for instance, and 'phy interface' which is the phy driver. For illustration purpose, the phy bus could look like this: struct phy_bus { int (*write)(u8 addr, u16 reg, u16 value); int (*read)(u8 addr, u16 reg, u16 *value); } and the driver would provide methods like struct phy_driver { int (*reset)(struct phy_bus*, u8 addr)) int (*init)(struct phy_bus*, u8 addr) ... } the set of methods could be fine tuned at any time obviously, the important thing is that each method would receive the pointer to the phy bus to be used to communicate with the device. Then, in the ethernet device structure we would add two pointers: to the bus serving the port and to the driver serving the port. This would allow any new ethernet controller provide its own mdio bus implementation and then use existing phy driver the same way any other controller uses it. This would also allow to attach different phy devices to different ethernet ports. And of course the multiple PHY implementations won't be needed anymore, just one instance will serve any ethernet device. What do you think? TIA, Vadim On Thu, Sep 25, 2008 at 11:09 PM, Ben Warren <biggerbadderben(a)gmail.com> wrote: > Wolfgang Denk wrote: >> Dear Ben, >> >> I just ran over this piece of code in NetLoop() [see "net/net.c"]: >> >> 286 int >> 287 NetLoop(proto_t protocol) >> 288 { >> ... >> 322 eth_halt(); >> 323 #ifdef CONFIG_NET_MULTI >> 324 eth_set_current(); >> 325 #endif >> 326 if (eth_init(bd) < 0) { >> 327 eth_halt(); >> 328 return(-1); >> 329 } >> >> Am I reading this correctly that we eth_halt() and eth_init() the >> network interface for each and every call to NetLoop? >> >> > Yes, it looks that way. Ripe for gutting. >> This looks terribly inefficient to me - is there any rationale behind >> this? >> >> > Probably, but it escapes me. It most certainly predates my involvement > in this project. >> Also, the eth_set_current() checking should IMHO be done just once, >> before we start a network transfer, or when we actually switch >> interfaces, but not for each and every call to NetLoop() ? >> >> > Maybe, but eth_set_current() is pretty lightweight. NetLoop is only > called when we start a network transfer, so this doesn't seem too > egregious. It could definitely stand to be refactored. >> Best regards, >> >> Wolfgang Denk >> >> > regards, > Ben > _______________________________________________ > U-Boot mailing list > U-Boot(a)lists.denx.de > http://lists.denx.de/mailman/listinfo/u-boot >

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[U-Boot] [PATCH] fdt: Overwrite /chosen node in bootm if it already exists in the dtb
by Stefan Roese 26 Sep '08

26 Sep '08

Set force parameter in fdt_chosen() call in do_bootm_linux() call. Without this, the chosen node is not overwritten if it already exists. Signed-off-by: Stefan Roese <sr(a)denx.de> --- lib_ppc/bootm.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/lib_ppc/bootm.c b/lib_ppc/bootm.c index 38266e1..5af25dd 100644 --- a/lib_ppc/bootm.c +++ b/lib_ppc/bootm.c @@ -145,7 +145,7 @@ int do_bootm_linux(int flag, int argc, char *argv[], bootm_headers_t *images) * if the user wants it (the logic is in the subroutines). */ if (of_size) { - if (fdt_chosen(of_flat_tree, 0) < 0) { + if (fdt_chosen(of_flat_tree, 1) < 0) { puts ("ERROR: "); puts ("/chosen node create failed"); puts (" - must RESET the board to recover.\n"); -- 1.6.0.2

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[U-Boot] Inefficient code in NetLoop() ?
by Wolfgang Denk 26 Sep '08

26 Sep '08

Dear Ben, I just ran over this piece of code in NetLoop() [see "net/net.c"]: 286 int 287 NetLoop(proto_t protocol) 288 { ... 322 eth_halt(); 323 #ifdef CONFIG_NET_MULTI 324 eth_set_current(); 325 #endif 326 if (eth_init(bd) < 0) { 327 eth_halt(); 328 return(-1); 329 } Am I reading this correctly that we eth_halt() and eth_init() the network interface for each and every call to NetLoop? This looks terribly inefficient to me - is there any rationale behind this? Also, the eth_set_current() checking should IMHO be done just once, before we start a network transfer, or when we actually switch interfaces, but not for each and every call to NetLoop() ? Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de All easy problems have already been solved.

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[U-Boot] [PATCH 08/11 v1] ARM: OMAP3: Add I2C and network support
by dirk.behme＠googlemail.com 26 Sep '08

26 Sep '08

Subject: [PATCH 08/11 v1] ARM: OMAP3: Add I2C and network support From: Dirk Behme <dirk.behme(a)gmail.com> Add I2C and network support Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- drivers/i2c/Makefile | 1 drivers/i2c/omap24xx_i2c.c | 132 ++++++++++++++++++++++++++------------------- drivers/net/Makefile | 1 net/eth.c | 5 + 4 files changed, 84 insertions(+), 55 deletions(-) Index: u-boot_master/drivers/i2c/Makefile =================================================================== --- u-boot_master.orig/drivers/i2c/Makefile +++ u-boot_master/drivers/i2c/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o Index: u-boot_master/drivers/i2c/omap24xx_i2c.c =================================================================== --- u-boot_master.orig/drivers/i2c/omap24xx_i2c.c +++ u-boot_master/drivers/i2c/omap24xx_i2c.c @@ -25,8 +25,10 @@ #include <asm/arch/i2c.h> #include <asm/io.h> +#define inb(a) __raw_readb(a) +#define outb(a, v) __raw_writeb(a, v) #define inw(a) __raw_readw(a) -#define outw(a,v) __raw_writew(a,v) +#define outw(a, v) __raw_writew(a, v) static void wait_for_bb (void); static u16 wait_for_pin (void); @@ -40,28 +42,28 @@ void i2c_init (int speed, int slaveadd) udelay(1000); outw(0x0, I2C_SYSC); /* will probably self clear but */ - if (inw (I2C_CON) & I2C_CON_EN) { - outw (0, I2C_CON); + if (inw(I2C_CON) & I2C_CON_EN) { + outw(0, I2C_CON); udelay (50000); } /* 12Mhz I2C module clock */ - outw (0, I2C_PSC); + outw(0, I2C_PSC); speed = speed/1000; /* 100 or 400 */ scl = ((12000/(speed*2)) - 7); /* use 7 when PSC = 0 */ - outw (scl, I2C_SCLL); - outw (scl, I2C_SCLH); + outw(scl, I2C_SCLL); + outw(scl, I2C_SCLH); /* own address */ - outw (slaveadd, I2C_OA); - outw (I2C_CON_EN, I2C_CON); + outw(slaveadd, I2C_OA); + outw(I2C_CON_EN, I2C_CON); /* have to enable intrrupts or OMAP i2c module doesn't work */ - outw (I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | - I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); + outw(I2C_IE_XRDY_IE | I2C_IE_RRDY_IE | I2C_IE_ARDY_IE | + I2C_IE_NACK_IE | I2C_IE_AL_IE, I2C_IE); udelay (1000); flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); + outw(0xFFFF, I2C_STAT); + outw(0, I2C_CNT); } static int i2c_read_byte (u8 devaddr, u8 regoffset, u8 * value) @@ -73,11 +75,11 @@ static int i2c_read_byte (u8 devaddr, u8 wait_for_bb (); /* one byte only */ - outw (1, I2C_CNT); + outw(1, I2C_CNT); /* set slave address */ - outw (devaddr, I2C_SA); + outw(devaddr, I2C_SA); /* no stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); + outw(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX, I2C_CON); status = wait_for_pin (); @@ -85,7 +87,7 @@ static int i2c_read_byte (u8 devaddr, u8 /* Important: have to use byte access */ *(volatile u8 *) (I2C_DATA) = regoffset; udelay (20000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { + if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -94,42 +96,46 @@ static int i2c_read_byte (u8 devaddr, u8 if (!i2c_error) { /* free bus, otherwise we can't use a combined transction */ - outw (0, I2C_CON); - while (inw (I2C_STAT) || (inw (I2C_CON) & I2C_CON_MST)) { + outw(0, I2C_CON); + while (inw(I2C_STAT) || (inw(I2C_CON) & I2C_CON_MST)) { udelay (10000); /* Have to clear pending interrupt to clear I2C_STAT */ - outw (0xFFFF, I2C_STAT); + outw(0xFFFF, I2C_STAT); } wait_for_bb (); /* set slave address */ - outw (devaddr, I2C_SA); + outw(devaddr, I2C_SA); /* read one byte from slave */ - outw (1, I2C_CNT); + outw(1, I2C_CNT); /* need stop bit here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, - I2C_CON); + outw(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, + I2C_CON); status = wait_for_pin (); if (status & I2C_STAT_RRDY) { - *value = inw (I2C_DATA); +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + *value = inb(I2C_DATA); +#else + *value = inw(I2C_DATA); +#endif udelay (20000); } else { i2c_error = 1; } if (!i2c_error) { - outw (I2C_CON_EN, I2C_CON); - while (inw (I2C_STAT) - || (inw (I2C_CON) & I2C_CON_MST)) { + outw(I2C_CON_EN, I2C_CON); + while (inw(I2C_STAT) + || (inw(I2C_CON) & I2C_CON_MST)) { udelay (10000); - outw (0xFFFF, I2C_STAT); + outw(0xFFFF, I2C_STAT); } } } flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); + outw(0xFFFF, I2C_STAT); + outw(0, I2C_CNT); return i2c_error; } @@ -142,22 +148,37 @@ static int i2c_write_byte (u8 devaddr, u wait_for_bb (); /* two bytes */ - outw (2, I2C_CNT); + outw(2, I2C_CNT); /* set slave address */ - outw (devaddr, I2C_SA); + outw(devaddr, I2C_SA); /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | - I2C_CON_STP, I2C_CON); + outw(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_TRX | + I2C_CON_STP, I2C_CON); /* wait until state change */ status = wait_for_pin (); if (status & I2C_STAT_XRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* send out 1 byte */ + outb(regoffset, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + status = wait_for_pin(); + if ((status & I2C_STAT_XRDY)) { + /* send out next 1 byte */ + outb(value, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + } else { + i2c_error = 1; + } +#else /* send out two bytes */ - outw ((value << 8) + regoffset, I2C_DATA); + outw((value << 8) + regoffset, I2C_DATA); +#endif + /* must have enough delay to allow BB bit to go low */ udelay (50000); - if (inw (I2C_STAT) & I2C_STAT_NACK) { + if (inw(I2C_STAT) & I2C_STAT_NACK) { i2c_error = 1; } } else { @@ -167,18 +188,18 @@ static int i2c_write_byte (u8 devaddr, u if (!i2c_error) { int eout = 200; - outw (I2C_CON_EN, I2C_CON); - while ((stat = inw (I2C_STAT)) || (inw (I2C_CON) & I2C_CON_MST)) { + outw(I2C_CON_EN, I2C_CON); + while ((stat = inw(I2C_STAT)) || (inw(I2C_CON) & I2C_CON_MST)) { udelay (1000); /* have to read to clear intrrupt */ - outw (0xFFFF, I2C_STAT); + outw(0xFFFF, I2C_STAT); if(--eout == 0) /* better leave with error than hang */ break; } } flush_fifo(); - outw (0xFFFF, I2C_STAT); - outw (0, I2C_CNT); + outw(0xFFFF, I2C_STAT); + outw(0, I2C_CNT); return i2c_error; } @@ -191,7 +212,11 @@ static void flush_fifo(void) while(1){ stat = inw(I2C_STAT); if(stat == I2C_STAT_RRDY){ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + inb(I2C_DATA); +#else inw(I2C_DATA); +#endif outw(I2C_STAT_RRDY,I2C_STAT); udelay(1000); }else @@ -203,34 +228,33 @@ int i2c_probe (uchar chip) { int res = 1; /* default = fail */ - if (chip == inw (I2C_OA)) { + if (chip == inw(I2C_OA)) return res; - } /* wait until bus not busy */ wait_for_bb (); /* try to read one byte */ - outw (1, I2C_CNT); + outw(1, I2C_CNT); /* set slave address */ - outw (chip, I2C_SA); + outw(chip, I2C_SA); /* stop bit needed here */ - outw (I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); + outw(I2C_CON_EN | I2C_CON_MST | I2C_CON_STT | I2C_CON_STP, I2C_CON); /* enough delay for the NACK bit set */ udelay (50000); - if (!(inw (I2C_STAT) & I2C_STAT_NACK)) { + if (!(inw(I2C_STAT) & I2C_STAT_NACK)) { res = 0; /* success case */ flush_fifo(); outw(0xFFFF, I2C_STAT); } else { outw(0xFFFF, I2C_STAT); /* failue, clear sources*/ - outw (inw (I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ + outw(inw(I2C_CON) | I2C_CON_STP, I2C_CON); /* finish up xfer */ udelay(20000); wait_for_bb (); } flush_fifo(); - outw (0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ + outw(0, I2C_CNT); /* don't allow any more data in...we don't want it.*/ outw(0xFFFF, I2C_STAT); return res; } @@ -291,14 +315,14 @@ static void wait_for_bb (void) u16 stat; outw(0xFFFF, I2C_STAT); /* clear current interruts...*/ - while ((stat = inw (I2C_STAT) & I2C_STAT_BB) && timeout--) { - outw (stat, I2C_STAT); + while ((stat = inw(I2C_STAT) & I2C_STAT_BB) && timeout--) { + outw(stat, I2C_STAT); udelay (50000); } if (timeout <= 0) { printf ("timed out in wait_for_bb: I2C_STAT=%x\n", - inw (I2C_STAT)); + inw(I2C_STAT)); } outw(0xFFFF, I2C_STAT); /* clear delayed stuff*/ } @@ -310,7 +334,7 @@ static u16 wait_for_pin (void) do { udelay (1000); - status = inw (I2C_STAT); + status = inw(I2C_STAT); } while ( !(status & (I2C_STAT_ROVR | I2C_STAT_XUDF | I2C_STAT_XRDY | I2C_STAT_RRDY | I2C_STAT_ARDY | I2C_STAT_NACK | @@ -318,7 +342,7 @@ static u16 wait_for_pin (void) if (timeout <= 0) { printf ("timed out in wait_for_pin: I2C_STAT=%x\n", - inw (I2C_STAT)); + inw(I2C_STAT)); outw(0xFFFF, I2C_STAT); } return status; Index: u-boot_master/drivers/net/Makefile =================================================================== --- u-boot_master.orig/drivers/net/Makefile +++ u-boot_master/drivers/net/Makefile @@ -69,6 +69,7 @@ COBJS-$(CONFIG_VSC7385_ENET) += vsc7385. COBJS-$(CONFIG_XILINX_EMAC) += xilinx_emac.o COBJS-$(CONFIG_XILINX_EMACLITE) += xilinx_emaclite.o COBJS-$(CONFIG_SH_ETHER) += sh_eth.o +COBJS-$(CONFIG_DRIVER_SMC911X) += smc911x.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) Index: u-boot_master/net/eth.c =================================================================== --- u-boot_master.orig/net/eth.c +++ u-boot_master/net/eth.c @@ -508,7 +508,7 @@ extern int emac4xx_miiphy_initialize(bd_ extern int mcf52x2_miiphy_initialize(bd_t *bis); extern int ns7520_miiphy_initialize(bd_t *bis); extern int davinci_eth_miiphy_initialize(bd_t *bis); - +extern int eth_init(bd_t *bd); int eth_initialize(bd_t *bis) { @@ -532,6 +532,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_DRIVER_TI_EMAC) davinci_eth_miiphy_initialize(bis); #endif +#if defined(CONFIG_DRIVER_SMC911X) + eth_init(bis); +#endif return 0; } #endif

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Re: [U-Boot] working with loadb & bootm on u-boot-v2 for imx27ads Board
by Lejin K Joy 26 Sep '08

26 Sep '08

-----Original Message----- From: Nishanth Menon [mailto:menon.nishanth@gmail.com] Sent: Thursday, September 25, 2008 7:07 PM To: Lejin K Joy Cc: Robert Schwebel; Sascha Hauer; wd(a)denx.de; u-boot(a)lists.denx.de Subject: Re: [U-Boot] working with loadb & bootm on u-boot-v2 for imx27ads Board On Thu, Sep 25, 2008 at 8:04 AM, Lejin K Joy <lejin(a)spacomp.com> wrote: > > --------------- > uboot:/ loadb -f /dev/ram0 -o 0x100000 Do you have /dev/ram0? is it mapped to 0xa0000000? there could be issues with mach-types.. I am not sure though.. I am not entirely sure about imx boot procedure(I am an OMAP guy ;) )..but it could be uImage you need there? I am not too sure.. does the piggy relocate the kernel? I am not too sure.. probably the kernel details would help.. > ## Ready for binary (kermit) download to 0x00100000 offset on /dev/ram0 > device a > t 115200 bps... > ## Total Size = 0x0014deb9 = 1367737 Bytes > > uboot:/ go 0xa0100000 Should'nt this be bootm 0xa0100000? Regards, Nishanth Menon ----------------------------- Hi All, The " bootm 0xa0100000" option is not helping.... It's displaying "could not open : No Such file or directory" And the help says the option is bootm [option] image. But nothing helps. The image being tried is getting loaded on the same board when board is flashed with redboot using the following commands. 1) load -r -b 0x100000 -m xmodem zimage 2) load -v -r -b 0x01000000 -m xmodem ramdisk.gz 3) exec -r 0x001000000 -s 0x00600000 -b 0x100000 -l 0x00200000 -c "init=/linuxrc console=ttymxc0,115200 root=/dev/ram" If any suggestions, please share..!! Thanks, Lejin

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Re: [U-Boot] CFI driver and P33 64M flash
by yusuf khan 26 Sep '08

26 Sep '08

>Message: 2 >Date: Thu, 25 Sep 2008 16:50:27 +0300 >From: Felix Radensky <felix(a)embedded-sol.com> >Subject: [U-Boot] CFI driver and P33 64M flash >To: u-boot(a)lists.denx.de >Message-ID: <48DB9723.2060708(a)embedded-sol.com> >Content-Type: text/plain; charset=ISO-8859-1; format=flowed >Hi, >'m running U-Boot 1.3.4 on custom 460EX based board, >equipped with 64M P33 flash (similar to Intel P30). See >http://www.numonyx.com/Documents/Datasheets/314749_P33_Discrete_DS.pdf<http://www.numonyx.com/Documents/Datasheets/314749_P33_Discrete_DS.pdf> >This flash is comprised internally of two 32M flashes. >I have the following declarations in configuration file: >#define CFG_FLASH_CFI /* The flash is CFI compatible */ >#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ >#define CFG_FLASH_BANKS_LIST {CFG_FLASH_BASE} >#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ >#define CFG_MAX_FLASH_SECT 518 /* max number of sectors on one >chip */ >#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x >faster) */ >#define CFG_FLASH_PROTECTION 1 /* use hardware flash >protection */ >#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on >flinfo */ >U-Boot identifies this flash as 32M flash. Below is debug output from >CFI driver: >FLASH: flash detect cfi >fwc addr fc000000 cmd f0 f0 8bit x 8 bit >fwc addr fc000000 cmd ff ff 8bit x 8 bit >fwc addr fc000055 cmd 98 98 8bit x 8 bit >is= cmd 51(Q) addr fc000010 is= 0 51 >fwc addr fc000555 cmd 98 98 8bit x 8 bit >is= cmd 51(Q) addr fc000010 is= 0 51 >fwc addr fc000000 cmd f0 f0f0 16bit x 8 bit >fwc addr fc000000 cmd ff ffff 16bit x 8 bit >fwc addr fc0000aa cmd 98 9898 16bit x 8 bit >is= cmd 51(Q) addr fc000020 is= 0051 5151 >fwc addr fc000aaa cmd 98 9898 16bit x 8 bit >is= cmd 51(Q) addr fc000020 is= 0051 5151 >fwc addr fc000000 cmd f0 00f0 16bit x 16 bit >fwc addr fc000000 cmd ff 00ff 16bit x 16 bit >fwc addr fc0000aa cmd 98 0098 16bit x 16 bit >is= cmd 51(Q) addr fc000020 is= 0051 0051 >is= cmd 52(R) addr fc000022 is= 0052 0052 >is= cmd 59(Y) addr fc000024 is= 0059 0059 >device interface is 1 >found port 2 chip 2 port 16 bits chip 16 bits >00 : 51 52 59 01 00 0a 01 00 00 00 00 23 36 85 95 08 QRY........#6... >10 : 09 0a 00 01 01 02 00 19 01 00 06 00 02 03 00 80 ................ >20 : 00 fe 00 00 02 00 00 00 00 ff ff ff ff fc 36 a4 ..............6. >fwc addr fc000000 cmd ff 00ff 16bit x 16 bit >fwc addr fc000000 cmd 90 0090 16bit x 16 bit >fwc addr fc000000 cmd ff 00ff 16bit x 16 bit >fwc addr fc0000aa cmd 98 0098 16bit x 16 bit >manufacturer is 1 >manufacturer id is 0x89 >device id is 0x22 >device id2 is 0x0 >cfi version is 0x3135 >size_ratio 1 port 16 bits chip 16 bits >found 2 erase regions >erase region 0: 0x00800003 >erase_region_count = 4 erase_region_size = 32768 >erase region 1: 0x020000fe >erase_region_count = 255 erase_region_size = 131072 >fwc addr fc000000 cmd ff 00ff 16bit x 16 bit >32 MB >What should I change in configuration/driver to get >all 64M of flash detected ? >Thanks a lot. >Felix. Hi Set the CFG_MAX_FLASH_SECT to 259 and adjust the sector size to 256K I think it should work than. -- Thanks & Regards Yusuf A Khan Multitech Software Systems Koramangala,Bangalore

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[U-Boot] [PATCH] 8xx: prevent a machine check in scc_init().
by Gary Jennejohn 26 Sep '08

26 Sep '08

Signed-off-by: Gary Jennejohn <garyj(a)denx.de> --- cpu/mpc8xx/scc.c | 17 +++++++++++++++++ 1 files changed, 17 insertions(+), 0 deletions(-) diff --git a/cpu/mpc8xx/scc.c b/cpu/mpc8xx/scc.c index 09a3db1..9ffeb11 100644 --- a/cpu/mpc8xx/scc.c +++ b/cpu/mpc8xx/scc.c @@ -70,6 +70,9 @@ static int scc_recv(struct eth_device* dev); static int scc_init (struct eth_device* dev, bd_t * bd); static void scc_halt(struct eth_device* dev); +/* avoid unnecessary reinitialization of the SCC */ +static int scc_init_completed; + int scc_initialize(bd_t *bis) { struct eth_device* dev; @@ -193,6 +196,19 @@ static int scc_init (struct eth_device *dev, bd_t * bis) volatile immap_t *immr = (immap_t *) CFG_IMMR; + /* + * This routine is called again and again from eth_init(), + * especially when CONFIG_NETCONSOLE is defined and + * stdout=nc. + * Avoid unneccessary flailing, otherwise we can get a panic here. + */ + if (scc_init_completed) { + immr->im_ioport.iop_pcso |= (PC_ENET_CLSN | PC_ENET_RENA); + immr->im_cpm.cp_scc[SCC_ENET].scc_gsmrl |= + (SCC_GSMRL_ENR | SCC_GSMRL_ENT); + return 1; + } + #if defined(CONFIG_LWMON) reset_phy(); #endif @@ -544,6 +560,7 @@ static int scc_init (struct eth_device *dev, bd_t * bis) udelay (100000); /* wait 100 ms */ #endif + scc_init_completed = 1; return 1; } -- 1.5.4.3 --- Gary Jennejohn ********************************************************************* DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de *********************************************************************

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[U-Boot] platform configuration
by Roman Mashak 26 Sep '08

26 Sep '08

Hello Reading u-boot's README paper and trying to figure out a few aspects: (1) as I know the bootloader sets up memory area for argument passing, initializes it with data structures and fill up with the values. Is this the structure defined in $(UBOOT)/include/asm-arm/global_data.h, named 'global_data' ? (2) this question is a consequence of the first. 'struct bd_info' from $(UBOOT)/include/asm-arm/u-boot.h is a structure holding board's specific information, am I right? How is the address of boot parameters determined ("bd->bi_boot_params"). If speaking about Linux, it is defined in $(LINUX)/arch/arm/mach-xxx/Makefile.boot -- but how is it defined to be what it is? (3) can't yet figure out how CONFIG_BOOTARGS is pulled in. Somwhow it should get into board's information structure? Thanks in advance for comments. -- Roman Mashak

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[U-Boot] [PATCH v2] i.MX31: switch to CFG_HZ=1000
by Guennadi Liakhovetski 25 Sep '08

25 Sep '08

Switch to the standard CFG_HZ=1000 value, while at it, minor white-space cleanup, remove CFG_CLKS_IN_HZ from config-headers. Tested on mx31ads, provides 2% or 0.4% precision depending on the CONFIG_MX31_TIMER_HIGH_PRECISION flag. Measured with stop-watch on 100s boot-delay. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- On Jean-Christophe's request: rebased against current top-of-tree, no changes since the previous changes otherwise, still, I decided to count the version up to make it easier to distinguish them... diff --git a/cpu/arm1136/mx31/interrupts.c b/cpu/arm1136/mx31/interrupts.c index 6e08c71..22f397a 100644 --- a/cpu/arm1136/mx31/interrupts.c +++ b/cpu/arm1136/mx31/interrupts.c @@ -27,30 +27,49 @@ #define TIMER_BASE 0x53f90000 /* General purpose timer 1 */ /* General purpose timers registers */ -#define GPTCR __REG(TIMER_BASE) /* Control register */ -#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ -#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ -#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ +#define GPTCR __REG(TIMER_BASE) /* Control register */ +#define GPTPR __REG(TIMER_BASE + 0x4) /* Prescaler register */ +#define GPTSR __REG(TIMER_BASE + 0x8) /* Status register */ +#define GPTCNT __REG(TIMER_BASE + 0x24) /* Counter register */ /* General purpose timers bitfields */ -#define GPTCR_SWR (1<<15) /* Software reset */ -#define GPTCR_FRR (1<<9) /* Freerun / restart */ -#define GPTCR_CLKSOURCE_32 (4<<6) /* Clock source */ -#define GPTCR_TEN (1) /* Timer enable */ +#define GPTCR_SWR (1 << 15) /* Software reset */ +#define GPTCR_FRR (1 << 9) /* Freerun / restart */ +#define GPTCR_CLKSOURCE_32 (4 << 6) /* Clock source */ +#define GPTCR_TEN 1 /* Timer enable */ + +/* "time" is measured in 1 / CFG_HZ seconds, "tick" is internal timer period */ +#ifdef CONFIG_MX31_TIMER_HIGH_PRECISION +/* ~0.4% error - measured with stop-watch on 100s boot-delay */ +#define TICK_TO_TIME(t) ((t) * CFG_HZ / CONFIG_MX31_CLK32) +#define TIME_TO_TICK(t) ((unsigned long long)(t) * CONFIG_MX31_CLK32 / CFG_HZ) +#define US_TO_TICK(t) (((unsigned long long)(t) * CONFIG_MX31_CLK32 + \ + 999999) / 1000000) +#else +/* ~2% error */ +#define TICK_PER_TIME ((CONFIG_MX31_CLK32 + CFG_HZ / 2) / CFG_HZ) +#define US_PER_TICK (1000000 / CONFIG_MX31_CLK32) +#define TICK_TO_TIME(t) ((t) / TICK_PER_TIME) +#define TIME_TO_TICK(t) ((unsigned long long)(t) * TICK_PER_TIME) +#define US_TO_TICK(t) (((t) + US_PER_TICK - 1) / US_PER_TICK) +#endif static ulong timestamp; static ulong lastinc; /* nothing really to do with interrupts, just starts up a counter. */ +/* The 32768Hz 32-bit timer overruns in 131072 seconds */ int interrupt_init (void) { int i; /* setup GP Timer 1 */ GPTCR = GPTCR_SWR; - for ( i=0; i<100; i++) GPTCR = 0; /* We have no udelay by now */ + for (i = 0; i < 100; i++) + GPTCR = 0; /* We have no udelay by now */ GPTPR = 0; /* 32Khz */ - GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; /* Freerun Mode, PERCLK1 input */ + /* Freerun Mode, PERCLK1 input */ + GPTCR |= GPTCR_CLKSOURCE_32 | GPTCR_TEN; return 0; } @@ -67,7 +86,7 @@ void reset_timer(void) reset_timer_masked(); } -ulong get_timer_masked (void) +unsigned long long get_ticks (void) { ulong now = GPTCNT; /* current tick value */ @@ -80,6 +99,17 @@ ulong get_timer_masked (void) return timestamp; } +ulong get_timer_masked (void) +{ + /* + * get_ticks() returns a long long (64 bit), it wraps in + * 2^64 / CONFIG_MX31_CLK32 = 2^64 / 2^15 = 2^49 ~ 5 * 10^14 (s) ~ + * 5 * 10^9 days... and get_ticks() * CFG_HZ wraps in + * 5 * 10^6 days - long enough. + */ + return TICK_TO_TIME(get_ticks()); +} + ulong get_timer (ulong base) { return get_timer_masked () - base; @@ -87,29 +117,20 @@ ulong get_timer (ulong base) void set_timer (ulong t) { + timestamp = TIME_TO_TICK(t); } /* delay x useconds AND perserve advance timstamp value */ void udelay (unsigned long usec) { - ulong tmo, tmp; - - if (usec >= 1000) { /* if "big" number, spread normalization to seconds */ - tmo = usec / 1000; /* start to normalize for usec to ticks per sec */ - tmo *= CFG_HZ; /* find number of "ticks" to wait to achieve target */ - tmo /= 1000; /* finish normalize. */ - } else { /* else small number, don't kill it prior to HZ multiply */ - tmo = usec * CFG_HZ; - tmo /= (1000*1000); - } - - tmp = get_timer (0); /* get current timestamp */ - if ( (tmo + tmp + 1) < tmp )/* if setting this forward will roll time stamp */ - reset_timer_masked (); /* reset "advancing" timestamp to 0, set lastinc value */ - else - tmo += tmp; /* else, set advancing stamp wake up time */ - while (get_timer_masked () < tmo)/* loop till event */ - /*NOP*/; + unsigned long long tmp; + ulong tmo; + + tmo = US_TO_TICK(usec); + tmp = get_ticks() + tmo; /* get current timestamp */ + + while (get_ticks() < tmp) /* loop till event */ + /*NOP*/; } void reset_cpu (ulong addr) diff --git a/include/configs/imx31_litekit.h b/include/configs/imx31_litekit.h index 60916b9..9a655aa 100644 --- a/include/configs/imx31_litekit.h +++ b/include/configs/imx31_litekit.h @@ -122,11 +122,9 @@ #define CFG_MEMTEST_START 0 /* memtest works on */ #define CFG_MEMTEST_END 0x10000 -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CFG_LOAD_ADDR 0 /* default load address */ -#define CFG_HZ 32000 +#define CFG_HZ 1000 #define CONFIG_CMDLINE_EDITING 1 diff --git a/include/configs/imx31_phycore.h b/include/configs/imx31_phycore.h index bf2a8dd..1540203 100644 --- a/include/configs/imx31_phycore.h +++ b/include/configs/imx31_phycore.h @@ -126,7 +126,7 @@ #define CFG_LOAD_ADDR 0 /* default load address */ -#define CFG_HZ 32000 +#define CFG_HZ 1000 #define CONFIG_CMDLINE_EDITING 1 diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h index b904d81..04790fd 100644 --- a/include/configs/mx31ads.h +++ b/include/configs/mx31ads.h @@ -139,11 +139,9 @@ #define CFG_MEMTEST_START 0 /* memtest works on */ #define CFG_MEMTEST_END 0x10000 -#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ - #define CFG_LOAD_ADDR CONFIG_LOADADDR -#define CFG_HZ CONFIG_MX31_CLK32 /* use 32kHz clock as source */ +#define CFG_HZ 1000 #define CONFIG_CMDLINE_EDITING 1

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[U-Boot] I2C source clock frequency on MPC8544
by Wolfgang Grandegger 25 Sep '08

25 Sep '08

Hello, the I2C source clock frequency for the MPC8544 is determined in cpu/mpc85xx/speed.c: #elif defined(CONFIG_MPC8544) /* * On the 8544, the I2C clock is the same as the SEC clock. This can be * either CCB/2 or CCB/3, depending on the value of cfg_sec_freq. See * 4.4.3.3 of the 8544 RM. Note that this might actually work for all * 85xx, but only the 8544 has cfg_sec_freq, so it's unknown if the * PORDEVSR2_SEC_CFG bit is 0 on all 85xx boards that are not an 8544. */ if (gur->pordevsr2 & MPC85xx_PORDEVSR2_SEC_CFG) gd->i2c1_clk = sys_info.freqSystemBus / 3; else gd->i2c1_clk = sys_info.freqSystemBus / 2; On our MPC8544 the MPC85xx_PORDEVSR2_SEC_CFG is set and the diver 3 therefore used. But that seems to be wrong. Measurements show, that the used divider is 2. Any idea what's going wrong? Is there an errata for the MPC8544? Wolfgang.

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