August 2008 - U-Boot

[U-Boot-Users] [PATCH] rtl8169: add support for RTL8110SCL
by Yoshihiro Shimoda 19 Aug '08

19 Aug '08

This patch fixes a problem that RTL8110SCL started transfer with an incorrect memory address. Signed-off-by: Yoshihiro Shimoda <shimoda.yoshihiro(a)renesas.com> --- drivers/net/rtl8169.c | 28 ++++++++++++++++++++++------ 1 files changed, 22 insertions(+), 6 deletions(-) diff --git a/drivers/net/rtl8169.c b/drivers/net/rtl8169.c index 7423bc0..b57219e 100644 --- a/drivers/net/rtl8169.c +++ b/drivers/net/rtl8169.c @@ -112,8 +112,10 @@ static int media[MAX_UNITS] = { -1, -1, -1, -1, -1, -1, -1, -1 }; enum RTL8169_registers { MAC0 = 0, /* Ethernet hardware address. */ MAR0 = 8, /* Multicast filter. */ - TxDescStartAddr = 0x20, - TxHDescStartAddr = 0x28, + TxDescStartAddrLow = 0x20, + TxDescStartAddrHigh = 0x24, + TxHDescStartAddrLow = 0x28, + TxHDescStartAddrHigh = 0x2c, FLASH = 0x30, ERSR = 0x36, ChipCmd = 0x37, @@ -138,7 +140,8 @@ enum RTL8169_registers { PHYstatus = 0x6C, RxMaxSize = 0xDA, CPlusCmd = 0xE0, - RxDescStartAddr = 0xE4, + RxDescStartAddrLow = 0xE4, + RxDescStartAddrHigh = 0xE8, EarlyTxThres = 0xEC, FuncEvent = 0xF0, FuncEventMask = 0xF4, @@ -478,6 +481,7 @@ static int rtl_send(struct eth_device *dev, volatile void *packet, int length) while (len < ETH_ZLEN) ptxb[len++] = '\0'; + tpc->TxDescArray[entry].buf_Haddr = 0; tpc->TxDescArray[entry].buf_addr = cpu_to_le32((unsigned long)ptxb); if (entry != (NUM_TX_DESC - 1)) { tpc->TxDescArray[entry].status = @@ -558,7 +562,11 @@ static void rtl8169_hw_start(struct eth_device *dev) #endif RTL_W8(Cfg9346, Cfg9346_Unlock); - RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + + /* RTL-8169sb/8110sb or previous version */ + if (tpc->chipset <= 5) + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + RTL_W8(EarlyTxThres, EarlyTxThld); /* For gigabit rtl8169 */ @@ -576,8 +584,15 @@ static void rtl8169_hw_start(struct eth_device *dev) tpc->cur_rx = 0; - RTL_W32(TxDescStartAddr, (unsigned long)tpc->TxDescArray); - RTL_W32(RxDescStartAddr, (unsigned long)tpc->RxDescArray); + RTL_W32(TxDescStartAddrLow, (unsigned long)tpc->TxDescArray); + RTL_W32(TxDescStartAddrHigh, (unsigned long)0); + RTL_W32(RxDescStartAddrLow, (unsigned long)tpc->RxDescArray); + RTL_W32(RxDescStartAddrHigh, (unsigned long)0); + + /* RTL-8169sc/8110sc or later version */ + if (tpc->chipset > 5) + RTL_W8(ChipCmd, CmdTxEnb | CmdRxEnb); + RTL_W8(Cfg9346, Cfg9346_Lock); udelay(10); @@ -737,6 +752,7 @@ static int rtl_init(struct eth_device *dev, bd_t *bis) bis->bi_enetaddr[i] = dev->enetaddr[i] = RTL_R8(MAC0 + i); #ifdef DEBUG_RTL8169 + printf("chipset = %d\n", tpc->chipset); printf("MAC Address"); for (i = 0; i < MAC_ADDR_LEN; i++) printf(":%02x", dev->enetaddr[i]);

2 2

[U-Boot-Users] [PATCH v4] Add MIMC200 board
by Mark Jackson 19 Aug '08

19 Aug '08

The MIMC200 board is based on Atmel's NGW100 dev kit, but with an extra 8MByte FLASH and 128KByte FRAM. --- CREDITS | 4 + MAINTAINERS | 4 + MAKEALL | 1 + Makefile | 3 + board/mimc/mimc200/Makefile | 40 ++++++++ board/mimc/mimc200/config.mk | 3 + board/mimc/mimc200/mimc200.c | 209 +++++++++++++++++++++++++++++++++++++++++ board/mimc/mimc200/u-boot.lds | 73 ++++++++++++++ include/configs/mimc200.h | 177 ++++++++++++++++++++++++++++++++++ 10 files changed, 519 insertions(+), 0 deletions(-) diff --git a/CREDITS b/CREDITS index 2b0dab7..5010c78 100644 --- a/CREDITS +++ b/CREDITS @@ -217,6 +217,10 @@ H: Rich Ireland E: r.ireland(a)computer.org D: FPGA device configuration driver +H: Mark Jackson +E: mpfj(a)mimc.co.uk +D: Port to MIMC200 board + N: Gary Jennejohn E: garyj(a)jennejohn.org, gj(a)denx.de D: Support for Samsung ARM920T S3C2400X, ARM920T "TRAB" diff --git a/MAINTAINERS b/MAINTAINERS index cbe5c47..d4f6639 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -709,6 +709,10 @@ Haavard Skinnemoen <hskinnemoen(a)atmel.com> ATSTK1006 AT32AP7000 ATNGW100 AT32AP7000 +Mark Jackson <mpfj(a)mimc.co.uk> + + MIMC200 AT32AP7000 + ######################################################################### # SuperH Systems: # # # diff --git a/MAKEALL b/MAKEALL index c1a9c60..cfd376c 100755 --- a/MAKEALL +++ b/MAKEALL @@ -715,6 +715,7 @@ LIST_avr32=" \ atstk1004 \ atstk1006 \ atngw100 \ + mimc200 \ " ######################################################################### diff --git a/Makefile b/Makefile index 369bbd7..d434ea3 100644 --- a/Makefile +++ b/Makefile @@ -2914,6 +2914,9 @@ atstk1004_config : unconfig atstk1006_config : unconfig @$(MKCONFIG) $(@:_config=) avr32 at32ap atstk1000 atmel at32ap700x +mimc200_config : unconfig + @$(MKCONFIG) $(@:_config=) avr32 at32ap mimc200 mimc at32ap700x + #======================================================================== # SH3 (SuperH) #======================================================================== diff --git a/board/mimc/mimc200/Makefile b/board/mimc/mimc200/Makefile new file mode 100644 index 0000000..9f3849f --- /dev/null +++ b/board/mimc/mimc200/Makefile @@ -0,0 +1,40 @@ +# +# Copyright (C) 2005-2006 Atmel Corporation +# +# See file CREDITS for list of people who contributed to this project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA + +include $(TOPDIR)/config.mk + +LIB := $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/mimc/mimc200/config.mk b/board/mimc/mimc200/config.mk new file mode 100644 index 0000000..9a794e5 --- /dev/null +++ b/board/mimc/mimc200/config.mk @@ -0,0 +1,3 @@ +TEXT_BASE = 0x00000000 +PLATFORM_RELFLAGS += -ffunction-sections -fdata-sections +PLATFORM_LDFLAGS += --gc-sections diff --git a/board/mimc/mimc200/mimc200.c b/board/mimc/mimc200/mimc200.c new file mode 100644 index 0000000..089fc6c --- /dev/null +++ b/board/mimc/mimc200/mimc200.c @@ -0,0 +1,209 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <common.h> + +#include <asm/io.h> +#include <asm/sdram.h> +#include <asm/arch/clk.h> +#include <asm/arch/gpio.h> +#include <asm/arch/hmatrix.h> +#include <lcd.h> + +#define SM_PM_GCCTRL 0x0060 + +DECLARE_GLOBAL_DATA_PTR; + +static const struct sdram_config sdram_config = { + .data_bits = SDRAM_DATA_16BIT, + .row_bits = 13, + .col_bits = 9, + .bank_bits = 2, + .cas = 3, + .twr = 2, + .trc = 6, + .trp = 2, + .trcd = 2, + .tras = 6, + .txsr = 6, + /* 15.6 us */ + .refresh_period = (156 * (SDRAMC_BUS_HZ / 1000)) / 10000, +}; + +int board_early_init_f(void) +{ + /* Enable SDRAM in the EBI mux */ + hmatrix_slave_write(EBI, SFR, HMATRIX_BIT(EBI_SDRAM_ENABLE)); + + gpio_enable_ebi(); + gpio_enable_usart1(); + + /* enable higher address lines for larger flash devices */ + gpio_select_periph_A(GPIO_PIN_PE16, 0); /* ADDR23 */ + gpio_select_periph_A(GPIO_PIN_PE17, 0); /* ADDR24 */ + gpio_select_periph_A(GPIO_PIN_PE18, 0); /* ADDR25 */ + + /* enable data flash chip select */ + gpio_select_periph_A(GPIO_PIN_PE25, 0); /* NCS2 */ + + /* de-assert "force sys reset" pin */ + gpio_set_value(GPIO_PIN_PD15, 1); /* FORCE RESET */ + gpio_select_pio(GPIO_PIN_PD15, GPIOF_OUTPUT); + + /* init custom i/o */ + /* cpu type inputs */ + gpio_select_pio(GPIO_PIN_PE19, 0); + gpio_select_pio(GPIO_PIN_PE20, 0); + gpio_select_pio(GPIO_PIN_PE23, 0); + /* main board type inputs */ + gpio_select_pio(GPIO_PIN_PB19, 0); + gpio_select_pio(GPIO_PIN_PB29, 0); + /* DEBUG input (use weak pullup) */ + gpio_select_pio(GPIO_PIN_PE21, GPIOF_PULLUP); + + /* are we suppressing the console ? */ + if (gpio_get_value(GPIO_PIN_PE21) == 1) + { + gd->flags |= GD_FLG_SILENT; + } + + /* reset phys */ + gpio_select_pio(GPIO_PIN_PE24, 0); + gpio_set_value(GPIO_PIN_PC18, 1); /* PHY RESET */ + gpio_select_pio(GPIO_PIN_PC18, GPIOF_OUTPUT); + + /* GCLK0 - 10MHz clock */ + writel(0x00000004, (void *)SM_BASE + SM_PM_GCCTRL); + gpio_select_periph_A(GPIO_PIN_PA30, 0); + + udelay(5000); + + /* release phys reset */ + gpio_set_value(GPIO_PIN_PC18, 0); /* PHY RESET (Release) */ + +#if defined(CONFIG_MACB) + /* init macb0 pins */ + gpio_select_periph_A(GPIO_PIN_PC3, 0); /* TXD0 */ + gpio_select_periph_A(GPIO_PIN_PC4, 0); /* TXD1 */ + gpio_select_periph_A(GPIO_PIN_PC7, 0); /* TXEN */ + gpio_select_periph_A(GPIO_PIN_PC8, 0); /* TXCK */ + gpio_select_periph_A(GPIO_PIN_PC9, 0); /* RXD0 */ + gpio_select_periph_A(GPIO_PIN_PC10, 0); /* RXD1 */ + gpio_select_periph_A(GPIO_PIN_PC13, 0); /* RXER */ + gpio_select_periph_A(GPIO_PIN_PC15, 0); /* RXDV */ + gpio_select_periph_A(GPIO_PIN_PC16, 0); /* MDC */ + gpio_select_periph_A(GPIO_PIN_PC17, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_A(GPIO_PIN_PC0, 0); /* COL */ + gpio_select_periph_A(GPIO_PIN_PC1, 0); /* CRS */ + gpio_select_periph_A(GPIO_PIN_PC2, 0); /* TXER */ + gpio_select_periph_A(GPIO_PIN_PC5, 0); /* TXD2 */ + gpio_select_periph_A(GPIO_PIN_PC6, 0); /* TXD3 */ + gpio_select_periph_A(GPIO_PIN_PC11, 0); /* RXD2 */ + gpio_select_periph_A(GPIO_PIN_PC12, 0); /* RXD3 */ + gpio_select_periph_A(GPIO_PIN_PC14, 0); /* RXCK */ +#endif + + /* init macb1 pins */ + gpio_select_periph_B(GPIO_PIN_PD13, 0); /* TXD0 */ + gpio_select_periph_B(GPIO_PIN_PD14, 0); /* TXD1 */ + gpio_select_periph_B(GPIO_PIN_PD11, 0); /* TXEN */ + gpio_select_periph_B(GPIO_PIN_PD12, 0); /* TXCK */ + gpio_select_periph_B(GPIO_PIN_PD10, 0); /* RXD0 */ + gpio_select_periph_B(GPIO_PIN_PD6, 0); /* RXD1 */ + gpio_select_periph_B(GPIO_PIN_PD5, 0); /* RXER */ + gpio_select_periph_B(GPIO_PIN_PD4, 0); /* RXDV */ + gpio_select_periph_B(GPIO_PIN_PD3, 0); /* MDC */ + gpio_select_periph_B(GPIO_PIN_PD2, 0); /* MDIO */ +#if !defined(CONFIG_RMII) + gpio_select_periph_B(GPIO_PIN_PC19, 0); /* COL */ + gpio_select_periph_B(GPIO_PIN_PC23, 0); /* CRS */ + gpio_select_periph_B(GPIO_PIN_PC26, 0); /* TXER */ + gpio_select_periph_B(GPIO_PIN_PC27, 0); /* TXD2 */ + gpio_select_periph_B(GPIO_PIN_PC28, 0); /* TXD3 */ + gpio_select_periph_B(GPIO_PIN_PC29, 0); /* RXD2 */ + gpio_select_periph_B(GPIO_PIN_PC30, 0); /* RXD3 */ + gpio_select_periph_B(GPIO_PIN_PC24, 0); /* RXCK */ +#endif +#endif + +#if defined(CONFIG_MMC) + gpio_enable_mmci(); +#endif + + return 0; +} + +phys_size_t initdram(int board_type) +{ + unsigned long expected_size; + unsigned long actual_size; + void *sdram_base; + + sdram_base = map_physmem(EBI_SDRAM_BASE, EBI_SDRAM_SIZE, MAP_NOCACHE); + + expected_size = sdram_init(sdram_base, &sdram_config); + actual_size = get_ram_size(sdram_base, expected_size); + + unmap_physmem(sdram_base, EBI_SDRAM_SIZE); + + if (expected_size != actual_size) + printf("Warning: Only %lu of %lu MiB SDRAM is working\n", + actual_size >> 20, expected_size >> 20); + + return actual_size; +} + +void board_init_info(void) +{ + gd->bd->bi_phy_id[0] = 0x01; + gd->bd->bi_phy_id[1] = 0x03; +} + +/* SPI chip select control */ +#ifdef CONFIG_ATMEL_SPI +#include <spi.h> + +int spi_cs_is_valid(unsigned int bus, unsigned int cs) +{ + return (bus == 0) && (cs == 0); +} + +void spi_cs_activate(struct spi_slave *slave) +{ +} + +void spi_cs_deactivate(struct spi_slave *slave) +{ +} +#endif /* CONFIG_ATMEL_SPI */ + +#ifdef CONFIG_CMD_NET +extern int macb_eth_initialize(int id, void *regs, unsigned int phy_addr); + +int board_eth_init(bd_t *bi) +{ + macb_eth_initialize(0, (void *)MACB0_BASE, bi->bi_phy_id[0]); + macb_eth_initialize(1, (void *)MACB1_BASE, bi->bi_phy_id[1]); + + return 0; +} +#endif diff --git a/board/mimc/mimc200/u-boot.lds b/board/mimc/mimc200/u-boot.lds new file mode 100644 index 0000000..e736adf --- /dev/null +++ b/board/mimc/mimc200/u-boot.lds @@ -0,0 +1,73 @@ +/* -*- Fundamental -*- + * + * Copyright (C) 2005-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +OUTPUT_FORMAT("elf32-avr32", "elf32-avr32", "elf32-avr32") +OUTPUT_ARCH(avr32) +ENTRY(_start) + +SECTIONS +{ + . = 0; + _text = .; + .text : { + *(.exception.text) + *(.text) + *(.text.*) + } + _etext = .; + + .rodata : { + *(.rodata) + *(.rodata.*) + } + + . = ALIGN(8); + _data = .; + .data : { + *(.data) + *(.data.*) + } + + . = ALIGN(4); + __u_boot_cmd_start = .; + .u_boot_cmd : { + KEEP(*(.u_boot_cmd)) + } + __u_boot_cmd_end = .; + + . = ALIGN(4); + _got = .; + .got : { + *(.got) + } + _egot = .; + + . = ALIGN(8); + _edata = .; + + .bss : { + *(.bss) + *(.bss.*) + } + . = ALIGN(8); + _end = .; +} diff --git a/include/configs/mimc200.h b/include/configs/mimc200.h new file mode 100644 index 0000000..3486be0 --- /dev/null +++ b/include/configs/mimc200.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2006 Atmel Corporation + * + * Configuration settings for the AVR32 Network Gateway + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/memory-map.h> + +#define CONFIG_AVR32 1 +#define CONFIG_AT32AP 1 +#define CONFIG_AT32AP7000 1 +#define CONFIG_MIMC200 1 + +#define CONFIG_MIMC200_EXT_FLASH 1 + +#define CFG_HZ 1000 + +/* + * Set up the PLL to run at 140 MHz, the CPU to run at the PLL + * frequency, the HSB and PBB busses to run at 1/2 the PLL frequency + * and the PBA bus to run at 1/4 the PLL frequency. + */ +#define CONFIG_PLL 1 +#define CFG_POWER_MANAGER 1 +#define CFG_OSC0_HZ 10000000 +#define CFG_PLL0_DIV 1 +#define CFG_PLL0_MUL 15 +#define CFG_PLL0_SUPPRESS_CYCLES 16 +#define CFG_CLKDIV_CPU 0 +#define CFG_CLKDIV_HSB 1 +#define CFG_CLKDIV_PBA 2 +#define CFG_CLKDIV_PBB 1 + +/* + * The PLLOPT register controls the PLL like this: + * icp = PLLOPT<2> + * ivco = PLLOPT<1:0> + * + * We want icp=1 (default) and ivco=0 (80-160 MHz) or ivco=2 (150-240MHz). + */ +#define CFG_PLL0_OPT 0x04 + +#define CONFIG_USART1 1 +#define CONFIG_MIMC200_DBGLINK 1 + +/* User serviceable stuff */ +#define CONFIG_DOS_PARTITION 1 + +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#define CONFIG_STACKSIZE (2048) + +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTARGS \ + "console=ttyS0 root=/dev/mtdblock1 fbmem=600k rootfstype=jffs2" +#define CONFIG_BOOTCOMMAND \ + "fsload; bootm" + +#define CONFIG_SILENT_CONSOLE 1 /* enable silent startup */ +#define CONFIG_SILENT_CONSOLE_INPUT 1 /* disable console inputs */ +#define CFG_DEVICE_NULLDEV 1 /* include nulldev device */ + +/* + * Only interrupt autoboot if <space> is pressed. Otherwise, garbage + * data on the serial line may interrupt the boot sequence. + */ +#define CONFIG_BOOTDELAY 0 +#define CONFIG_ZERO_BOOTDELAY_CHECK 1 +#define CONFIG_AUTOBOOT 1 + +/* + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. + */ +#define CONFIG_OVERWRITE_ETHADDR_ONCE 1 +#define CONFIG_NET_MULTI 1 + +/* + * BOOTP/DHCP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY + +#define CONFIG_DOS_PARTITION 1 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_FAT +#define CONFIG_CMD_JFFS2 +#define CONFIG_CMD_MMC +#define CONFIG_CMD_NET + +#define CONFIG_ATMEL_USART 1 +#define CONFIG_MACB 1 +#define CONFIG_PIO2 1 +#define CFG_NR_PIOS 5 +#define CFG_HSDRAMC 1 +#define CONFIG_MMC 1 +#define CONFIG_ATMEL_MCI 1 + +#define CFG_DCACHE_LINESZ 32 +#define CFG_ICACHE_LINESZ 32 + +#define CONFIG_NR_DRAM_BANKS 1 + +#define CFG_FLASH_CFI 1 +#define CFG_FLASH_CFI_DRIVER 1 + +#define CFG_FLASH_BASE 0x00000000 +#define CFG_FLASH_SIZE 0x800000 +#define CFG_MAX_FLASH_BANKS 1 +#define CFG_MAX_FLASH_SECT 135 + +#define CFG_MONITOR_BASE CFG_FLASH_BASE + +#define CFG_INTRAM_BASE INTERNAL_SRAM_BASE +#define CFG_INTRAM_SIZE INTERNAL_SRAM_SIZE +#define CFG_SDRAM_BASE EBI_SDRAM_BASE + +#define CFG_FRAM_BASE 0x08000000 +#define CFG_FRAM_SIZE 0x20000 + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 65536 +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_FLASH_SIZE - CFG_ENV_SIZE) + +#define CFG_INIT_SP_ADDR (CFG_INTRAM_BASE + CFG_INTRAM_SIZE) + +#define CFG_MALLOC_LEN (1024*1024) +#define CFG_DMA_ALLOC_LEN (16384) + +/* Allow 4MB for the kernel run-time image */ +#define CFG_LOAD_ADDR (EBI_SDRAM_BASE + 0x00400000) +#define CFG_BOOTPARAMS_LEN (16 * 1024) + +/* Other configuration settings that shouldn't have to change all that often */ +#define CFG_PROMPT "U-Boot> " +#define CFG_CBSIZE 256 +#define CFG_MAXARGS 16 +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_LONGHELP 1 + +#define CFG_MEMTEST_START EBI_SDRAM_BASE +#define CFG_MEMTEST_END (CFG_MEMTEST_START + 0x1f00000) + +#define CFG_BAUDRATE_TABLE { 115200, 38400, 19200, 9600, 2400 } + +#endif /* __CONFIG_H */

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Re: [U-Boot] ARM: net.c: UDP Checksum code failing every packet
by Ben Warren 19 Aug '08

19 Aug '08

Tom Evans wrote: > Ben Warren wrote: >> Tom Evans wrote: >>> Ben Warren wrote: >> number of steps: >> 1. $ git clone <repo> You've done this already >> 2. <edit/test> > > That's the bit I can't do. The u-boot distribution DOESN'T support our > hardware. I can only test it on our "variant" version of u-boot. > Right, but as you said, this block of code hasn't changed. Testing what you can, and posting a patch relative to top-of-tree is OK. >> 3. $ git commit -a -s (this assumes git knows your name and e-mail. > > 4. $ git format-patch origin > > I could change it in my version (which I have), paste the changes > untested into the official one then generate patches, but it's an > untested change. Yes and no. The code block is tested. > > It can be tested by anyone working from the official distribution, > turning CONFIG_UDP_CHECKSUM on for their board and then running tftp. > > Which isn't me. > If you post a good patch and it's pulled in, somebody will test this configuration. >> True, but you found the bug and made the fix. There's > > no way I'm going to post this patch without having the > > hardware to test it on. Others >> may, but it's better if you do it. > > I don't have the hardware. > > I think it is worth sending a summary of our discussion back to the > list (excluding the "I'm not meant to be doing this" bit). Have you > sent anything yet? Yes, my other response and this one are CC'd to the list, to be archived in perpetuity and looked at by an infinitesimally small number of people. :) cheers, Ben

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Re: [U-Boot] ARM: net.c: UDP Checksum code failing every packet
by Ben Warren 19 Aug '08

19 Aug '08

Tom Evans wrote: > Ben Warren wrote: >> Hi Tom, >> >> Tom Evans wrote: > >> ... >>> I'm afraid I can't generate a patch to do this. Could someone else >>> please incorporate this change if required? >>> >>> >> Everything seems logical until this point. Why can't you create a >> patch? > > Because I'm NOT working from a copy of the "official git archive". > > We've bought a package (u-boot, linux kernel and root filesystem) for > a CPU and board that isn't currently supported in u-boot. Our > suppliers aren't taking the time and effort required to feed the > changes back into the u-boot master copies, so I'm working from a > "non-branch" that is somewhat elderly. > > I've only just worked out how to fetch the current "master" using git, > just to see that this bug is still current. > > Besides which, I've never made a patch before, and couldn't find any > instructions on how to do so. > There is good documentation out there, just not where you looked. People are always glad to help in this area anyway. There are a small number of steps: 1. $ git clone <repo> You've done this already 2. <edit/test> 3. $ git commit -a -s (this assumes git knows your name and e-mail. That's easy to set up - the easiest is by editing the config file in the .git directory of your repository) 4. $ git format-patch origin 5. $ git send-email (preferred) or paste in e-mail You may find this helpful. I have: http://www.kernel.org/pub/software/scm/git/docs/everyday.html > Besides which, I'm not meant to be doing this (working on u-boot or > sending bug reports back) at all. > Well, but you are anyway, and we're thankful for that. I'm sure it's pointless, but you have a pretty good defense that your employer is getting a lot of sophisticated software for free, and all that's asked for in return are the legalities of the GPL and the softer concept of helping out when and if you can. > It is only six lines of code in one file. > True, but you found the bug and made the fix. There's no way I'm going to post this patch without having the hardware to test it on. Others may, but it's better if you do it. regards, Ben

1 0

[U-Boot] ARM: net.c: UDP Checksum code failing every packet
by Tom Evans 19 Aug '08

19 Aug '08

UDP Checksumming is enabled with the configuration variable CONFIG_UDP_CHECKSUM. This is only enabled in 7 out of 437 include/configs/*.h files. Enabling UDP checksumming can be useful, as it allows any errors (in downloading via TFTP) to be retried rather than resulting in an image CRC error when the whole download has finished. The download isn't meant to fail, but I'm seeing intermittent corrupted downloads currently. If CONFIG_UDP_CHECKSUM is enabled on an ARM core, and the CPU is prior to ARM Core Version 6, all packets are reported as having checksum errors. This is due to the ARM's 32-bit alignment requirements and the following four lines of code in net/net.c::NetReceive() xsum += (ntohl(ip->ip_src) >> 16) & 0x0000ffff; xsum += (ntohl(ip->ip_src) >> 0) & 0x0000ffff; xsum += (ntohl(ip->ip_dst) >> 16) & 0x0000ffff; xsum += (ntohl(ip->ip_dst) >> 0) & 0x0000ffff; The original Ethernet packet is (usually, this is not controlled) 32-bit aligned, the Ethernet header is 14 bytes long, so by design the aligned fields in the IP (and other) headers are all misaligned, at least with the NE2000 driver we're using. ARM (prior to V6) "silently corrupts" misaligned reads. For 32-bit reads offset by 16 bits it reads 32-bits from the aligned address two bytes below that requested, and then swaps the words. If the above lines are changed to match other related ARM-related modifications as follows, then the UDP checksum code works: tmp = NetReadIP(&ip->ip_src); xsum += (ntohl(tmp) >> 16) & 0x0000ffff; xsum += (ntohl(tmp) >> 0) & 0x0000ffff; tmp = NetReadIP(&ip->ip_dst); xsum += (ntohl(tmp) >> 16) & 0x0000ffff; xsum += (ntohl(tmp) >> 0) & 0x0000ffff; I'm afraid I can't generate a patch to do this. Could someone else please incorporate this change if required? ---- Tom Evans

2 1

[U-Boot-Users] [Part 2 of A PATCH SERIES for STLS]: Upate Makefile, MAKEALL and MAINTAINERS files in root directory!
by Ryan CHEN 19 Aug '08

19 Aug '08

Hi all, This is part 2 of a patch series for STLS. It will update Makefile, MAKEALL and MAINTAINERS files with STLS information! Signed-off-by: Ryan Chen <ryan.chen(a)st.com> diff --git a/MAINTAINERS b/MAINTAINERS old mode 100644 new mode 100755 index cbe5c47..acd931c --- a/MAINTAINERS +++ b/MAINTAINERS @@ -752,5 +752,16 @@ Blackfin Team <u-boot-devel(a)blackfin.uclinux.org> BF561-EZKIT BF561 ######################################################################### +# STLS Systems: # +# # +# Maintainer Name, Email Address # +# Board CPU # +######################################################################### + +Ryan Chen <ryan.chen(a)st.com> + + ST-STLS STLS + +######################################################################### # End of MAINTAINERS list # ######################################################################### diff --git a/MAKEALL b/MAKEALL index c1a9c60..3b82470 100755 --- a/MAKEALL +++ b/MAKEALL @@ -623,10 +623,15 @@ LIST_au1xx0_el=" \ pb1000 \ " +LIST_stls=" \ + stls \ +" + LIST_mips_el=" \ ${LIST_mips4kc_el} \ ${LIST_mips5kc_el} \ ${LIST_au1xx0_el} \ + ${LIST_stls} \ " ######################################################################### diff --git a/Makefile b/Makefile index 369bbd7..e851d5b 100644 --- a/Makefile +++ b/Makefile @@ -283,6 +283,9 @@ ALL += $(obj)u-boot.srec $(obj)u-boot.bin $(obj)System.map $(U_BOOT_NAND) $(U_BO ifeq ($(ARCH),blackfin) ALL += $(obj)u-boot.ldr endif +ifeq ($(CPU),stls) +ALL += u-boot-compressed +endif all: $(ALL) @@ -359,6 +362,11 @@ $(VERSION_FILE): ) > $@.tmp @cmp -s $@ $@.tmp && rm -f $@.tmp || mv -f $@.tmp $@ +ifeq ($(CPU),stls) +u-boot-compressed: $(obj)u-boot + $(MAKE) -C cpu/$(CPU)/bootstrap all +endif + gdbtools: $(MAKE) -C tools/gdb all || exit 1 @@ -2776,6 +2784,12 @@ qemu_mips_config : unconfig purple_config : unconfig @$(MKCONFIG) $(@:_config=) mips mips purple + +#======================================================================== +# STLS board +#======================================================================== +stls_config: unconfig + @$(MKCONFIG) $(@:_config=) mips stls stls st #======================================================================== # Nios Best Regards, Ryan Chen

2 2

Re: [U-Boot] Resubmit : [PATCH] Correct ARM Versatile TimerInitialization
by Gururaja Hebbar K R 19 Aug '08

19 Aug '08

Hi, Today I download u-boot-1.3.4 and checked drivers\rtc directory with u-boot-1.3.3\drivers\rtc . There is change in the files that this patch touches. So I think the same patch can be applied to u-boot-1.3.4 also. Kindly update me if any changes is needed Regards Gururaja

1 0

[U-Boot] [PATCH v2] fdt: rework fdt_fixup_ethernet() to use env instead of bd_t
by Kumar Gala 19 Aug '08

19 Aug '08

Move to using the environment variables 'ethaddr', 'eth1addr', etc.. instead of bd->bi_enetaddr, bi_enet1addr, etc. This makes the code a bit more flexible to the number of ethernet interfaces. Right now we assume a max of 10 interfaces. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Since we can support 10 interfaces and aren't coupled to the bd we can remove the conditionality of HAS_ETHn for fdt_fixup_ethernet. - k common/fdt_support.c | 69 ++++++++++++++++++++++--------------------------- cpu/74xx_7xx/cpu.c | 2 +- cpu/mpc512x/cpu.c | 2 +- cpu/mpc8260/cpu.c | 2 +- cpu/mpc83xx/fdt.c | 2 +- cpu/mpc85xx/fdt.c | 2 +- cpu/mpc86xx/fdt.c | 2 +- cpu/mpc8xx/fdt.c | 2 +- cpu/ppc4xx/fdt.c | 2 +- include/fdt_support.h | 2 +- 10 files changed, 40 insertions(+), 47 deletions(-) diff --git a/common/fdt_support.c b/common/fdt_support.c index 93b144e..b8f6fde 100644 --- a/common/fdt_support.c +++ b/common/fdt_support.c @@ -368,55 +368,48 @@ int fdt_fixup_memory(void *blob, u64 start, u64 size) return 0; } -#if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ - defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - -void fdt_fixup_ethernet(void *fdt, bd_t *bd) +#define CFG_MAX_NUM_ETH (10) +void fdt_fixup_ethernet(void *fdt) { + int i, j; int node; const char *path; node = fdt_path_offset(fdt, "/aliases"); if (node >= 0) { -#if defined(CONFIG_HAS_ETH0) - path = fdt_getprop(fdt, node, "ethernet0", NULL); - if (path) { - do_fixup_by_path(fdt, path, "mac-address", - bd->bi_enetaddr, 6, 0); - do_fixup_by_path(fdt, path, "local-mac-address", - bd->bi_enetaddr, 6, 1); - } -#endif -#if defined(CONFIG_HAS_ETH1) - path = fdt_getprop(fdt, node, "ethernet1", NULL); - if (path) { - do_fixup_by_path(fdt, path, "mac-address", - bd->bi_enet1addr, 6, 0); - do_fixup_by_path(fdt, path, "local-mac-address", - bd->bi_enet1addr, 6, 1); - } -#endif -#if defined(CONFIG_HAS_ETH2) - path = fdt_getprop(fdt, node, "ethernet2", NULL); - if (path) { - do_fixup_by_path(fdt, path, "mac-address", - bd->bi_enet2addr, 6, 0); - do_fixup_by_path(fdt, path, "local-mac-address", - bd->bi_enet2addr, 6, 1); - } -#endif -#if defined(CONFIG_HAS_ETH3) - path = fdt_getprop(fdt, node, "ethernet3", NULL); - if (path) { + char enet[12], mac[10], *tmp, *end; + unsigned char mac_addr[6]; + + for (i = 0; i < CFG_MAX_NUM_ETH; i++) { + sprintf(enet, "ethernet%d", i); + sprintf(mac, "eth%daddr",i); + + sprintf(mac, i ? "eth%daddr" : "ethaddr", i); + tmp = getenv(mac); + path = fdt_getprop(fdt, node, enet, NULL); + + if (!path) { + debug("No alias for %s\n", enet); + continue; + } + if (!tmp) { + debug("No environment variable for %s\n", mac); + continue; + } + + for (j = 0; j < 6; j++) { + mac_addr[j] = tmp ? simple_strtoul(tmp, &end, 16) : 0; + if (tmp) + tmp = (*end) ? end+1 : end; + } + do_fixup_by_path(fdt, path, "mac-address", - bd->bi_enet3addr, 6, 0); + &mac_addr, 6, 0); do_fixup_by_path(fdt, path, "local-mac-address", - bd->bi_enet3addr, 6, 1); + &mac_addr, 6, 1); } -#endif } } -#endif #ifdef CONFIG_HAS_FSL_DR_USB void fdt_fixup_dr_usb(void *blob, bd_t *bd) diff --git a/cpu/74xx_7xx/cpu.c b/cpu/74xx_7xx/cpu.c index ea43c9a..c007abc 100644 --- a/cpu/74xx_7xx/cpu.c +++ b/cpu/74xx_7xx/cpu.c @@ -314,7 +314,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); } #endif /* ------------------------------------------------------------------------- */ diff --git a/cpu/mpc512x/cpu.c b/cpu/mpc512x/cpu.c index 703e188..1f39ac4 100644 --- a/cpu/mpc512x/cpu.c +++ b/cpu/mpc512x/cpu.c @@ -191,7 +191,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif ft_clock_setup(blob, bd); #ifdef CONFIG_HAS_ETH0 - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); #endif } #endif diff --git a/cpu/mpc8260/cpu.c b/cpu/mpc8260/cpu.c index 4d5d141..efb8ed6 100644 --- a/cpu/mpc8260/cpu.c +++ b/cpu/mpc8260/cpu.c @@ -307,7 +307,7 @@ void ft_cpu_setup (void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); #endif do_fixup_by_path_u32(blob, cpu_path, "bus-frequency", bd->bi_busfreq, 1); diff --git a/cpu/mpc83xx/fdt.c b/cpu/mpc83xx/fdt.c index fda85c1..39bd9dc 100644 --- a/cpu/mpc83xx/fdt.c +++ b/cpu/mpc83xx/fdt.c @@ -53,7 +53,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index c159934..bc1550d 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -212,7 +212,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); #endif do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index 80a5c78..12d9052 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -25,7 +25,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) \ || defined(CONFIG_HAS_ETH2) || defined(CONFIG_HAS_ETH3) - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); #endif #ifdef CFG_NS16550 diff --git a/cpu/mpc8xx/fdt.c b/cpu/mpc8xx/fdt.c index 567094a..7130983 100644 --- a/cpu/mpc8xx/fdt.c +++ b/cpu/mpc8xx/fdt.c @@ -40,7 +40,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) gd->brg_clk, 1); /* Fixup ethernet MAC addresses */ - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); } diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 0323dc5..a97484f 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -130,7 +130,7 @@ void ft_cpu_setup(void *blob, bd_t *bd) * Fixup all ethernet nodes * Note: aliases in the dts are required for this */ - fdt_fixup_ethernet(blob, bd); + fdt_fixup_ethernet(blob); /* * Fixup all available PCIe nodes by setting the device_type property diff --git a/include/fdt_support.h b/include/fdt_support.h index a7c6326..f2f2cd5 100644 --- a/include/fdt_support.h +++ b/include/fdt_support.h @@ -45,7 +45,7 @@ void do_fixup_by_compat(void *fdt, const char *compat, void do_fixup_by_compat_u32(void *fdt, const char *compat, const char *prop, u32 val, int create); int fdt_fixup_memory(void *blob, u64 start, u64 size); -void fdt_fixup_ethernet(void *fdt, bd_t *bd); +void fdt_fixup_ethernet(void *fdt); int fdt_find_and_setprop(void *fdt, const char *node, const char *prop, const void *val, int len, int create); void fdt_fixup_qe_firmware(void *fdt); -- 1.5.5.1

4 8

[U-Boot] [PATCH] Fix OneNAND read_oob/write_oob functions compatability
by Kyungmin Park 19 Aug '08

19 Aug '08

Also sync with kernel OneNAND codes Thank you, Kyungmin Park Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index 5e2062b..8d87b78 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -85,15 +85,25 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong addr = simple_strtoul(argv[2], NULL, 16); ulong ofs = simple_strtoul(argv[3], NULL, 16); size_t len = simple_strtoul(argv[4], NULL, 16); - size_t retlen = 0; int oob = strncmp(argv[1], "read.oob", 8) ? 0 : 1; + struct mtd_oob_ops ops; + + ops.mode = MTD_OOB_PLACE; + + if (oob) { + ops.len = 0; + ops.datbuf = NULL; + ops.ooblen = len; + ops.oobbuf = (u_char *) addr; + } else { + ops.len = len; + ops.datbuf = (u_char *) addr; + ops.ooblen = 0; + ops.oobbuf = NULL; + } + ops.retlen = ops.oobretlen = 0; - if (oob) - onenand_read_oob(&onenand_mtd, ofs, len, - &retlen, (u_char *) addr); - else - onenand_read(&onenand_mtd, ofs, len, &retlen, - (u_char *) addr); + onenand_mtd.read_oob(&onenand_mtd, ofs, &ops); printf("Done\n"); return 0; @@ -117,9 +127,12 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) ulong block = simple_strtoul(argv[3], NULL, 10); ulong page = simple_strtoul(argv[4], NULL, 10); size_t len = simple_strtol(argv[5], NULL, 10); - size_t retlen = 0; ulong ofs; int oob = strncmp(argv[1], "block.oob", 9) ? 0 : 1; + struct mtd_oob_ops ops; + + ops.mode = MTD_OOB_PLACE; + ofs = block << onenand_chip.erase_shift; if (page) @@ -127,17 +140,21 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) if (!len) { if (oob) - len = 64; + ops.ooblen = 64; else - len = 512; + ops.len = 512; + } + + if (oob) { + ops.datbuf = NULL; + ops.oobbuf = (u_char *) addr; + } else { + ops.datbuf = (u_char *) addr; + ops.oobbuf = NULL; } + ops.retlen = ops.oobretlen = 0; - if (oob) - onenand_read_oob(&onenand_mtd, ofs, len, - &retlen, (u_char *) addr); - else - onenand_read(&onenand_mtd, ofs, len, &retlen, - (u_char *) addr); + onenand_read_oob(&onenand_mtd, ofs, &ops); return 0; } diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 9ce68e1..d14586d 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -526,83 +526,269 @@ static void onenand_release_device(struct mtd_info *mtd) } /** - * onenand_read_ecc - [MTD Interface] Read data with ECC + * onenand_transfer_auto_oob - [Internal] oob auto-placement transfer + * @param mtd MTD device structure + * @param buf destination address + * @param column oob offset to read from + * @param thislen oob length to read + */ +static int onenand_transfer_auto_oob(struct mtd_info *mtd, uint8_t *buf, + int column, int thislen) +{ + struct onenand_chip *this = mtd->priv; + struct nand_oobfree *free; + int readcol = column; + int readend = column + thislen; + int lastgap = 0; + unsigned int i; + uint8_t *oob_buf = this->oob_buf; + + free = this->ecclayout->oobfree; + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + if (readcol >= lastgap) + readcol += free->offset - lastgap; + if (readend >= lastgap) + readend += free->offset - lastgap; + lastgap = free->offset + free->length; + } + this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); + free = this->ecclayout->oobfree; + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + int free_end = free->offset + free->length; + if (free->offset < readend && free_end > readcol) { + int st = max_t(int,free->offset,readcol); + int ed = min_t(int,free_end,readend); + int n = ed - st; + memcpy(buf, oob_buf + st, n); + buf += n; + } else if (column == 0) + break; + } + return 0; +} + +/** + * onenand_read_ops_nolock - [OneNAND Interface] OneNAND read main and/or out-of-band * @param mtd MTD device structure * @param from offset to read from - * @param len number of bytes to read - * @param retlen pointer to variable to store the number of read bytes - * @param buf the databuffer to put data - * @param oob_buf filesystem supplied oob data buffer - * @param oobsel oob selection structure + * @param ops oob operation description structure * - * OneNAND read with ECC + * OneNAND read main and/or out-of-band data */ -static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, - size_t * retlen, u_char * buf, - u_char * oob_buf, struct nand_oobinfo *oobsel) +static int onenand_read_ops_nolock(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops) { struct onenand_chip *this = mtd->priv; - int read = 0, column; - int thislen; - int ret = 0; + struct mtd_ecc_stats stats; + size_t len = ops->len; + size_t ooblen = ops->ooblen; + u_char *buf = ops->datbuf; + u_char *oobbuf = ops->oobbuf; + int read = 0, column, thislen; + int oobread = 0, oobcolumn, thisooblen, oobsize; + int ret = 0, boundary = 0; + int writesize = this->writesize; + + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_ops_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + if (ops->mode == MTD_OOB_AUTO) + oobsize = this->ecclayout->oobavail; + else + oobsize = mtd->oobsize; - MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_read_ecc: " - "from = 0x%08x, len = %i\n", - (unsigned int)from, (int)len); + oobcolumn = from & (mtd->oobsize - 1); /* Do not allow reads past end of device */ if ((from + len) > mtd->size) { - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_read_ecc: " - "Attempt read beyond end of device\n"); - *retlen = 0; + printk(KERN_ERR "onenand_read_ops_nolock: Attempt read beyond end of device\n"); + ops->retlen = 0; + ops->oobretlen = 0; return -EINVAL; } - /* Grab the lock and see if the device is available */ - onenand_get_device(mtd, FL_READING); - - while (read < len) { - thislen = min_t(int, mtd->writesize, len - read); + stats = mtd->ecc_stats; - column = from & (mtd->writesize - 1); - if (column + thislen > mtd->writesize) - thislen = mtd->writesize - column; + /* Read-while-load method */ + /* Do first load to bufferRAM */ + if (read < len) { if (!onenand_check_bufferram(mtd, from)) { - this->command(mtd, ONENAND_CMD_READ, from, - mtd->writesize); + this->command(mtd, ONENAND_CMD_READ, from, writesize); ret = this->wait(mtd, FL_READING); - /* First copy data and check return value for ECC handling */ - onenand_update_bufferram(mtd, from, 1); + onenand_update_bufferram(mtd, from, !ret); + if (ret == -EBADMSG) + ret = 0; } + } - this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, - thislen); + thislen = min_t(int, writesize, len - read); + column = from & (writesize - 1); + if (column + thislen > writesize) + thislen = writesize - column; - read += thislen; - if (read == len) - break; + while (!ret) { + /* If there is more to load then start next load */ + from += thislen; + if (read + thislen < len) { + this->command(mtd, ONENAND_CMD_READ, from, writesize); + /* + * Chip boundary handling in DDP + * Now we issued chip 1 read and pointed chip 1 + * bufferam so we have to point chip 0 bufferam. + */ + if (ONENAND_IS_DDP(this) && + unlikely(from == (this->chipsize >> 1))) { + this->write_word(ONENAND_DDP_CHIP0, this->base + ONENAND_REG_START_ADDRESS2); + boundary = 1; + } else + boundary = 0; + ONENAND_SET_PREV_BUFFERRAM(this); + } - if (ret) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_read_ecc: read failed = %d\n", ret); - break; + /* While load is going, read from last bufferRAM */ + this->read_bufferram(mtd, ONENAND_DATARAM, buf, column, thislen); + + /* Read oob area if needed */ + if (oobbuf) { + thisooblen = oobsize - oobcolumn; + thisooblen = min_t(int, thisooblen, ooblen - oobread); + + if (ops->mode == MTD_OOB_AUTO) + onenand_transfer_auto_oob(mtd, oobbuf, oobcolumn, thisooblen); + else + this->read_bufferram(mtd, ONENAND_SPARERAM, oobbuf, oobcolumn, thisooblen); + oobread += thisooblen; + oobbuf += thisooblen; + oobcolumn = 0; } - from += thislen; + /* See if we are done */ + read += thislen; + if (read == len) + break; + /* Set up for next read from bufferRAM */ + if (unlikely(boundary)) + this->write_word(ONENAND_DDP_CHIP1, this->base + ONENAND_REG_START_ADDRESS2); + ONENAND_SET_NEXT_BUFFERRAM(this); buf += thislen; - } + thislen = min_t(int, writesize, len - read); + column = 0; - /* Deselect and wake up anyone waiting on the device */ - onenand_release_device(mtd); + /* Now wait for load */ + ret = this->wait(mtd, FL_READING); + onenand_update_bufferram(mtd, from, !ret); + if (ret == -EBADMSG) + ret = 0; + } /* * Return success, if no ECC failures, else -EBADMSG * fs driver will take care of that, because * retlen == desired len and result == -EBADMSG */ - *retlen = read; - return ret; + ops->retlen = read; + ops->oobretlen = oobread; + + if (ret) + return ret; + + if (mtd->ecc_stats.failed - stats.failed) + return -EBADMSG; + + return mtd->ecc_stats.corrected - stats.corrected ? -EUCLEAN : 0; +} + +/** + * onenand_read_oob_nolock - [MTD Interface] OneNAND read out-of-band + * @param mtd MTD device structure + * @param from offset to read from + * @param ops oob operation description structure + * + * OneNAND read out-of-band data from the spare area + */ +static int onenand_read_oob_nolock(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops) +{ + struct onenand_chip *this = mtd->priv; + struct mtd_ecc_stats stats; + int read = 0, thislen, column, oobsize; + size_t len = ops->ooblen; + mtd_oob_mode_t mode = ops->mode; + u_char *buf = ops->oobbuf; + int ret = 0; + + from += ops->ooboffs; + + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_read_oob_nolock: from = 0x%08x, len = %i\n", (unsigned int) from, (int) len); + + /* Initialize return length value */ + ops->oobretlen = 0; + + if (mode == MTD_OOB_AUTO) + oobsize = this->ecclayout->oobavail; + else + oobsize = mtd->oobsize; + + column = from & (mtd->oobsize - 1); + + if (unlikely(column >= oobsize)) { + printk(KERN_ERR "onenand_read_oob_nolock: Attempted to start read outside oob\n"); + return -EINVAL; + } + + /* Do not allow reads past end of device */ + if (unlikely(from >= mtd->size || + column + len > ((mtd->size >> this->page_shift) - + (from >> this->page_shift)) * oobsize)) { + printk(KERN_ERR "onenand_read_oob_nolock: Attempted to read beyond end of device\n"); + return -EINVAL; + } + + stats = mtd->ecc_stats; + + while (read < len) { + thislen = oobsize - column; + thislen = min_t(int, thislen, len); + + this->command(mtd, ONENAND_CMD_READOOB, from, mtd->oobsize); + + onenand_update_bufferram(mtd, from, 0); + + ret = this->wait(mtd, FL_READING); + if (ret && ret != -EBADMSG) { + printk(KERN_ERR "onenand_read_oob_nolock: read failed = 0x%x\n", ret); + break; + } + + if (mode == MTD_OOB_AUTO) + onenand_transfer_auto_oob(mtd, buf, column, thislen); + else + this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); + + read += thislen; + + if (read == len) + break; + + buf += thislen; + + /* Read more? */ + if (read < len) { + /* Page size */ + from += mtd->writesize; + column = 0; + } + } + + ops->oobretlen = read; + + if (ret) + return ret; + + if (mtd->ecc_stats.failed - stats.failed) + return -EBADMSG; + + return 0; } /** @@ -618,38 +804,124 @@ static int onenand_read_ecc(struct mtd_info *mtd, loff_t from, size_t len, int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf) { - return onenand_read_ecc(mtd, from, len, retlen, buf, NULL, NULL); + struct mtd_oob_ops ops = { + .len = len, + .ooblen = 0, + .datbuf = buf, + .oobbuf = NULL, + }; + int ret; + + onenand_get_device(mtd, FL_READING); + ret = onenand_read_ops_nolock(mtd, from, &ops); + onenand_release_device(mtd); + + *retlen = ops.retlen; + return ret; } /** * onenand_read_oob - [MTD Interface] OneNAND read out-of-band * @param mtd MTD device structure * @param from offset to read from - * @param len number of bytes to read - * @param retlen pointer to variable to store the number of read bytes - * @param buf the databuffer to put data + * @param ops oob operations description structure * - * OneNAND read out-of-band data from the spare area + * OneNAND main and/or out-of-band + */ +int onenand_read_oob(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops) +{ + int ret; + + switch (ops->mode) { + case MTD_OOB_PLACE: + case MTD_OOB_AUTO: + break; + case MTD_OOB_RAW: + /* Not implemented yet */ + default: + return -EINVAL; + } + + onenand_get_device(mtd, FL_READING); + if (ops->datbuf) + ret = onenand_read_ops_nolock(mtd, from, ops); + else + ret = onenand_read_oob_nolock(mtd, from, ops); + onenand_release_device(mtd); + + return ret; +} + +/** + * onenand_bbt_wait - [DEFAULT] wait until the command is done + * @param mtd MTD device structure + * @param state state to select the max. timeout value + * + * Wait for command done. + */ +static int onenand_bbt_wait(struct mtd_info *mtd, int state) +{ + struct onenand_chip *this = mtd->priv; + unsigned int flags = ONENAND_INT_MASTER; + unsigned int interrupt; + unsigned int ctrl; + + while (1) { + interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); + if (interrupt & flags) + break; + } + + /* To get correct interrupt status in timeout case */ + interrupt = this->read_word(this->base + ONENAND_REG_INTERRUPT); + ctrl = this->read_word(this->base + ONENAND_REG_CTRL_STATUS); + + /* Initial bad block case: 0x2400 or 0x0400 */ + if (ctrl & ONENAND_CTRL_ERROR) { + printk(KERN_DEBUG "onenand_bbt_wait: controller error = 0x%04x\n", ctrl); + return ONENAND_BBT_READ_ERROR; + } + + if (interrupt & ONENAND_INT_READ) { + int ecc = this->read_word(this->base + ONENAND_REG_ECC_STATUS); + if (ecc & ONENAND_ECC_2BIT_ALL) + return ONENAND_BBT_READ_ERROR; + } else { + printk(KERN_ERR "onenand_bbt_wait: read timeout!" + "ctrl=0x%04x intr=0x%04x\n", ctrl, interrupt); + return ONENAND_BBT_READ_FATAL_ERROR; + } + + return 0; +} + +/** + * onenand_bbt_read_oob - [MTD Interface] OneNAND read out-of-band for bbt scan + * @param mtd MTD device structure + * @param from offset to read from + * @param ops oob operation description structure + * + * OneNAND read out-of-band data from the spare area for bbt scan */ -int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, - size_t * retlen, u_char * buf) +int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops) { struct onenand_chip *this = mtd->priv; int read = 0, thislen, column; int ret = 0; + size_t len = ops->ooblen; + u_char *buf = ops->oobbuf; - MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_read_oob: " - "from = 0x%08x, len = %i\n", - (unsigned int)from, (int)len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_bbt_read_oob: from = 0x%08x, len = %zi\n", (unsigned int) from, len); - /* Initialize return length value */ - *retlen = 0; + /* Initialize return value */ + ops->oobretlen = 0; /* Do not allow reads past end of device */ if (unlikely((from + len) > mtd->size)) { - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_read_oob: " - "Attempt read beyond end of device\n"); - return -EINVAL; + printk(KERN_ERR "onenand_bbt_read_oob: Attempt read beyond end of device\n"); + return ONENAND_BBT_READ_FATAL_ERROR; } /* Grab the lock and see if the device is available */ @@ -658,6 +930,7 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, column = from & (mtd->oobsize - 1); while (read < len) { + thislen = mtd->oobsize - column; thislen = min_t(int, thislen, len); @@ -665,27 +938,21 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, onenand_update_bufferram(mtd, from, 0); - ret = this->wait(mtd, FL_READING); - /* First copy data and check return value for ECC handling */ - - this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, - thislen); + ret = onenand_bbt_wait(mtd, FL_READING); + if (ret) + break; + this->read_bufferram(mtd, ONENAND_SPARERAM, buf, column, thislen); read += thislen; if (read == len) break; - if (ret) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_read_oob: read failed = %d\n", ret); - break; - } - buf += thislen; + /* Read more? */ if (read < len) { - /* Page size */ - from += mtd->writesize; + /* Update Page size */ + from += this->writesize; column = 0; } } @@ -693,224 +960,421 @@ int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, /* Deselect and wake up anyone waiting on the device */ onenand_release_device(mtd); - *retlen = read; + ops->oobretlen = read; return ret; } + #ifdef CONFIG_MTD_ONENAND_VERIFY_WRITE /** - * onenand_verify_page - [GENERIC] verify the chip contents after a write - * @param mtd MTD device structure - * @param buf the databuffer to verify - * - * Check DataRAM area directly + * onenand_verify_oob - [GENERIC] verify the oob contents after a write + * @param mtd MTD device structure + * @param buf the databuffer to verify + * @param to offset to read from */ -static int onenand_verify_page(struct mtd_info *mtd, u_char * buf, - loff_t addr) +static int onenand_verify_oob(struct mtd_info *mtd, const u_char *buf, loff_t to) { struct onenand_chip *this = mtd->priv; - void __iomem *dataram0, *dataram1; + u_char *oob_buf = this->oob_buf; + int status, i; + + this->command(mtd, ONENAND_CMD_READOOB, to, mtd->oobsize); + onenand_update_bufferram(mtd, to, 0); + status = this->wait(mtd, FL_READING); + if (status) + return status; + + this->read_bufferram(mtd, ONENAND_SPARERAM, oob_buf, 0, mtd->oobsize); + for (i = 0; i < mtd->oobsize; i++) + if (buf[i] != 0xFF && buf[i] != oob_buf[i]) + return -EBADMSG; + + return 0; +} + +/** + * onenand_verify - [GENERIC] verify the chip contents after a write + * @param mtd MTD device structure + * @param buf the databuffer to verify + * @param addr offset to read from + * @param len number of bytes to read and compare + */ +static int onenand_verify(struct mtd_info *mtd, const u_char *buf, loff_t addr, size_t len) +{ + struct onenand_chip *this = mtd->priv; + void __iomem *dataram; int ret = 0; + int thislen, column; - this->command(mtd, ONENAND_CMD_READ, addr, mtd->writesize); + while (len != 0) { + thislen = min_t(int, this->writesize, len); + column = addr & (this->writesize - 1); + if (column + thislen > this->writesize) + thislen = this->writesize - column; - ret = this->wait(mtd, FL_READING); - if (ret) - return ret; + this->command(mtd, ONENAND_CMD_READ, addr, this->writesize); - onenand_update_bufferram(mtd, addr, 1); + onenand_update_bufferram(mtd, addr, 0); - /* Check, if the two dataram areas are same */ - dataram0 = this->base + ONENAND_DATARAM; - dataram1 = dataram0 + mtd->writesize; + ret = this->wait(mtd, FL_READING); + if (ret) + return ret; - if (memcmp(dataram0, dataram1, mtd->writesize)) - return -EBADMSG; + onenand_update_bufferram(mtd, addr, 1); + + dataram = this->base + ONENAND_DATARAM; + dataram += onenand_bufferram_offset(mtd, ONENAND_DATARAM); + + if (memcmp(buf, dataram + column, thislen)) + return -EBADMSG; + + len -= thislen; + buf += thislen; + addr += thislen; + } return 0; } #else -#define onenand_verify_page(...) (0) +#define onenand_verify(...) (0) +#define onenand_verify_oob(...) (0) #endif #define NOTALIGNED(x) ((x & (mtd->writesize - 1)) != 0) /** - * onenand_write_ecc - [MTD Interface] OneNAND write with ECC - * @param mtd MTD device structure - * @param to offset to write to - * @param len number of bytes to write - * @param retlen pointer to variable to store the number of written bytes - * @param buf the data to write - * @param eccbuf filesystem supplied oob data buffer - * @param oobsel oob selection structure + * onenand_fill_auto_oob - [Internal] oob auto-placement transfer + * @param mtd MTD device structure + * @param oob_buf oob buffer + * @param buf source address + * @param column oob offset to write to + * @param thislen oob length to write + */ +static int onenand_fill_auto_oob(struct mtd_info *mtd, u_char *oob_buf, + const u_char *buf, int column, int thislen) +{ + struct onenand_chip *this = mtd->priv; + struct nand_oobfree *free; + int writecol = column; + int writeend = column + thislen; + int lastgap = 0; + unsigned int i; + + free = this->ecclayout->oobfree; + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + if (writecol >= lastgap) + writecol += free->offset - lastgap; + if (writeend >= lastgap) + writeend += free->offset - lastgap; + lastgap = free->offset + free->length; + } + free = this->ecclayout->oobfree; + for (i = 0; i < MTD_MAX_OOBFREE_ENTRIES && free->length; i++, free++) { + int free_end = free->offset + free->length; + if (free->offset < writeend && free_end > writecol) { + int st = max_t(int,free->offset,writecol); + int ed = min_t(int,free_end,writeend); + int n = ed - st; + memcpy(oob_buf + st, buf, n); + buf += n; + } else if (column == 0) + break; + } + return 0; +} + +/** + * onenand_write_ops_nolock - [OneNAND Interface] write main and/or out-of-band + * @param mtd MTD device structure + * @param to offset to write to + * @param ops oob operation description structure * - * OneNAND write with ECC + * Write main and/or oob with ECC */ -static int onenand_write_ecc(struct mtd_info *mtd, loff_t to, size_t len, - size_t * retlen, const u_char * buf, - u_char * eccbuf, struct nand_oobinfo *oobsel) +static int onenand_write_ops_nolock(struct mtd_info *mtd, loff_t to, + struct mtd_oob_ops *ops) { struct onenand_chip *this = mtd->priv; - int written = 0; + int written = 0, column, thislen, subpage; + int oobwritten = 0, oobcolumn, thisooblen, oobsize; + size_t len = ops->len; + size_t ooblen = ops->ooblen; + const u_char *buf = ops->datbuf; + const u_char *oob = ops->oobbuf; + u_char *oobbuf; int ret = 0; - MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_write_ecc: " - "to = 0x%08x, len = %i\n", - (unsigned int)to, (int)len); + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_write_ops_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ - *retlen = 0; + ops->retlen = 0; + ops->oobretlen = 0; /* Do not allow writes past end of device */ if (unlikely((to + len) > mtd->size)) { - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_ecc: " - "Attempt write to past end of device\n"); + printk(KERN_ERR "onenand_write_ops_nolock: Attempt write to past end of device\n"); return -EINVAL; } /* Reject writes, which are not page aligned */ - if (unlikely(NOTALIGNED(to)) || unlikely(NOTALIGNED(len))) { - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_ecc: " - "Attempt to write not page aligned data\n"); + if (unlikely(NOTALIGNED(to) || NOTALIGNED(len))) { + printk(KERN_ERR "onenand_write_ops_nolock: Attempt to write not page aligned data\n"); return -EINVAL; } - /* Grab the lock and see if the device is available */ - onenand_get_device(mtd, FL_WRITING); + if (ops->mode == MTD_OOB_AUTO) + oobsize = this->ecclayout->oobavail; + else + oobsize = mtd->oobsize; + + oobcolumn = to & (mtd->oobsize - 1); + + column = to & (mtd->writesize - 1); /* Loop until all data write */ while (written < len) { - int thislen = min_t(int, mtd->writesize, len - written); + u_char *wbuf = (u_char *) buf; - this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->writesize); + thislen = min_t(int, mtd->writesize - column, len - written); + thisooblen = min_t(int, oobsize - oobcolumn, ooblen - oobwritten); - this->write_bufferram(mtd, ONENAND_DATARAM, buf, 0, thislen); - this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, - mtd->oobsize); + this->command(mtd, ONENAND_CMD_BUFFERRAM, to, thislen); - this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); + /* Partial page write */ + subpage = thislen < mtd->writesize; + if (subpage) { + memset(this->page_buf, 0xff, mtd->writesize); + memcpy(this->page_buf + column, buf, thislen); + wbuf = this->page_buf; + } + + this->write_bufferram(mtd, ONENAND_DATARAM, wbuf, 0, mtd->writesize); + + if (oob) { + oobbuf = this->oob_buf; - onenand_update_bufferram(mtd, to, 1); + /* We send data to spare ram with oobsize + * * to prevent byte access */ + memset(oobbuf, 0xff, mtd->oobsize); + if (ops->mode == MTD_OOB_AUTO) + onenand_fill_auto_oob(mtd, oobbuf, oob, oobcolumn, thisooblen); + else + memcpy(oobbuf + oobcolumn, oob, thisooblen); + + oobwritten += thisooblen; + oob += thisooblen; + oobcolumn = 0; + } else + oobbuf = (u_char *) ffchars; + + this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); + + this->command(mtd, ONENAND_CMD_PROG, to, mtd->writesize); ret = this->wait(mtd, FL_WRITING); + + /* In partial page write we don't update bufferram */ + onenand_update_bufferram(mtd, to, !ret && !subpage); + if (ONENAND_IS_2PLANE(this)) { + ONENAND_SET_BUFFERRAM1(this); + onenand_update_bufferram(mtd, to + this->writesize, !ret && !subpage); + } + if (ret) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_write_ecc: write filaed %d\n", ret); + printk(KERN_ERR "onenand_write_ops_nolock: write filaed %d\n", ret); break; } - written += thislen; - /* Only check verify write turn on */ - ret = onenand_verify_page(mtd, (u_char *) buf, to); + ret = onenand_verify(mtd, buf, to, thislen); if (ret) { - MTDDEBUG (MTD_DEBUG_LEVEL0, - "onenand_write_ecc: verify failed %d\n", ret); + printk(KERN_ERR "onenand_write_ops_nolock: verify failed %d\n", ret); break; } + written += thislen; + if (written == len) break; + column = 0; to += thislen; buf += thislen; } - /* Deselect and wake up anyone waiting on the device */ - onenand_release_device(mtd); - - *retlen = written; + ops->retlen = written; return ret; } /** - * onenand_write - [MTD Interface] compability function for onenand_write_ecc - * @param mtd MTD device structure - * @param to offset to write to - * @param len number of bytes to write - * @param retlen pointer to variable to store the number of written bytes - * @param buf the data to write - * - * This function simply calls onenand_write_ecc - * with oob buffer and oobsel = NULL - */ -int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, - size_t * retlen, const u_char * buf) -{ - return onenand_write_ecc(mtd, to, len, retlen, buf, NULL, NULL); -} - -/** - * onenand_write_oob - [MTD Interface] OneNAND write out-of-band - * @param mtd MTD device structure - * @param to offset to write to - * @param len number of bytes to write - * @param retlen pointer to variable to store the number of written bytes - * @param buf the data to write + * onenand_write_oob_nolock - [Internal] OneNAND write out-of-band + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * @param mode operation mode * * OneNAND write out-of-band */ -int onenand_write_oob(struct mtd_info *mtd, loff_t to, size_t len, - size_t * retlen, const u_char * buf) +static int onenand_write_oob_nolock(struct mtd_info *mtd, loff_t to, + struct mtd_oob_ops *ops) { struct onenand_chip *this = mtd->priv; - int column, status; + int column, ret = 0, oobsize; int written = 0; + u_char *oobbuf; + size_t len = ops->ooblen; + const u_char *buf = ops->oobbuf; + mtd_oob_mode_t mode = ops->mode; - MTDDEBUG (MTD_DEBUG_LEVEL3, "onenand_write_oob: " - "to = 0x%08x, len = %i\n", - (unsigned int)to, (int)len); + to += ops->ooboffs; + + MTDDEBUG(MTD_DEBUG_LEVEL3, "onenand_write_oob_nolock: to = 0x%08x, len = %i\n", (unsigned int) to, (int) len); /* Initialize retlen, in case of early exit */ - *retlen = 0; + ops->oobretlen = 0; - /* Do not allow writes past end of device */ - if (unlikely((to + len) > mtd->size)) { - MTDDEBUG (MTD_DEBUG_LEVEL0, "onenand_write_oob: " - "Attempt write to past end of device\n"); + if (mode == MTD_OOB_AUTO) + oobsize = this->ecclayout->oobavail; + else + oobsize = mtd->oobsize; + + column = to & (mtd->oobsize - 1); + + if (unlikely(column >= oobsize)) { + printk(KERN_ERR "onenand_write_oob_nolock: Attempted to start write outside oob\n"); return -EINVAL; } - /* Grab the lock and see if the device is available */ - onenand_get_device(mtd, FL_WRITING); + /* For compatibility with NAND: Do not allow write past end of page */ + if (unlikely(column + len > oobsize)) { + printk(KERN_ERR "onenand_write_oob_nolock: " + "Attempt to write past end of page\n"); + return -EINVAL; + } + + /* Do not allow reads past end of device */ + if (unlikely(to >= mtd->size || + column + len > ((mtd->size >> this->page_shift) - + (to >> this->page_shift)) * oobsize)) { + printk(KERN_ERR "onenand_write_oob_nolock: Attempted to write past end of device\n"); + return -EINVAL; + } + + oobbuf = this->oob_buf; /* Loop until all data write */ while (written < len) { - int thislen = min_t(int, mtd->oobsize, len - written); - - column = to & (mtd->oobsize - 1); + int thislen = min_t(int, oobsize, len - written); this->command(mtd, ONENAND_CMD_BUFFERRAM, to, mtd->oobsize); - this->write_bufferram(mtd, ONENAND_SPARERAM, ffchars, 0, - mtd->oobsize); - this->write_bufferram(mtd, ONENAND_SPARERAM, buf, column, - thislen); + /* We send data to spare ram with oobsize + * to prevent byte access */ + memset(oobbuf, 0xff, mtd->oobsize); + if (mode == MTD_OOB_AUTO) + onenand_fill_auto_oob(mtd, oobbuf, buf, column, thislen); + else + memcpy(oobbuf + column, buf, thislen); + this->write_bufferram(mtd, ONENAND_SPARERAM, oobbuf, 0, mtd->oobsize); this->command(mtd, ONENAND_CMD_PROGOOB, to, mtd->oobsize); onenand_update_bufferram(mtd, to, 0); + if (ONENAND_IS_2PLANE(this)) { + ONENAND_SET_BUFFERRAM1(this); + onenand_update_bufferram(mtd, to + this->writesize, 0); + } - status = this->wait(mtd, FL_WRITING); - if (status) + ret = this->wait(mtd, FL_WRITING); + if (ret) { + printk(KERN_ERR "onenand_write_oob_nolock: write failed %d\n", ret); break; + } + + ret = onenand_verify_oob(mtd, oobbuf, to); + if (ret) { + printk(KERN_ERR "onenand_write_oob_nolock: verify failed %d\n", ret); + break; + } written += thislen; if (written == len) break; - to += thislen; + to += mtd->writesize; buf += thislen; + column = 0; } - /* Deselect and wake up anyone waiting on the device */ + ops->oobretlen = written; + + return ret; +} + +/** + * onenand_write - [MTD Interface] compability function for onenand_write_ecc + * @param mtd MTD device structure + * @param to offset to write to + * @param len number of bytes to write + * @param retlen pointer to variable to store the number of written bytes + * @param buf the data to write + * + * Write with ECC + */ +int onenand_write(struct mtd_info *mtd, loff_t to, size_t len, + size_t * retlen, const u_char * buf) +{ + struct mtd_oob_ops ops = { + .len = len, + .ooblen = 0, + .datbuf = (u_char *) buf, + .oobbuf = NULL, + }; + int ret; + + onenand_get_device(mtd, FL_WRITING); + ret = onenand_write_ops_nolock(mtd, to, &ops); onenand_release_device(mtd); - *retlen = written; + *retlen = ops.retlen; + return ret; +} + +/** + * onenand_write_oob - [MTD Interface] OneNAND write out-of-band + * @param mtd MTD device structure + * @param to offset to write to + * @param ops oob operation description structure + * + * OneNAND write main and/or out-of-band + */ +int onenand_write_oob(struct mtd_info *mtd, loff_t to, + struct mtd_oob_ops *ops) +{ + int ret; + + switch (ops->mode) { + case MTD_OOB_PLACE: + case MTD_OOB_AUTO: + break; + case MTD_OOB_RAW: + /* Not implemented yet */ + default: + return -EINVAL; + } + + onenand_get_device(mtd, FL_WRITING); + if (ops->datbuf) + ret = onenand_write_ops_nolock(mtd, to, ops); + else + ret = onenand_write_oob_nolock(mtd, to, ops); + onenand_release_device(mtd); + + return ret; - return 0; } /** @@ -1277,6 +1741,8 @@ static int onenand_probe(struct mtd_info *mtd) this->page_shift = ffs(mtd->writesize) - 1; this->ppb_shift = (this->erase_shift - this->page_shift); this->page_mask = (mtd->erasesize / mtd->writesize) - 1; + /* It's real page size */ + this->writesize = mtd->writesize; /* REVIST: Multichip handling */ @@ -1346,6 +1812,28 @@ int onenand_scan(struct mtd_info *mtd, int maxchips) this->read_bufferram = onenand_sync_read_bufferram; } + /* Allocate buffers, if necessary */ + if (!this->page_buf) { + this->page_buf = kzalloc(mtd->writesize, GFP_KERNEL); + if (!this->page_buf) { + printk(KERN_ERR "onenand_scan(): Can't allocate page_buf\n"); + return -ENOMEM; + } + this->options |= ONENAND_PAGEBUF_ALLOC; + } + if (!this->oob_buf) { + this->oob_buf = kzalloc(mtd->oobsize, GFP_KERNEL); + if (!this->oob_buf) { + printk(KERN_ERR "onenand_scan: Can't allocate oob_buf\n"); + if (this->options & ONENAND_PAGEBUF_ALLOC) { + this->options &= ~ONENAND_PAGEBUF_ALLOC; + kfree(this->page_buf); + } + return -ENOMEM; + } + this->options |= ONENAND_OOBBUF_ALLOC; + } + onenand_unlock(mtd, 0, mtd->size); return onenand_default_bbt(mtd); diff --git a/drivers/mtd/onenand/onenand_bbt.c b/drivers/mtd/onenand/onenand_bbt.c index d13d277..dde11ae 100644 --- a/drivers/mtd/onenand/onenand_bbt.c +++ b/drivers/mtd/onenand/onenand_bbt.c @@ -68,6 +68,7 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, int startblock; loff_t from; size_t readlen, ooblen; + struct mtd_oob_ops ops; printk(KERN_INFO "Scanning device for bad blocks\n"); @@ -85,25 +86,26 @@ static int create_bbt(struct mtd_info *mtd, uint8_t * buf, startblock = 0; from = 0; + ops.mode = MTD_OOB_PLACE; + ops.ooblen = readlen; + ops.oobbuf = buf; + ops.len = ops.ooboffs = ops.retlen = ops.oobretlen = 0; + for (i = startblock; i < numblocks;) { int ret; for (j = 0; j < len; j++) { - size_t retlen; - /* No need to read pages fully, * just read required OOB bytes */ - ret = onenand_read_oob(mtd, + ret = onenand_bbt_read_oob(mtd, from + j * mtd->writesize + - bd->offs, readlen, &retlen, - &buf[0]); + bd->offs, &ops); - if (ret && ret != -EAGAIN) { - printk("ret = %d\n", ret); - return ret; - } + /* If it is a initial bad block, just ignore it */ + if (ret == ONENAND_BBT_READ_FATAL_ERROR) + return -EIO; - if (check_short_pattern + if (ret || check_short_pattern (&buf[j * scanlen], scanlen, mtd->writesize, bd)) { bbm->bbt[i >> 3] |= 0x03 << (i & 0x6); printk(KERN_WARNING diff --git a/include/linux/mtd/bbm.h b/include/linux/mtd/bbm.h index bffb25b..abf8f1a 100644 --- a/include/linux/mtd/bbm.h +++ b/include/linux/mtd/bbm.h @@ -97,6 +97,13 @@ struct nand_bbt_descr { */ #define ONENAND_BADBLOCK_POS 0 +/* + * Bad block scanning errors + */ +#define ONENAND_BBT_READ_ERROR 1 +#define ONENAND_BBT_READ_ECC_ERROR 2 +#define ONENAND_BBT_READ_FATAL_ERROR 4 + /** * struct bbt_info - [GENERIC] Bad Block Table data structure * @param bbt_erase_shift [INTERN] number of address bits in a bbt entry diff --git a/include/linux/mtd/onenand.h b/include/linux/mtd/onenand.h index 8a0fd0d..d73ea14 100644 --- a/include/linux/mtd/onenand.h +++ b/include/linux/mtd/onenand.h @@ -75,6 +75,7 @@ struct onenand_chip { unsigned int page_shift; unsigned int ppb_shift; /* Pages per block shift */ unsigned int page_mask; + unsigned int writesize; unsigned int bufferram_index; struct onenand_bufferram bufferram[MAX_BUFFERRAM]; @@ -96,22 +97,38 @@ struct onenand_chip { spinlock_t chip_lock; wait_queue_head_t wq; int state; + unsigned char *page_buf; + unsigned char *oob_buf; struct nand_oobinfo *autooob; + struct nand_ecclayout *ecclayout; void *bbm; void *priv; }; +/* + * Helper macros + */ #define ONENAND_CURRENT_BUFFERRAM(this) (this->bufferram_index) #define ONENAND_NEXT_BUFFERRAM(this) (this->bufferram_index ^ 1) #define ONENAND_SET_NEXT_BUFFERRAM(this) (this->bufferram_index ^= 1) +#define ONENAND_SET_PREV_BUFFERRAM(this) (this->bufferram_index ^= 1) +#define ONENAND_SET_BUFFERRAM0(this) (this->bufferram_index = 0) +#define ONENAND_SET_BUFFERRAM1(this) (this->bufferram_index = 1) + +#define ONENAND_IS_DDP(this) \ + (this->device_id & ONENAND_DEVICE_IS_DDP) + +#define ONENAND_IS_2PLANE(this) (0) /* * Options bits */ #define ONENAND_CONT_LOCK (0x0001) +#define ONENAND_PAGEBUF_ALLOC (0x1000) +#define ONENAND_OOBBUF_ALLOC (0x2000) /* * OneNAND Flash Manufacturer ID Codes @@ -129,4 +146,7 @@ struct onenand_manufacturers { char *name; }; +int onenand_bbt_read_oob(struct mtd_info *mtd, loff_t from, + struct mtd_oob_ops *ops); + #endif /* __LINUX_MTD_ONENAND_H */ diff --git a/include/linux/mtd/onenand_regs.h b/include/linux/mtd/onenand_regs.h index c8a9f3e..6a8aa28 100644 --- a/include/linux/mtd/onenand_regs.h +++ b/include/linux/mtd/onenand_regs.h @@ -83,6 +83,8 @@ * Start Address 1 F100h (R/W) */ #define ONENAND_DDP_SHIFT (15) +#define ONENAND_DDP_CHIP0 (0) +#define ONENAND_DDP_CHIP1 (1 << ONENAND_DDP_SHIFT) /* * Start Address 8 F107h (R/W) diff --git a/include/onenand_uboot.h b/include/onenand_uboot.h index 4260ee7..2886a6f 100644 --- a/include/onenand_uboot.h +++ b/include/onenand_uboot.h @@ -15,24 +15,18 @@ #define __UBOOT_ONENAND_H #include <linux/types.h> - -struct kvec { - void *iov_base; - size_t iov_len; -}; - -typedef int spinlock_t; -typedef int wait_queue_head_t; +#include <mtd_uboot.h> struct mtd_info; struct erase_info; +extern struct mtd_info onenand_mtd; + /* Functions */ extern void onenand_init(void); extern int onenand_read(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, u_char * buf); -extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, size_t len, - size_t * retlen, u_char * buf); +extern int onenand_read_oob(struct mtd_info *mtd, loff_t from, struct mtd_oob_ops *ops); extern int onenand_write(struct mtd_info *mtd, loff_t from, size_t len, size_t * retlen, const u_char * buf); extern int onenand_erase(struct mtd_info *mtd, struct erase_info *instr);

2 3

[U-Boot] [PATCH 1/2]: Add support for the muas3001 board
by Heiko Schocher 19 Aug '08

19 Aug '08

Hello, [POWERPC] Added support for the muas3001 board from IAI, based on a MPC8270 CPU. Signed-off-by: Heiko Schocher <hs(a)denx.de> --- Makefile | 9 + board/muas3001/Makefile | 50 ++++++ board/muas3001/config.mk | 24 +++ board/muas3001/muas3001.c | 388 ++++++++++++++++++++++++++++++++++++++++++++ include/configs/muas3001.h | 382 +++++++++++++++++++++++++++++++++++++++++++ 5 files changed, 853 insertions(+), 0 deletions(-) create mode 100644 board/muas3001/Makefile create mode 100644 board/muas3001/config.mk create mode 100644 board/muas3001/muas3001.c create mode 100644 include/configs/muas3001.h diff --git a/Makefile b/Makefile index 3179c67..9c3de1c 100644 --- a/Makefile +++ b/Makefile @@ -1672,6 +1672,15 @@ PQ2FADS-ZU_66MHz_lowboot_config \ MPC8266ADS_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc8260 mpc8266ads freescale +muas3001_dev_config \ +muas3001_config : unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)board/muas3001 + @if [ "$(findstring dev,$@)" ] ; then \ + echo "#define CONFIG_MUAS_DEV_BOARD" > $(obj)include/config.h ; \ + fi + @$(MKCONFIG) -a muas3001 ppc mpc8260 muas3001 + # PM825/PM826 default configuration: small (= 8 MB) Flash / boot from 64-bit flash PM825_config \ PM825_ROMBOOT_config \ diff --git a/board/muas3001/Makefile b/board/muas3001/Makefile new file mode 100644 index 0000000..a4413b2 --- /dev/null +++ b/board/muas3001/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2008 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := $(BOARD).o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/muas3001/config.mk b/board/muas3001/config.mk new file mode 100644 index 0000000..cdd0ec9 --- /dev/null +++ b/board/muas3001/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2008 +# Heiko Schocher, DENX Software Engineering, hs(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0xFF000000 diff --git a/board/muas3001/muas3001.c b/board/muas3001/muas3001.c new file mode 100644 index 0000000..1c33493 --- /dev/null +++ b/board/muas3001/muas3001.c @@ -0,0 +1,388 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <mpc8260.h> +#include <ioports.h> + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +#include <libfdt.h> +#endif + +/* + * I/O Port configuration table + * + * if conf is 1, then that port pin will be configured at boot time + * according to the five values podr/pdir/ppar/psor/pdat for that entry + */ +const iop_conf_t iop_conf_tab[4][32] = { + + /* Port A */ + { /* conf ppar psor pdir podr pdat */ + /* PA31 */ { 0, 0, 0, 0, 0, 0 }, /* PA31 */ + /* PA30 */ { 0, 0, 0, 0, 0, 0 }, /* PA30 */ + /* PA29 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXER */ + /* PA28 */ { 1, 1, 1, 1, 0, 0 }, /* FCC1 TXEN */ + /* PA27 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXDV */ + /* PA26 */ { 1, 1, 1, 0, 0, 0 }, /* FCC1 RXER */ + /* PA25 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_PWRDWN */ + /* PA24 */ { 1, 0, 0, 1, 0, 1 }, /* ETH_RESET */ + /* PA23 */ { 0, 0, 0, 0, 0, 0 }, /* PA23 */ + /* PA22 */ { 0, 0, 0, 0, 0, 0 }, /* PA22 */ + /* PA21 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD3 */ + /* PA20 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD2 */ + /* PA19 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD1 */ + /* PA18 */ { 1, 1, 0, 1, 0, 0 }, /* FCC1 TXD0 */ + /* PA17 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD0 */ + /* PA16 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD1 */ + /* PA15 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD2 */ + /* PA14 */ { 1, 1, 0, 0, 0, 0 }, /* FCC1 RXD3 */ + /* PA13 */ { 0, 0, 0, 0, 0, 0 }, /* PA13 */ + /* PA12 */ { 1, 0, 0, 1, 0, 0 }, /* ETH_SLEEP */ + /* PA11 */ { 0, 0, 0, 0, 0, 0 }, /* PA11 */ + /* PA10 */ { 1, 0, 0, 1, 0, 0 }, /* MDIO */ + /* PA9 */ { 1, 0, 0, 1, 0, 0 }, /* MDC */ + /* PA8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC2 RxD */ + /* PA7 */ { 0, 0, 0, 0, 0, 0 }, /* PA7 */ + /* PA6 */ { 0, 0, 0, 0, 0, 0 }, /* PA6 */ + /* PA5 */ { 0, 0, 0, 0, 0, 0 }, /* PA5 */ + /* PA4 */ { 0, 0, 0, 0, 0, 0 }, /* PA4 */ + /* PA3 */ { 0, 0, 0, 0, 0, 0 }, /* PA3 */ + /* PA2 */ { 0, 0, 0, 0, 0, 0 }, /* PA2 */ + /* PA1 */ { 0, 0, 0, 0, 0, 0 }, /* PA1 */ + /* PA0 */ { 0, 0, 0, 0, 0, 0 } /* PA0 */ + }, + + /* Port B */ + { /* conf ppar psor pdir podr pdat */ + /* PB31 */ { 0, 0, 0, 0, 0, 0 }, /* PB31 */ + /* PB30 */ { 0, 0, 0, 0, 0, 0 }, /* PB30 */ + /* PB29 */ { 0, 0, 0, 0, 0, 0 }, /* PB29 */ + /* PB28 */ { 1, 1, 1, 1, 0, 0 }, /* SCC1 TxD */ + /* PB27 */ { 0, 0, 0, 0, 0, 0 }, /* PB27 */ + /* PB26 */ { 0, 0, 0, 0, 0, 0 }, /* PB26 */ + /* PB25 */ { 0, 0, 0, 0, 0, 0 }, /* PB25 */ + /* PB24 */ { 0, 0, 0, 0, 0, 0 }, /* PB24 */ + /* PB23 */ { 0, 0, 0, 0, 0, 0 }, /* PB23 */ + /* PB22 */ { 0, 0, 0, 0, 0, 0 }, /* PB22 */ + /* PB21 */ { 0, 0, 0, 0, 0, 0 }, /* PB21 */ + /* PB20 */ { 0, 0, 0, 0, 0, 0 }, /* PB20 */ + /* PB19 */ { 0, 0, 0, 0, 0, 0 }, /* PB19 */ + /* PB18 */ { 0, 0, 0, 0, 0, 0 }, /* PB18 */ + /* PB17 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB16 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB15 */ { 1, 1, 0, 0, 0, 0 }, /* SCC2 RxD */ + /* PB14 */ { 1, 1, 0, 0, 0, 0 }, /* SCC3 RxD */ + /* PB13 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB12 */ { 1, 1, 1, 1, 0, 0 }, /* SCC2 TxD */ + /* PB11 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB10 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB9 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB8 */ { 1, 1, 1, 1, 0, 0 }, /* SCC3 TxD */ + /* PB7 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB6 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB5 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB4 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PB0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + }, + + /* Port C */ + { /* conf ppar psor pdir podr pdat */ + /* PC31 */ { 0, 0, 0, 0, 0, 0 }, /* PC31 */ + /* PC30 */ { 1, 1, 1, 1, 0, 0 }, /* Timer1 OUT */ + /* PC29 */ { 0, 0, 0, 0, 0, 0 }, /* PC29 */ + /* PC28 */ { 0, 0, 0, 0, 0, 0 }, /* PC28 */ + /* PC27 */ { 0, 0, 0, 0, 0, 0 }, /* PC27 */ + /* PC26 */ { 0, 0, 0, 0, 0, 0 }, /* PC26 */ + /* PC25 */ { 0, 0, 0, 0, 0, 0 }, /* PC25 */ + /* PC24 */ { 0, 0, 0, 0, 0, 0 }, /* PC24 */ + /* PC23 */ { 0, 0, 0, 0, 0, 0 }, /* PC23 */ + /* PC22 */ { 0, 0, 0, 0, 0, 0 }, /* PC22 */ + /* PC21 */ { 1, 1, 0, 0, 0, 0 }, /* FCC RxCLK 11 */ + /* PC20 */ { 1, 1, 0, 0, 0, 0 }, /* FCC TxCLK 12 */ + /* PC19 */ { 0, 0, 0, 0, 0, 0 }, /* PC19 */ + /* PC18 */ { 0, 0, 0, 0, 0, 0 }, /* PC18 */ + /* PC17 */ { 0, 0, 0, 0, 0, 0 }, /* PC17 */ + /* PC16 */ { 0, 0, 0, 0, 0, 0 }, /* PC16 */ + /* PC15 */ { 1, 1, 0, 1, 0, 0 }, /* SMC2 TxD */ + /* PC14 */ { 0, 0, 0, 0, 0, 0 }, /* PC14 */ + /* PC13 */ { 0, 0, 0, 0, 0, 0 }, /* PC13 */ + /* PC12 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW1 */ + /* PC11 */ { 1, 0, 0, 1, 0, 0 }, /* TX OUTPUT SLEW0 */ + /* PC10 */ { 0, 0, 0, 0, 0, 0 }, /* PC10 */ + /* PC9 */ { 1, 0, 0, 1, 0, 1 }, /* SPA_TX_EN */ + /* PC8 */ { 0, 0, 0, 0, 0, 0 }, /* PC8 */ + /* PC7 */ { 0, 0, 0, 0, 0, 0 }, /* PC7 */ + /* PC6 */ { 0, 0, 0, 0, 0, 0 }, /* PC6 */ + /* PC5 */ { 0, 0, 0, 0, 0, 0 }, /* PC5 */ + /* PC4 */ { 0, 0, 0, 0, 0, 0 }, /* PC4 */ + /* PC3 */ { 0, 0, 0, 0, 0, 0 }, /* PC3 */ + /* PC2 */ { 0, 0, 0, 0, 0, 0 }, /* PC2 */ + /* PC1 */ { 0, 0, 0, 0, 0, 0 }, /* PC1 */ + /* PC0 */ { 0, 0, 0, 0, 0, 0 }, /* PC0 */ + }, + + /* Port D */ + { /* conf ppar psor pdir podr pdat */ + /* PD31 */ { 1, 1, 0, 0, 0, 0 }, /* SCC1 RxD */ + /* PD30 */ { 0, 0, 0, 0, 0, 0 }, /* PD30 */ + /* PD29 */ { 0, 0, 0, 0, 0, 0 }, /* PD29 */ + /* PD28 */ { 0, 0, 0, 0, 0, 0 }, /* PD28 */ + /* PD27 */ { 0, 0, 0, 0, 0, 0 }, /* PD27 */ + /* PD26 */ { 0, 0, 0, 0, 0, 0 }, /* PD26 */ + /* PD25 */ { 0, 0, 0, 0, 0, 0 }, /* PD25 */ + /* PD24 */ { 0, 0, 0, 0, 0, 0 }, /* PD24 */ + /* PD23 */ { 0, 0, 0, 0, 0, 0 }, /* PD23 */ + /* PD22 */ { 1, 1, 0, 0, 0, 0 }, /* SCC4: RXD */ + /* PD21 */ { 1, 1, 0, 1, 0, 0 }, /* SCC4: TXD */ + /* PD20 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD19 */ { 0, 0, 0, 0, 0, 0 }, /* PD19 */ + /* PD18 */ { 0, 0, 0, 0, 0, 0 }, /* PD18 */ + /* PD17 */ { 0, 0, 0, 0, 0, 0 }, /* PD17 */ + /* PD16 */ { 0, 0, 0, 0, 0, 0 }, /* PD16 */ + /* PD15 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SDA */ + /* PD14 */ { 1, 1, 1, 0, 0, 0 }, /* I2C SCL */ + /* PD13 */ { 0, 0, 0, 0, 0, 0 }, /* PD13 */ + /* PD12 */ { 0, 0, 0, 0, 0, 0 }, /* PD12 */ + /* PD11 */ { 0, 0, 0, 0, 0, 0 }, /* PD11 */ + /* PD10 */ { 0, 0, 0, 0, 0, 0 }, /* PD10 */ + /* PD9 */ { 1, 1, 0, 1, 0, 0 }, /* SMC1 TxD */ + /* PD8 */ { 1, 1, 0, 0, 0, 0 }, /* SMC1 RxD */ + /* PD7 */ { 0, 0, 0, 0, 0, 0 }, /* PD7 */ + /* PD6 */ { 0, 0, 0, 0, 0, 0 }, /* PD6 */ + /* PD5 */ { 0, 0, 0, 0, 0, 0 }, /* PD5 */ + /* PD4 */ { 0, 0, 0, 0, 0, 0 }, /* PD4 */ + /* PD3 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD2 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD1 */ { 0, 0, 0, 0, 0, 0 }, /* non-existent */ + /* PD0 */ { 0, 0, 0, 0, 0, 0 } /* non-existent */ + } +}; + +/* Try SDRAM initialization with P/LSDMR=sdmr and ORx=orx + * + * This routine performs standard 8260 initialization sequence + * and calculates the available memory size. It may be called + * several times to try different SDRAM configurations on both + * 60x and local buses. + */ +static long int try_init (volatile memctl8260_t * memctl, ulong sdmr, + ulong orx, volatile uchar * base) +{ + volatile uchar c = 0xff; + volatile uint *sdmr_ptr; + volatile uint *orx_ptr; + ulong maxsize, size; + int i; + + /* We must be able to test a location outsize the maximum legal size + * to find out THAT we are outside; but this address still has to be + * mapped by the controller. That means, that the initial mapping has + * to be (at least) twice as large as the maximum expected size. + */ + maxsize = (1 + (~orx | 0x7fff))/* / 2*/; + + sdmr_ptr = &memctl->memc_psdmr; + orx_ptr = &memctl->memc_or1; + + *orx_ptr = orx; + + /* + * Quote from 8260 UM (10.4.2 SDRAM Power-On Initialization, 10-35): + * + * "At system reset, initialization software must set up the + * programmable parameters in the memory controller banks registers + * (ORx, BRx, P/LSDMR). After all memory parameters are configured, + * system software should execute the following initialization sequence + * for each SDRAM device. + * + * 1. Issue a PRECHARGE-ALL-BANKS command + * 2. Issue eight CBR REFRESH commands + * 3. Issue a MODE-SET command to initialize the mode register + * + * The initial commands are executed by setting P/LSDMR[OP] and + * accessing the SDRAM with a single-byte transaction." + * + * The appropriate BRx/ORx registers have already been set when we + * get here. The SDRAM can be accessed at the address CFG_SDRAM_BASE. + */ + + *sdmr_ptr = sdmr | PSDMR_OP_PREA; + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_CBRR; + for (i = 0; i < 8; i++) + *base = c; + + *sdmr_ptr = sdmr | PSDMR_OP_MRW; + *(base + CFG_MRS_OFFS) = c; /* setting MR on address lines */ + + *sdmr_ptr = sdmr | PSDMR_OP_NORM | PSDMR_RFEN; + *base = c; + + size = get_ram_size((long *)base, maxsize); + *orx_ptr = orx | ~(size - 1); + + return (size); +} + +long int initdram(int board_type) +{ + volatile immap_t *immap = (immap_t *) CFG_IMMR; + volatile memctl8260_t *memctl = &immap->im_memctl; + + long psize; + + memctl->memc_psrt = CFG_PSRT; + memctl->memc_mptpr = CFG_MPTPR; + +#ifndef CFG_RAMBOOT + /* 60x SDRAM setup: + */ + psize = try_init (memctl, CFG_PSDMR, CFG_OR1, + (uchar *) CFG_SDRAM_BASE); +#endif /* CFG_RAMBOOT */ + + icache_enable (); + + return (psize); +} + +int checkboard(void) +{ + puts("Board: MUAS3001\n"); + + return 0; +} + +/* + * Early board initalization. + */ +int board_early_init_r(void) +{ + return 0; +} + +#if defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) +/* + * update "memory" property in the blob + */ +void ft_blob_update(void *blob, bd_t *bd) +{ + int ret, nodeoffset = 0; + ulong memory_data[2] = {0}; + ulong flash_data[4] = {0}; + ulong freq = 0; + ulong speed = 0; + + memory_data[0] = cpu_to_be32(bd->bi_memstart); + memory_data[1] = cpu_to_be32(bd->bi_memsize); + + nodeoffset = fdt_path_offset (blob, "/memory"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "reg", memory_data, + sizeof(memory_data)); + if (ret < 0) + printf("ft_blob_update): cannot set /memory/reg " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /memory node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + /* update Flash addr, size */ + flash_data[2] = cpu_to_be32(CFG_FLASH_BASE); + flash_data[3] = cpu_to_be32(CFG_FLASH_SIZE); + nodeoffset = fdt_path_offset (blob, "/localbus"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "ranges", flash_data, + sizeof(flash_data)); + if (ret < 0) + printf("ft_blob_update): cannot set /localbus/ranges " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /localbus node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + /* MAC Adresse */ + nodeoffset = fdt_path_offset (blob, "/soc/cpm/ethernet"); + if (nodeoffset >= 0) { + ret = fdt_setprop(blob, nodeoffset, "mac-address", bd->bi_enetaddr, + sizeof(uchar) * 6); + if (ret < 0) + printf("ft_blob_update): cannot set /soc/cpm/ethernet/mac-address " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /soc/cpm/ethernet node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + + /* brg clock */ + nodeoffset = fdt_path_offset (blob, "/soc/cpm/brg"); + if (nodeoffset >= 0) { + freq = cpu_to_be32(bd->bi_brgfreq); + ret = fdt_setprop(blob, nodeoffset, "clock-frequency", &freq, + sizeof(unsigned long)); + if (ret < 0) + printf("ft_blob_update): cannot set /soc/cpm/brg/clock-frequency " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* memory node is required in dts */ + printf("ft_blob_update(): cannot find /soc/cpm/brg/clock-frequency node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + + /* baudrate */ + nodeoffset = fdt_path_offset (blob, "/soc/cpm/serial"); + if (nodeoffset >= 0) { + speed = cpu_to_be32(bd->bi_baudrate); + ret = fdt_setprop(blob, nodeoffset, "current-speed", &speed, + sizeof(unsigned long)); + if (ret < 0) + printf("ft_blob_update): cannot set /soc/cpm/serial/current-speed " + "property err:%s\n", fdt_strerror(ret)); + } + else { + /* baudrate is required in dts */ + printf("ft_blob_update(): cannot find /soc/cpm/smc2/current-speed node " + "err:%s\n", fdt_strerror(nodeoffset)); + } + + +} + +void ft_board_setup(void *blob, bd_t *bd) +{ + ft_cpu_setup( blob, bd); + ft_blob_update(blob, bd); +} +#endif /* defined(CONFIG_OF_BOARD_SETUP) && defined(CONFIG_OF_LIBFDT) */ diff --git a/include/configs/muas3001.h b/include/configs/muas3001.h new file mode 100644 index 0000000..f915e55 --- /dev/null +++ b/include/configs/muas3001.h @@ -0,0 +1,382 @@ +/* + * (C) Copyright 2008 + * Heiko Schocher, DENX Software Engineering, hs(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_8260 1 +#define CONFIG_MPC8260 1 +#define CONFIG_MUAS3001 1 + +#define CONFIG_CPM2 1 /* Has a CPM2 */ + +/* Do boardspecific init */ +#define CONFIG_BOARD_EARLY_INIT_R 1 + +/* + * Select serial console configuration + * + * If either CONFIG_CONS_ON_SMC or CONFIG_CONS_ON_SCC is selected, then + * CONFIG_CONS_INDEX must be set to the channel number (1-2 for SMC, 1-4 + * for SCC). + */ +#define CONFIG_CONS_ON_SMC /* Console is on SMC */ +#undef CONFIG_CONS_ON_SCC /* It's not on SCC */ +#undef CONFIG_CONS_NONE /* It's not on external UART */ +#if defined(CONFIG_MUAS_DEV_BOARD) +#define CONFIG_CONS_INDEX 2 /* SMC2 is used for console */ +#else +#define CONFIG_CONS_INDEX 1 /* SMC1 is used for console */ +#endif + +/* + * Select ethernet configuration + * + * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, + * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for + * SCC, 1-3 for FCC) + * + * If CONFIG_ETHER_NONE is defined, then either the ethernet routines + * must be defined elsewhere (as for the console), or CONFIG_CMD_NET + * must be unset. + */ +#undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ +#define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ +#undef CONFIG_ETHER_NONE /* No external Ethernet */ + +#define CONFIG_ETHER_INDEX 1 +#define CONFIG_ETHER_ON_FCC1 +#define FCC_ENET + +/* + * - Rx-CLK is CLK11 + * - Tx-CLK is CLK12 + */ +# define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK11 | CMXFCR_TF1CS_CLK12) +# define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) +/* + * - RAM for BD/Buffers is on the 60x Bus (see 28-13) + */ +# define CFG_CPMFCR_RAMTYPE (0) +/* know on local Bus */ +//# define CFG_CPMFCR_RAMTYPE (CPMFCR_DTB | CPMFCR_BDB) +/* + * - Enable Full Duplex in FSMR + */ +# define CFG_FCC_PSMR (FCC_PSMR_FDE|FCC_PSMR_LPB) + +#define CONFIG_MII /* MII PHY management */ +#define CONFIG_BITBANGMII /* bit-bang MII PHY management */ +# define CFG_PHY_ADDR 1 +/* + * GPIO pins used for bit-banged MII communications + */ +#define MDIO_PORT 0 /* Port A */ + +#define CFG_MDIO_PIN 0x00200000 /* PA10 */ +#define CFG_MDC_PIN 0x00400000 /* PA9 */ + +#define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) +#define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) +#define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) + +#define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ + else iop->pdat &= ~CFG_MDIO_PIN + +#define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ + else iop->pdat &= ~CFG_MDC_PIN + +#define MIIDELAY udelay(1) + +#ifndef CONFIG_8260_CLKIN +#define CONFIG_8260_CLKIN 66000000 /* in Hz */ +#endif + +#define CONFIG_BAUDRATE 115200 + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ECHO +#define CONFIG_CMD_IMMAP +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_I2C + +/* + * Default environment settings + */ +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "u-boot_addr=100000\0" \ + "kernel_addr=200000\0" \ + "fdt_addr=400000\0" \ + "rootpath=/opt/eldk-4.2-2008-04-01/ppc_82xx\0" \ + "u-boot=u-boot.bin\0" \ + "bootfile=uImage\0" \ + "fdt_file=muas3001.dtb\0" \ + "kernel_file=uImage\0" \ + "ramdisk_file=uRamdisk\0" \ + "load=tftp ${u-boot_addr} ${u-boot}\0" \ + "update=prot off ff000000 ff03ffff; era ff000000 ff03ffff; " \ + "cp.b ${u-boot_addr} ff000000 ${filesize};" \ + "prot on ff000000 ff03ffff\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "addcons=setenv bootargs ${bootargs} console=ttyCPM0,${baudrate}\0" \ + "addmtd=setenv bootargs ${bootargs} ${mtdparts}\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:" \ + "${netmask}:${hostname}:${netdev}:off panic=1\0" \ + "net_nfs=tftp ${kernel_addr} ${bootfile}; " \ + "tftp ${fdt_addr} ${fdt_file}; run nfsargs addip addcons;" \ + "bootm ${kernel_addr} - ${fdt_addr}\0" \ + "net_self=tftp ${kernel_addr} ${bootfile}; " \ + "tftp ${fdt_addr} ${fdt_file}; " \ + "tftp ${ramdisk_addr} ${ramdisk_file}; " \ + "run ramargs addip; " \ + "bootm ${kernel_addr} ${ramdisk_addr} ${fdt_addr}\0" \ + "ramdisk_addr=ff210000\0" \ + "kernel_addr_self=ff050000\0" \ + "fdt_addr_self=ff200000\0" \ + "flash_self=run ramargs addip addcons;bootm ${kernel_addr_self}" \ + " ${ramdisk_addr} ${fdt_addr_self}\0" \ + "updateramdisk=era ${ramdisk_addr} +1f0000;tftpb ${kernel_addr} ${ramdisk_file};" \ + "cp.b ${kernel_addr} ${ramdisk_addr} ${filesize}\0" \ + "updatekernel=era ${kernel_addr_self} +1b0000;tftpb ${kernel_addr} ${kernel_file};" \ + "cp.b ${kernel_addr} ${kernel_addr_self} ${filesize}\0" \ + "updatefdt=era ${fdt_addr_self} +10000;tftpb ${fdt_addr} ${fdt_file};" \ + "cp.b ${fdt_addr} ${fdt_addr_self} ${filesize}\0" \ + "" + +#define CONFIG_BOOTCOMMAND "run net_nfs" +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#undef CONFIG_WATCHDOG /* disable platform specific watchdog */ + +/* + * Miscellaneous configurable options + */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00f00000 /* 1 ... 15 MB in DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } + +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0xFF000000 +#define CFG_FLASH_SIZE 32 +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +#define CFG_MAX_FLASH_BANKS 1 /* max num of flash banks */ +#define CFG_MAX_FLASH_SECT 512 /* max num of sects on one chip */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MONITOR_BASE TEXT_BASE +#if (CFG_MONITOR_BASE < CFG_FLASH_BASE) +#define CFG_RAMBOOT +#endif + +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256KB for Monitor */ + +#define CFG_ENV_IS_IN_FLASH + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + CFG_MONITOR_LEN) +#endif /* CFG_ENV_IS_IN_FLASH */ + +/* + * I2C Bus + */ +#define CONFIG_HARD_I2C 1 /* To enable I2C support */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F + +#define CFG_IMMR 0xF0000000 +#define CFG_DEFAULT_IMMR 0x0F010000 + +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2000 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/* Hard reset configuration word */ +#define CFG_HRCW_MASTER 0x0E028200 /* BPS=11 CIP=1 ISB=010 BMS=1 */ + +/* No slaves */ +#define CFG_HRCW_SLAVE1 0 +#define CFG_HRCW_SLAVE2 0 +#define CFG_HRCW_SLAVE3 0 +#define CFG_HRCW_SLAVE4 0 +#define CFG_HRCW_SLAVE5 0 +#define CFG_HRCW_SLAVE6 0 +#define CFG_HRCW_SLAVE7 0 + +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#define CFG_MALLOC_LEN (4096 << 10) /* Reserve 4 MB for malloc() */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +#define CFG_CACHELINE_SIZE 32 /* For MPC8260 CPUs */ +#if defined(CONFIG_CMD_KGDB) +# define CFG_CACHELINE_SHIFT 5 /* log base 2 of the above value */ +#endif + +#define CFG_HID0_INIT 0 +#define CFG_HID0_FINAL (HID0_ICE | HID0_IFEM | HID0_ABE) + +#define CFG_HID2 0 + +#define CFG_SIUMCR 0x00200000 +#define CFG_SYPCR 0xFFFFFFC3 +#define CFG_BCR 0x004c0000 +#define CFG_SCCR 0x0 + +/*----------------------------------------------------------------------- + * RMR - Reset Mode Register 5-5 + *----------------------------------------------------------------------- + * turn on Checkstop Reset Enable + */ +#define CFG_RMR 0 + +/*----------------------------------------------------------------------- + * TMCNTSC - Time Counter Status and Control 4-40 + *----------------------------------------------------------------------- + * Clear once per Second and Alarm Interrupt Status, Set 32KHz timersclk, + * and enable Time Counter + */ +#define CFG_TMCNTSC (TMCNTSC_SEC|TMCNTSC_ALR|TMCNTSC_TCF|TMCNTSC_TCE) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 4-42 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Set 32KHz timersclk, and enable + * Periodic timer + */ +#define CFG_PISCR (PISCR_PS|PISCR_PTF|PISCR_PTE) + +/*----------------------------------------------------------------------- + * RCCR - RISC Controller Configuration 13-7 + *----------------------------------------------------------------------- + */ +#define CFG_RCCR 0 + +/* + * Init Memory Controller: + * + * Bank Bus Machine PortSz Device + * ---- --- ------- ------ ------ + * 0 60x GPCM 32 bit FLASH + * 1 60x SDRAM 64 bit SDRAM + * 4 60x GPCM 16 bit I/O Ctrl + * + */ +/* Bank 0 - FLASH + */ +#define CFG_BR0_PRELIM ((CFG_FLASH_BASE & BRx_BA_MSK) |\ + BRx_PS_32 |\ + BRx_MS_GPCM_P |\ + BRx_V) + +#define CFG_OR0_PRELIM (0xff000020) + +/* Bank 1 - 60x bus SDRAM + */ +#define SDRAM_MAX_SIZE 0x08000000 /* max. 128 MB */ +#define CFG_GLOBAL_SDRAM_LIMIT (256 << 20) /* less than 256 MB */ + +#define CFG_MPTPR 0x2800 + +/*----------------------------------------------------------------------------- + * Address for Mode Register Set (MRS) command + *----------------------------------------------------------------------------- + */ +#define CFG_MRS_OFFS 0x00000110 +#define CFG_PSRT 0x13 + +#define CFG_BR1_PRELIM ((CFG_SDRAM_BASE & BRx_BA_MSK) |\ + BRx_PS_64 |\ + BRx_MS_SDRAM_P |\ + BRx_V) + +#define CFG_OR1_PRELIM CFG_OR1 + +/* SDRAM initialization values +*/ +#define CFG_OR1 0xfe002ec0 +#define CFG_PSDMR 0x004b36a3 + +/* IO on CS4 initialization values +*/ +#define CFG_IO_BASE 0xc0000000 +#define CFG_IO_SIZE 1 + +#define CFG_BR4_PRELIM ((CFG_IO_BASE & BRx_BA_MSK) |\ + BRx_PS_32 | BRx_MS_GPCM_L | BRx_V) + +#define CFG_OR4_PRELIM (0xfff80020) + +#define CFG_RESET_ADDRESS 0xFDFFFFFC /* "bad" address */ + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + +#define OF_CPU "PowerPC,8270@0" +#define OF_SOC "soc@f0000000" +#define OF_TBCLK (bd->bi_busfreq / 4) +#if defined(CONFIG_MUAS_DEV_BOARD) +#define OF_STDOUT_PATH "/soc/cpm/serial@11a90" +#else +#define OF_STDOUT_PATH "/soc/cpm/serial@11a80" +#endif + +#endif /* __CONFIG_H */ -- 1.5.6.1 -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany

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