August 2008 - U-Boot

[U-Boot] [PATCH 1/1] Adding bootlimit/bootcount feature for MPC5XXX on TQM5200 Boards
by Axel Beierlein 21 Aug '08

21 Aug '08

Tested with TQM5200S on STK52XX.200 Board Signed-off-by: Axel Beierlein <belatronix(a)web.de> --- cpu/mpc5xxx/cpu.c | 20 ++++++++++++++++++++ include/configs/TQM5200.h | 1 + include/mpc5xxx.h | 1 + 3 files changed, 22 insertions(+), 0 deletions(-) diff --git a/cpu/mpc5xxx/cpu.c b/cpu/mpc5xxx/cpu.c index ace1653..d87f42c 100644 --- a/cpu/mpc5xxx/cpu.c +++ b/cpu/mpc5xxx/cpu.c @@ -135,3 +135,23 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif } #endif + +#ifdef CONFIG_BOOTCOUNT_LIMIT + +void bootcount_store (ulong a) +{ + volatile ulong *save_addr = (volatile ulong *)(MPC5XXX_CDM_BRDCRMB); + + *save_addr = (BOOTCOUNT_MAGIC & 0xffff0000) | a; +} + +ulong bootcount_load (void) +{ + volatile ulong *save_addr = (volatile ulong *)(MPC5XXX_CDM_BRDCRMB); + + if ((*save_addr & 0xffff0000) != (BOOTCOUNT_MAGIC & 0xffff0000)) + return 0; + else + return (*save_addr & 0x0000ffff); +} +#endif /* CONFIG_BOOTCOUNT_LIMIT */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bfb478a..5fb5f80 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -55,6 +55,7 @@ #define CONFIG_PSC_CONSOLE 1 /* console is on PSC1 */ #define CONFIG_BAUDRATE 115200 /* ... at 115200 bps */ #define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_BOOTCOUNT_LIMIT 1 #ifdef CONFIG_FO300 #define CFG_DEVICE_NULLDEV 1 /* enable null device */ diff --git a/include/mpc5xxx.h b/include/mpc5xxx.h index 5d11ef0..0f5bee5 100644 --- a/include/mpc5xxx.h +++ b/include/mpc5xxx.h @@ -137,6 +137,7 @@ /* Clock Distribution Module */ #define MPC5XXX_CDM_JTAGID (MPC5XXX_CDM + 0x0000) #define MPC5XXX_CDM_PORCFG (MPC5XXX_CDM + 0x0004) +#define MPC5XXX_CDM_BRDCRMB (MPC5XXX_CDM + 0x0008) #define MPC5XXX_CDM_CFG (MPC5XXX_CDM + 0x000c) #define MPC5XXX_CDM_48_FDC (MPC5XXX_CDM + 0x0010) #define MPC5XXX_CDM_SRESET (MPC5XXX_CDM + 0x0020) -- 1.5.4.3

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[U-Boot] [PATCH] mod_i2c_mem() bugfix
by Peter Tyser 21 Aug '08

21 Aug '08

The last used chip, address, and address length were not being stored for the imm and imn commands. Signed-off-by: Peter Tyser <ptyser(a)xes-inc.com> --- common/cmd_i2c.c | 6 +++--- 1 files changed, 3 insertions(+), 3 deletions(-) diff --git a/common/cmd_i2c.c b/common/cmd_i2c.c index aac7e9a..91bf25b 100644 --- a/common/cmd_i2c.c +++ b/common/cmd_i2c.c @@ -529,9 +529,9 @@ mod_i2c_mem(cmd_tbl_t *cmdtp, int incrflag, int flag, int argc, char *argv[]) } } while (nbytes); - chip = i2c_mm_last_chip; - addr = i2c_mm_last_addr; - alen = i2c_mm_last_alen; + i2c_mm_last_chip = chip; + i2c_mm_last_addr = addr; + i2c_mm_last_alen = alen; return 0; } -- 1.5.4.3

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[U-Boot] [RFC] setting pio modes for IDE devices
by Steven A. Falco 21 Aug '08

21 Aug '08

The following patch adds the ability to call-out from the ide_ident routine to a board-specific routine to set the PIO mode of an attached device. This feature is controlled by the preprocessor variable CONFIG_TUNE_CFA. cmd_ide.c is modified to use the "drive identify information" read from the device to compute a pio mode in the range 0 to 6. This is then passed to a board-specific routine, ide_set_piomode, to set the mode in hardware. Two other files are touched: file ata.h, to include word 163, which is the "advanced CF parameters", and file ide.h, to add a prototype for the board-specific routine (again controlled by the CONFIG_TUNE_CFA variable). Please let me know if this or some variation on the idea would be acceptible. Steve diff --git a/common/cmd_ide.c b/common/cmd_ide.c index b4d9719..00b85db 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -1054,6 +1054,10 @@ static void ide_ident (block_dev_desc_t *dev_desc) int do_retry = 0; #endif +#ifdef CONFIG_TUNE_CFA + int pio_mode; +#endif + #if 0 int mode, cycle_time; #endif @@ -1169,6 +1173,40 @@ static void ide_ident (block_dev_desc_t *dev_desc) else dev_desc->removable = 0; +#ifdef CONFIG_TUNE_CFA + /* Mode 0 - 2 only, are directly determined by word 51. */ + pio_mode = iop->tPIO; + if(pio_mode > 2) { + printf("WARNING: Invalid PIO (word 51 = %d).\n", pio_mode); + pio_mode = 0; /* Force it to dead slow, and hope for the best... */ + } + + /* Any CompactFlash Storage Card that supports PIO mode 3 or above + * shall set bit 1 of word 53 to one and support the fields contained + * in words 64 through 70. + */ + if(iop->field_valid & 0x02) { + /* Mode 3 and above are possible. Check in order from slow + * to fast, so we wind up with the highest mode allowed. + */ + if(iop->eide_pio_modes & 0x01) { + pio_mode = 3; + } + if(iop->eide_pio_modes & 0x02) { + pio_mode = 4; + } + if((iop->cf_advanced_caps & 0x07) == 0x01) { + pio_mode = 5; + } + if((iop->cf_advanced_caps & 0x07) == 0x02) { + pio_mode = 6; + } + } + + /* System-specific, depends on bus speeds, etc. */ + ide_set_piomode(pio_mode); +#endif /* CONFIG_TUNE_CFA */ + #if 0 /* * Drive PIO mode autoselection diff --git a/include/ata.h b/include/ata.h index aa6e90d..3269636 100644 --- a/include/ata.h +++ b/include/ata.h @@ -294,7 +294,9 @@ typedef struct hd_driveid { unsigned short words130_155[26];/* reserved vendor words 130-155 */ unsigned short word156; unsigned short words157_159[3];/* reserved vendor words 157-159 */ - unsigned short words160_255[95];/* reserved words 160-255 */ + unsigned short words160_162[3];/* reserved words 160-162 */ + unsigned short cf_advanced_caps; + unsigned short words164_255[92];/* reserved words 164-255 */ } hd_driveid_t; diff --git a/include/ide.h b/include/ide.h index 222f4f8..ae4624b 100644 --- a/include/ide.h +++ b/include/ide.h @@ -54,4 +54,9 @@ void ide_init(void); ulong ide_read(int device, lbaint_t blknr, ulong blkcnt, void *buffer); ulong ide_write(int device, lbaint_t blknr, ulong blkcnt, void *buffer); +#ifdef CONFIG_TUNE_CFA +/* Returns 0 on success, else returns 1. pio_mode can be 0 through 6. */ +extern int ide_set_piomode(int pio_mode); +#endif + #endif /* _IDE_H */

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Re: [U-Boot] [U-boot-Users][GIT PULL] Please pull coldfire tree
by Jean-Christophe PLAGNIOL-VILLARD 21 Aug '08

21 Aug '08

On 22:43 Thu 14 Aug , Wolfgang Denk wrote: > Dear John Rigby, > > In message <48A47C31.4010104(a)freescale.com> you wrote: > > > > The following changes since commit 855efd04e440754297769849f4d7fb52c7dc6bf4: > > Wolfgang Denk (1): > > Merge branch 'master' of git://git.denx.de/u-boot-cfi-flash > > > > are available in the git repository at: > > > > git://git.denx.de/u-boot-coldfire.git master > > > > TsiChung Liew (13): > > ColdFire: Fix M5253EVB dram bring up issue > > ColdFire: Raise M5253EVBE uart baudrate to 115200 bps > > ColdFire: Add M5253DEMO platform support for MCF5253 > > ColdFire: Use CFI Flash driver for M54455EVB > > ColdFire: Add SSPI feature for MCF5445x > > ColdFire: Implement SBF feature for M5445EVB > > ColdFire: Add Serial Flash support for M54455EVB > > ColdFire: Add M54451EVB platform support for MCF5445x > > ColdFire: Move m5271evb from board to board/freescale > > ColdFire: Move m5272c3 from board to board/freescale > > ColdFire: Move m5282evb from board to board/freescale > > ColdFire: Multiple fixes for M5282EVB > > Change CFG_ENV_SIZE to CFG_ENV_SECT_SIZE for SPI sector erase Hi TsiChung, Note I've rename CFG_FLASH_CFI_DRIVER to CONFIG_FLASH_CFI_DRIVER I'll send patch for your new boards Best Regards, J.

3 4

[U-Boot] [cfi-flash] Please pull git://www.denx.de/git/u-boot-cfi-flash.git
by Stefan Roese 21 Aug '08

21 Aug '08

The following changes since commit fcd69a1a57fb2af4d26201422095a4be9f36963e: Kumar Gala (1): Clean up usage of icache_disable/dcache_disable are available in the git repository at: git://www.denx.de/git/u-boot-cfi-flash.git master Nick Spence (1): CFI: Add CFI_CMDSET_INTEL_EXTENDED to fix flash_real_protect() TsiChung Liew (1): CFI: Fix AMD Legacy sector protect drivers/mtd/cfi_flash.c | 13 ++++++++++--- 1 files changed, 10 insertions(+), 3 deletions(-)

2 1

[U-Boot] Pull request - net
by Ben Warren 21 Aug '08

21 Aug '08

Wolfgang, The following changes since commit fcd69a1a57fb2af4d26201422095a4be9f36963e: Kumar Gala (1): Clean up usage of icache_disable/dcache_disable are available in the git repository at: git://git.denx.de/u-boot-net.git master TsiChung Liew (1): Fix dm9000 receive status and len little endian issue Yoshihiro Shimoda (1): rtl8169: add support for RTL8110SCL drivers/net/dm9000x.c | 16 ++++++++++------ drivers/net/rtl8169.c | 28 ++++++++++++++++++++++------ 2 files changed, 32 insertions(+), 12 deletions(-) regards, Ben

2 1

[U-Boot] [PATCH] RTC: Fix Makefile problem with COBJS-$(CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338)
by Stefan Roese 20 Aug '08

20 Aug '08

This "||" doesn't seem to work. So I created 2 lines, one for each config option. Not sure if this really can be combined into one line in the Makefile but this approach seems clearer to me. And it works. Signed-off-by: Stefan Roese <sr(a)denx.de> --- drivers/rtc/Makefile | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af3ee5..0c048c5 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -32,8 +32,9 @@ COBJS-y += date.o COBJS-$(CONFIG_RTC_DS12887) += ds12887.o COBJS-$(CONFIG_RTC_DS1302) += ds1302.o COBJS-$(CONFIG_RTC_DS1306) += ds1306.o -COBJS-$(CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338) += ds1307.o +COBJS-$(CONFIG_RTC_DS1307) += ds1307.o COBJS-$(CONFIG_RTC_DS1337) += ds1337.o +COBJS-$(CONFIG_RTC_DS1338) += ds1307.o COBJS-$(CONFIG_RTC_DS1374) += ds1374.o COBJS-$(CONFIG_RTC_DS1556) += ds1556.o COBJS-$(CONFIG_RTC_DS164x) += ds164x.o -- 1.5.6.5

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[U-Boot] [PATCH] ppc4xx: Optimize PLB4 arbiter and memory queue settings for PPC 440SP/SPe, PPC405EX and PPC 460EX/GT
by Prodyut Hazarika 20 Aug '08

20 Aug '08

Read pipeline depth set to 4 for PPC440SP/SPE, PPC405EX, PPC460EX/GT/SX processors Moved PLB4 Arbiter register definitions to ppc4xx.h since it is shared across processors Optimize Memory Queue settings for PPC440SP/SPE and PPC460EX/GT/SX processors Add register bit definitions for Memory Queue Configuration registers Signed-off-by: Prodyut Hazarika <phazarika(a)amcc.com> --- cpu/ppc4xx/44x_spd_ddr2.c | 27 ++++++++++++++++--- cpu/ppc4xx/cpu_init.c | 16 ++++++++++- include/asm-ppc/ppc4xx-sdram.h | 48 ++++++++++++++++++++++----------- include/ppc440.h | 47 --------------------------------- include/ppc4xx.h | 56 ++++++++++++++++++++++++++++++++++++++++ 5 files changed, 126 insertions(+), 68 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 1c36324..0431754 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -2172,6 +2172,11 @@ static void program_memory_queue(unsigned long *dimm_populated, unsigned long i; unsigned long bank_0_populated = 0; phys_size_t total_size = 0; +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + unsigned long val; +#endif /*------------------------------------------------------------------ * Reset the rank_base_address. @@ -2249,17 +2254,31 @@ static void program_memory_queue(unsigned long *dimm_populated, } } -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + /* - * Enable high bandwidth access on 460EX/GT. - * This should/could probably be done on other - * PPC's too, like 440SPe. + * Enable high bandwidth access * This is currently not used, but with this setup * it is possible to use it later on in e.g. the Linux * EMAC driver for performance gain. */ mtdcr(SDRAM_PLBADDULL, 0x00000000); /* MQ0_BAUL */ mtdcr(SDRAM_PLBADDUHB, 0x00000008); /* MQ0_BAUH */ + + /* + * Set optimal value for Memory Queue HB/LL Configuration registers + */ + + val = (mfdcr(SDRAM_CONF1HB) | SDRAM_CONF1HB_AAFR | SDRAM_CONF1HB_RPEN | SDRAM_CONF1HB_RFTE); + mtdcr(SDRAM_CONF1HB, val); + + val = (mfdcr(SDRAM_CONF1LL) | SDRAM_CONF1LL_AAFR | SDRAM_CONF1LL_RPEN | SDRAM_CONF1LL_RFTE); + mtdcr(SDRAM_CONF1LL, val); + + val = (mfdcr(SDRAM_CONFPATHB) | SDRAM_CONFPATHB_TPEN); + mtdcr(SDRAM_CONFPATHB, val); #endif } diff --git a/cpu/ppc4xx/cpu_init.c b/cpu/ppc4xx/cpu_init.c index e2d0402..c7c429e 100644 --- a/cpu/ppc4xx/cpu_init.c +++ b/cpu/ppc4xx/cpu_init.c @@ -138,7 +138,9 @@ void reconfigure_pll(u32 new_cpu_freq) void cpu_init_f (void) { -#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) +#if defined(CONFIG_WATCHDOG) || defined(CONFIG_440GX) || defined(CONFIG_460EX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || defined(CONFIG_405EX) || \ + defined(CONFIG_460GT) || defined(CONFIG_460SX) u32 val; #endif @@ -301,6 +303,18 @@ cpu_init_f (void) val |= 0x400; mtsdr(SDR0_USB2HOST_CFG, val); #endif /* CONFIG_460EX */ + +#if defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_405EX) || defined(CONFIG_460SX) + /* + * Set PLB4 arbiter (Segment 0 and 1) to 4 deep pipeline read + */ + val = (mfdcr(plb0_acr) & ~plb0_acr_rdp_mask) | plb0_acr_rdp_4deep; + mtdcr(plb0_acr, val); + val = (mfdcr(plb1_acr) & ~plb1_acr_rdp_mask) | plb1_acr_rdp_4deep; + mtdcr(plb1_acr, val); +#endif /* CONFIG_440SP/SPE || CONFIG_460EX/GT || CONFIG_405EX */ } /* diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index df787b3..0174d62 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -259,23 +259,39 @@ /* * Memory queue defines */ -#define SDRAMQ_DCR_BASE 0x040 - -#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ -#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ -#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ -#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ -#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ -#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ -#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ -#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ -#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ -#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ -#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ -#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ -#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ -#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ -#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ +#define SDRAMQ_DCR_BASE 0x040 + +#define SDRAM_R0BAS (SDRAMQ_DCR_BASE+0x0) /* rank 0 base address & size */ +#define SDRAM_R1BAS (SDRAMQ_DCR_BASE+0x1) /* rank 1 base address & size */ +#define SDRAM_R2BAS (SDRAMQ_DCR_BASE+0x2) /* rank 2 base address & size */ +#define SDRAM_R3BAS (SDRAMQ_DCR_BASE+0x3) /* rank 3 base address & size */ +#define SDRAM_CONF1HB (SDRAMQ_DCR_BASE+0x5) /* configuration 1 HB */ +#define SDRAM_CONF1HB_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ +#define SDRAM_CONF1HB_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ +#define SDRAM_CONF1HB_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ +#define SDRAM_CONF1HB_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1HB_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ +#define SDRAM_CONF1HB_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ + +#define SDRAM_ERRSTATHB (SDRAMQ_DCR_BASE+0x7) /* error status HB */ +#define SDRAM_ERRADDUHB (SDRAMQ_DCR_BASE+0x8) /* error address upper 32 HB */ +#define SDRAM_ERRADDLHB (SDRAMQ_DCR_BASE+0x9) /* error address lower 32 HB */ +#define SDRAM_PLBADDULL (SDRAMQ_DCR_BASE+0xA) /* PLB base address upper 32 LL */ +#define SDRAM_CONF1LL (SDRAMQ_DCR_BASE+0xB) /* configuration 1 LL */ +#define SDRAM_CONF1LL_AAFR 0x80000000 /* Address Ack on First Request - Bit 0 */ +#define SDRAM_CONF1LL_PRPD 0x00080000 /* PLB Read pipeline Disable - Bit 12 */ +#define SDRAM_CONF1LL_PWPD 0x00040000 /* PLB Write pipeline Disable - Bit 13 */ +#define SDRAM_CONF1LL_PRW 0x00020000 /* PLB Read Wait - Bit 14 */ +#define SDRAM_CONF1LL_RPEN 0x00000800 /* Read Passing Enable - Bit 20 */ +#define SDRAM_CONF1LL_RFTE 0x00000400 /* Read Flow Through Enable - Bit 21 */ + +#define SDRAM_ERRSTATLL (SDRAMQ_DCR_BASE+0xC) /* error status LL */ +#define SDRAM_ERRADDULL (SDRAMQ_DCR_BASE+0xD) /* error address upper 32 LL */ +#define SDRAM_ERRADDLLL (SDRAMQ_DCR_BASE+0xE) /* error address lower 32 LL */ +#define SDRAM_CONFPATHB (SDRAMQ_DCR_BASE+0xF) /* configuration between paths */ +#define SDRAM_CONFPATHB_TPEN 0x08000000 /* Transaction Passing Enable - Bit 4 */ + +#define SDRAM_PLBADDUHB (SDRAMQ_DCR_BASE+0x10) /* PLB base address upper 32 LL */ #if !defined(CONFIG_405EX) /* diff --git a/include/ppc440.h b/include/ppc440.h index 92db15f..3584fd2 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -341,53 +341,6 @@ #define PLB4_ACR_WRP (0x80000000 >> 7) -/* Nebula PLB4 Arbiter - PowerPC440EP */ -#define PLB_ARBITER_BASE 0x80 - -#define plb0_revid (PLB_ARBITER_BASE+ 0x00) -#define plb0_acr (PLB_ARBITER_BASE+ 0x01) -#define plb0_acr_ppm_mask 0xF0000000 -#define plb0_acr_ppm_fixed 0x00000000 -#define plb0_acr_ppm_fair 0xD0000000 -#define plb0_acr_hbu_mask 0x08000000 -#define plb0_acr_hbu_disabled 0x00000000 -#define plb0_acr_hbu_enabled 0x08000000 -#define plb0_acr_rdp_mask 0x06000000 -#define plb0_acr_rdp_disabled 0x00000000 -#define plb0_acr_rdp_2deep 0x02000000 -#define plb0_acr_rdp_3deep 0x04000000 -#define plb0_acr_rdp_4deep 0x06000000 -#define plb0_acr_wrp_mask 0x01000000 -#define plb0_acr_wrp_disabled 0x00000000 -#define plb0_acr_wrp_2deep 0x01000000 - -#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) -#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) -#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) -#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) -#define plb0_ccr (PLB_ARBITER_BASE+ 0x08) - -#define plb1_acr (PLB_ARBITER_BASE+ 0x09) -#define plb1_acr_ppm_mask 0xF0000000 -#define plb1_acr_ppm_fixed 0x00000000 -#define plb1_acr_ppm_fair 0xD0000000 -#define plb1_acr_hbu_mask 0x08000000 -#define plb1_acr_hbu_disabled 0x00000000 -#define plb1_acr_hbu_enabled 0x08000000 -#define plb1_acr_rdp_mask 0x06000000 -#define plb1_acr_rdp_disabled 0x00000000 -#define plb1_acr_rdp_2deep 0x02000000 -#define plb1_acr_rdp_3deep 0x04000000 -#define plb1_acr_rdp_4deep 0x06000000 -#define plb1_acr_wrp_mask 0x01000000 -#define plb1_acr_wrp_disabled 0x00000000 -#define plb1_acr_wrp_2deep 0x01000000 - -#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) -#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) -#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) -#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) - /* Pin Function Control Register 1 */ #define SDR0_PFC1 0x4101 #define SDR0_PFC1_U1ME_MASK 0x02000000 /* UART1 Mode Enable */ diff --git a/include/ppc4xx.h b/include/ppc4xx.h index c71da60..e1613dd 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -46,6 +46,62 @@ #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif +/* PLB4 CrossBar Arbiter Core supported across PPC4xx families */ +#if defined(CONFIG_405EX) || \ + defined(CONFIG_440EP) || defined(CONFIG_440EPX) || \ + defined(CONFIG_440GR) || defined(CONFIG_440GRX) || \ + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) + +#define PLB_ARBITER_BASE 0x80 + +#define plb0_revid (PLB_ARBITER_BASE+ 0x00) +#define plb0_acr (PLB_ARBITER_BASE+ 0x01) +#define plb0_acr_ppm_mask 0xF0000000 +#define plb0_acr_ppm_fixed 0x00000000 +#define plb0_acr_ppm_fair 0xD0000000 +#define plb0_acr_hbu_mask 0x08000000 +#define plb0_acr_hbu_disabled 0x00000000 +#define plb0_acr_hbu_enabled 0x08000000 +#define plb0_acr_rdp_mask 0x06000000 +#define plb0_acr_rdp_disabled 0x00000000 +#define plb0_acr_rdp_2deep 0x02000000 +#define plb0_acr_rdp_3deep 0x04000000 +#define plb0_acr_rdp_4deep 0x06000000 +#define plb0_acr_wrp_mask 0x01000000 +#define plb0_acr_wrp_disabled 0x00000000 +#define plb0_acr_wrp_2deep 0x01000000 + +#define plb0_besrl (PLB_ARBITER_BASE+ 0x02) +#define plb0_besrh (PLB_ARBITER_BASE+ 0x03) +#define plb0_bearl (PLB_ARBITER_BASE+ 0x04) +#define plb0_bearh (PLB_ARBITER_BASE+ 0x05) +#define plb0_ccr (PLB_ARBITER_BASE+ 0x08) + +#define plb1_acr (PLB_ARBITER_BASE+ 0x09) +#define plb1_acr_ppm_mask 0xF0000000 +#define plb1_acr_ppm_fixed 0x00000000 +#define plb1_acr_ppm_fair 0xD0000000 +#define plb1_acr_hbu_mask 0x08000000 +#define plb1_acr_hbu_disabled 0x00000000 +#define plb1_acr_hbu_enabled 0x08000000 +#define plb1_acr_rdp_mask 0x06000000 +#define plb1_acr_rdp_disabled 0x00000000 +#define plb1_acr_rdp_2deep 0x02000000 +#define plb1_acr_rdp_3deep 0x04000000 +#define plb1_acr_rdp_4deep 0x06000000 +#define plb1_acr_wrp_mask 0x01000000 +#define plb1_acr_wrp_disabled 0x00000000 +#define plb1_acr_wrp_2deep 0x01000000 + +#define plb1_besrl (PLB_ARBITER_BASE+ 0x0A) +#define plb1_besrh (PLB_ARBITER_BASE+ 0x0B) +#define plb1_bearl (PLB_ARBITER_BASE+ 0x0C) +#define plb1_bearh (PLB_ARBITER_BASE+ 0x0D) + +#endif /* 440EP/EPX 440GR/GRX 440SP/SPE 460EX/GT/SX 405EX*/ + #if defined(CONFIG_440) /* * Enable long long (%ll ...) printf format on 440 PPC's since most of -- 1.5.5

1 0

[U-Boot] [PATCH] at91: Update board NAND drivers to current API.
by Scott Wood 20 Aug '08

20 Aug '08

Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- I don't have hardware to test, so any help in that regard is appreciated. Applied to u-boot-nand-flash. board/atmel/at91cap9adk/nand.c | 37 ++++++++++++++++++------------------- board/atmel/at91sam9260ek/nand.c | 37 ++++++++++++++++++------------------- board/atmel/at91sam9261ek/nand.c | 37 ++++++++++++++++++------------------- board/atmel/at91sam9263ek/nand.c | 37 ++++++++++++++++++------------------- board/atmel/at91sam9rlek/nand.c | 37 ++++++++++++++++++------------------- 5 files changed, 90 insertions(+), 95 deletions(-) diff --git a/board/atmel/at91cap9adk/nand.c b/board/atmel/at91cap9adk/nand.c index 0432ef1..1dec558 100644 --- a/board/atmel/at91cap9adk/nand.c +++ b/board/atmel/at91cap9adk/nand.c @@ -37,36 +37,35 @@ #define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */ -static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void at91cap9adk_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - switch (cmd) { - case NAND_CTL_SETCLE: - IO_ADDR_W |= MASK_CLE; - break; - case NAND_CTL_SETALE: - IO_ADDR_W |= MASK_ALE; - break; - case NAND_CTL_CLRNCE: - at91_set_gpio_value(AT91_PIN_PD15, 1); - break; - case NAND_CTL_SETNCE: - at91_set_gpio_value(AT91_PIN_PD15, 0); - break; + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; } - this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } int board_nand_init(struct nand_chip *nand) { - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; #ifdef CFG_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif - nand->hwcontrol = at91cap9adk_nand_hwcontrol; + nand->cmd_ctrl = at91cap9adk_nand_hwcontrol; nand->chip_delay = 20; return 0; diff --git a/board/atmel/at91sam9260ek/nand.c b/board/atmel/at91sam9260ek/nand.c index 9738f0f..665e35c 100644 --- a/board/atmel/at91sam9260ek/nand.c +++ b/board/atmel/at91sam9260ek/nand.c @@ -37,27 +37,26 @@ #define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */ -static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void at91sam9260ek_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - switch (cmd) { - case NAND_CTL_SETCLE: - IO_ADDR_W |= MASK_CLE; - break; - case NAND_CTL_SETALE: - IO_ADDR_W |= MASK_ALE; - break; - case NAND_CTL_CLRNCE: - at91_set_gpio_value(AT91_PIN_PC14, 1); - break; - case NAND_CTL_SETNCE: - at91_set_gpio_value(AT91_PIN_PC14, 0); - break; + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; } - this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } static int at91sam9260ek_nand_ready(struct mtd_info *mtd) @@ -67,11 +66,11 @@ static int at91sam9260ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; #ifdef CFG_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif - nand->hwcontrol = at91sam9260ek_nand_hwcontrol; + nand->cmd_ctrl = at91sam9260ek_nand_hwcontrol; nand->dev_ready = at91sam9260ek_nand_ready; nand->chip_delay = 20; diff --git a/board/atmel/at91sam9261ek/nand.c b/board/atmel/at91sam9261ek/nand.c index 35b26db..fccb9d7 100644 --- a/board/atmel/at91sam9261ek/nand.c +++ b/board/atmel/at91sam9261ek/nand.c @@ -37,27 +37,26 @@ #define MASK_ALE (1 << 22) /* our ALE is AD22 */ #define MASK_CLE (1 << 21) /* our CLE is AD21 */ -static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void at91sam9261ek_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - switch (cmd) { - case NAND_CTL_SETCLE: - IO_ADDR_W |= MASK_CLE; - break; - case NAND_CTL_SETALE: - IO_ADDR_W |= MASK_ALE; - break; - case NAND_CTL_CLRNCE: - at91_set_gpio_value(AT91_PIN_PC14, 1); - break; - case NAND_CTL_SETNCE: - at91_set_gpio_value(AT91_PIN_PC14, 0); - break; + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PC14, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; } - this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } static int at91sam9261ek_nand_ready(struct mtd_info *mtd) @@ -67,11 +66,11 @@ static int at91sam9261ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; #ifdef CFG_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif - nand->hwcontrol = at91sam9261ek_nand_hwcontrol; + nand->cmd_ctrl = at91sam9261ek_nand_hwcontrol; nand->dev_ready = at91sam9261ek_nand_ready; nand->chip_delay = 20; diff --git a/board/atmel/at91sam9263ek/nand.c b/board/atmel/at91sam9263ek/nand.c index 5079972..250ec7f 100644 --- a/board/atmel/at91sam9263ek/nand.c +++ b/board/atmel/at91sam9263ek/nand.c @@ -37,27 +37,26 @@ #define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */ -static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void at91sam9263ek_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - switch (cmd) { - case NAND_CTL_SETCLE: - IO_ADDR_W |= MASK_CLE; - break; - case NAND_CTL_SETALE: - IO_ADDR_W |= MASK_ALE; - break; - case NAND_CTL_CLRNCE: - at91_set_gpio_value(AT91_PIN_PD15, 1); - break; - case NAND_CTL_SETNCE: - at91_set_gpio_value(AT91_PIN_PD15, 0); - break; + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PD15, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; } - this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } static int at91sam9263ek_nand_ready(struct mtd_info *mtd) @@ -67,11 +66,11 @@ static int at91sam9263ek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; #ifdef CFG_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif - nand->hwcontrol = at91sam9263ek_nand_hwcontrol; + nand->cmd_ctrl = at91sam9263ek_nand_hwcontrol; nand->dev_ready = at91sam9263ek_nand_ready; nand->chip_delay = 20; diff --git a/board/atmel/at91sam9rlek/nand.c b/board/atmel/at91sam9rlek/nand.c index 5af1a31..eb342b8 100644 --- a/board/atmel/at91sam9rlek/nand.c +++ b/board/atmel/at91sam9rlek/nand.c @@ -37,27 +37,26 @@ #define MASK_ALE (1 << 21) /* our ALE is AD21 */ #define MASK_CLE (1 << 22) /* our CLE is AD22 */ -static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, int cmd) +static void at91sam9rlek_nand_hwcontrol(struct mtd_info *mtd, + int cmd, unsigned int ctrl) { struct nand_chip *this = mtd->priv; - ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; - IO_ADDR_W &= ~(MASK_ALE|MASK_CLE); - switch (cmd) { - case NAND_CTL_SETCLE: - IO_ADDR_W |= MASK_CLE; - break; - case NAND_CTL_SETALE: - IO_ADDR_W |= MASK_ALE; - break; - case NAND_CTL_CLRNCE: - at91_set_gpio_value(AT91_PIN_PB6, 1); - break; - case NAND_CTL_SETNCE: - at91_set_gpio_value(AT91_PIN_PB6, 0); - break; + if (ctrl & NAND_CTRL_CHANGE) { + ulong IO_ADDR_W = (ulong) this->IO_ADDR_W; + IO_ADDR_W &= ~(MASK_ALE | MASK_CLE); + + if (ctrl & NAND_CLE) + IO_ADDR_W |= MASK_CLE; + if (ctrl & NAND_ALE) + IO_ADDR_W |= MASK_ALE; + + at91_set_gpio_value(AT91_PIN_PB6, !(ctrl & NAND_NCE)); + this->IO_ADDR_W = (void *) IO_ADDR_W; } - this->IO_ADDR_W = (void *) IO_ADDR_W; + + if (cmd != NAND_CMD_NONE) + writeb(cmd, this->IO_ADDR_W); } static int at91sam9rlek_nand_ready(struct mtd_info *mtd) @@ -67,11 +66,11 @@ static int at91sam9rlek_nand_ready(struct mtd_info *mtd) int board_nand_init(struct nand_chip *nand) { - nand->eccmode = NAND_ECC_SOFT; + nand->ecc.mode = NAND_ECC_SOFT; #ifdef CFG_NAND_DBW_16 nand->options = NAND_BUSWIDTH_16; #endif - nand->hwcontrol = at91sam9rlek_nand_hwcontrol; + nand->cmd_ctrl = at91sam9rlek_nand_hwcontrol; nand->dev_ready = at91sam9rlek_nand_ready; nand->chip_delay = 20; -- 1.5.6.rc1.6.gc53ad

3 2

[U-Boot] [PATCH] rtc: Fix drivers/rtc/Makefile for DS1307/DS1338 chips
by Matthias Fuchs 20 Aug '08

20 Aug '08

Boards with DS1307/DS1338 rtc like DU440 and kilauea fail to build without this fix. Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- drivers/rtc/Makefile | 3 ++- 1 files changed, 2 insertions(+), 1 deletions(-) diff --git a/drivers/rtc/Makefile b/drivers/rtc/Makefile index 2af3ee5..af101fa 100644 --- a/drivers/rtc/Makefile +++ b/drivers/rtc/Makefile @@ -32,7 +32,8 @@ COBJS-y += date.o COBJS-$(CONFIG_RTC_DS12887) += ds12887.o COBJS-$(CONFIG_RTC_DS1302) += ds1302.o COBJS-$(CONFIG_RTC_DS1306) += ds1306.o -COBJS-$(CONFIG_RTC_DS1307 || CONFIG_RTC_DS1338) += ds1307.o +COBJS-$(CONFIG_RTC_DS1307) += ds1307.o +COBJS-$(CONFIG_RTC_DS1338) += ds1307.o COBJS-$(CONFIG_RTC_DS1337) += ds1337.o COBJS-$(CONFIG_RTC_DS1374) += ds1374.o COBJS-$(CONFIG_RTC_DS1556) += ds1556.o -- 1.5.3

2 1