August 2008 - U-Boot

[U-Boot] [PATCH] sh: Fix compile error sh7785lcr board
by Nobuhiro Iwamatsu 28 Aug '08

28 Aug '08

This boards used old type preprocessor. This patch fix compile error. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- include/configs/sh7785lcr.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/sh7785lcr.h b/include/configs/sh7785lcr.h index e27c5d1..c4cb065 100644 --- a/include/configs/sh7785lcr.h +++ b/include/configs/sh7785lcr.h @@ -76,7 +76,7 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF1 1 #define CONFIG_SCIF_EXT_CLOCK 1 #undef CFG_CONSOLE_INFO_QUIET @@ -103,8 +103,8 @@ #define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI -#define CFG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO #define CFG_FLASH_BASE (SH7785LCR_FLASH_BASE_1) -- 1.5.6.3

1 0

[U-Boot] [PATCH] sh: Fix compile error rsk7203 board
by Nobuhiro Iwamatsu 28 Aug '08

28 Aug '08

This boards used old type preprocessor. This patch fix compile error. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- include/configs/rsk7203.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/include/configs/rsk7203.h b/include/configs/rsk7203.h index 270c149..54d2032 100644 --- a/include/configs/rsk7203.h +++ b/include/configs/rsk7203.h @@ -65,7 +65,7 @@ #define CFG_BAUDRATE_TABLE { 115200 } /* SCIF */ -#define CFG_SCIF_CONSOLE 1 +#define CONFIG_SCIF_CONSOLE 1 #define CONFIG_CONS_SCIF0 1 #define CFG_MEMTEST_START RSK7203_SDRAM_BASE @@ -82,9 +82,9 @@ #define CFG_BOOTMAPSZ (8 * 1024 * 1024) /* FLASH */ +#define CONFIG_FLASH_CFI_DRIVER #define CFG_FLASH_CFI #define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT -#define CFG_FLASH_CFI_DRIVER #undef CFG_FLASH_QUIET_TEST #define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ #define CFG_FLASH_BASE RSK7203_FLASH_BASE_1 -- 1.5.6.3

1 0

[U-Boot] [PATCH] sh: Add support sh2 to MAKEALL
by Nobuhiro Iwamatsu 28 Aug '08

28 Aug '08

Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- MAKEALL | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/MAKEALL b/MAKEALL index 56cc38d..752ed68 100755 --- a/MAKEALL +++ b/MAKEALL @@ -803,7 +803,7 @@ do |mips|mips_el \ |nios|nios2 \ |ppc|5xx|5xxx|512x|8xx|8220|824x|8260|83xx|85xx|86xx|4xx|7xx|74xx|TSEC \ - |sh|sh3|sh4 \ + |sh|sh2|sh3|sh4 \ |sparc \ |x86|I486 \ ) -- 1.5.6.3

1 0

[U-Boot] [PATCH 2/2] sh: rsk7203: Add support pkt_data_pull and pkt_data_push function
by Nobuhiro Iwamatsu 28 Aug '08

28 Aug '08

Add function of smc911x, pkt_data_pull and pkt_data_push. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- board/rsk7203/rsk7203.c | 20 ++++++++++++++++++++ 1 files changed, 20 insertions(+), 0 deletions(-) diff --git a/board/rsk7203/rsk7203.c b/board/rsk7203/rsk7203.c index beb943e..99cc10a 100644 --- a/board/rsk7203/rsk7203.c +++ b/board/rsk7203/rsk7203.c @@ -48,3 +48,23 @@ int dram_init(void) void led_set_state(unsigned short value) { } + +/* + * The RSK board has the SMSC9118 wired up 'incorrectly'. + * Byte-swapping is necessary, and so poor performance is inevitable. + * This problem cannot evade by the swap function of CHIP, this can + * evade by software Byte-swapping. + * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push + * functions necessary to solve this problem. + */ +u32 pkt_data_pull(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return (((swab16(*addr_16) << 16) & 0xFFFF0000)|swab16(*(addr_16 + 1))); +} + +void pkt_data_push(u32 addr, u32 val) +{ + *(volatile u16 *)(addr + 2) = swab16((u16)val); + *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); +} -- 1.5.6.3

1 0

[U-Boot] BUG: hang with an empty flash (due to recent bootm changes) bisected
by Ira Snyder 28 Aug '08

28 Aug '08

Hello, I'm working with an MPC8349EMDS board, doing testing. I usually just leave the flash blank, and let the autoboot time out, where it sits with the following message: Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! => Since commit 396f635b8ff3ccbc38d75d5eda98444c6466810a, this is no longer the case. The board hangs up after the autoboot times out, showing the following: Hit any key to stop autoboot: 0 Wrong Image Format for bootm command ERROR: can't get kernel image! XIP Invalid Image ... OK OK NOTE: If you press a key before the autoboot times out, the board is fine. This was done with a completely blank flash (other than U-Boot). I get the "bad CRC, using default environment" message. Reverting 396f635b8ff3ccbc38d75d5eda98444c6466810a solved the problem for me. Here is the bisection log, just for kicks: git-bisect start # good: [cd82919e6c8a73b363a26f34b734923844e52d1c] Coding style cleanup, update CHANGELOG, prepare release git-bisect good cd82919e6c8a73b363a26f34b734923844e52d1c # bad: [b5710d9974f6f0f3ddb4e67d6cccc262ab37049e] FSL DDR: Remove old SPD support from cpu/mpc86xx git-bisect bad b5710d9974f6f0f3ddb4e67d6cccc262ab37049e # good: [4cb4e654cafabaa1ac180d37b00c8f6095dae9c9] ColdFire: Multiple fixes for M5282EVB git-bisect good 4cb4e654cafabaa1ac180d37b00c8f6095dae9c9 # good: [c66830263af19831f2b7db307f79d1943febf7f9] dtc: Enable and fix -Wcast-qual warnings git-bisect good c66830263af19831f2b7db307f79d1943febf7f9 # good: [c5d11e79a260415448c152ed557c9bfb93759067] Merge branch 'master' of git://git.denx.de/u-boot-mpc83xx git-bisect good c5d11e79a260415448c152ed557c9bfb93759067 # bad: [306620b762a4f9fa6678568ad2e8772dec145208] remove MVS1 board git-bisect bad 306620b762a4f9fa6678568ad2e8772dec145208 # good: [e906cfae08e8cc2447f59b1bc4c22ab9c3c286d2] bootm: move lmb into the bootm_headers_t structure git-bisect good e906cfae08e8cc2447f59b1bc4c22ab9c3c286d2 # bad: [2a1a2cb6e2b87ee550e6f27b647d23331dfd5e1b] fdt: refactor initrd related code git-bisect bad 2a1a2cb6e2b87ee550e6f27b647d23331dfd5e1b # bad: [3082d2348c8e13342f5fdd10e9b3f7408062dbf9] fdt: refactor fdt resize code git-bisect bad 3082d2348c8e13342f5fdd10e9b3f7408062dbf9 # bad: [396f635b8ff3ccbc38d75d5eda98444c6466810a] bootm: refactor image detection and os load steps git-bisect bad 396f635b8ff3ccbc38d75d5eda98444c6466810a Hope it helps, Ira

3 4

[U-Boot] [PATCH] ppc4xx: Optimization for DDR2 initialization for IBM DDR2 memory controller
by Prodyut Hazarika 28 Aug '08

28 Aug '08

>From 5dd36e0d171286f59e4ca4e9eb2a040143b4ec33 Mon Sep 17 00:00:00 2001 From: Prodyut Hazarika <phazarika(a)amcc.com> Date: Wed, 27 Aug 2008 14:51:08 -0700 Subject: [PATCH] Optimization for DDR2 initialization for IBM DDR2 memory controller Optimized values suggested by Hardware Team at AMCC Removed Magic numbers from Initialization preload registers Tested with Kilauea, Glacier, Canyonlands and Katmai boards About 5-7% improvement seen for LMBench memtests Signed-off-by: Prodyut Hazarika <phazarika(a)amcc.com> --- cpu/ppc4xx/44x_spd_ddr2.c | 59 ++++++++++++++++++++++++++++++++------------- 1 files changed, 42 insertions(+), 17 deletions(-) diff --git a/cpu/ppc4xx/44x_spd_ddr2.c b/cpu/ppc4xx/44x_spd_ddr2.c index 001f2c1..c24cfec 100644 --- a/cpu/ppc4xx/44x_spd_ddr2.c +++ b/cpu/ppc4xx/44x_spd_ddr2.c @@ -118,6 +118,7 @@ static inline void ppc4xx_ibm_ddr2_register_dump(void); #define ODS_FULL 0x00000000 #define ODS_REDUCED 0x00000002 +#define OCD_CALIB_DEF 0x00000380 /* defines for ODT (On Die Termination) of the 440SP(e) DDR2 controller */ #define ODT_EB0R (0x80000000 >> 8) @@ -570,15 +571,24 @@ phys_size_t initdram(int board_type) mtsdram(SDRAM_MCOPT2, (val & ~(SDRAM_MCOPT2_SREN_MASK | SDRAM_MCOPT2_DCEN_MASK | SDRAM_MCOPT2_IPTR_MASK | SDRAM_MCOPT2_ISIE_MASK)) | - (SDRAM_MCOPT2_DCEN_ENABLE | SDRAM_MCOPT2_IPTR_EXECUTE)); + SDRAM_MCOPT2_IPTR_EXECUTE); /*------------------------------------------------------------------ - * Wait for SDRAM_CFG0_DC_EN to complete. + * Wait for IPTR_EXECUTE init sequence to complete. *-----------------------------------------------------------------*/ do { mfsdram(SDRAM_MCSTAT, val); } while ((val & SDRAM_MCSTAT_MIC_MASK) == SDRAM_MCSTAT_MIC_NOTCOMP); + /* enable the controller only after init sequence completes */ + mfsdram(SDRAM_MCOPT2, val); + mtsdram(SDRAM_MCOPT2, (val | SDRAM_MCOPT2_DCEN_ENABLE)); + + /* Make sure delay-line calibration is done before proceeding */ + do { + mfsdram(SDRAM_DLCR, val); + } while (!(val & SDRAM_DLCR_DLCS_COMPLETE)); + /* get installed memory size */ dram_size = sdram_memsize(); @@ -1343,22 +1353,36 @@ static void program_initplr(unsigned long *dimm_populated, emr = CMD_EMR | SELECT_EMR | odt | ods; emr2 = CMD_EMR | SELECT_EMR2; emr3 = CMD_EMR | SELECT_EMR3; - mtsdram(SDRAM_INITPLR0, 0xB5000000 | CMD_NOP); /* NOP */ + mtsdram(SDRAM_INITPLR0, SDRAM_INITPLR_ENABLE | CMD_NOP | /* NOP */ + SDRAM_INITPLR_IMWT_ENCODE(106)); /* Wait 106 MemClk cycles */ udelay(1000); - mtsdram(SDRAM_INITPLR1, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */ - mtsdram(SDRAM_INITPLR2, 0x80800000 | emr2); /* EMR2 */ - mtsdram(SDRAM_INITPLR3, 0x80800000 | emr3); /* EMR3 */ - mtsdram(SDRAM_INITPLR4, 0x80800000 | emr); /* EMR DLL ENABLE */ - mtsdram(SDRAM_INITPLR5, 0x80800000 | mr | DLL_RESET); /* MR w/ DLL reset */ + mtsdram(SDRAM_INITPLR1, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE | /* precharge 4 MemClk cycles */ + SDRAM_INITPLR_IMWT_ENCODE(4)); + mtsdram(SDRAM_INITPLR2, SDRAM_INITPLR_ENABLE | emr2 | /* EMR2 */ + SDRAM_INITPLR_IMWT_ENCODE(2)); /* Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR3, SDRAM_INITPLR_ENABLE | emr3 | /* EMR3 */ + SDRAM_INITPLR_IMWT_ENCODE(2)); /* Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR4, SDRAM_INITPLR_ENABLE | emr | /* EMR DLL ENABLE */ + SDRAM_INITPLR_IMWT_ENCODE(2)); /* Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR5, SDRAM_INITPLR_ENABLE | mr | DLL_RESET | /* MR w/ DLL reset */ + SDRAM_INITPLR_IMWT_ENCODE(200)); /* 200 cycle wait for DLL reset */ udelay(1000); - mtsdram(SDRAM_INITPLR6, 0x82000400 | CMD_PRECHARGE); /* precharge 8 DDR clock cycle */ - mtsdram(SDRAM_INITPLR7, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ - mtsdram(SDRAM_INITPLR8, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ - mtsdram(SDRAM_INITPLR9, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ - mtsdram(SDRAM_INITPLR10, 0x8a000000 | CMD_REFRESH); /* Refresh 50 DDR clock cycle */ - mtsdram(SDRAM_INITPLR11, 0x80000000 | mr); /* MR w/o DLL reset */ - mtsdram(SDRAM_INITPLR12, 0x80800380 | emr); /* EMR OCD Default */ - mtsdram(SDRAM_INITPLR13, 0x80800000 | emr); /* EMR OCD Exit */ + mtsdram(SDRAM_INITPLR6, SDRAM_INITPLR_ENABLE | CMD_PRECHARGE | + SDRAM_INITPLR_IMWT_ENCODE(4)); /* precharge 4 MemClk cycles */ + mtsdram(SDRAM_INITPLR7, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR8, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR9, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR10, SDRAM_INITPLR_ENABLE | CMD_REFRESH | + SDRAM_INITPLR_IMWT_ENCODE(25)); /* Refresh 25 MemClk cycles */ + mtsdram(SDRAM_INITPLR11, SDRAM_INITPLR_ENABLE | mr | /* MR w/o DLL reset */ + SDRAM_INITPLR_IMWT_ENCODE(2)); /* Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR12, SDRAM_INITPLR_ENABLE | OCD_CALIB_DEF | /* EMR OCD Default */ + SDRAM_INITPLR_IMWT_ENCODE(2) | emr); /* Wait tMRD (2 MemClk cycles) */ + mtsdram(SDRAM_INITPLR13, SDRAM_INITPLR_ENABLE | emr | /* EMR OCD Exit */ + SDRAM_INITPLR_IMWT_ENCODE(2)); } else { printf("ERROR: ucode error as unknown DDR type in program_initplr"); spd_ddr_init_hang (); @@ -2466,12 +2490,13 @@ static void program_DQS_calibration(unsigned long *dimm_populated, * Program RFDC register * Set Feedback Fractional Oversample * Auto-detect read sample cycle enable + * Set RFOS to 1/4 of memclk cycle (0x3f) *-----------------------------------------------------------------*/ mfsdram(SDRAM_RFDC, val); mtsdram(SDRAM_RFDC, (val & ~(SDRAM_RFDC_ARSE_MASK | SDRAM_RFDC_RFOS_MASK | SDRAM_RFDC_RFFD_MASK)) - | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0) | + | (SDRAM_RFDC_ARSE_ENABLE | SDRAM_RFDC_RFOS_ENCODE(0x3f) | SDRAM_RFDC_RFFD_ENCODE(0))); DQS_calibration_process(); -- 1.5.5

2 1

Re: [U-Boot] [U-boot-Users][GIT PULL] Please pull mpc5xxx tree
by Wolfgang Denk 28 Aug '08

28 Aug '08

Dear John Rigby, In message <48B5D197.3090903(a)freescale.com> you wrote: > Wolfgang, > > The following changes since commit b5710d9974f6f0f3ddb4e67d6cccc262ab37049e: > Kumar Gala (1): > FSL DDR: Remove old SPD support from cpu/mpc86xx > > are available in the git repository at: > > git://git.denx.de/u-boot-mpc5xxx.git master > > Heiko Schocher (1): > mpc52xx: added support for the MPC5200 based MUC.MC52 board from MAN. > > MAINTAINERS | 1 + > Makefile | 3 + > board/mucmc52/Makefile | 53 ++++++ > board/mucmc52/config.mk | 45 +++++ > board/mucmc52/mucmc52.c | 400 +++++++++++++++++++++++++++++++++++++++++++++ > cpu/mpc5xxx/fec.c | 6 +- > include/configs/mucmc52.h | 376 ++++++++++++++++++++++++++++++++++++++++++ > 7 files changed, 882 insertions(+), 2 deletions(-) > create mode 100644 board/mucmc52/Makefile > create mode 100644 board/mucmc52/config.mk > create mode 100644 board/mucmc52/mucmc52.c > create mode 100644 include/configs/mucmc52.h Applied, thanks a lot. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "The first rule of magic is simple. Don't waste your time waving your hands and hoping when a rock or a club will do." - McCloctnik the Lucid

1 0

[U-Boot] [U-boot-Users][GIT PULL] Please pull mpc5xxx tree
by John Rigby 28 Aug '08

28 Aug '08

Wolfgang, The following changes since commit b5710d9974f6f0f3ddb4e67d6cccc262ab37049e: Kumar Gala (1): FSL DDR: Remove old SPD support from cpu/mpc86xx are available in the git repository at: git://git.denx.de/u-boot-mpc5xxx.git master Heiko Schocher (1): mpc52xx: added support for the MPC5200 based MUC.MC52 board from MAN. MAINTAINERS | 1 + Makefile | 3 + board/mucmc52/Makefile | 53 ++++++ board/mucmc52/config.mk | 45 +++++ board/mucmc52/mucmc52.c | 400 +++++++++++++++++++++++++++++++++++++++++++++ cpu/mpc5xxx/fec.c | 6 +- include/configs/mucmc52.h | 376 ++++++++++++++++++++++++++++++++++++++++++ 7 files changed, 882 insertions(+), 2 deletions(-) create mode 100644 board/mucmc52/Makefile create mode 100644 board/mucmc52/config.mk create mode 100644 board/mucmc52/mucmc52.c create mode 100644 include/configs/mucmc52.h

1 0

[U-Boot] network bootp/tftp hang with tsec on MPC8343
by Andre Schwarz 27 Aug '08

27 Aug '08

Hi, after moving to the latest u-boot (v1.3.4) I can observe strange "hangs" during network transfer. This is clearly related to U-Boot since network is running smoothly after booting linux from flash. It's a MPC8343 with a Vitesse VSC8601 PHY connected via RGMII. This happens both at 100M and 1000M. Any ideas ? Have I missed a change lately ? regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

2 3

[U-Boot-Users] NAND: bad block in whole chip
by Alemao 27 Aug '08

27 Aug '08

Hi all, Im trying to use my NAND flash at MPC8360E-RDK based board. But it seems that the whole chip is bad blocked. Dont know if Im missing something... below some outputs: => nand info Device 0: NAND 64MiB 3,3V 8-bit, sector size 16 KiB => nand bad 00000000 00004000 . . . 03ff4000 03ff8000 03ffc000 => nand erase clean NAND erase: device 0 whole chip Skipping bad block at 0x00000000 Skipping bad block at 0x00004000 . . . Skipping bad block at 0x03ff8000 Skipping bad block at 0x03ffc000 OK => I read that any block that contains bytes != 0xff in the OOB is marked as "factory bad" block. At nand_block_bad() function (drivers/nand/nand_base.c) I saw the implementation of the statment above. --- this->cmdfunc (mtd, NAND_CMD_READOOB, this->badblockpos, page); if (this->read_byte(mtd) != 0xff) res = 1; --- So I did some dumps in NAND: => nand dump 0x00004000 Page 0x00004000 dump: . . . OOB: 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 00 => nand dump 0x03ff8000 Page 03ff8000 dump: . . . OOB: 81 81 81 01 81 81 81 81 81 81 81 81 81 81 81 81 All dumps had OOB != 0xff I also tried to write only 1 byte... no success: => tftpboot 0x02000000 kernel_blob.img => nand write.jffs2 0x02000000 0x0 0x1 . . . Bad block at 0x2010000 in erase block from 0x2010000 will be skipped writing NAND page at offset 0x2014000 failed Data did not fit into device, due to bad blocks 1 bytes written: ERROR => Any help/suggestions welcome. Im using U-Boot-1.1.4 with NAND and FSL_UPM drivers from U-Boot-1.3.3 Cheers, -- Alemao

3 6