August 2008 - U-Boot

[U-Boot] U-Boot bootup process
by Ahmed, Muzammal 29 Aug '08

29 Aug '08

Hello there, I'm very new to U-Boot. I'm programming an AMCC PPC440EP (Yosemite) board that will run LynxOS. Would anyone help me with U-Boot bootup process? On power up, where U-Boot starts executing from and what's the flow of it? What functions it calls? I need to understand the whole picture, like what gets initialized when! Any kind of information/block-diagram would greatly be appreciated. Thanks, Muzammal

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[U-Boot] [PATCH 1/1] CONFIG_MENUKEY: RFC: Is this how CONFIG_MENUKEY supposed to work?
by richardretanubun 28 Aug '08

28 Aug '08

I noticed that CONFIG_MENUKEY aborts autoboot unconditionally and executes the "menucmd" env.variable if it found a match later on. This seems odd. It is possible that I misunderstood the intent of the logic. The only other user of it now is AmigaOneG3SE. I made a patch to make the logic only aborts autoboot if there is a match detected. If the person who wrote the logic is reading this, did I understood the logic correctly? If so please Sign-off the patch to have it applied. Signed-off-by: Richard Retanubun <RichardRetanubun_at_ruggedcom.com> ---- diff --git a/common/main.c b/common/main.c index 187ef8a..5a4308d 100644 --- a/common/main.c +++ b/common/main.c @@ -238,14 +238,19 @@ static __inline__ int abortboot(int bootdelay) /* delay 100 * 10ms */ for (i=0; !abort && i<100; ++i) { if (tstc()) { /* we got a key press */ - abort = 1; /* don't auto boot */ - bootdelay = 0; /* no more delay */ # ifdef CONFIG_MENUKEY menukey = getc(); + if (menukey == CONFIG_MENUKEY) { /* we got a match */ + abort = 1; /* don't auto boot */ + bootdelay = 0; /* no more delay */ + break; + } # else - (void) getc(); /* consume input */ -# endif + (void) getc(); /* consume input */ + abort = 1; /* don't auto boot */ + bootdelay = 0; /* no more delay */ break; +# endif } udelay(10000); }

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[U-Boot] [PATCH] mpc83xx: clean up cache operations and unlock_ram_in_cache() functions
by Nick Spence 28 Aug '08

28 Aug '08

Cleans up some latent issues with the data cache control so that dcache_enable() and dcache_disable() will work reliably (after unlock_ram_in_cache() has been called) Signed-off-by: Nick Spence <nick.spence(a)freescale.com> --- cpu/mpc83xx/start.S | 51 ++++++++++++++++++++++++++++++--------------------- 1 files changed, 30 insertions(+), 21 deletions(-) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index e452bfb..14bfbda 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -208,7 +208,7 @@ in_flash: bl enable_addr_trans sync - /* enable and invalidate the data cache */ + /* enable the data cache */ bl dcache_enable sync #ifdef CFG_INIT_RAM_LOCK @@ -496,15 +496,16 @@ init_e300_core: /* time t 10 */ /* Initialize the Hardware Implementation-dependent Registers */ /* HID0 also contains cache control */ + /* - force invalidation of data and instruction caches */ /*------------------------------------------------------*/ lis r3, CFG_HID0_INIT@h - ori r3, r3, CFG_HID0_INIT@l + ori r3, r3, (CFG_HID0_INIT | HID0_ICFI | HID0_DCFI)@l SYNC mtspr HID0, r3 lis r3, CFG_HID0_FINAL@h - ori r3, r3, CFG_HID0_FINAL@l + ori r3, r3, (CFG_HID0_FINAL & ~(HID0_ICFI | HID0_DCFI))@l SYNC mtspr HID0, r3 @@ -714,8 +715,7 @@ disable_addr_trans: icache_enable: mfspr r3, HID0 ori r3, r3, HID0_ICE - lis r4, 0 - ori r4, r4, HID0_ILOCK + li r4, HID0_ICFI|HID0_ILOCK andc r3, r3, r4 ori r4, r3, HID0_ICFI isync @@ -728,13 +728,10 @@ icache_enable: icache_disable: mfspr r3, HID0 lis r4, 0 - ori r4, r4, HID0_ICE|HID0_ILOCK + ori r4, r4, HID0_ICE|HID0_ICFI|HID0_ILOCK andc r3, r3, r4 - ori r4, r3, HID0_ICFI isync - mtspr HID0, r4 /* sets invalidate, clears enable and lock*/ - isync - mtspr HID0, r3 /* clears invalidate */ + mtspr HID0, r3 /* clears invalidate, enable and lock */ blr .globl icache_status @@ -748,25 +745,24 @@ dcache_enable: mfspr r3, HID0 li r5, HID0_DCFI|HID0_DLOCK andc r3, r3, r5 - mtspr HID0, r3 /* no invalidate, unlock */ ori r3, r3, HID0_DCE - ori r5, r3, HID0_DCFI - mtspr HID0, r5 /* enable + invalidate */ - mtspr HID0, r3 /* enable */ sync + mtspr HID0, r3 /* enable, no invalidate */ blr .globl dcache_disable dcache_disable: + mflr r4 + bl flush_dcache /* uses r3 and r5 */ mfspr r3, HID0 - lis r4, 0 - ori r4, r4, HID0_DCE|HID0_DLOCK - andc r3, r3, r4 - ori r4, r3, HID0_DCI + li r5, HID0_DCE|HID0_DLOCK + andc r3, r3, r5 + ori r5, r3, HID0_DCFI sync - mtspr HID0, r4 /* sets invalidate, clears enable and lock */ + mtspr HID0, r5 /* sets invalidate, clears enable and lock */ sync mtspr HID0, r3 /* clears invalidate */ + mtlr r4 blr .globl dcache_status @@ -775,6 +771,18 @@ dcache_status: rlwinm r3, r3, (31 - HID0_DCE_SHIFT + 1), 31, 31 blr + .globl flush_dcache +flush_dcache: + lis r3, 0 + lis r5, CFG_CACHELINE_SIZE +1: cmp 0, 1, r3, r5 + bge 2f + lwz r5, 0(r3) + lis r5, CFG_CACHELINE_SIZE + addi r3, r3, 0x4 + b 1b +2: blr + .globl get_pvr get_pvr: mfspr r3, PVR @@ -1081,7 +1089,7 @@ lock_ram_in_cache: /* Lock the data cache */ mfspr r0, HID0 - ori r0, r0, 0x1000 + ori r0, r0, HID0_DLOCK sync mtspr HID0, r0 sync @@ -1108,9 +1116,10 @@ unlock_ram_in_cache: li r5, HID0_DLOCK|HID0_DCFI andc r3, r3, r5 /* no invalidate, unlock */ ori r5, r3, HID0_DCFI /* invalidate, unlock */ + sync mtspr HID0, r5 /* invalidate, unlock */ - mtspr HID0, r3 /* no invalidate, unlock */ sync + mtspr HID0, r3 /* no invalidate, unlock */ blr #endif /* !CONFIG_NAND_SPL */ #endif /* CFG_INIT_RAM_LOCK */ -- 1.5.2.2

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[U-Boot] [PATCH] mpc83xx: Store and display Arbiter Event Register values
by Nick Spence 28 Aug '08

28 Aug '08

Record the Arbiter Event Register values and optionally display them. The Arbiter Event Register can record the type and effective address of an arbiter error, even through an HRESET. This patch stores the values in the global data structure. Display of the Arbiter Event registers immediately after the RSR value can be enabled with defines. The Arbiter values will only be displayed if an arbiter event has occured since the last Power On Reset, and either of the following defines exist: #define CONFIG_DISPLAY_AER_BRIEF - display only the arbiter address and and type register values #define CONFIG_DISPLAY_AER_FULL - display and interpret the arbiter event register values Address Only transactions are one of the trapped events that can register as an arbiter event. They occur with some cache manipulation instructions if the HID0_ABE (Address Broadcast Enable) is set and the memory region has the MEMORY_COHERENCE WIMG bit set. Setting: #define CONFIG_MASK_AER_AO - prevents the arbiter from recording address only events, so that it can still capture other real problems. Signed-off-by: Nick Spence <nick.spence(a)freescale.com> --- cpu/mpc83xx/cpu_init.c | 136 ++++++++++++++++++++++++++++++++++++++++- cpu/mpc83xx/start.S | 11 +++ include/asm-ppc/global_data.h | 4 + 3 files changed, 150 insertions(+), 1 deletions(-) diff --git a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c index 4514dbb..ff01cf1 100644 --- a/cpu/mpc83xx/cpu_init.c +++ b/cpu/mpc83xx/cpu_init.c @@ -167,6 +167,10 @@ void cpu_init_f (volatile immap_t * im) gd->reset_status = im->reset.rsr; im->reset.rsr = ~(RSR_RES); + /* AER - Arbiter Event Register - store status */ + gd->arbiter_event_attributes = im->arbiter.aeatr; + gd->arbiter_event_address = im->arbiter.aeadr; + /* * RMR - Reset Mode Register * contains checkstop reset enable (4.6.1.4) @@ -303,6 +307,130 @@ int cpu_init_r (void) } /* + * Print out the bus arbiter event + */ +#if defined(CONFIG_DISPLAY_AER_FULL) +static int print_83xx_arb_event(int force) +{ + static char* event[] = { + "Address Time Out", + "Data Time Out", + "Address Only Transfer Type", + "External Control Word Transfer Type", + "Reserved Transfer Type", + "Transfer Error", + "reserved", + "reserved" + }; + static char* master[] = { + "e300 Core Data Transaction", + "reserved", + "e300 Core Instruction Fetch", + "reserved", + "TSEC1", + "TSEC2", + "USB MPH", + "USB DR", + "Encryption Core", + "I2C Boot Sequencer", + "JTAG", + "reserved", + "eSDHC", + "PCI1", + "PCI2", + "DMA", + "QUICC Engine 00", + "QUICC Engine 01", + "QUICC Engine 10", + "QUICC Engine 11", + "reserved", + "reserved", + "reserved", + "reserved", + "SATA1", + "SATA2", + "SATA3", + "SATA4", + "reserved", + "PCI Express 1", + "PCI Express 2", + "TDM-DMAC" + }; + static char *transfer[] = { + "Address-only, Clean Block", + "Address-only, lwarx reservation set", + "Single-beat or Burst write", + "reserved", + "Address-only, Flush Block", + "reserved", + "Burst write", + "reserved", + "Address-only, sync", + "Address-only, tlbsync", + "Single-beat or Burst read", + "Single-beat or Burst read", + "Address-only, Kill Block", + "Address-only, icbi", + "Burst read", + "reserved", + "Address-only, eieio", + "reserved", + "Single-beat write", + "reserved", + "ecowx - Illegal single-beat write", + "reserved", + "reserved", + "reserved", + "Address-only, TLB Invalidate", + "reserved", + "Single-beat or Burst read", + "reserved", + "eciwx - Illegal single-beat read", + "reserved", + "Burst read", + "reserved" + }; + + int etype = (gd->arbiter_event_attributes & AEATR_EVENT) + >> AEATR_EVENT_SHIFT; + int mstr_id = (gd->arbiter_event_attributes & AEATR_MSTR_ID) + >> AEATR_MSTR_ID_SHIFT; + int tbst = (gd->arbiter_event_attributes & AEATR_TBST) + >> AEATR_TBST_SHIFT; + int tsize = (gd->arbiter_event_attributes & AEATR_TSIZE) + >> AEATR_TSIZE_SHIFT; + int ttype = (gd->arbiter_event_attributes & AEATR_TTYPE) + >> AEATR_TTYPE_SHIFT; + + if (!force && !gd->arbiter_event_address) + return 0; + + puts("Arbiter Event Status:\n"); + printf(" Event Address: 0x%08lX\n", gd->arbiter_event_address); + printf(" Event Type: 0x%1x = %s\n", etype, event[etype]); + printf(" Master ID: 0x%02x = %s\n", mstr_id, master[mstr_id]); + printf(" Transfer Size: 0x%1x = %d bytes\n", (tbst<<3) | tsize, + tbst ? (tsize ? tsize : 8) : 16 + 8 * tsize); + printf(" Transfer Type: 0x%02x = %s\n", ttype, transfer[ttype]); + + return gd->arbiter_event_address; +} + +#elif defined(CONFIG_DISPLAY_AER_BRIEF) + +static int print_83xx_arb_event(int force) +{ + if (!force && !gd->arbiter_event_address) + return 0; + + printf("Arbiter Event Status: AEATR=0x%08lX, AEADR=0x%08lX\n", + gd->arbiter_event_attributes, gd->arbiter_event_address); + + return gd->arbiter_event_address; +} +#endif /* CONFIG_DISPLAY_AER_xxxx */ + +/* * Figure out the cause of the reset */ int prt_83xx_rsr(void) @@ -334,6 +462,12 @@ int prt_83xx_rsr(void) printf("%s%s", sep, bits[i].desc); sep = ", "; } - puts("\n\n"); + puts("\n"); + +#if defined(CONFIG_DISPLAY_AER_FULL) || defined(CONFIG_DISPLAY_AER_BRIEF) + print_83xx_arb_event(rsr & RSR_BMRS); +#endif + puts("\n"); + return 0; } diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 75ad36c..e452bfb 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -483,6 +483,17 @@ init_e300_core: /* time t 10 */ 1: #endif /* CONFIG_WATCHDOG */ +#if defined(CONFIG_MASK_AER_AO) + /* Write the Arbiter Event Enable to mask Address Only traps. */ + /* This prevents the dcbz instruction from being trapped when */ + /* HID0_ABE Address Broadcast Enable is set and the MEMORY */ + /* COHERENCY bit is set in the WIMG bits, which is often */ + /* needed for PCI operation. */ + lwz r4, 0x0808(r3) + rlwinm r0, r4, 0, ~AER_AO + stw r0, 0x0808(r3) +#endif /* CONFIG_MASK_AER_AO */ + /* Initialize the Hardware Implementation-dependent Registers */ /* HID0 also contains cache control */ /*------------------------------------------------------*/ diff --git a/include/asm-ppc/global_data.h b/include/asm-ppc/global_data.h index be2ce24..a236c4b 100644 --- a/include/asm-ppc/global_data.h +++ b/include/asm-ppc/global_data.h @@ -122,6 +122,10 @@ typedef struct global_data { phys_size_t ram_size; /* RAM size */ unsigned long reloc_off; /* Relocation Offset */ unsigned long reset_status; /* reset status register at boot */ +#if defined(CONFIG_MPC83XX) + unsigned long arbiter_event_attributes; + unsigned long arbiter_event_address; +#endif unsigned long env_addr; /* Address of Environment struct */ unsigned long env_valid; /* Checksum of Environment valid? */ unsigned long have_console; /* serial_init() was called */ -- 1.5.2.2

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[U-Boot] [PATCH] mpc83xx: use r4 instead of r2 in lock_ram_in_cache and unlock_ram_in_cache
by Nick Spence 28 Aug '08

28 Aug '08

This is needed in unlock_ram_in_cache() because it is called from C and will corrupt the small data area anchor that is kept in R2. lock_ram_in_cache() is modified similarly as good coding practice, but is not called from C. Signed-off-by: Nick Spence <nick.spence(a)freescale.com> --- cpu/mpc83xx/start.S | 9 +++++---- 1 files changed, 5 insertions(+), 4 deletions(-) diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 16ed494..75ad36c 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -1060,9 +1060,9 @@ lock_ram_in_cache: */ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2, ((CFG_INIT_RAM_END & ~31) + \ + li r4, ((CFG_INIT_RAM_END & ~31) + \ (CFG_INIT_RAM_ADDR & 31) + 31) / 32 - mtctr r2 + mtctr r4 1: dcbz r0, r3 addi r3, r3, 32 @@ -1082,8 +1082,9 @@ unlock_ram_in_cache: /* invalidate the INIT_RAM section */ lis r3, (CFG_INIT_RAM_ADDR & ~31)@h ori r3, r3, (CFG_INIT_RAM_ADDR & ~31)@l - li r2,512 - mtctr r2 + li r4, ((CFG_INIT_RAM_END & ~31) + \ + (CFG_INIT_RAM_ADDR & 31) + 31) / 32 + mtctr r4 1: icbi r0, r3 dcbi r0, r3 addi r3, r3, 32 -- 1.5.2.2

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[U-Boot] [PATCH 1/1] ppc4xx: fix UIC hang if critical or non-critical interrupt is set at the same time as a normal interrupt is set on UIC0
by fkan＠amcc.com 28 Aug '08

28 Aug '08

From: Victor Gallardo <vgallardo(a)amcc.com> Signed-off-by: Victor Gallardo <vgallardo(a)amcc.com> --- cpu/ppc4xx/uic.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/cpu/ppc4xx/uic.c b/cpu/ppc4xx/uic.c index 7944c6c..a95d1cb 100644 --- a/cpu/ppc4xx/uic.c +++ b/cpu/ppc4xx/uic.c @@ -129,11 +129,11 @@ void external_interrupt(struct pt_regs *regs) uic_interrupt(UIC3_DCR_BASE, 96); #endif + mtdcr(uic0sr, (uic_msr & UICB0_ALL)); + if (uic_msr & ~(UICB0_ALL)) uic_interrupt(UIC0_DCR_BASE, 0); - mtdcr(uic0sr, uic_msr); - return; } -- 1.5.5

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[U-Boot] [PATCH] ADS5121: Fix NOR and CPLD ALE timing for rev 2 silicon
by John Rigby 28 Aug '08

28 Aug '08

MPC5121 rev 2 silicon has a new register for controlling how long CS is asserted after deassertion of ALE in multiplexed mode. The default is to assert CS together with ALE. The alternative is to assert CS (ALEN+1)*LPC_CLK clocks after deassertion of ALE. The default is wrong for the NOR flash and CPLD on the ADS5121. This patch turns on the alternative for CS0 (NOR) and CS2 (CPLD) it does so conditionally based on silicon rev 2.0 or greater. Signed-off-by: Martha J Marx <mmarx(a)silicontkx.com> Signed-off-by: John Rigby <jrigby(a)freescale.com> --- board/ads5121/ads5121.c | 4 ++++ include/configs/ads5121.h | 1 + include/mpc512x.h | 1 + 3 files changed, 6 insertions(+), 0 deletions(-) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index ba3d7d2..9acf56b 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -25,6 +25,7 @@ #include <mpc512x.h> #include <asm/bitops.h> #include <command.h> +#include <asm/processor.h> #include <fdt_support.h> #ifdef CONFIG_MISC_INIT_R #include <i2c.h> @@ -92,6 +93,9 @@ int board_early_init_f (void) * Configure Flash Speed */ *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS0_CONFIG)) = CFG_CS0_CFG; + if (SVR_MJREV (im->sysconf.spridr)>=2) { + *((volatile u32 *)(CFG_IMMR + LPC_OFFSET + CS_ALE_TIMING_CONFIG)) = CFG_CS_ALETIMING; + } /* * Enable clocks */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 5f74afb..ee585da 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -210,6 +210,7 @@ #define CFG_CS0_CFG 0x05059310 /* ALE active low, data size 4bytes */ #define CFG_CS2_CFG 0x05059010 /* ALE active low, data size 1byte */ +#define CFG_CS_ALETIMING 0x00000005 /* For rev 2 silicon CS assert after isolation */ /* Use SRAM for initial stack */ #define CFG_INIT_RAM_ADDR CFG_SRAM_BASE /* Initial RAM address */ diff --git a/include/mpc512x.h b/include/mpc512x.h index a76b1ca..cb418d1 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -58,6 +58,7 @@ #define CS5_CONFIG 0x00014 #define CS6_CONFIG 0x00018 #define CS7_CONFIG 0x0001C +#define CS_ALE_TIMING_CONFIG 0x00034 #define CS_CTRL 0x00020 #define CS_CTRL_ME 0x01000000 /* CS Master Enable bit */ -- 1.5.6.2.255.gbed62

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[U-Boot] [PATCH] mtd: SPI Flash: Support the STMicro Flash
by Tsi-Chung Liew 28 Aug '08

28 Aug '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Add MTD SPI Flash support for M25P16, M25P20, M25P32, M25P40, M25P64, M25P80, M25P128. Signed-off-by: Jason McMullan <mcmullan(a)netapp.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- drivers/mtd/spi/Makefile | 1 + drivers/mtd/spi/spi_flash.c | 5 + drivers/mtd/spi/spi_flash_internal.h | 1 + drivers/mtd/spi/stmicro.c | 355 ++++++++++++++++++++++++++++++++++ 4 files changed, 362 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/spi/stmicro.c diff --git a/drivers/mtd/spi/Makefile b/drivers/mtd/spi/Makefile index af6af97..3d4f892 100644 --- a/drivers/mtd/spi/Makefile +++ b/drivers/mtd/spi/Makefile @@ -27,6 +27,7 @@ LIB := $(obj)libspi_flash.a COBJS-$(CONFIG_SPI_FLASH) += spi_flash.o COBJS-$(CONFIG_SPI_FLASH_ATMEL) += atmel.o +COBJS-$(CONFIG_SPI_FLASH_STMICRO) += stmicro.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/spi/spi_flash.c b/drivers/mtd/spi/spi_flash.c index d581cb3..d1d81af 100644 --- a/drivers/mtd/spi/spi_flash.c +++ b/drivers/mtd/spi/spi_flash.c @@ -134,6 +134,11 @@ struct spi_flash *spi_flash_probe(unsigned int bus, unsigned int cs, flash = spi_flash_probe_atmel(spi, idcode); break; #endif +#ifdef CONFIG_SPI_FLASH_STMICRO + case 0x20: + flash = spi_flash_probe_stmicro(spi, idcode); + break; +#endif default: debug("SF: Unsupported manufacturer %02X\n", idcode[0]); flash = NULL; diff --git a/drivers/mtd/spi/spi_flash_internal.h b/drivers/mtd/spi/spi_flash_internal.h index 1438050..e5f758e 100644 --- a/drivers/mtd/spi/spi_flash_internal.h +++ b/drivers/mtd/spi/spi_flash_internal.h @@ -43,3 +43,4 @@ int spi_flash_read_common(struct spi_flash *flash, const u8 *cmd, /* Manufacturer-specific probe functions */ struct spi_flash *spi_flash_probe_spansion(struct spi_slave *spi, u8 *idcode); struct spi_flash *spi_flash_probe_atmel(struct spi_slave *spi, u8 *idcode); +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 *idcode); diff --git a/drivers/mtd/spi/stmicro.c b/drivers/mtd/spi/stmicro.c new file mode 100644 index 0000000..846b105 --- /dev/null +++ b/drivers/mtd/spi/stmicro.c @@ -0,0 +1,355 @@ +/* + * (C) Copyright 2000-2002 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * Copyright 2008, Network Appliance Inc. + * Jason McMullan <mcmullan(a)netapp.com> + * + * Copyright (C) 2004-2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <spi_flash.h> + +#include "spi_flash_internal.h" + +/* M25Pxx-specific commands */ +#define CMD_M25PXX_WREN 0x06 /* Write Enable */ +#define CMD_M25PXX_WRDI 0x04 /* Write Disable */ +#define CMD_M25PXX_RDSR 0x05 /* Read Status Register */ +#define CMD_M25PXX_WRSR 0x01 /* Write Status Register */ +#define CMD_M25PXX_READ 0x03 /* Read Data Bytes */ +#define CMD_M25PXX_FAST_READ 0x0b /* Read Data Bytes at Higher Speed */ +#define CMD_M25PXX_PP 0x02 /* Page Program */ +#define CMD_M25PXX_SE 0xd8 /* Sector Erase */ +#define CMD_M25PXX_BE 0xc7 /* Bulk Erase */ +#define CMD_M25PXX_DP 0xb9 /* Deep Power-down */ +#define CMD_M25PXX_RES 0xab /* Release from DP, and Read Signature */ + +#define STM_ID_M25P16 0x15 +#define STM_ID_M25P20 0x12 +#define STM_ID_M25P32 0x16 +#define STM_ID_M25P40 0x13 +#define STM_ID_M25P64 0x17 +#define STM_ID_M25P80 0x14 +#define STM_ID_M25P128 0x18 + +#define STMICRO_SR_WIP (1 << 0) /* Write-in-Progress */ + +struct stmicro_spi_flash_params { + u8 idcode1; + u16 page_size; + u16 pages_per_sector; + u16 nr_sectors; + const char *name; +}; + +struct stmicro_spi_flash { + const struct stmicro_spi_flash_params *params; + struct spi_flash flash; +}; + +static inline struct stmicro_spi_flash *to_stmicro_spi_flash(struct spi_flash + *flash) +{ + return container_of(flash, struct stmicro_spi_flash, flash); +} + +static const struct stmicro_spi_flash_params stmicro_spi_flash_table[] = { + { + .idcode1 = STM_ID_M25P16, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 32, + .name = "M25P16", + }, + { + .idcode1 = STM_ID_M25P20, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 4, + .name = "M25P20", + }, + { + .idcode1 = STM_ID_M25P32, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 64, + .name = "M25P32", + }, + { + .idcode1 = STM_ID_M25P40, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 8, + .name = "M25P40", + }, + { + .idcode1 = STM_ID_M25P64, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 128, + .name = "M25P64", + }, + { + .idcode1 = STM_ID_M25P80, + .page_size = 256, + .pages_per_sector = 256, + .nr_sectors = 16, + .name = "M25P80", + }, + { + .idcode1 = STM_ID_M25P128, + .page_size = 256, + .pages_per_sector = 1024, + .nr_sectors = 64, + .name = "M25P128", + }, +}; + +static int stmicro_wait_ready(struct spi_flash *flash, unsigned long timeout) +{ + struct spi_slave *spi = flash->spi; + unsigned long timebase; + int ret; + u8 status; + u8 cmd[4] = { CMD_M25PXX_RDSR, 0xff, 0xff, 0xff }; + + ret = spi_xfer(spi, 32, &cmd[0], NULL, SPI_XFER_BEGIN); + if (ret) { + debug("SF: Failed to send command %02x: %d\n", cmd, ret); + return ret; + } + + timebase = get_timer(0); + do { + ret = spi_xfer(spi, 8, NULL, &status, 0); + if (ret) + return -1; + + if ((status & STMICRO_SR_WIP) == 0) + break; + + } while (get_timer(timebase) < timeout); + + spi_xfer(spi, 0, NULL, NULL, SPI_XFER_END); + + if ((status & STMICRO_SR_WIP) == 0) + return 0; + + /* Timed out */ + return -1; +} + +static int stmicro_read_fast(struct spi_flash *flash, + u32 offset, size_t len, void *buf) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long page_addr; + unsigned long page_size; + u8 cmd[5]; + + page_size = stm->params->page_size; + page_addr = offset / page_size; + + cmd[0] = CMD_READ_ARRAY_FAST; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = offset % page_size; + cmd[4] = 0x00; + + return spi_flash_read_common(flash, cmd, sizeof(cmd), buf, len); +} + +static int stmicro_write(struct spi_flash *flash, + u32 offset, size_t len, const void *buf) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long page_addr; + unsigned long byte_addr; + unsigned long page_size; + size_t chunk_len; + size_t actual; + int ret; + u8 cmd[4]; + + page_size = stm->params->page_size; + page_addr = offset / page_size; + byte_addr = offset % page_size; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual += chunk_len) { + chunk_len = min(len - actual, page_size - byte_addr); + + cmd[0] = CMD_M25PXX_PP; + cmd[1] = page_addr >> 8; + cmd[2] = page_addr; + cmd[3] = byte_addr; + + debug + ("PP: 0x%p => cmd = { 0x%02x 0x%02x%02x%02x } chunk_len = %d\n", + buf + actual, cmd[0], cmd[1], cmd[2], cmd[3], chunk_len); + + ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, + buf + actual, chunk_len); + if (ret < 0) { + debug("SF: STMicro Page Program failed\n"); + break; + } + + ret = stmicro_wait_ready(flash, SPI_FLASH_PROG_TIMEOUT); + if (ret < 0) { + debug("SF: STMicro page programming timed out\n"); + break; + } + + page_addr++; + byte_addr = 0; + } + + debug("SF: STMicro: Successfully programmed %u bytes @ 0x%x\n", + len, offset); + + spi_release_bus(flash->spi); + return ret; +} + +int stmicro_erase(struct spi_flash *flash, u32 offset, size_t len) +{ + struct stmicro_spi_flash *stm = to_stmicro_spi_flash(flash); + unsigned long sector_size; + size_t actual; + int ret; + u8 cmd[4]; + + /* + * This function currently uses sector erase only. + * probably speed things up by using bulk erase + * when possible. + */ + + sector_size = stm->params->page_size * stm->params->pages_per_sector; + + if (offset % sector_size || len % sector_size) { + debug("SF: Erase offset/length not multiple of sector size\n"); + return -1; + } + + len /= sector_size; + cmd[0] = CMD_M25PXX_SE; + cmd[2] = 0x00; + cmd[3] = 0x00; + + ret = spi_claim_bus(flash->spi); + if (ret) { + debug("SF: Unable to claim SPI bus\n"); + return ret; + } + + ret = 0; + for (actual = 0; actual < len; actual++) { + cmd[1] = (offset / sector_size) + actual; + + ret = spi_flash_cmd(flash->spi, CMD_M25PXX_WREN, NULL, 0); + if (ret < 0) { + debug("SF: Enabling Write failed\n"); + break; + } + + ret = spi_flash_cmd_write(flash->spi, cmd, 4, NULL, 0); + if (ret < 0) { + debug("SF: STMicro page erase failed\n"); + break; + } + + ret = stmicro_wait_ready(flash, 2 * CFG_HZ); /* Up to 2 seconds */ + if (ret < 0) { + debug("SF: STMicro page erase timed out\n"); + break; + } + } + + debug("SF: STMicro: Successfully erased %u bytes @ 0x%x\n", + len * sector_size, offset); + + spi_release_bus(flash->spi); + return ret; +} + +struct spi_flash *spi_flash_probe_stmicro(struct spi_slave *spi, u8 * idcode) +{ + const struct stmicro_spi_flash_params *params; + struct stmicro_spi_flash *stm; + unsigned int i; + int ret; + u8 id[3]; + + ret = spi_flash_cmd(spi, CMD_READ_ID, id, sizeof(id)); + if (ret) + return NULL; + + for (i = 0; i < ARRAY_SIZE(stmicro_spi_flash_table); i++) { + params = &stmicro_spi_flash_table[i]; + if (params->idcode1 == idcode[2]) { + break; + } + } + + if (i == ARRAY_SIZE(stmicro_spi_flash_table)) { + debug("SF: Unsupported STMicro ID %02x\n", id[1]); + return NULL; + } + + stm = malloc(sizeof(struct stmicro_spi_flash)); + if (!stm) { + debug("SF: Failed to allocate memory\n"); + return NULL; + } + + stm->params = params; + stm->flash.spi = spi; + stm->flash.name = params->name; + + stm->flash.write = stmicro_write; + stm->flash.erase = stmicro_erase; + stm->flash.read = stmicro_read_fast; + stm->flash.size = params->page_size * params->pages_per_sector + * params->nr_sectors; + + debug("SF: Detected %s with page size %u, total %u bytes\n", + params->name, params->page_size, stm->flash.size); + + return &stm->flash; +} -- 1.5.6.4

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[U-Boot] [patch] i.MX use u-boot baud rate and don't assume UART master clock
by Andrew Dyer 28 Aug '08

28 Aug '08

1) Change the i.MX serial driver to use the baud rate set in the u-boot environment 2) don't assume a 16MHz value for PERCLK1 in baud rate calculations 3) don't write a 1 to the RDR bit in the USR2 reg. (bit is not "write one to clear" like other status bits in the reg.) Signed-off-by: Andrew Dyer <adyer(a)righthandtech.com> --- cpu/arm920t/imx/serial.c | 34 ++++++++++++++++++++++++++++++---- 1 files changed, 30 insertions(+), 4 deletions(-) diff --git a/cpu/arm920t/imx/serial.c b/cpu/arm920t/imx/serial.c index 6c56acb..ea5f42c 100644 --- a/cpu/arm920t/imx/serial.c +++ b/cpu/arm920t/imx/serial.c @@ -52,6 +52,8 @@ struct imx_serial { volatile uint32_t uts; }; +DECLARE_GLOBAL_DATA_PTR; + void serial_setbrg (void) { serial_init(); @@ -67,6 +69,9 @@ extern void imx_gpio_mode(int gpio_mode); int serial_init (void) { volatile struct imx_serial* base = (struct imx_serial *)UART_BASE; + unsigned int ufcr_rfdiv; + unsigned int refclk; + #ifdef CONFIG_IMX_SERIAL1 imx_gpio_mode(PC11_PF_UART1_TXD); imx_gpio_mode(PC12_PF_UART1_RXD); @@ -95,11 +100,33 @@ int serial_init (void) /* Configure FIFOs */ base->ufcr = 0xa81; + /* set the baud rate. + * + * baud * 16 x + * --------- = - + * refclk y + * + * x - 1 = UBIR + * y - 1 = UBMR + * + * each register is 16 bits wide. refclk max is 96 MHz + * + */ + + ufcr_rfdiv = ((base->ufcr) & UFCR_RFDIV) >> 7; + if (ufcr_rfdiv == 6) + ufcr_rfdiv = 7; + else + ufcr_rfdiv = 6 - ufcr_rfdiv; + + refclk = get_PERCLK1(); + refclk /= ufcr_rfdiv; + /* Set the numerator value minus one of the BRM ratio */ - base->ubir = (CONFIG_BAUDRATE / 100) - 1; + base->ubir = (gd->baudrate / 100) - 1; /* Set the denominator value minus one of the BRM ratio */ - base->ubmr = 10000 - 1; + base->ubmr = (refclk/(16 * 100)) - 1; /* Set to 8N1 */ base->ucr2 &= ~UCR2_PREN; @@ -123,8 +150,7 @@ int serial_init (void) USR2_WAKE | USR2_RTSF | USR2_BRCD | - USR2_ORE | - USR2_RDR; + USR2_ORE; /* Clear status flags */ base->usr1 |= USR1_PARITYERR | -- 1.5.4.3

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Re: [U-Boot] [U-Boot-Users] [PATCH 4/4] ARM DaVinci: Standardize names ofdirectories/files
by Hugo Villeneuve 28 Aug '08

28 Aug '08

Jean-Christophe PLAGNIOL-VILLARD wrote: > On 15:10 Fri 11 Jul , Hugo Villeneuve wrote: >> ARM DaVinci: Standardize names of directories/files. >> >> Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> >> >> --- >> >> Makefile | 2 +- >> board/davinci/{dv-evm => dvevm}/Makefile | 2 +- >> board/davinci/{dv-evm => dvevm}/board_init.S | 0 >> board/davinci/{dv-evm => dvevm}/config.mk | 0 >> board/davinci/{dv-evm/dv_board.c => dvevm/dvevm.c} | 0 >> board/davinci/{dv-evm => dvevm}/u-boot.lds | 0 >> board/davinci/schmoogie/Makefile | 2 +- >> .../davinci/schmoogie/{dv_board.c => schmoogie.c} | 0 >> board/davinci/sonata/Makefile | 2 +- >> board/davinci/sonata/{dv_board.c => sonata.c} | 0 >> 10 files changed, 4 insertions(+), 4 deletions(-) >> > Applied to u-boot-arm with merge > please check Everything seems OK. Hugo V. Hugo Villeneuve Hardware developer | Concepteur matériel Lyrtech Phone/Tél. : (1) (418) 877-4644 #2395 Toll-free/Sans frais - Canada & USA : (1) (888) 922-4644 #2395 Fax/Téléc. : (1) (418) 877-7710 www.lyrtech.com Infinite possibilities...TM

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