July 2008 - U-Boot

[U-Boot-Users] [PATCH 2/3] Add initial PPC460SX reference board (redwood) config file and defines.
by fkan＠amcc.com 04 Jul '08

04 Jul '08

From: Feng Kan <fkan(a)amcc.com> Add config file for AMCC redwood reference board for PPC460SX. Also include defines for PPC460SX processor. Signed-off-by: Feng Kan <fkan(a)amcc.com> --- include/asm-ppc/ppc4xx-sdram.h | 3 +- include/asm-ppc/processor.h | 4 + include/configs/redwood.h | 211 ++++++++++++++++++++++++++++++++++++++++ include/ppc440.h | 20 +++-- include/ppc4xx.h | 3 +- 5 files changed, 232 insertions(+), 9 deletions(-) create mode 100644 include/configs/redwood.h diff --git a/include/asm-ppc/ppc4xx-sdram.h b/include/asm-ppc/ppc4xx-sdram.h index 83931f1..6eb8209 100644 --- a/include/asm-ppc/ppc4xx-sdram.h +++ b/include/asm-ppc/ppc4xx-sdram.h @@ -282,7 +282,8 @@ * Memory Bank 0-7 configuration */ #if defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define SDRAM_RXBAS_SDBA_MASK 0xFFE00000 /* Base address */ #define SDRAM_RXBAS_SDBA_ENCODE(n) ((((u32)(n))&0xFFE00000)>>2) #define SDRAM_RXBAS_SDBA_DECODE(n) ((((u32)(n))&0xFFE00000)<<2) diff --git a/include/asm-ppc/processor.h b/include/asm-ppc/processor.h index 5b50679..7f1e34f 100644 --- a/include/asm-ppc/processor.h +++ b/include/asm-ppc/processor.h @@ -810,6 +810,10 @@ #define PVR_460EX_RA 0x130218A3 /* 460EX rev A without Security Engine */ #define PVR_460GT_SE_RA 0x130218A0 /* 460GT rev A with Security Engine */ #define PVR_460GT_RA 0x130218A1 /* 460GT rev A without Security Engine */ +#define PVR_460SX_RA 0x13541800 /* 460SX rev A */ +#define PVR_460SX_RA_V1 0x13541801 /* 460SX rev A Variant 1 Security disabled */ +#define PVR_460GX_RA 0x13541802 /* 460GX rev A */ +#define PVR_460GX_RA_V1 0x13541803 /* 460GX rev A Variant 1 Security disabled */ #define PVR_601 0x00010000 #define PVR_602 0x00050000 #define PVR_603 0x00030000 diff --git a/include/configs/redwood.h b/include/configs/redwood.h new file mode 100644 index 0000000..bf4468b --- /dev/null +++ b/include/configs/redwood.h @@ -0,0 +1,211 @@ +/* + * Configuration for AMCC 460SX Ref (redwood) + * + * (C) Copyright 2008 + * Feng Kan, Applied Micro Circuits Corp., fkan(a)amcc.com + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_440 1 /* ... PPC460 family */ +#define CONFIG_460SX 1 /* ... PPC460 family */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_pre_init */ + +/*----------------------------------------------------------------------- + * Include common defines/options for all AMCC boards + *----------------------------------------------------------------------*/ +#define CONFIG_HOSTNAME redwood + +#include "amcc-common.h" + +#define CONFIG_SYS_CLK_FREQ 33333333 /* external freq to pll */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0xfff00000 /* start of FLASH */ +#define CFG_PERIPHERAL_BASE 0xa0000000 /* internal peripherals */ +#define CFG_ISRAM_BASE 0x90000000 /* internal SRAM */ + +#define CFG_PCI_BASE 0xd0000000 /* internal PCI regs */ + +#define CFG_PCIE_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE0_MEMBASE 0x90000000 /* mapped PCIe memory */ +#define CFG_PCIE1_MEMBASE 0xa0000000 /* mapped PCIe memory */ +#define CFG_PCIE_MEMSIZE 0x01000000 + +#define CFG_PCIE0_XCFGBASE 0xb0000000 +#define CFG_PCIE1_XCFGBASE 0xb2000000 +#define CFG_PCIE2_XCFGBASE 0xb4000000 +#define CFG_PCIE0_CFGBASE 0xb6000000 +#define CFG_PCIE1_CFGBASE 0xb8000000 +#define CFG_PCIE2_CFGBASE 0xba000000 + +/* PCIe mapped UTL registers */ +#define CFG_PCIE0_REGBASE 0xd0000000 +#define CFG_PCIE1_REGBASE 0xd0010000 +#define CFG_PCIE2_REGBASE 0xd0020000 + +/* System RAM mapped to PCI space */ +#define CONFIG_PCI_SYS_MEM_BUS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_PHYS CFG_SDRAM_BASE +#define CONFIG_PCI_SYS_MEM_SIZE (1024 * 1024 * 1024) + +#define CFG_FPGA_BASE 0xe2000000 /* epld */ +#define CFG_OPER_FLASH 0xe7000000 /* SRAM - OPER Flash */ + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer (placed in internal SRAM) + *----------------------------------------------------------------------*/ +#define CFG_TEMP_STACK_OCM 1 +#define CFG_OCM_DATA_ADDR CFG_ISRAM_BASE +#define CFG_INIT_RAM_ADDR CFG_ISRAM_BASE /* Initial RAM address */ +#define CFG_INIT_RAM_END 0x2000 /* End of used area in RAM */ +#define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ + +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) +#define CFG_INIT_SP_OFFSET CFG_POST_WORD_ADDR + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CONFIG_SPD_EEPROM 1 /* Use SPD EEPROM for setup */ +#define CONFIG_DDR_ECC 1 /* with ECC support */ + +#define CFG_SPD_MAX_DIMMS 2 + +/* SPD i2c spd addresses */ +#if CFG_SPD_MAX_DIMMS == 4 +#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR, IIC0_DIMM2_ADDR, IIC0_DIMM3_ADDR} +#define IIC0_DIMM0_ADDR 0x53 +#define IIC0_DIMM1_ADDR 0x52 +#define IIC0_DIMM2_ADDR 0x51 +#define IIC0_DIMM3_ADDR 0x50 + +#elif CFG_SPD_MAX_DIMMS == 3 +#define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR, IIC0_DIMM2_ADDR} +#define IIC0_DIMM0_ADDR 0x53 +#define IIC0_DIMM1_ADDR 0x52 +#define IIC0_DIMM2_ADDR 0x51 + +#elif CFG_SPD_MAX_DIMMS == 2 + #define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR, IIC0_DIMM1_ADDR} + #define IIC0_DIMM0_ADDR 0x53 + #define IIC0_DIMM1_ADDR 0x52 + +#elif CFG_SPD_MAX_DIMMS == 1 + #define SPD_EEPROM_ADDRESS {IIC0_DIMM0_ADDR} + #define IIC0_DIMM0_ADDR 0x53 +#endif + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CFG_I2C_SPEED 400000 /* I2C speed */ + +#define IIC0_BOOTPROM_ADDR 0x50 +#define IIC0_ALT_BOOTPROM_ADDR 0x54 + +/* Don't probe these addrs */ +#define CFG_I2C_NOPROBES {0x50, 0x52, 0x53, 0x54} + +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* Bytes of address */ + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#undef CFG_ENV_IS_IN_NVRAM /* ... not in NVRAM */ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment uses flash */ +#undef CFG_ENV_IS_IN_EEPROM /* ... not in EEPROM */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + CONFIG_AMCC_DEF_ENV \ + CONFIG_AMCC_DEF_ENV_POWERPC \ + CONFIG_AMCC_DEF_ENV_NOR_UPD \ + CONFIG_AMCC_DEF_ENV_NAND_UPD \ + "kernel_addr=fc000000\0" \ + "fdt_addr=fc1e0000\0" \ + "ramdisk_addr=fc200000\0" \ + "" + +/*----------------------------------------------------------------------------+ +| Commands in addition to amcc-common.h ++----------------------------------------------------------------------------*/ +#define CONFIG_CMD_SDRAM + +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_RESET_DELAY 1000 +#define CONFIG_M88E1141_PHY 1 /* Enable phy */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CONFIG_HAS_ETH1 +#define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ +#define CONFIG_PHY1_ADDR 1 /* PHY address, See schematics */ +#define CONFIG_PHY2_ADDR 2 /* PHY address, See schematics */ +#define CONFIG_PHY3_ADDR 3 /* PHY address, See schematics */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ +#define CFG_FLASH_CFI_AMD_RESET 1 /* Use AMD (Spansion) reset cmd */ + +#define CFG_MAX_FLASH_BANKS 3 /* number of banks */ +#define CFG_MAX_FLASH_SECT 256 /* sectors per device */ + +#undef CFG_FLASH_CHECKSUM +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_ADDR0 0x5555 +#define CFG_FLASH_ADDR1 0x2aaa +#define CFG_FLASH_WORD_SIZE unsigned char + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x10000 /* size of one complete sector */ +#define CFG_ENV_ADDR 0xfffa0000 +#define CFG_ENV_SIZE 0x10000 /* Size of Environment vars */ +#endif /* CFG_ENV_IS_IN_FLASH */ + +/*---------------------------------------------------------------------------*/ + +#endif /* __CONFIG_H */ diff --git a/include/ppc440.h b/include/ppc440.h index c581f1b..fe988fb 100644 --- a/include/ppc440.h +++ b/include/ppc440.h @@ -749,7 +749,8 @@ +----------------------------------------------------------------------------*/ #if defined (CONFIG_440GX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define L2_CACHE_BASE 0x030 #define l2_cache_cfg (L2_CACHE_BASE+0x00) /* L2 Cache Config */ #define l2_cache_cmd (L2_CACHE_BASE+0x01) /* L2 Cache Command */ @@ -837,7 +838,8 @@ /*----------------------------------------------------------------------------- | Clocking, Power Management and Chip Control +----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define CNTRL_DCR_BASE 0x160 #else #define CNTRL_DCR_BASE 0x0b0 @@ -896,7 +898,8 @@ #if defined(CONFIG_440SPE) || \ defined(CONFIG_440EPX) || defined(CONFIG_440GRX) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define UIC2_DCR_BASE 0xe0 #define uic2sr (UIC2_DCR_BASE+0x0) /* UIC2 status-Read Clear */ #define uic2srs (UIC2_DCR_BASE+0x1) /* UIC2 status-Read Set */ @@ -1608,7 +1611,8 @@ #define UICB0_ALL (UICB0_UIC0CI | UICB0_UIC0NCI | UICB0_UIC1CI | \ UICB0_UIC1NCI | UICB0_UIC2CI | UICB0_UIC2NCI) -#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) +#elif defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define UICB0_UIC1NCI 0x00000002 /* UIC1 Noncritical Interrupt */ #define UICB0_UIC1CI 0x00000001 /* UIC1 Critical Interrupt */ @@ -1855,7 +1859,7 @@ #define SDR0_DDR0_TUNE_DECODE(n) ((((unsigned long)(n))>>0)&0x2FF) #endif -#if defined(CONFIG_440SPE) +#if defined(CONFIG_440SPE) || defined(CONFIG_460SX) #define SDR0_CP440 0x0180 #define SDR0_CP440_ERPN_MASK 0x30000000 #define SDR0_CP440_ERPN_MASK_HI 0x3000 @@ -2793,7 +2797,8 @@ /*-----------------------------------------------------------------------------+ | Clocking +-----------------------------------------------------------------------------*/ -#if defined(CONFIG_460EX) || defined(CONFIG_460GT) +#if defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define PLLSYS0_FWD_DIV_A_MASK 0x000000f0 /* Fwd Div A */ #define PLLSYS0_FWD_DIV_B_MASK 0x0000000f /* Fwd Div B */ #define PLLSYS0_FB_DIV_MASK 0x0000ff00 /* Feedback divisor */ @@ -3145,7 +3150,8 @@ * GPIO macro register defines ******************************************************************************/ #if defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ - defined(CONFIG_440SP) || defined(CONFIG_440SPE) + defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ + defined(CONFIG_460SX) #define GPIO0_BASE (CFG_PERIPHERAL_BASE+0x00000700) #define GPIO0_OR (GPIO0_BASE+0x0) diff --git a/include/ppc4xx.h b/include/ppc4xx.h index 0a8479f..54897f7 100644 --- a/include/ppc4xx.h +++ b/include/ppc4xx.h @@ -41,7 +41,8 @@ #if defined(CONFIG_405EX) || \ defined(CONFIG_440SP) || defined(CONFIG_440SPE) || \ - defined(CONFIG_460EX) || defined(CONFIG_460GT) + defined(CONFIG_460EX) || defined(CONFIG_460GT) || \ + defined(CONFIG_460SX) #define CONFIG_SDRAM_PPC4xx_IBM_DDR2 /* IBM DDR(2) controller */ #endif -- 1.5.6.1

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[U-Boot-Users] u-boot and OneNAND
by Mile Davidovic 04 Jul '08

04 Jul '08

Hello If I read code correctly u-boot have OneNAND driver. But when I check JFFS2 in u-boot it seems that JFFS2 can not work on OneNAND. What is proposed way of working with OneNAND and u-boot? Do we have some support for bad block management? Thanks in advace Mile

3 5

[U-Boot-Users] Flash Functions !!
by Amit Kumar 04 Jul '08

04 Jul '08

Hello, We are using board pxa255, UBoot version 1.3.3, FLASH chipset is PC28F256P30B85 (two chipsets) connected to same chip select. This FLASH supports CFI and U-Boot code has CFI_FLASH.c. Do we need to write functions (Read, Write, erase) for this FLASH or U-Boot has support for this already? Regards Amit Kumar P.S: Please ignore the disclaimer as I cannot remove it. **************** CAUTION - Disclaimer ***************** This e-mail contains PRIVILEGED AND CONFIDENTIAL INFORMATION intended solely for the use of the addressee(s). If you are not the intended recipient, please notify the sender by e-mail and delete the original message. Further, you are not to copy, disclose, or distribute this e-mail or its contents to any other person and any such actions are unlawful. This e-mail may contain viruses. Infosys has taken every reasonable precaution to minimize this risk, but is not liable for any damage you may sustain as a result of any virus in this e-mail. You should carry out your own virus checks before opening the e-mail or attachment. Infosys reserves the right to monitor and review the content of all messages sent to or from this e-mail address. Messages sent to or from this e-mail address may be stored on the Infosys e-mail system. ***INFOSYS******** End of Disclaimer ********INFOSYS***

2 1

[U-Boot-Users] (no subject)
by 钟文辉 04 Jul '08

04 Jul '08

各位老总：您们好！诚祝：您们在2008年里；有鼠不尽的快乐！鼠不尽的收获！鼠不尽的钞票！　鼠不尽的幸福！鼠不尽的美满生活！愿：您们阖家欢乐！幸福安康！我公司可以长期提供：出口报关单，核销单，等等一系列手续；代理：出口报关，商检，境内外运输......等等；还可以代办：出口欧盟许可证，欧盟产地证；并且还有（广州国际贸易交易会）的摊位可以转让；价格特别优惠；有意者请来邮件或来电联系。谢谢合作！　电话：0755-81153047。　传真：0755-81172940。　手机：15817477278。　联系人：钟文辉。　电子邮箱:shanhu.dao@163.com 此致：敬礼！

3 4

[U-Boot-Users] [PATCH] update e1000 ifdef
by Andre Schwarz 04 Jul '08

04 Jul '08

Change ifdef to match "MVBC_P" board name. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- Ben, this is a mini-patch and should do no harm. Since MVBC_1G has gone to oblivion and the new board is named MVBC_P. I'll submit the board patch in a few minutes. Thanks, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner drivers/net/e1000.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index c31029a..754a0bb 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -3031,7 +3031,7 @@ e1000_initialize(bd_t * bis) free(nic); return 0; } -#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) +#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_P)) if (e1000_validate_eeprom_checksum(nic) < 0) { printf("The EEPROM Checksum Is Not Valid\n"); free(hw);

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[U-Boot-Users] [PATCH　v2] net: smc911x: Add support RSK7203 board to smc911x
by Nobuhiro Iwamatsu 04 Jul '08

04 Jul '08

The RSK board has the SMSC9118 wired up 'incorrectly'. Byte-swapping is necessary, and so poor performance is inevitable. This problem cannot evade by the swap function of CHIP, this can evade by software Byte-swapping. And this has problem by FIFO access only. pkt_data_pull/pkt_data_push functions necessary to solve this problem. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- drivers/net/smc911x.c | 34 +++++++++++++++++++++++++++++++--- 1 files changed, 31 insertions(+), 3 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 1484b0b..cc8aaf0 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -1,5 +1,5 @@ /* - * SMSC LAN9[12]1[567] Network driver + * SMSC LAN9[12]1[5678] Network driver * * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> * @@ -26,6 +26,7 @@ #include <command.h> #include <net.h> #include <miiphy.h> +#include <asm/byteorder.h> #if defined (CONFIG_DRIVER_SMC911X_32_BIT) && \ defined (CONFIG_DRIVER_SMC911X_16_BIT) @@ -53,6 +54,33 @@ static inline void reg_write(u32 addr, u32 val) *(volatile u16*)addr = (u16)val; *(volatile u16*)(addr + 2) = (u16)(val >> 16); } + +#if defined(CONFIG_RSK7203) +/* + * The RSK board has the SMSC9118 wired up 'incorrectly'. + * Byte-swapping is necessary, and so poor performance is inevitable. + * This problem cannot evade by the swap function of CHIP, this can + * evade by software Byte-swapping. + * And this has problem by FIFO access only. pkt_data_pull/pkt_data_push + * functions necessary to solve this problem. + */ +static inline u32 pkt_data_pull(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + return (((swab16(*addr_16) << 16) & 0xFFFF0000)|swab16(*(addr_16 + 1))); +} + +static inline void pkt_data_push(u32 addr, u32 val) +{ + *(volatile u16 *)(addr + 2) = swab16((u16)val); + *(volatile u16 *)(addr) = swab16((u16)(val >> 16)); +} + +#else +# define pkt_data_pull(x) reg_read(x) +# define pkt_data_push(x, l) reg_write(x, l) +#endif /* CONFIG_RSK7203 */ + #else #error "SMC911X: undefined bus width" #endif /* CONFIG_DRIVER_SMC911X_16_BIT */ @@ -641,7 +669,7 @@ int eth_send(volatile void *packet, int length) tmplen = (length + 3) / 4; while (tmplen--) - reg_write(TX_DATA_FIFO, *data++); + pkt_data_push(TX_DATA_FIFO, *data++); /* wait for transmission */ while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16)); @@ -684,7 +712,7 @@ int eth_rx(void) tmplen = (pktlen + 2+ 3) / 4; while (tmplen--) - *data++ = reg_read(RX_DATA_FIFO); + *data++ = pkt_data_pull(RX_DATA_FIFO); if (status & RX_STS_ES) printf(DRIVERNAME -- 1.5.5.1

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[U-Boot-Users] Unable to erase or write into flash
by navin karnam 04 Jul '08

04 Jul '08

Hi all, I ported u-boot-1.3.3 on board, when boot the board iam getting messagesas below. ------------------------------------------------------------------------------------------- U-Boot 1.3.3 (Jul 3 2008 - 10:17:59) DRAM: 64 MB Flash: 64 MB *** Warning - bad CRC, using default environment In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 ----------------------------------------------------------------------------------------------------------- But when try erasing flash : #erase all Erase Flash Bank # 1 - Warning: 259 protected sectors will not be erased! done So i enabled the flash for writing using: #protect off all Un-Protect Flash Bank # 1 After that also i am unable erase the flash: #erase all --------------------------------------------------- Flash erase error at address 680000 Block Erase Error. Block locked. Flash erase error at address 6c0000 Block Erase Error. Block locked. Flash erase error at address 700000 Block Erase Error. Block locked. Flash erase error at address 740000 Block Erase Error. Block locked. Flash erase error at address 780000 Block Erase Error. Block locked. Flash erase error at address 7c0000 Block Erase Error. Block locked. Flash erase error at address 800000 Block Erase Error. Block locked. Flash erase error at address 840000 Block Erase Error. Block locked. Flash erase error at address 880000 Block Erase Error. Block locked. Flash erase error at address 8c0000 Block Erase Error. Block locked. Flash erase error at address 900000 Block Erase Error. Block locked. Flash erase error at address 940000 Block Erase Error. Block locked. Flash erase error at address 980000 Block Erase Error. Block locked. Flash erase error at address 9c0000 Block Erase Error. Block locked. Flash erase error at address a00000 Block Erase Error. Block locked. Flash erase error at address a40000 Block Erase Error. Block locked. Flash erase error at address a80000 Block Erase Error. Block locked. Flash erase error at address ac0000 Block Erase Error. Block locked. Flash erase error at address b00000 Block Erase Error. Block locked. Flash erase error at address b40000 Block Erase Error. Block locked. Flash erase error at address b80000 Block Erase Error. Block locked. Flash erase error at address bc0000 Block Erase Error. Block locked. Flash erase error at address c00000 Block Erase Error. Block locked. Flash erase error at address c40000 Block Erase Error. Block locked. Flash erase error at address c80000 Block Erase Error. Block locked. Flash erase error at address cc0000 Block Erase Error. Block locked. Flash erase error at address d00000 Block Erase Error. Block locked. Flash erase error at address d40000 Block Erase Error. Block locked. Flash erase error at address d80000 Block Erase Error. Block locked. Flash erase error at address dc0000 Block Erase Error. Block locked. Flash erase error at address e00000 Block Erase Error. Block locked. Flash erase error at address e40000 Block Erase Error. Block locked. Flash erase error at address e80000 Block Erase Error. Block locked. Flash erase error at address ec0000 Block Erase Error. Block locked. Flash erase error at address f00000 Block Erase Error. Block locked. Flash erase error at address f40000 Block Erase Error. Block locked. Flash erase error at address f80000 Block Erase Error. Block locked. Flash erase error at address fc0000 Block Erase Error. Block locked. Flash erase error at address 1000000 Block Erase Error. Block locked. Flash erase error at address 1040000 Block Erase Error. Block locked. Flash erase error at address 1080000 Block Erase Error. Block locked. Flash erase error at address 10c0000 Block Erase Error. Block locked. Flash erase error at address 1100000 Block Erase Error. Block locked. Flash erase error at address 1140000 Block Erase Error. Block locked. Flash erase error at address 1180000 Block Erase Error. Block locked. Flash erase error at address 11c0000 Block Erase Error. Block locked. Flash erase error at address 1200000 Block Erase Error. Block locked. Flash erase error at address 1240000 Block Erase Error. Block locked. Flash erase error at address 1280000 Block Erase Error. Block locked. Flash erase error at address 12c0000 Block Erase Error. Block locked. Flash erase error at address 1300000 Block Erase Error. Block locked. Flash erase error at address 1340000 Block Erase Error. Block locked. Flash erase error at address 1380000 Block Erase Error. Block locked. Flash erase error at address 13c0000 Block Erase Error. Block locked. Flash erase error at address 1400000 Block Erase Error. Block locked. Flash erase error at address 1440000 Block Erase Error. Block locked. Flash erase error at address 1480000 Block Erase Error. Block locked. Flash erase error at address 14c0000 Block Erase Error. Block locked. Flash erase error at address 1500000 Block Erase Error. Block locked. Flash erase error at address 1540000 Block Erase Error. Block locked. Flash erase error at address 1580000 Block Erase Error. --------------------------------------------------------------------------------------- So how do i erase or write into flash, do i need to write my code which should do erase and writting into flash? or The code in u-boot is sufficient to that? Regards, Naveen Application Engineer Innovate Software Solutions Pvt Ltd., Bengalooru

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[U-Boot-Users] [PATCH] net: smc911x: sh: Add support RSK7203 board to smc911x
by Nobuhiro Iwamatsu 04 Jul '08

04 Jul '08

The RSK board has the SMSC9118 wired up 'incorrectly'. This problem can support in the software side. I put a code to evade it. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- drivers/net/smc911x.c | 37 +++++++++++++++++++++++++++++++++++-- 1 files changed, 35 insertions(+), 2 deletions(-) diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c index 1484b0b..ec731ea 100644 --- a/drivers/net/smc911x.c +++ b/drivers/net/smc911x.c @@ -53,6 +53,39 @@ static inline void reg_write(u32 addr, u32 val) *(volatile u16*)addr = (u16)val; *(volatile u16*)(addr + 2) = (u16)(val >> 16); } + +#if 0 //defined(CONFIG_RSK7203) +/* + * The RSK board has the SMSC9118 wired up 'incorrectly'. + * Byte-swapping is necessary, and so poor performance is inevitable. + * It seems that this is a problem with the SMSC chip, which has an + * endian facility, but it only works at the word level so... + */ +/* 2301_6745 --> 0123_4567 */ +#define PKT_SWAP(x) ((vu_long)((((vu_long)x << 8) & 0x0000FF00)|\ + (((vu_long)x >> 8) & 0x000000FF)|\ + (((vu_long)x << 8) & 0xFF000000)|\ + (((vu_long)x >> 8) & 0x00FF0000))) + +static inline u32 pkt_data_pull(u32 addr) +{ + volatile u16 *addr_16 = (u16 *)addr; + u32 d0 = (((*addr_16) << 16) & 0xFFFF0000); + u32 d1 = ((*(addr_16 + 1) & 0x0000FFFF)); + return PKT_SWAP((d0|d1)); +} + +static inline void pkt_data_push(u32 addr, u32 val) +{ + *(volatile u16 *)(addr + 2) = PKT_SWAP((u16)val); + *(volatile u16 *)(addr) = PKT_SWAP((u16)(val >> 16)); +} + +#else +# define pkt_data_pull(x) reg_read(x) +# define pkt_data_push(x, l) reg_write(x, l) +#endif /* CONFIG_RSK7203*/ + #else #error "SMC911X: undefined bus width" #endif /* CONFIG_DRIVER_SMC911X_16_BIT */ @@ -641,7 +674,7 @@ int eth_send(volatile void *packet, int length) tmplen = (length + 3) / 4; while (tmplen--) - reg_write(TX_DATA_FIFO, *data++); + pkt_data_push(TX_DATA_FIFO, *data++); /* wait for transmission */ while (!((reg_read(TX_FIFO_INF) & TX_FIFO_INF_TSUSED) >> 16)); @@ -684,7 +717,7 @@ int eth_rx(void) tmplen = (pktlen + 2+ 3) / 4; while (tmplen--) - *data++ = reg_read(RX_DATA_FIFO); + *data++ = pkt_data_pull(RX_DATA_FIFO); if (status & RX_STS_ES) printf(DRIVERNAME -- 1.5.5.1

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[U-Boot-Users] Whozat, the People Search Engine. Your account has been activated.
by team＠whozat.com 04 Jul '08

04 Jul '08

Dear New User, Thank you very much for joining Whozat, The People Search Engine, as a beta user. Your Whozat account is now active. You can now go to www.whozat.com and start searching! Help Us! If you love Whozat, and we know that you will, tell your friends about the new power at your fingertips. We also welcome your feedback to help us improve Whozat. During our product beta period, this is even more important: you have the chance to really shape the future. If you find any bugs, please let us know by e-mailing tellus(a)whozat.com. Whozat away, and welcome to Whozat! _______________________________________________________________________________ The Whozat team. � 2006-2008 Whozat, Inc. All rights reserved. Whozat is an abInventio company. You can remove yourself at any time by sending an email to unsubscribe(a)whozat.com

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[U-Boot-Users] e1000 problem @ current u-boot
by Andre Schwarz 03 Jul '08

03 Jul '08

Wolfgang, as far as I can see on the list you sent the latest patches for the e1000 driver. My e1000 (82541ER) stopped working on a MPC5200 based board with latest u-boot. I have a similar problem on another board ... Is your e1000 working properly on the latest u-boot ? Do I need any additional defines or environment settings to get it working again ? Obviously it is - again :-[ - my fault or is related to my build system. Any help is welcome. regards, Andre MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

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