July 2008 - U-Boot

[U-Boot-Users] [PATCH] Allow negative offset in command loads
by Ricardo Ribalda Delgado 18 Aug '08

18 Aug '08

Comand loads only allows positive offset for relocating the .srec files, this patch allows negative offsets Signed-off-by: Ricardo Ribalda Delgado <ricardo.ribalda(a)uam.es> --- common/cmd_load.c | 8 ++++---- 1 files changed, 4 insertions(+), 4 deletions(-) diff --git a/common/cmd_load.c b/common/cmd_load.c index 89f6403..ae56543 100644 --- a/common/cmd_load.c +++ b/common/cmd_load.c @@ -53,7 +53,7 @@ static int do_echo = 1; #if defined(CONFIG_CMD_LOADS) int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) { - ulong offset = 0; + long offset = 0; ulong addr; int i; char *env_echo; @@ -72,7 +72,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) #ifdef CFG_LOADS_BAUD_CHANGE if (argc >= 2) { - offset = simple_strtoul(argv[1], NULL, 16); + offset = simple_strtol(argv[1], NULL, 16); } if (argc == 3) { load_baudrate = (int)simple_strtoul(argv[2], NULL, 10); @@ -95,7 +95,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #else /* ! CFG_LOADS_BAUD_CHANGE */ if (argc == 2) { - offset = simple_strtoul(argv[1], NULL, 16); + offset = simple_strtol(argv[1], NULL, 16); } #endif /* CFG_LOADS_BAUD_CHANGE */ @@ -141,7 +141,7 @@ int do_load_serial (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } static ulong -load_serial (ulong offset) +load_serial (long offset) { char record[SREC_MAXRECLEN + 1]; /* buffer for one S-Record */ char binbuf[SREC_MAXBINLEN]; /* buffer for binary data */ -- 1.5.6.3

3 6

[U-Boot-Users] [PATCH] add 'unzip' command to u-boot commandline
by Harald Welte 18 Aug '08

18 Aug '08

[PATCH] add new 'unzip' command to u-boot commandline common/cmd_mem.c: new command "unzip srcaddr dstaddr [dstsize]" to unzip from memory to memory, and option CONFIG_CMD_UNZIP to enable it Signed-off-by: Werner Almesberger <werner(a)openmoko.org> Signed-off-by: Harald Welte <laforge(a)openmoko.org> diff --git a/common/cmd_mem.c b/common/cmd_mem.c index d6d7a5b..656f519 100644 --- a/common/cmd_mem.c +++ b/common/cmd_mem.c @@ -1191,6 +1191,34 @@ int do_mem_crc (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) } #endif /* CONFIG_CRC32_VERIFY */ + +#ifdef CONFIG_CMD_UNZIP +int gunzip (void *, int, unsigned char *, unsigned long *); + +int do_unzip ( cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long src, dst; + unsigned long src_len = ~0UL, dst_len = ~0UL; + int err; + + switch (argc) { + case 4: + dst_len = simple_strtoul(argv[3], NULL, 16); + /* fall through */ + case 3: + src = simple_strtoul(argv[1], NULL, 16); + dst = simple_strtoul(argv[2], NULL, 16); + break; + default: + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return !!gunzip((void *) dst, dst_len, (void *) src, &src_len); +} +#endif /* CONFIG_CMD_UNZIP */ + + /**************************************************/ #if defined(CONFIG_CMD_MEMORY) U_BOOT_CMD( @@ -1294,5 +1322,13 @@ U_BOOT_CMD( ); #endif /* CONFIG_MX_CYCLIC */ +#ifdef CONFIG_CMD_UNZIP +U_BOOT_CMD( + unzip, 4, 1, do_unzip, + "unzip - unzip a memory region\n", + "srcaddr dstaddr [dstsize]\n" +); +#endif /* CONFIG_CMD_UNZIP */ + #endif #endif diff --git a/include/config_cmd_all.h b/include/config_cmd_all.h index c2bb094..2cb2f67 100644 --- a/include/config_cmd_all.h +++ b/include/config_cmd_all.h @@ -77,6 +77,7 @@ #define CONFIG_CMD_SPI /* SPI utility */ #define CONFIG_CMD_TERMINAL /* built-in Serial Terminal */ #define CONFIG_CMD_UNIVERSE /* Tundra Universe Support */ +#define CONFIG_CMD_UNZIP /* unzip from memory to memory */ #define CONFIG_CMD_USB /* USB Support */ #define CONFIG_CMD_VFD /* VFD support (TRAB) */ #define CONFIG_CMD_XIMG /* Load part of Multi Image */ -- - Harald Welte <laforge(a)gnumonks.org> http://laforge.gnumonks.org/ ============================================================================ "Privacy in residential applications is a desirable marketing option." (ETSI EN 300 175-7 Ch. A6)

2 2

[U-Boot-Users] [PATCH] Allow console input to be disabled
by Mark Jackson 11 Aug '08

11 Aug '08

Added CONFIG_SILENT_CONSOLE_INPUT define. When used (in conjunction with CONFIG_SILENT_CONSOLE) it disables all console input. --- common/console.c | 10 ++++++++++ 1 files changed, 10 insertions(+), 0 deletions(-) diff --git a/common/console.c b/common/console.c index 1b095b1..ab071e2 100644 --- a/common/console.c +++ b/common/console.c @@ -162,6 +162,11 @@ void fprintf (int file, const char *fmt, ...) int getc (void) { +#if defined(CONFIG_SILENT_CONSOLE) && defined(CONFIG_SILENT_CONSOLE_INPUT) + if (gd->flags & GD_FLG_SILENT) + return 0; +#endif + if (gd->flags & GD_FLG_DEVINIT) { /* Get from the standard input */ return fgetc (stdin); @@ -173,6 +178,11 @@ int getc (void) int tstc (void) { +#if defined(CONFIG_SILENT_CONSOLE) && defined(CONFIG_SILENT_CONSOLE_INPUT) + if (gd->flags & GD_FLG_SILENT) + return 0; +#endif + if (gd->flags & GD_FLG_DEVINIT) { /* Test the standard input */ return ftstc (stdin);

5 13

[U-Boot-Users] [UPDATED] [PATCH v2] cfi-flash: Added support to flash_real_protect for Atmel flash devices (tested with AT49BV6416)
by Rafael Campos 06 Aug '08

06 Aug '08

Some of the flash memories produced by ATMEL start in read-only mode. We need to unprotect it. This patch allows the AT49BV6416 to work with cfi_flash memories. Tested in the at91rm9200ek board. Style modifications suggested by Stefan Roese. Signed-off-by: Rafael Campos Las Heras <rafael.campos(a)hanscan.com> --- drivers/mtd/cfi_flash.c | 49 +++++++++++++++++++++++++++++++++++++++++----- 1 files changed, 43 insertions(+), 6 deletions(-) diff --git a/drivers/mtd/cfi_flash.c b/drivers/mtd/cfi_flash.c index 12647ef..b72c144 100644 --- a/drivers/mtd/cfi_flash.c +++ b/drivers/mtd/cfi_flash.c @@ -103,6 +103,10 @@ #define AMD_STATUS_TOGGLE 0x40 #define AMD_STATUS_ERROR 0x20 +#define ATM_CMD_UNLOCK_SECT 0x70 +#define ATM_CMD_SOFTLOCK_START 0x80 +#define ATM_CMD_LOCK_SECT 0x40 + #define FLASH_OFFSET_MANUFACTURER_ID 0x00 #define FLASH_OFFSET_DEVICE_ID 0x01 #define FLASH_OFFSET_DEVICE_ID2 0x0E @@ -1351,12 +1355,45 @@ int flash_real_protect (flash_info_t * info, long sector, int prot) { int retcode = 0; - flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); - if (prot) - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_SET); - else - flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT_CLEAR); + switch (info->vendor) { + case CFI_CMDSET_INTEL_PROG_REGIONS: + case CFI_CMDSET_INTEL_STANDARD: + flash_write_cmd (info, sector, 0, + FLASH_CMD_CLEAR_STATUS); + flash_write_cmd (info, sector, 0, FLASH_CMD_PROTECT); + if (prot) + flash_write_cmd (info, sector, 0, + FLASH_CMD_PROTECT_SET); + else + flash_write_cmd (info, sector, 0, + FLASH_CMD_PROTECT_CLEAR); + break; + case CFI_CMDSET_AMD_EXTENDED: + case CFI_CMDSET_AMD_STANDARD: +#ifdef CONFIG_FLASH_CFI_LEGACY + case CFI_CMDSET_AMD_LEGACY: +#endif + /* U-Boot only checks the first byte */ + if (info->manufacturer_id == (uchar)ATM_MANUFACT) { + if (prot) { + flash_unlock_seq (info, 0); + flash_write_cmd (info, 0, + info->addr_unlock1, + ATM_CMD_SOFTLOCK_START); + flash_unlock_seq (info, 0); + flash_write_cmd (info, sector, 0, + ATM_CMD_LOCK_SECT); + } else { + flash_write_cmd (info, 0, + info->addr_unlock1, + AMD_CMD_UNLOCK_START); + if (info->device_id == ATM_ID_BV6416) + flash_write_cmd (info, sector, + 0, ATM_CMD_UNLOCK_SECT); + } + } + break; + }; if ((retcode = flash_full_status_check (info, sector, info->erase_blk_tout, -- 1.5.6.3

3 2

[U-Boot-Users] [PATCH 6/7] NAND: add NAND driver for s3c64xx
by Guennadi Liakhovetski 05 Aug '08

05 Aug '08

Ported from u-boot-1.1.6 driver by Samsung. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/s3c64xx.c | 373 ++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 374 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/s3c64xx.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 7bd22a0..236cf03 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -33,6 +33,7 @@ COBJS-y += nand_bbt.o COBJS-y += nand_util.o COBJS-y += fsl_upm.o +COBJS-$(CONFIG_NAND_S3C64XX) += s3c64xx.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/mtd/nand/s3c64xx.c b/drivers/mtd/nand/s3c64xx.c new file mode 100644 index 0000000..49d3440 --- /dev/null +++ b/drivers/mtd/nand/s3c64xx.c @@ -0,0 +1,315 @@ +/* + * (C) Copyright 2006 DENX Software Engineering + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#include <nand.h> +#include <s3c6400.h> + +#include <asm/io.h> + +#ifdef CONFIG_NAND_SPL +#define printf(arg...) do {} while (0) +#endif + +/* Nand flash definition values by jsgood */ +#define S3C_NAND_CFG_HWECC +#undef S3C_NAND_DEBUG + +#ifdef S3C_NAND_DEBUG +/* + * Function to print out oob buffer for debugging + * Written by jsgood + */ +static void print_oob(const char *header, struct mtd_info *mtd) +{ + int i; + struct nand_chip *chip = mtd->priv; + + printf("%s:\t", header); + + for(i = 0; i < 64; i++) + printf("%02x ", chip->oob_poi[i]); + + printf("\n"); +} +#endif /* S3C_NAND_DEBUG */ + +#ifdef CONFIG_NAND_SPL +static u_char nand_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *this = mtd->priv; + return readb(this->IO_ADDR_R); +} + +static void nand_write_byte(struct mtd_info *mtd, u_char byte) +{ + struct nand_chip *this = mtd->priv; + writeb(byte, this->IO_ADDR_W); +} + +static void nand_read_buf(struct mtd_info *mtd, u_char *buf, int len) +{ + int i; + struct nand_chip *this = mtd->priv; + + for (i = 0; i < len; i++) + buf[i] = readb(this->IO_ADDR_R); +} +#endif + +static void s3c_nand_select_chip(struct mtd_info *mtd, int chip) +{ + int ctrl = readl(NFCONT); + + switch (chip) { + case -1: + ctrl |= 6; + break; + case 0: + ctrl &= ~2; + break; + case 1: + ctrl &= ~4; + break; + default: + return; + } + + writel(ctrl, NFCONT); +} + +/* + * Hardware specific access to control-lines function + * Written by jsgood + */ +static void s3c_nand_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *this = mtd->priv; + + switch (cmd) { + case NAND_CTL_SETCLE: + this->IO_ADDR_W = (void __iomem *)NFCMMD; + break; + case NAND_CTL_CLRCLE: + this->IO_ADDR_W = (void __iomem *)NFDATA; + break; + case NAND_CTL_SETALE: + this->IO_ADDR_W = (void __iomem *)NFADDR; + break; + case NAND_CTL_CLRALE: + this->IO_ADDR_W = (void __iomem *)NFDATA; + break; + case NAND_CTL_SETNCE: + s3c_nand_select_chip(mtd, 0); + break; + case NAND_CTL_CLRNCE: + s3c_nand_select_chip(mtd, -1); + break; + } +} + +/* + * Function for checking device ready pin + * Written by jsgood + */ +static int s3c_nand_device_ready(struct mtd_info *mtdinfo) +{ + while (!(readl(NFSTAT) & NFSTAT_RnB)) {} + return 1; +} + +#ifdef S3C_NAND_CFG_HWECC +/* + * This function is called before encoding ecc codes to ready ecc engine. + * Written by jsgood + */ +static void s3c_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + u_long nfcont, nfconf; + + /* + * The original driver used 4-bit ECC for "new" MLC chips, i.e., for + * those with non-zero ID[3][3:2], which anyway only holds for ST + * (Numonyx) chips + */ + nfconf = readl(NFCONF) & ~NFCONF_ECC_4BIT; + + writel(nfconf, NFCONF); + + /* Initialize & unlock */ + nfcont = readl(NFCONT); + nfcont |= NFCONT_INITECC; + nfcont &= ~NFCONT_MECCLOCK; + + if (mode == NAND_ECC_WRITE) + nfcont |= NFCONT_ECC_ENC; + else if (mode == NAND_ECC_READ) + nfcont &= ~NFCONT_ECC_ENC; + + writel(nfcont, NFCONT); +} + +/* + * This function is called immediately after encoding ecc codes. + * This function returns encoded ecc codes. + * Written by jsgood + */ +static int s3c_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + u_long nfcont, nfmecc0; + + /* Lock */ + nfcont = readl(NFCONT); + nfcont |= NFCONT_MECCLOCK; + writel(nfcont, NFCONT); + + nfmecc0 = readl(NFMECC0); + + ecc_code[0] = nfmecc0 & 0xff; + ecc_code[1] = (nfmecc0 >> 8) & 0xff; + ecc_code[2] = (nfmecc0 >> 16) & 0xff; + ecc_code[3] = (nfmecc0 >> 24) & 0xff; + + return 0; +} + +/* + * This function determines whether read data is good or not. + * If SLC, must write ecc codes to controller before reading status bit. + * If MLC, status bit is already set, so only reading is needed. + * If status bit is good, return 0. + * If correctable errors occured, do that. + * If uncorrectable errors occured, return -1. + * Written by jsgood + */ +static int s3c_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + int ret = -1; + u_long nfestat0, nfmeccdata0, nfmeccdata1; + u_char err_type; + + /* SLC: Write ecc to compare */ + nfmeccdata0 = (calc_ecc[1] << 16) | calc_ecc[0]; + nfmeccdata1 = (calc_ecc[3] << 16) | calc_ecc[2]; + writel(nfmeccdata0, NFMECCDATA0); + writel(nfmeccdata1, NFMECCDATA1); + + /* Read ecc status */ + nfestat0 = readl(NFESTAT0); + err_type = nfestat0 & 0x3; + + switch (err_type) { + case 0: /* No error */ + ret = 0; + break; + + case 1: /* 1 bit error (Correctable) + (nfestat0 >> 7) & 0x7ff :error byte number + (nfestat0 >> 4) & 0x7 :error bit number */ + printf("S3C NAND: 1 bit error detected at byte %ld. Correcting from " + "0x%02x ", (nfestat0 >> 7) & 0x7ff, dat[(nfestat0 >> 7) & 0x7ff]); + dat[(nfestat0 >> 7) & 0x7ff] ^= (1 << ((nfestat0 >> 4) & 0x7)); + printf("to 0x%02x...OK\n", dat[(nfestat0 >> 7) & 0x7ff]); + ret = 1; + break; + + case 2: /* Multiple error */ + case 3: /* ECC area error */ + printf("S3C NAND: ECC uncorrectable error detected. Not correctable.\n"); + ret = -1; + break; + } + + return ret; +} +#endif /* S3C_NAND_CFG_HWECC */ + +/* + * Board-specific NAND initialization. The following members of the + * argument are board-specific (per include/linux/mtd/nand.h): + * - IO_ADDR_R?: address to read the 8 I/O lines of the flash device + * - IO_ADDR_W?: address to write the 8 I/O lines of the flash device + * - hwcontrol: hardwarespecific function for accesing control-lines + * - dev_ready: hardwarespecific function for accesing device ready/busy line + * - enable_hwecc?: function to enable (reset) hardware ecc generator. Must + * only be provided if a hardware ECC is available + * - eccmode: mode of ecc, see defines + * - chip_delay: chip dependent delay for transfering data from array to + * read regs (tR) + * - options: various chip options. They can partly be set to inform + * nand_scan about special functionality. See the defines for further + * explanation + * Members with a "?" were not set in the merged testing-NAND branch, + * so they are not set here either. + */ +#include <linux/mtd/mtd.h> +int board_nand_init(struct nand_chip *nand) +{ + NFCONT_REG = (NFCONT_REG & ~NFCONT_WP) | NFCONT_ENABLE | 0x6; + + nand->IO_ADDR_R = (void __iomem *)NFDATA; + nand->IO_ADDR_W = (void __iomem *)NFDATA; + nand->hwcontrol = s3c_nand_hwcontrol; + nand->dev_ready = s3c_nand_device_ready; + nand->select_chip = s3c_nand_select_chip; + nand->options = 0; +#ifdef CONFIG_NAND_SPL + nand->read_byte = nand_read_byte; + nand->write_byte = nand_write_byte; + nand->read_buf = nand_read_buf; +#endif + + do { + struct mtd_info m; + int cellinfo; + + m.priv = nand; + + s3c_nand_select_chip(&m, 0); + s3c_nand_hwcontrol(&m, NAND_CTL_SETCLE); + writeb(NAND_CMD_READID, nand->IO_ADDR_W); + s3c_nand_hwcontrol(&m, NAND_CTL_CLRCLE); + s3c_nand_device_ready(&m); + cellinfo = readb(nand->IO_ADDR_R); + cellinfo += readb(nand->IO_ADDR_R); + cellinfo += readb(nand->IO_ADDR_R); + s3c_nand_select_chip(&m, -1); + nand->eccmode = cellinfo; + } while (0); + +#ifdef S3C_NAND_CFG_HWECC + nand->enable_hwecc = s3c_nand_enable_hwecc; + nand->calculate_ecc = s3c_nand_calculate_ecc; + nand->correct_data = s3c_nand_correct_data; + + /* A shot in the dark, I don't know how to use this smart ECC-mode + * selection with the current driver */ + nand->eccmode = NAND_ECC_HW12_2048; +#else + nand->eccmode = NAND_ECC_SOFT; +#endif /* ! S3C_NAND_CFG_HWECC */ + + return 0; +} -- 1.5.4

4 35

[U-Boot-Users] [PATCH] NAND: Coding-style fixes
by Guennadi Liakhovetski 04 Aug '08

04 Aug '08

Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- drivers/mtd/nand/nand_base.c | 33 +++++++++++++++++---------------- 1 files changed, 17 insertions(+), 16 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 6416d15..49bf51d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -596,7 +596,7 @@ static void nand_command (struct mtd_info *mtd, unsigned command, int column, in /* * program and erase have their own busy handlers * status and sequential in needs no delay - */ + */ switch (command) { case NAND_CMD_PAGEPROG: @@ -621,7 +621,7 @@ static void nand_command (struct mtd_info *mtd, unsigned command, int column, in /* * If we don't have access to the busy pin, we apply the given * command delay - */ + */ if (!this->dev_ready) { udelay (this->chip_delay); return; @@ -690,7 +690,7 @@ static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, /* * program and erase have their own busy handlers * status and sequential in needs no delay - */ + */ switch (command) { case NAND_CMD_CACHEDPROG: @@ -726,7 +726,7 @@ static void nand_command_lp (struct mtd_info *mtd, unsigned command, int column, /* * If we don't have access to the busy pin, we apply the given * command delay - */ + */ if (!this->dev_ready) { udelay (this->chip_delay); return; @@ -758,7 +758,7 @@ static void nand_get_device (struct nand_chip *this, struct mtd_info *mtd, int n /* * Grab the lock and see if the device is available - */ + */ retry: /* Hardware controller shared among independend devices */ if (this->controller) { @@ -1070,7 +1070,7 @@ static int nand_verify_pages (struct mtd_info *mtd, struct nand_chip *this, int * is marked as NOAUTOINCR by the board driver. * Do this also before returning, so the chip is * ready for the next command. - */ + */ if (!this->dev_ready) udelay (this->chip_delay); else @@ -1153,13 +1153,13 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, } /* Grab the lock and see if the device is available */ - nand_get_device (this, mtd ,FL_READING); + nand_get_device (this, mtd, FL_READING); /* use userspace supplied oobinfo, if zero */ if (oobsel == NULL) oobsel = &mtd->oobinfo; - /* Autoplace of oob data ? Use the default placement scheme */ + /* Autoplace of oob data? Use the default placement scheme */ if (oobsel->useecc == MTD_NANDECC_AUTOPLACE) oobsel = this->autooob; @@ -1346,7 +1346,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, * Do this before the AUTOINCR check, so no problems * arise if a chip which does auto increment * is marked as NOAUTOINCR by the board driver. - */ + */ if (!this->dev_ready) udelay (this->chip_delay); else @@ -1369,7 +1369,7 @@ static int nand_read_ecc (struct mtd_info *mtd, loff_t from, size_t len, } /* Check, if the chip supports auto page increment * or if we have hit a block boundary. - */ + */ if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) sndcmd = 1; } @@ -1446,7 +1446,7 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t * Do this before the AUTOINCR check, so no problems * arise if a chip which does auto increment * is marked as NOAUTOINCR by the board driver. - */ + */ if (!this->dev_ready) udelay (this->chip_delay); else @@ -1466,7 +1466,7 @@ static int nand_read_oob (struct mtd_info *mtd, loff_t from, size_t len, size_t /* Check, if the chip supports auto page increment * or if we have hit a block boundary. - */ + */ if (!NAND_CANAUTOINCR(this) || !(page & blockcheck)) { /* For subsequent page reads set offset to 0 */ this->cmdfunc (mtd, NAND_CMD_READOOB, 0x0, page & this->pagemask); @@ -1731,7 +1731,7 @@ static int nand_write_ecc (struct mtd_info *mtd, loff_t to, size_t len, /* Have we hit a block boundary ? Then we have to verify and * if verify is ok, we have to setup the oob buffer for * the next pages. - */ + */ if (!(page & (ppblock - 1))){ int ofs; this->data_poi = bufstart; @@ -2376,7 +2376,8 @@ int nand_scan (struct mtd_info *mtd, int maxchips) if (nand_dev_id != nand_flash_ids[i].id) continue; - if (!mtd->name) mtd->name = nand_flash_ids[i].name; + if (!mtd->name) + mtd->name = nand_flash_ids[i].name; this->chipsize = nand_flash_ids[i].chipsize << 20; /* New devices have all the information in additional id bytes */ @@ -2549,7 +2550,7 @@ int nand_scan (struct mtd_info *mtd, int maxchips) * check ECC mode, default to software * if 3byte/512byte hardware ECC is selected and we have 256 byte pagesize * fallback to software ECC - */ + */ this->eccsize = 256; /* set default eccsize */ this->eccbytes = 3; @@ -2597,7 +2598,7 @@ int nand_scan (struct mtd_info *mtd, int maxchips) /* Check hardware ecc function availability and adjust number of ecc bytes per * calculation step - */ + */ switch (this->eccmode) { case NAND_ECC_HW12_2048: this->eccbytes += 4; -- 1.5.4

2 1

[U-Boot-Users] [PATCH] NAND: Do not write or read a whole block if it is larger than the environment
by Guennadi Liakhovetski 04 Aug '08

04 Aug '08

Environment can be smaller than NAND block size, do not need to read a whole block and minimum for writing is one page. Also remove an unused variable. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- common/env_nand.c | 18 +++++++++--------- 1 files changed, 9 insertions(+), 9 deletions(-) diff --git a/common/env_nand.c b/common/env_nand.c index 104f085..2a80bef 100644 --- a/common/env_nand.c +++ b/common/env_nand.c @@ -159,22 +159,23 @@ int writeenv(size_t offset, u_char *buf) { size_t end = offset + CFG_ENV_RANGE; size_t amount_saved = 0; - size_t blocksize; + size_t blocksize, len; u_char *char_ptr; blocksize = nand_info[0].erasesize; + len = min(blocksize, CFG_ENV_RANGE); while (amount_saved < CFG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { offset += blocksize; } else { char_ptr = &buf[amount_saved]; - if (nand_write(&nand_info[0], offset, &blocksize, + if (nand_write(&nand_info[0], offset, &len, char_ptr)) return 1; offset += blocksize; - amount_saved += blocksize; + amount_saved += len; } } if (amount_saved != CFG_ENV_SIZE) @@ -261,21 +262,22 @@ int readenv (size_t offset, u_char * buf) { size_t end = offset + CFG_ENV_RANGE; size_t amount_loaded = 0; - size_t blocksize; + size_t blocksize, len; u_char *char_ptr; blocksize = nand_info[0].erasesize; + len = min(blocksize, CFG_ENV_RANGE); while (amount_loaded < CFG_ENV_SIZE && offset < end) { if (nand_block_isbad(&nand_info[0], offset)) { offset += blocksize; } else { char_ptr = &buf[amount_loaded]; - if (nand_read(&nand_info[0], offset, &blocksize, char_ptr)) + if (nand_read(&nand_info[0], offset, &len, char_ptr)) return 1; offset += blocksize; - amount_loaded += blocksize; + amount_loaded += len; } } if (amount_loaded != CFG_ENV_SIZE) @@ -345,12 +347,10 @@ void env_relocate_spec (void) void env_relocate_spec (void) { #if !defined(ENV_IS_EMBEDDED) - size_t total; int ret; - total = CFG_ENV_SIZE; ret = readenv(CFG_ENV_OFFSET, (u_char *) env_ptr); - if (ret || total != CFG_ENV_SIZE) + if (ret) return use_default(); if (crc32(0, env_ptr->data, ENV_SIZE) != env_ptr->crc) -- 1.5.4

2 1

[U-Boot-Users] [PATCH] Move mpc5121 iopoin feature from board specific to common files.
by Kenneth Johansson 04 Aug '08

04 Aug '08

And in the process eliminate some duplicate register defines. Signed-off-by: Kenneth Johansson <kenneth(a)southpole.se> --- board/ads5121/Makefile | 2 +- board/ads5121/ads5121.c | 58 ++++++++++- board/ads5121/iopin.c | 115 --------------------- board/ads5121/iopin.h | 222 ----------------------------------------- cpu/mpc512x/Makefile | 2 +- cpu/mpc512x/iopin.c | 49 +++++++++ include/mpc512x.h | 251 ++++++++++++++++++++++++++++++++++++++++------ 7 files changed, 323 insertions(+), 376 deletions(-) delete mode 100644 board/ads5121/iopin.c delete mode 100644 board/ads5121/iopin.h create mode 100644 cpu/mpc512x/iopin.c diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index 5b95682..470848f 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -27,7 +27,7 @@ $(shell mkdir -p $(OBJTREE)/board/freescale/common) LIB = $(obj)lib$(BOARD).a -COBJS-y := $(BOARD).o iopin.o +COBJS-y := $(BOARD).o COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 8452054..ba3d7d2 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -23,14 +23,12 @@ #include <common.h> #include <mpc512x.h> -#include "iopin.h" #include <asm/bitops.h> #include <command.h> #include <fdt_support.h> #ifdef CONFIG_MISC_INIT_R #include <i2c.h> #endif -#include "iopin.h" /* for iopin_initialize() prototype */ /* Clocks in use */ #define SCCR1_CLOCKS_EN (CLOCK_SCCR1_CFG_EN | \ @@ -124,7 +122,7 @@ long int fixed_sdram (void) u32 i; /* Initialize IO Control */ - im->io_ctrl.regs[MEM_IDX] = IOCTRL_MUX_DDR; + im->io_ctrl.regs[IOCTL_MEM/4] = IOCTRL_MUX_DDR; /* Initialize DDR Local Window */ im->sysconf.ddrlaw.bar = CFG_DDR_BASE & 0xFFFFF000; @@ -237,6 +235,56 @@ int misc_init_r(void) return 0; } +static iopin_t ioregs_init[] = { + /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ + { + IOCTL_SPDIF_TXCLK, 3, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* Set highest Slew on 9 PATA pins */ + { + IOCTL_PATA_CE1, 9, 1, + IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ + { + IOCTL_PSC0_0, 15, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC1=SPDIF_TXCLK */ + { + IOCTL_LPC_CS1, 1, 0, + IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ + { + IOCTL_I2C1_SCL, 2, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=DIU CLK */ + { + IOCTL_PSC6_0, 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) + }, + /* FUNC2=DIU_HSYNC */ + { + IOCTL_PSC6_1, 1, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + }, + /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ + { + IOCTL_PSC6_4, 26, 0, + IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | + IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) + } +}; int checkboard (void) { @@ -246,7 +294,9 @@ int checkboard (void) printf ("Board: ADS5121 rev. 0x%04x (CPLD rev. 0x%02x)\n", brd_rev, cpld_rev); /* initialize function mux & slew rate IO inter alia on IO Pins */ - iopin_initialize(); + + + iopin_initialize(ioregs_init, sizeof(ioregs_init) / sizeof(ioregs_init[0])); return 0; } diff --git a/board/ads5121/iopin.c b/board/ads5121/iopin.c deleted file mode 100644 index a6792a0..0000000 --- a/board/ads5121/iopin.c +++ /dev/null @@ -1,115 +0,0 @@ -/* - * (C) Copyright 2008 - * Martha J Marx, Silicon Turnkey Express, mmarx(a)silicontkx.com - * mpc512x I/O pin/pad initialization for the ADS5121 board - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <linux/types.h> -#include "iopin.h" - -/* IO pin fields */ -#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ -#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ -#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ -#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ -#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ -#define IO_PIN_DS(v) ((v)) /* slew rate */ - -static struct iopin_t { - int p_offset; /* offset from IOCTL_MEM_OFFSET */ - int nr_pins; /* number of pins to set this way */ - int bit_or; /* or in the value instead of overwrite */ - u_long val; /* value to write or or */ -} ioregs_init[] = { - /* FUNC1=FEC_RX_DV Sets Next 3 to FEC pads */ - { - IOCTL_SPDIF_TXCLK, 3, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* Set highest Slew on 9 PATA pins */ - { - IOCTL_PATA_CE1, 9, 1, - IO_PIN_FMUX(0) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=FEC_COL Sets Next 15 to FEC pads */ - { - IOCTL_PSC0_0, 15, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC1=SPDIF_TXCLK */ - { - IOCTL_LPC_CS1, 1, 0, - IO_PIN_FMUX(1) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=SPDIF_TX and sets Next pin to SPDIF_RX */ - { - IOCTL_I2C1_SCL, 2, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU CLK */ - { - IOCTL_PSC6_0, 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(1) | IO_PIN_DS(3) - }, - /* FUNC2=DIU_HSYNC */ - { - IOCTL_PSC6_1, 1, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - }, - /* FUNC2=DIUVSYNC Sets Next 26 to DIU Pads */ - { - IOCTL_PSC6_4, 26, 0, - IO_PIN_FMUX(2) | IO_PIN_HOLD(0) | IO_PIN_PUD(0) | - IO_PIN_PUE(0) | IO_PIN_ST(0) | IO_PIN_DS(3) - } -}; - -void iopin_initialize(void) -{ - short i, j, n, p; - u_long *reg; - immap_t *im = (immap_t *)CFG_IMMR; - - reg = (u_long *)&(im->io_ctrl.regs[0]); - - if (sizeof(ioregs_init) == 0) - return; - - n = sizeof(ioregs_init) / sizeof(ioregs_init[0]); - - for (i = 0; i < n; i++) { - for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); - p < ioregs_init[i].nr_pins; p++, j++) { - if (ioregs_init[i].bit_or) - reg[j] |= ioregs_init[i].val; - else - reg[j] = ioregs_init[i].val; - } - } - return; -} diff --git a/board/ads5121/iopin.h b/board/ads5121/iopin.h deleted file mode 100644 index 7ef8472..0000000 --- a/board/ads5121/iopin.h +++ /dev/null @@ -1,222 +0,0 @@ -/* - * (C) Copyright 2008 - * Martha J Marx, Silicon Turnkey Express, mmarx(a)silicontkx.com - * mpc512x I/O pin/pad initialization for the ADS5121 board - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#define IOCTL_MEM 0x000 -#define IOCTL_GP 0x004 -#define IOCTL_LPC_CLK 0x008 -#define IOCTL_LPC_OE 0x00C -#define IOCTL_LPC_RWB 0x010 -#define IOCTL_LPC_ACK 0x014 -#define IOCTL_LPC_CS0 0x018 -#define IOCTL_NFC_CE0 0x01C -#define IOCTL_LPC_CS1 0x020 -#define IOCTL_LPC_CS2 0x024 -#define IOCTL_LPC_AX03 0x028 -#define IOCTL_EMB_AX02 0x02C -#define IOCTL_EMB_AX01 0x030 -#define IOCTL_EMB_AX00 0x034 -#define IOCTL_EMB_AD31 0x038 -#define IOCTL_EMB_AD30 0x03C -#define IOCTL_EMB_AD29 0x040 -#define IOCTL_EMB_AD28 0x044 -#define IOCTL_EMB_AD27 0x048 -#define IOCTL_EMB_AD26 0x04C -#define IOCTL_EMB_AD25 0x050 -#define IOCTL_EMB_AD24 0x054 -#define IOCTL_EMB_AD23 0x058 -#define IOCTL_EMB_AD22 0x05C -#define IOCTL_EMB_AD21 0x060 -#define IOCTL_EMB_AD20 0x064 -#define IOCTL_EMB_AD19 0x068 -#define IOCTL_EMB_AD18 0x06C -#define IOCTL_EMB_AD17 0x070 -#define IOCTL_EMB_AD16 0x074 -#define IOCTL_EMB_AD15 0x078 -#define IOCTL_EMB_AD14 0x07C -#define IOCTL_EMB_AD13 0x080 -#define IOCTL_EMB_AD12 0x084 -#define IOCTL_EMB_AD11 0x088 -#define IOCTL_EMB_AD10 0x08C -#define IOCTL_EMB_AD09 0x090 -#define IOCTL_EMB_AD08 0x094 -#define IOCTL_EMB_AD07 0x098 -#define IOCTL_EMB_AD06 0x09C -#define IOCTL_EMB_AD05 0x0A0 -#define IOCTL_EMB_AD04 0x0A4 -#define IOCTL_EMB_AD03 0x0A8 -#define IOCTL_EMB_AD02 0x0AC -#define IOCTL_EMB_AD01 0x0B0 -#define IOCTL_EMB_AD00 0x0B4 -#define IOCTL_PATA_CE1 0x0B8 -#define IOCTL_PATA_CE2 0x0BC -#define IOCTL_PATA_ISOLATE 0x0C0 -#define IOCTL_PATA_IOR 0x0C4 -#define IOCTL_PATA_IOW 0x0C8 -#define IOCTL_PATA_IOCHRDY 0x0CC -#define IOCTL_PATA_INTRQ 0x0D0 -#define IOCTL_PATA_DRQ 0x0D4 -#define IOCTL_PATA_DACK 0x0D8 -#define IOCTL_NFC_WP 0x0DC -#define IOCTL_NFC_RB 0x0E0 -#define IOCTL_NFC_ALE 0x0E4 -#define IOCTL_NFC_CLE 0x0E8 -#define IOCTL_NFC_WE 0x0EC -#define IOCTL_NFC_RE 0x0F0 -#define IOCTL_PCI_AD31 0x0F4 -#define IOCTL_PCI_AD30 0x0F8 -#define IOCTL_PCI_AD29 0x0FC -#define IOCTL_PCI_AD28 0x100 -#define IOCTL_PCI_AD27 0x104 -#define IOCTL_PCI_AD26 0x108 -#define IOCTL_PCI_AD25 0x10C -#define IOCTL_PCI_AD24 0x110 -#define IOCTL_PCI_AD23 0x114 -#define IOCTL_PCI_AD22 0x118 -#define IOCTL_PCI_AD21 0x11C -#define IOCTL_PCI_AD20 0x120 -#define IOCTL_PCI_AD19 0x124 -#define IOCTL_PCI_AD18 0x128 -#define IOCTL_PCI_AD17 0x12C -#define IOCTL_PCI_AD16 0x130 -#define IOCTL_PCI_AD15 0x134 -#define IOCTL_PCI_AD14 0x138 -#define IOCTL_PCI_AD13 0x13C -#define IOCTL_PCI_AD12 0x140 -#define IOCTL_PCI_AD11 0x144 -#define IOCTL_PCI_AD10 0x148 -#define IOCTL_PCI_AD09 0x14C -#define IOCTL_PCI_AD08 0x150 -#define IOCTL_PCI_AD07 0x154 -#define IOCTL_PCI_AD06 0x158 -#define IOCTL_PCI_AD05 0x15C -#define IOCTL_PCI_AD04 0x160 -#define IOCTL_PCI_AD03 0x164 -#define IOCTL_PCI_AD02 0x168 -#define IOCTL_PCI_AD01 0x16C -#define IOCTL_PCI_AD00 0x170 -#define IOCTL_PCI_CBE0 0x174 -#define IOCTL_PCI_CBE1 0x178 -#define IOCTL_PCI_CBE2 0x17C -#define IOCTL_PCI_CBE3 0x180 -#define IOCTL_PCI_GNT2 0x184 -#define IOCTL_PCI_REQ2 0x188 -#define IOCTL_PCI_GNT1 0x18C -#define IOCTL_PCI_REQ1 0x190 -#define IOCTL_PCI_GNT0 0x194 -#define IOCTL_PCI_REQ0 0x198 -#define IOCTL_PCI_INTA 0x19C -#define IOCTL_PCI_CLK 0x1A0 -#define IOCTL_PCI_RST_OUT 0x1A4 -#define IOCTL_PCI_FRAME 0x1A8 -#define IOCTL_PCI_IDSEL 0x1AC -#define IOCTL_PCI_DEVSEL 0x1B0 -#define IOCTL_PCI_IRDY 0x1B4 -#define IOCTL_PCI_TRDY 0x1B8 -#define IOCTL_PCI_STOP 0x1BC -#define IOCTL_PCI_PAR 0x1C0 -#define IOCTL_PCI_PERR 0x1C4 -#define IOCTL_PCI_SERR 0x1C8 -#define IOCTL_SPDIF_TXCLK 0x1CC -#define IOCTL_SPDIF_TX 0x1D0 -#define IOCTL_SPDIF_RX 0x1D4 -#define IOCTL_I2C0_SCL 0x1D8 -#define IOCTL_I2C0_SDA 0x1DC -#define IOCTL_I2C1_SCL 0x1E0 -#define IOCTL_I2C1_SDA 0x1E4 -#define IOCTL_I2C2_SCL 0x1E8 -#define IOCTL_I2C2_SDA 0x1EC -#define IOCTL_IRQ0 0x1F0 -#define IOCTL_IRQ1 0x1F4 -#define IOCTL_CAN1_TX 0x1F8 -#define IOCTL_CAN2_TX 0x1FC -#define IOCTL_J1850_TX 0x200 -#define IOCTL_J1850_RX 0x204 -#define IOCTL_PSC_MCLK_IN 0x208 -#define IOCTL_PSC0_0 0x20C -#define IOCTL_PSC0_1 0x210 -#define IOCTL_PSC0_2 0x214 -#define IOCTL_PSC0_3 0x218 -#define IOCTL_PSC0_4 0x21C -#define IOCTL_PSC1_0 0x220 -#define IOCTL_PSC1_1 0x224 -#define IOCTL_PSC1_2 0x228 -#define IOCTL_PSC1_3 0x22C -#define IOCTL_PSC1_4 0x230 -#define IOCTL_PSC2_0 0x234 -#define IOCTL_PSC2_1 0x238 -#define IOCTL_PSC2_2 0x23C -#define IOCTL_PSC2_3 0x240 -#define IOCTL_PSC2_4 0x244 -#define IOCTL_PSC3_0 0x248 -#define IOCTL_PSC3_1 0x24C -#define IOCTL_PSC3_2 0x250 -#define IOCTL_PSC3_3 0x254 -#define IOCTL_PSC3_4 0x258 -#define IOCTL_PSC4_0 0x25C -#define IOCTL_PSC4_1 0x260 -#define IOCTL_PSC4_2 0x264 -#define IOCTL_PSC4_3 0x268 -#define IOCTL_PSC4_4 0x26C -#define IOCTL_PSC5_0 0x270 -#define IOCTL_PSC5_1 0x274 -#define IOCTL_PSC5_2 0x278 -#define IOCTL_PSC5_3 0x27C -#define IOCTL_PSC5_4 0x280 -#define IOCTL_PSC6_0 0x284 -#define IOCTL_PSC6_1 0x288 -#define IOCTL_PSC6_2 0x28C -#define IOCTL_PSC6_3 0x290 -#define IOCTL_PSC6_4 0x294 -#define IOCTL_PSC7_0 0x298 -#define IOCTL_PSC7_1 0x29C -#define IOCTL_PSC7_2 0x2A0 -#define IOCTL_PSC7_3 0x2A4 -#define IOCTL_PSC7_4 0x2A8 -#define IOCTL_PSC8_0 0x2AC -#define IOCTL_PSC8_1 0x2B0 -#define IOCTL_PSC8_2 0x2B4 -#define IOCTL_PSC8_3 0x2B8 -#define IOCTL_PSC8_4 0x2BC -#define IOCTL_PSC9_0 0x2C0 -#define IOCTL_PSC9_1 0x2C4 -#define IOCTL_PSC9_2 0x2C8 -#define IOCTL_PSC9_3 0x2CC -#define IOCTL_PSC9_4 0x2D0 -#define IOCTL_PSC10_0 0x2D4 -#define IOCTL_PSC10_1 0x2D8 -#define IOCTL_PSC10_2 0x2DC -#define IOCTL_PSC10_3 0x2E0 -#define IOCTL_PSC10_4 0x2E4 -#define IOCTL_PSC11_0 0x2E8 -#define IOCTL_PSC11_1 0x2EC -#define IOCTL_PSC11_2 0x2F0 -#define IOCTL_PSC11_3 0x2F4 -#define IOCTL_PSC11_4 0x2F8 -#define IOCTL_HRESET 0x2FC -#define IOCTL_SRESET 0x300 -#define IOCTL_CKSTP_OUT 0x304 -#define IOCTL_USB2_VBUS_PWR_FAULT 0x308 -#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C -#define IOCTL_USB2_PHY_DRVV_BUS 0x310 - -extern void iopin_initialize(void); diff --git a/cpu/mpc512x/Makefile b/cpu/mpc512x/Makefile index 2be35b2..8ba8ae8 100644 --- a/cpu/mpc512x/Makefile +++ b/cpu/mpc512x/Makefile @@ -25,7 +25,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o -COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o +COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o serial.o fec.o i2c.o iopin.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) diff --git a/cpu/mpc512x/iopin.c b/cpu/mpc512x/iopin.c new file mode 100644 index 0000000..01ab34a --- /dev/null +++ b/cpu/mpc512x/iopin.c @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2008 + * Martha J Marx, Silicon Turnkey Express, mmarx(a)silicontkx.com + * mpc512x I/O pin/pad initialization for the ADS5121 board + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <linux/types.h> +#include <mpc512x.h> + +void iopin_initialize(iopin_t *ioregs_init, int len) +{ + short i, j, n, p; + u_long *reg; + immap_t *im = (immap_t *)CFG_IMMR; + + reg = (u_long *)&(im->io_ctrl.regs[0]); + + if (sizeof(ioregs_init) == 0) + return; + + for (i = 0; i < len; i++) { + for (p = 0, j = ioregs_init[i].p_offset / sizeof(u_long); + p < ioregs_init[i].nr_pins; p++, j++) { + if (ioregs_init[i].bit_or) + reg[j] |= ioregs_init[i].val; + else + reg[j] = ioregs_init[i].val; + } + } + return; +} diff --git a/include/mpc512x.h b/include/mpc512x.h index b4cc2b9..a76b1ca 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -347,41 +347,226 @@ /* IO Control Register */ +#define IOCTL_MEM 0x000 +#define IOCTL_GP 0x004 +#define IOCTL_LPC_CLK 0x008 +#define IOCTL_LPC_OE 0x00C +#define IOCTL_LPC_RWB 0x010 +#define IOCTL_LPC_ACK 0x014 +#define IOCTL_LPC_CS0 0x018 +#define IOCTL_NFC_CE0 0x01C +#define IOCTL_LPC_CS1 0x020 +#define IOCTL_LPC_CS2 0x024 +#define IOCTL_LPC_AX03 0x028 +#define IOCTL_EMB_AX02 0x02C +#define IOCTL_EMB_AX01 0x030 +#define IOCTL_EMB_AX00 0x034 +#define IOCTL_EMB_AD31 0x038 +#define IOCTL_EMB_AD30 0x03C +#define IOCTL_EMB_AD29 0x040 +#define IOCTL_EMB_AD28 0x044 +#define IOCTL_EMB_AD27 0x048 +#define IOCTL_EMB_AD26 0x04C +#define IOCTL_EMB_AD25 0x050 +#define IOCTL_EMB_AD24 0x054 +#define IOCTL_EMB_AD23 0x058 +#define IOCTL_EMB_AD22 0x05C +#define IOCTL_EMB_AD21 0x060 +#define IOCTL_EMB_AD20 0x064 +#define IOCTL_EMB_AD19 0x068 +#define IOCTL_EMB_AD18 0x06C +#define IOCTL_EMB_AD17 0x070 +#define IOCTL_EMB_AD16 0x074 +#define IOCTL_EMB_AD15 0x078 +#define IOCTL_EMB_AD14 0x07C +#define IOCTL_EMB_AD13 0x080 +#define IOCTL_EMB_AD12 0x084 +#define IOCTL_EMB_AD11 0x088 +#define IOCTL_EMB_AD10 0x08C +#define IOCTL_EMB_AD09 0x090 +#define IOCTL_EMB_AD08 0x094 +#define IOCTL_EMB_AD07 0x098 +#define IOCTL_EMB_AD06 0x09C +#define IOCTL_EMB_AD05 0x0A0 +#define IOCTL_EMB_AD04 0x0A4 +#define IOCTL_EMB_AD03 0x0A8 +#define IOCTL_EMB_AD02 0x0AC +#define IOCTL_EMB_AD01 0x0B0 +#define IOCTL_EMB_AD00 0x0B4 +#define IOCTL_PATA_CE1 0x0B8 +#define IOCTL_PATA_CE2 0x0BC +#define IOCTL_PATA_ISOLATE 0x0C0 +#define IOCTL_PATA_IOR 0x0C4 +#define IOCTL_PATA_IOW 0x0C8 +#define IOCTL_PATA_IOCHRDY 0x0CC +#define IOCTL_PATA_INTRQ 0x0D0 +#define IOCTL_PATA_DRQ 0x0D4 +#define IOCTL_PATA_DACK 0x0D8 +#define IOCTL_NFC_WP 0x0DC +#define IOCTL_NFC_RB 0x0E0 +#define IOCTL_NFC_ALE 0x0E4 +#define IOCTL_NFC_CLE 0x0E8 +#define IOCTL_NFC_WE 0x0EC +#define IOCTL_NFC_RE 0x0F0 +#define IOCTL_PCI_AD31 0x0F4 +#define IOCTL_PCI_AD30 0x0F8 +#define IOCTL_PCI_AD29 0x0FC +#define IOCTL_PCI_AD28 0x100 +#define IOCTL_PCI_AD27 0x104 +#define IOCTL_PCI_AD26 0x108 +#define IOCTL_PCI_AD25 0x10C +#define IOCTL_PCI_AD24 0x110 +#define IOCTL_PCI_AD23 0x114 +#define IOCTL_PCI_AD22 0x118 +#define IOCTL_PCI_AD21 0x11C +#define IOCTL_PCI_AD20 0x120 +#define IOCTL_PCI_AD19 0x124 +#define IOCTL_PCI_AD18 0x128 +#define IOCTL_PCI_AD17 0x12C +#define IOCTL_PCI_AD16 0x130 +#define IOCTL_PCI_AD15 0x134 +#define IOCTL_PCI_AD14 0x138 +#define IOCTL_PCI_AD13 0x13C +#define IOCTL_PCI_AD12 0x140 +#define IOCTL_PCI_AD11 0x144 +#define IOCTL_PCI_AD10 0x148 +#define IOCTL_PCI_AD09 0x14C +#define IOCTL_PCI_AD08 0x150 +#define IOCTL_PCI_AD07 0x154 +#define IOCTL_PCI_AD06 0x158 +#define IOCTL_PCI_AD05 0x15C +#define IOCTL_PCI_AD04 0x160 +#define IOCTL_PCI_AD03 0x164 +#define IOCTL_PCI_AD02 0x168 +#define IOCTL_PCI_AD01 0x16C +#define IOCTL_PCI_AD00 0x170 +#define IOCTL_PCI_CBE0 0x174 +#define IOCTL_PCI_CBE1 0x178 +#define IOCTL_PCI_CBE2 0x17C +#define IOCTL_PCI_CBE3 0x180 +#define IOCTL_PCI_GNT2 0x184 +#define IOCTL_PCI_REQ2 0x188 +#define IOCTL_PCI_GNT1 0x18C +#define IOCTL_PCI_REQ1 0x190 +#define IOCTL_PCI_GNT0 0x194 +#define IOCTL_PCI_REQ0 0x198 +#define IOCTL_PCI_INTA 0x19C +#define IOCTL_PCI_CLK 0x1A0 +#define IOCTL_PCI_RST_OUT 0x1A4 +#define IOCTL_PCI_FRAME 0x1A8 +#define IOCTL_PCI_IDSEL 0x1AC +#define IOCTL_PCI_DEVSEL 0x1B0 +#define IOCTL_PCI_IRDY 0x1B4 +#define IOCTL_PCI_TRDY 0x1B8 +#define IOCTL_PCI_STOP 0x1BC +#define IOCTL_PCI_PAR 0x1C0 +#define IOCTL_PCI_PERR 0x1C4 +#define IOCTL_PCI_SERR 0x1C8 +#define IOCTL_SPDIF_TXCLK 0x1CC +#define IOCTL_SPDIF_TX 0x1D0 +#define IOCTL_SPDIF_RX 0x1D4 +#define IOCTL_I2C0_SCL 0x1D8 +#define IOCTL_I2C0_SDA 0x1DC +#define IOCTL_I2C1_SCL 0x1E0 +#define IOCTL_I2C1_SDA 0x1E4 +#define IOCTL_I2C2_SCL 0x1E8 +#define IOCTL_I2C2_SDA 0x1EC +#define IOCTL_IRQ0 0x1F0 +#define IOCTL_IRQ1 0x1F4 +#define IOCTL_CAN1_TX 0x1F8 +#define IOCTL_CAN2_TX 0x1FC +#define IOCTL_J1850_TX 0x200 +#define IOCTL_J1850_RX 0x204 +#define IOCTL_PSC_MCLK_IN 0x208 +#define IOCTL_PSC0_0 0x20C +#define IOCTL_PSC0_1 0x210 +#define IOCTL_PSC0_2 0x214 +#define IOCTL_PSC0_3 0x218 +#define IOCTL_PSC0_4 0x21C +#define IOCTL_PSC1_0 0x220 +#define IOCTL_PSC1_1 0x224 +#define IOCTL_PSC1_2 0x228 +#define IOCTL_PSC1_3 0x22C +#define IOCTL_PSC1_4 0x230 +#define IOCTL_PSC2_0 0x234 +#define IOCTL_PSC2_1 0x238 +#define IOCTL_PSC2_2 0x23C +#define IOCTL_PSC2_3 0x240 +#define IOCTL_PSC2_4 0x244 +#define IOCTL_PSC3_0 0x248 +#define IOCTL_PSC3_1 0x24C +#define IOCTL_PSC3_2 0x250 +#define IOCTL_PSC3_3 0x254 +#define IOCTL_PSC3_4 0x258 +#define IOCTL_PSC4_0 0x25C +#define IOCTL_PSC4_1 0x260 +#define IOCTL_PSC4_2 0x264 +#define IOCTL_PSC4_3 0x268 +#define IOCTL_PSC4_4 0x26C +#define IOCTL_PSC5_0 0x270 +#define IOCTL_PSC5_1 0x274 +#define IOCTL_PSC5_2 0x278 +#define IOCTL_PSC5_3 0x27C +#define IOCTL_PSC5_4 0x280 +#define IOCTL_PSC6_0 0x284 +#define IOCTL_PSC6_1 0x288 +#define IOCTL_PSC6_2 0x28C +#define IOCTL_PSC6_3 0x290 +#define IOCTL_PSC6_4 0x294 +#define IOCTL_PSC7_0 0x298 +#define IOCTL_PSC7_1 0x29C +#define IOCTL_PSC7_2 0x2A0 +#define IOCTL_PSC7_3 0x2A4 +#define IOCTL_PSC7_4 0x2A8 +#define IOCTL_PSC8_0 0x2AC +#define IOCTL_PSC8_1 0x2B0 +#define IOCTL_PSC8_2 0x2B4 +#define IOCTL_PSC8_3 0x2B8 +#define IOCTL_PSC8_4 0x2BC +#define IOCTL_PSC9_0 0x2C0 +#define IOCTL_PSC9_1 0x2C4 +#define IOCTL_PSC9_2 0x2C8 +#define IOCTL_PSC9_3 0x2CC +#define IOCTL_PSC9_4 0x2D0 +#define IOCTL_PSC10_0 0x2D4 +#define IOCTL_PSC10_1 0x2D8 +#define IOCTL_PSC10_2 0x2DC +#define IOCTL_PSC10_3 0x2E0 +#define IOCTL_PSC10_4 0x2E4 +#define IOCTL_PSC11_0 0x2E8 +#define IOCTL_PSC11_1 0x2EC +#define IOCTL_PSC11_2 0x2F0 +#define IOCTL_PSC11_3 0x2F4 +#define IOCTL_PSC11_4 0x2F8 +#define IOCTL_HRESET 0x2FC +#define IOCTL_SRESET 0x300 +#define IOCTL_CKSTP_OUT 0x304 +#define IOCTL_USB2_VBUS_PWR_FAULT 0x308 +#define IOCTL_USB2_VBUS_PWR_SELECT 0x30C +#define IOCTL_USB2_PHY_DRVV_BUS 0x310 + +#ifndef __ASSEMBLY__ + + +/* IO pin fields */ +#define IO_PIN_FMUX(v) ((v) << 7) /* pin function */ +#define IO_PIN_HOLD(v) ((v) << 5) /* hold time, pci only */ +#define IO_PIN_PUD(v) ((v) << 4) /* if PUE, 0=pull-down, 1=pull-up */ +#define IO_PIN_PUE(v) ((v) << 3) /* pull up/down enable */ +#define IO_PIN_ST(v) ((v) << 2) /* schmitt trigger */ +#define IO_PIN_DS(v) ((v)) /* slew rate */ + +typedef struct iopin_t { + int p_offset; /* offset from IOCTL_MEM_OFFSET */ + int nr_pins; /* number of pins to set this way */ + int bit_or; /* or in the value instead of overwrite */ + u_long val; /* value to write or or */ +}iopin_t; + +void iopin_initialize(iopin_t *,int); +#endif /* Indexes in regs array */ -#define MEM_IDX 0x00 -#define PATA_CE1_IDX 0x2e -#define PATA_CE2_IDX 0x2f -#define PATA_ISOLATE_IDX 0x30 -#define PATA_IOR_IDX 0x31 -#define PATA_IOW_IDX 0x32 -#define PATA_IOCHRDY_IDX 0x33 -#define PATA_INTRQ_IDX 0x34 -#define PATA_DRQ_IDX 0x35 -#define PATA_DACK_IDX 0x36 -#define SPDIF_TXCLOCK_IDX 0x73 -#define SPDIF_TX_IDX 0x74 -#define SPDIF_RX_IDX 0x75 -#define PSC0_0_IDX 0x83 -#define PSC0_1_IDX 0x84 -#define PSC0_2_IDX 0x85 -#define PSC0_3_IDX 0x86 -#define PSC0_4_IDX 0x87 -#define PSC1_0_IDX 0x88 -#define PSC1_1_IDX 0x89 -#define PSC1_2_IDX 0x8a -#define PSC1_3_IDX 0x8b -#define PSC1_4_IDX 0x8c -#define PSC2_0_IDX 0x8d -#define PSC2_1_IDX 0x8e -#define PSC2_2_IDX 0x8f -#define PSC2_3_IDX 0x90 -#define PSC2_4_IDX 0x91 - -#define IOCTRL_FUNCMUX_SHIFT 7 -#define IOCTRL_FUNCMUX_FEC 1 -#define IOCTRL_MUX_FEC (IOCTRL_FUNCMUX_FEC << IOCTRL_FUNCMUX_SHIFT) - /* Set for DDR */ #define IOCTRL_MUX_DDR 0x00000036 -- 1.5.6.GIT

3 2

[U-Boot-Users] using a flat device tree to drive u-boot config
by Kumar Gala 04 Aug '08

04 Aug '08

One topic that come up during OLS in discussions and u-boot BOF was the idea of driving u-boot configuration from a device tree instead of from "config.h". I was wondering if anyone has actually looked at doing this. One question I have is how does (or should) u-boot identify where to find the device tree. I think the idea would be that this "area" could be easily reflashed with a new blob to get a new configuration. - k

16 37

[U-Boot-Users] Question about Bad CRC
by Rugunda, Solo 04 Aug '08

04 Aug '08

Hi I know that with UBoot, to fix the Bad CRC, all you have to do is to type saveenv during the boot process. However, what if someone does not have access to a terminal to be able to type in the saveenv command? Basically, I want to know of a way that a Bad CRC can be fixed without a user having to interact with the boot up process. Thank you. Solo

4 10