May 2008 - U-Boot

[U-Boot-Users] [PATCH] Add PPC405 External Bus Controller (EBC) Register Field Mnemonics
by Grant Erickson 12 Jun '08

12 Jun '08

Added preprocessor definitions for External Bus Controller (EBC) configuration, bank configuration and access parameter register fields along with a macro for defining them and verifying them against the data sheet or user's manual easier. Tested against AMCC "Haleakala". Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- include/ppc405.h | 98 ++++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 98 insertions(+), 0 deletions(-) diff --git a/include/ppc405.h b/include/ppc405.h index 37b121c..009aa68 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -22,6 +22,9 @@ #ifndef __PPC405_H__ #define __PPC405_H__ +#define PPC_REG_BITS 32 +#define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) + #ifndef CONFIG_IOP480 #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ #else @@ -363,6 +366,101 @@ #endif /* defined(CONFIG_405EZ) */ /****************************************************************************** + * External Bus Controller (EBC) + *****************************************************************************/ + +/* Bank Configuration Register */ +#define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) +#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&EBC_BXCR_BAS_MASK)<<0) +#define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) +#define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) +#define EBC_BXCR_BS_4MB PPC_REG_VAL(14, 0x2) +#define EBC_BXCR_BS_8MB PPC_REG_VAL(14, 0x3) +#define EBC_BXCR_BS_16MB PPC_REG_VAL(14, 0x4) +#define EBC_BXCR_BS_32MB PPC_REG_VAL(14, 0x5) +#define EBC_BXCR_BS_64MB PPC_REG_VAL(14, 0x6) +#define EBC_BXCR_BS_128MB PPC_REG_VAL(14, 0x7) +#define EBC_BXCR_BU_MASK PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BU_NONE PPC_REG_VAL(16, 0x0) +#define EBC_BXCR_BU_R PPC_REG_VAL(16, 0x1) +#define EBC_BXCR_BU_W PPC_REG_VAL(16, 0x2) +#define EBC_BXCR_BU_RW PPC_REG_VAL(16, 0x3) +#define EBC_BXCR_BW_MASK PPC_REG_VAL(18, 0x3) +#define EBC_BXCR_BW_8BIT PPC_REG_VAL(18, 0x0) +#define EBC_BXCR_BW_16BIT PPC_REG_VAL(18, 0x1) +#define EBC_BXCR_BW_32BIT PPC_REG_VAL(18, 0x3) + +/* Bank Access Parameter Register */ +#define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) +#define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, ((unsigned long)(n)) & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, ((unsigned long)(n)) & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, ((unsigned long)(n)) & 0x7) +#define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) +#define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) +#define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_BCT_2TRANS PPC_REG_VAL(11, 0x0) +#define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) +#define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) +#define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, ((unsigned long)(n)) & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, ((unsigned long)(n)) & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, ((unsigned long)(n)) & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, ((unsigned long)(n)) & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, ((unsigned long)(n)) & 0x7) +#define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) +#define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) +#define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) +#define EBC_BXAP_SOR_NONDELAYED PPC_REG_VAL(24, 0x1) +#define EBC_BXAP_BEM_WRITEONLY PPC_REG_VAL(25, 0x0) +#define EBC_BXAP_BEM_RW PPC_REG_VAL(25, 0x1) +#define EBC_BXAP_PEN_DISABLED PPC_REG_VAL(26, 0x0) +#define EBC_BXAP_PEN_ENABLED PPC_REG_VAL(26, 0x1) + +/* Configuration Register */ +#define EBC_CFG_LE_MASK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_LE_UNLOCK PPC_REG_VAL(0, 0x0) +#define EBC_CFG_LE_LOCK PPC_REG_VAL(0, 0x1) +#define EBC_CFG_PTD_MASK PPC_REG_VAL(1, 0x1) +#define EBC_CFG_PTD_ENABLE PPC_REG_VAL(1, 0x0) +#define EBC_CFG_PTD_DISABLE PPC_REG_VAL(1, 0x1) +#define EBC_CFG_RTC_MASK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_RTC_16PERCLK PPC_REG_VAL(4, 0x0) +#define EBC_CFG_RTC_32PERCLK PPC_REG_VAL(4, 0x1) +#define EBC_CFG_RTC_64PERCLK PPC_REG_VAL(4, 0x2) +#define EBC_CFG_RTC_128PERCLK PPC_REG_VAL(4, 0x3) +#define EBC_CFG_RTC_256PERCLK PPC_REG_VAL(4, 0x4) +#define EBC_CFG_RTC_512PERCLK PPC_REG_VAL(4, 0x5) +#define EBC_CFG_RTC_1024PERCLK PPC_REG_VAL(4, 0x6) +#define EBC_CFG_RTC_2048PERCLK PPC_REG_VAL(4, 0x7) +#define EBC_CFG_ATC_MASK PPC_REG_VAL(5, 0x1) +#define EBC_CFG_ATC_HI PPC_REG_VAL(5, 0x0) +#define EBC_CFG_ATC_PREVIOUS PPC_REG_VAL(5, 0x1) +#define EBC_CFG_DTC_MASK PPC_REG_VAL(6, 0x1) +#define EBC_CFG_DTC_HI PPC_REG_VAL(6, 0x0) +#define EBC_CFG_DTC_PREVIOUS PPC_REG_VAL(6, 0x1) +#define EBC_CFG_CTC_MASK PPC_REG_VAL(7, 0x1) +#define EBC_CFG_CTC_HI PPC_REG_VAL(7, 0x0) +#define EBC_CFG_CTC_PREVIOUS PPC_REG_VAL(7, 0x1) +#define EBC_CFG_OEO_MASK PPC_REG_VAL(8, 0x1) +#define EBC_CFG_OEO_DISABLE PPC_REG_VAL(8, 0x0) +#define EBC_CFG_OEO_ENABLE PPC_REG_VAL(8, 0x1) +#define EBC_CFG_EMC_MASK PPC_REG_VAL(9, 0x1) +#define EBC_CFG_EMC_NONDEFAULT PPC_REG_VAL(9, 0x0) +#define EBC_CFG_EMC_DEFAULT PPC_REG_VAL(9, 0x1) +#define EBC_CFG_PME_MASK PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) +#define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) +#define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, ((unsigned long)(n)) & 0x1F) +#define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) +#define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) +#define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) +#define EBC_CFG_PR_64 PPC_REG_VAL(21, 0x2) +#define EBC_CFG_PR_128 PPC_REG_VAL(21, 0x3) + +/****************************************************************************** * SDRAM Controller ******************************************************************************/ /* values for memcfga register - indirect addressing of these regs */ -- 1.5.4.3

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[U-Boot-Users] [PATCH] mips: tolerate the MIPS 'CFG_HZ' values in the MHZ range for NAND delays
by Jason McMullan 12 Jun '08

12 Jun '08

Rewrite the nand_wait() FL_ERASING case to handle CFG_HZ values in the MHZ range. This is needed for mips processors, as the timer's timebase ticks at CPU clock frequency. Signed-off-by: Jason McMullan <mcmullan(a)netapp.com> --- drivers/mtd/nand/nand_base.c | 7 +++++++ 1 files changed, 7 insertions(+), 0 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 2da1d46..ac690ac 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -837,10 +837,17 @@ static int nand_wait(struct mtd_info *mtd, struct nand_chip *this, int state) { unsigned long timeo; +#if CFG_HZ > 100000 + if (state == FL_ERASING) + timeo = (CFG_HZ / 1000) * 400; + else + timeo = (CFG_HZ / 1000) * 20; +#else if (state == FL_ERASING) timeo = (CFG_HZ * 400) / 1000; else timeo = (CFG_HZ * 20) / 1000; +#endif if ((state == FL_ERASING) && (this->options & NAND_IS_AND)) this->cmdfunc(mtd, NAND_CMD_STATUS_MULTI, -1, -1); -- 1.5.4.3

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[U-Boot-Users] [PATCH] 85xx: Add setting of cache props in the device tree.
by Kumar Gala 11 Jun '08

11 Jun '08

Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- cpu/mpc85xx/fdt.c | 128 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 128 insertions(+), 0 deletions(-) diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index bb87740..92952e6 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -26,6 +26,7 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include <asm/processor.h> extern void ft_qe_setup(void *blob); #ifdef CONFIG_MP @@ -77,6 +78,131 @@ void ft_fixup_cpu(void *blob, u64 memory_limit) } #endif +#ifdef CONFIG_L2_CACHE +/* return size in kilobytes */ +static inline u32 l2cache_size(void) +{ + volatile ccsr_l2cache_t *l2cache = (void *)CFG_MPC85xx_L2_ADDR; + volatile u32 l2siz_field = (l2cache->l2ctl >> 28) & 0x3; + u32 ver = SVR_SOC_VER(get_svr()); + + switch (l2siz_field) { + case 0x0: + break; + case 0x1: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 128; + else + return 256; + break; + case 0x2: + if (ver == SVR_8540 || ver == SVR_8560 || + ver == SVR_8541 || ver == SVR_8541_E || + ver == SVR_8555 || ver == SVR_8555_E) + return 256; + else + return 512; + break; + case 0x3: + return 1024; + break; + } + + return 0; +} + +static inline void ft_fixup_l2cache(void *blob) +{ + int len, off; + u32 *ph; + struct cpu_type *cpu = identify_cpu(SVR_SOC_VER(get_svr())); + char compat_buf[38]; + + const u32 line_size = 32; + const u32 num_ways = 8; + const u32 size = l2cache_size() * 1024; + const u32 num_sets = size / (line_size * num_ways); + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + if (off < 0) { + debug("no cpu node fount\n"); + return; + } + + ph = (u32 *)fdt_getprop(blob, off, "next-level-cache", 0); + + if (ph == NULL) { + debug("no next-level-cache property\n"); + return ; + } + + off = fdt_node_offset_by_phandle(blob, *ph); + if (off < 0) { + printf("%s: %s\n", __func__, fdt_strerror(off)); + return ; + } + + if (cpu) { + len = sprintf(compat_buf, "fsl,mpc%s-l2-cache-controller", + cpu->name); + sprintf(&compat_buf[len + 1], "cache"); + } + fdt_setprop(blob, off, "cache-unified", NULL, 0); + fdt_setprop_cell(blob, off, "cache-block-size", line_size); + fdt_setprop_cell(blob, off, "cache-line-size", line_size); + fdt_setprop_cell(blob, off, "cache-size", size); + fdt_setprop_cell(blob, off, "cache-sets", num_sets); + fdt_setprop_cell(blob, off, "cache-level", 2); + fdt_setprop(blob, off, "compatible", compat_buf, sizeof(compat_buf)); +} +#else +#define ft_fixup_l2cache(x) +#endif + +static inline void ft_fixup_cache(void *blob) +{ + int off; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + + while (off != -FDT_ERR_NOTFOUND) { + u32 l1cfg0 = mfspr(SPRN_L1CFG0); + u32 l1cfg1 = mfspr(SPRN_L1CFG1); + u32 isize, iline_size, inum_sets, inum_ways; + u32 dsize, dline_size, dnum_sets, dnum_ways; + + /* d-side config */ + dsize = (l1cfg0 & 0x7ff) * 1024; + dnum_ways = ((l1cfg0 >> 11) & 0xff) + 1; + dline_size = (((l1cfg0 >> 23) & 0x3) + 1) * 32; + dnum_sets = dsize / (dline_size * dnum_ways); + + fdt_setprop_cell(blob, off, "d-cache-block-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-line-size", dline_size); + fdt_setprop_cell(blob, off, "d-cache-size", dsize); + fdt_setprop_cell(blob, off, "d-cache-sets", dnum_sets); + + /* i-side config */ + isize = (l1cfg1 & 0x7ff) * 1024; + inum_ways = ((l1cfg1 >> 11) & 0xff) + 1; + iline_size = (((l1cfg1 >> 23) & 0x3) + 1) * 32; + inum_sets = isize / (iline_size * inum_ways); + + fdt_setprop_cell(blob, off, "i-cache-block-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-line-size", iline_size); + fdt_setprop_cell(blob, off, "i-cache-size", isize); + fdt_setprop_cell(blob, off, "i-cache-sets", inum_sets); + + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + ft_fixup_l2cache(blob); +} + + void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ @@ -114,4 +240,6 @@ void ft_cpu_setup(void *blob, bd_t *bd) #ifdef CONFIG_MP ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); #endif + + ft_fixup_cache(blob); } -- 1.5.4.5

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[U-Boot-Users] Pull Request for mpc86xx repository
by Jon Loeliger 11 Jun '08

11 Jun '08

The following changes since commit 180a90abdae72587c0f679edf8991455e559440d: Wolfgang Denk (1): Release v1.3.3 are available in the git repository at: git://www.denx.de/git/u-boot-mpc86xx.git master Jon Loeliger (1): mpc86xx: Removed unused and unconfigured memory test code. board/freescale/mpc8610hpcd/mpc8610hpcd.c | 36 ----------------------------- board/freescale/mpc8641hpcn/mpc8641hpcn.c | 36 ----------------------------- include/configs/MPC8610HPCD.h | 2 - include/configs/MPC8641HPCN.h | 1 - 4 files changed, 0 insertions(+), 75 deletions(-)

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[U-Boot-Users] Command history no longer working
by Hugo Villeneuve 10 Jun '08

10 Jun '08

Hi, I have observed that after this commit, the command history is no longer working: --- commit 597f6c26a18b389903a64692bacbf9a1ca69355b Author: James Yang <James.Yang(a)freescale.com> Date: Mon May 5 10:22:53 2008 -0500 Fix readline_into_buffer() with CONFIG_CMDLINE_EDITING before relocating When CONFIG_CMDLINE_EDITING is enabled, readline_into_buffer() doesn't work before relocating to RAM because command history is written into a global array that is not writable before relocation. This patch defers to the no-editing and no-history code in readline_into_buffer() if it is called before relocation. --- Based on the comments, I dont understand why it ceases to work because, in my case, U-Boot runs entirely from RAM (it is copied from flash to RAM by a first stage bootloader). I have CONFIG_CMDLINE_EDITING defined. Hugo V. Hugo Villeneuve Hardware developer | Concepteur matériel Lyrtech Phone/Tél. : (1) (418) 877-4644 #2395 Toll-free/Sans frais — Canada & USA : (1) (888) 922-4644 #2395 Fax/Téléc. : (1) (418) 877-7710 www.lyrtech.com Infinite possibilities…TM

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[U-Boot-Users] [PATCH 1/8] New board SIMPC8313 support: MAINTAINERS, MAKEALL, Makefile
by Ron Madrid 10 Jun '08

10 Jun '08

New board SIMPC8313 support: MAINTAINERS, MAKEALL, Makefile Signed-off-by: Ron Madrid --- MAINTAINERS | 5 +++++ MAKEALL | 2 ++ Makefile | 18 ++++++++++++++++++ 3 files changed, 25 insertions(+), 0 deletions(-) diff --git a/MAINTAINERS b/MAINTAINERS index ac7572c..021fc4b 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -255,6 +255,11 @@ Jon Loeliger <jdl(a)freescale.com> MPC8555CDS MPC8555 MPC8641HPCN MPC8641D + +Ron Madrid <ron_madrid(a)sbcglobal.net> + + SIMPC8313 MPC8313 + Dan Malek <dan(a)embeddedalley.com> diff --git a/MAKEALL b/MAKEALL index 0674069..493a489 100755 --- a/MAKEALL +++ b/MAKEALL @@ -331,6 +331,8 @@ LIST_83xx=" \ MPC837XEMDS \ MPC837XERDB \ sbc8349 \ + SIMPC8313_LP \ + SIMPC8313_SP \ TQM834x \ " diff --git a/Makefile b/Makefile index 3401203..03e514f 100644 --- a/Makefile +++ b/Makefile @@ -2101,6 +2101,24 @@ MPC837XEMDS_HOST_config: unconfig MPC837XERDB_config: unconfig @$(MKCONFIG) -a MPC837XERDB ppc mpc83xx mpc837xerdb freescale + +SIMPC8313_LP_config \ +SIMPC8313_SP_config: unconfig + @mkdir -p $(obj)include + @mkdir -p $(obj)nand_spl/board/sheldon/simpc8313 + @if [ "$(findstring _LP_,$@)" ] ; then \ + echo -n "... Large Page NAND " ; \ + echo "#define CONFIG_NAND_LP" >> $(obj)include/config.h ; \ + $(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon; \ + echo "PAD_TO = 0xFFF20000" >> $(obj)board/sheldon/simpc8313/config.tmp ; \ + fi ; + @if [ "$(findstring _SP_,$@)" ] ; then \ + echo -n "... Small Page NAND " ; \ + echo "#define CONFIG_NAND_SP" >> $(obj)include/config.h ; \ + $(MKCONFIG) -a SIMPC8313 ppc mpc83xx simpc8313 sheldon; \ + echo "PAD_TO = 0xFFF04000" >> $(obj)board/sheldon/simpc8313/config.tmp ; \ + fi ; + @echo "CONFIG_NAND_U_BOOT = y" >> $(obj)include/config.mk sbc8349_config: unconfig @$(MKCONFIG) $(@:_config=) ppc mpc83xx sbc8349 -- 1.5.5.1

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[U-Boot-Users] [PATCH] 86xx: mpc8610_hpcd: add support for NAND
by Anton Vorontsov 09 Jun '08

09 Jun '08

This patch adds support for NAND on MPC8610HPCD target. We're using BAT7 and LAW4 entries for 4MB NAND mapping. MPC8610HPCD has four NAND chips in one package, bases as follows: - 0xe8400000 - 0xe8440000 - 0xe8480000 - 0xe84c0000 Also, this patch adds some localbus definitions to mpc86xx.h (straight copy from mpc83xx.h). Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> --- board/freescale/mpc8610hpcd/law.c | 2 +- include/configs/MPC8610HPCD.h | 37 +++++++-- include/mpc86xx.h | 164 +++++++++++++++++++++++++++++++++++++ 3 files changed, 196 insertions(+), 7 deletions(-) diff --git a/board/freescale/mpc8610hpcd/law.c b/board/freescale/mpc8610hpcd/law.c index b4d222d..072a997 100644 --- a/board/freescale/mpc8610hpcd/law.c +++ b/board/freescale/mpc8610hpcd/law.c @@ -33,7 +33,7 @@ struct law_entry law_table[] = { #endif SET_LAW_ENTRY(2, CFG_PCIE1_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(3, CFG_PCIE2_MEM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_PCIE_2), - SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_2M, LAW_TRGT_IF_LBC), + SET_LAW_ENTRY(4, PIXIS_BASE, LAW_SIZE_8M, LAW_TRGT_IF_LBC), /* + NAND */ SET_LAW_ENTRY(5, CFG_PCIE1_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_1), SET_LAW_ENTRY(6, CFG_PCIE2_IO_PHYS, LAW_SIZE_1M, LAW_TRGT_IF_PCIE_2), SET_LAW_ENTRY(7, CFG_FLASH_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 15ff0ea..3299942 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -158,10 +158,34 @@ #define CFG_BR1_PRELIM 0xf0001001 /* port size 16bit */ #define CFG_OR1_PRELIM 0xf8006e65 /* 128MB Promjet */ -#if 0 /* TODO */ -#define CFG_BR2_PRELIM 0xf0000000 -#define CFG_OR2_PRELIM 0xf0000000 /* 256MB NAND Flash - bank 1 */ -#endif + +/* + * NAND Flash on Local Bus + */ +#define CFG_NAND_BASE 0xe8400000 +#define CFG_NAND_BR_PRELIM(idx) ((CFG_NAND_BASE + 0x40000 * (idx)) | \ + (2 << BR_DECC_SHIFT) | /* Use HW ECC */ \ + BR_PS_8 | /* Port Size 8 bit */ \ + BR_MS_FCM | /* MSEL FCM */ \ + BR_V) /* valid */ + +#define CFG_NAND_OR_PRELIM (0xFFFF8000 | /* length 32K */ \ + OR_FCM_CSCT | \ + OR_FCM_CST | \ + OR_FCM_CHT | \ + OR_FCM_SCY_1 | \ + OR_FCM_TRLX | \ + OR_FCM_EHTR) + +#define CFG_BR2_PRELIM CFG_NAND_BR_PRELIM(0) +#define CFG_OR2_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR4_PRELIM CFG_NAND_BR_PRELIM(1) +#define CFG_OR4_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR5_PRELIM CFG_NAND_BR_PRELIM(2) +#define CFG_OR5_PRELIM CFG_NAND_OR_PRELIM +#define CFG_BR6_PRELIM CFG_NAND_BR_PRELIM(3) +#define CFG_OR6_PRELIM CFG_NAND_OR_PRELIM + #define CFG_BR3_PRELIM 0xe8000801 /* port size 8bit */ #define CFG_OR3_PRELIM 0xfff06ff7 /* 1MB PIXIS area*/ @@ -428,12 +452,13 @@ #define CFG_IBAT6U CFG_DBAT6U /* - * BAT7 4M Cache-inhibited, guarded + * BAT7 8M Cache-inhibited, guarded * 0xe800_0000 4M PIXIS + * 0xe840_0000 4M NAND */ #define CFG_DBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT \ | BATL_GUARDEDSTORAGE) -#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_1M | BATU_VS | BATU_VP) +#define CFG_DBAT7U (PIXIS_BASE | BATU_BL_8M | BATU_VS | BATU_VP) #define CFG_IBAT7L (PIXIS_BASE | BATL_PP_RW | BATL_CACHEINHIBIT) #define CFG_IBAT7U CFG_DBAT7U diff --git a/include/mpc86xx.h b/include/mpc86xx.h index 9fd349a..54bc649 100644 --- a/include/mpc86xx.h +++ b/include/mpc86xx.h @@ -77,6 +77,170 @@ #define HID0_HIGH_BAT_EN 0x00800000 #define HID0_XAEN 0x00020000 +/* BR - Base Registers + */ +#define BR0 0x5000 /* Register offset to immr */ +#define BR1 0x5008 +#define BR2 0x5010 +#define BR3 0x5018 +#define BR4 0x5020 +#define BR5 0x5028 +#define BR6 0x5030 +#define BR7 0x5038 + +#define BR_BA 0xFFFF8000 +#define BR_BA_SHIFT 15 +#define BR_PS 0x00001800 +#define BR_PS_SHIFT 11 +#define BR_PS_8 0x00000800 /* Port Size 8 bit */ +#define BR_PS_16 0x00001000 /* Port Size 16 bit */ +#define BR_PS_32 0x00001800 /* Port Size 32 bit */ +#define BR_DECC 0x00000600 +#define BR_DECC_SHIFT 9 +#define BR_DECC_OFF 0x00000000 +#define BR_DECC_CHK 0x00000200 +#define BR_DECC_CHK_GEN 0x00000400 +#define BR_WP 0x00000100 +#define BR_WP_SHIFT 8 +#define BR_MSEL 0x000000E0 +#define BR_MSEL_SHIFT 5 +#define BR_MS_GPCM 0x00000000 /* GPCM */ +#define BR_MS_FCM 0x00000020 /* FCM */ +#define BR_MS_SDRAM 0x00000060 /* SDRAM */ +#define BR_MS_UPMA 0x00000080 /* UPMA */ +#define BR_MS_UPMB 0x000000A0 /* UPMB */ +#define BR_MS_UPMC 0x000000C0 /* UPMC */ +#define BR_ATOM 0x0000000C +#define BR_ATOM_SHIFT 2 +#define BR_V 0x00000001 +#define BR_V_SHIFT 0 + +#define BR_RES ~(BR_BA | BR_PS | BR_DECC | BR_WP | BR_MSEL | BR_ATOM | BR_V) + +/* OR - Option Registers + */ +#define OR0 0x5004 /* Register offset to immr */ +#define OR1 0x500C +#define OR2 0x5014 +#define OR3 0x501C +#define OR4 0x5024 +#define OR5 0x502C +#define OR6 0x5034 +#define OR7 0x503C + +#define OR_GPCM_AM 0xFFFF8000 +#define OR_GPCM_AM_SHIFT 15 +#define OR_GPCM_BCTLD 0x00001000 +#define OR_GPCM_BCTLD_SHIFT 12 +#define OR_GPCM_CSNT 0x00000800 +#define OR_GPCM_CSNT_SHIFT 11 +#define OR_GPCM_ACS 0x00000600 +#define OR_GPCM_ACS_SHIFT 9 +#define OR_GPCM_ACS_0b10 0x00000400 +#define OR_GPCM_ACS_0b11 0x00000600 +#define OR_GPCM_XACS 0x00000100 +#define OR_GPCM_XACS_SHIFT 8 +#define OR_GPCM_SCY 0x000000F0 +#define OR_GPCM_SCY_SHIFT 4 +#define OR_GPCM_SCY_1 0x00000010 +#define OR_GPCM_SCY_2 0x00000020 +#define OR_GPCM_SCY_3 0x00000030 +#define OR_GPCM_SCY_4 0x00000040 +#define OR_GPCM_SCY_5 0x00000050 +#define OR_GPCM_SCY_6 0x00000060 +#define OR_GPCM_SCY_7 0x00000070 +#define OR_GPCM_SCY_8 0x00000080 +#define OR_GPCM_SCY_9 0x00000090 +#define OR_GPCM_SCY_10 0x000000a0 +#define OR_GPCM_SCY_11 0x000000b0 +#define OR_GPCM_SCY_12 0x000000c0 +#define OR_GPCM_SCY_13 0x000000d0 +#define OR_GPCM_SCY_14 0x000000e0 +#define OR_GPCM_SCY_15 0x000000f0 +#define OR_GPCM_SETA 0x00000008 +#define OR_GPCM_SETA_SHIFT 3 +#define OR_GPCM_TRLX 0x00000004 +#define OR_GPCM_TRLX_SHIFT 2 +#define OR_GPCM_EHTR 0x00000002 +#define OR_GPCM_EHTR_SHIFT 1 +#define OR_GPCM_EAD 0x00000001 +#define OR_GPCM_EAD_SHIFT 0 + +#define OR_FCM_AM 0xFFFF8000 +#define OR_FCM_AM_SHIFT 15 +#define OR_FCM_BCTLD 0x00001000 +#define OR_FCM_BCTLD_SHIFT 12 +#define OR_FCM_PGS 0x00000400 +#define OR_FCM_PGS_SHIFT 10 +#define OR_FCM_CSCT 0x00000200 +#define OR_FCM_CSCT_SHIFT 9 +#define OR_FCM_CST 0x00000100 +#define OR_FCM_CST_SHIFT 8 +#define OR_FCM_CHT 0x00000080 +#define OR_FCM_CHT_SHIFT 7 +#define OR_FCM_SCY 0x00000070 +#define OR_FCM_SCY_SHIFT 4 +#define OR_FCM_SCY_1 0x00000010 +#define OR_FCM_SCY_2 0x00000020 +#define OR_FCM_SCY_3 0x00000030 +#define OR_FCM_SCY_4 0x00000040 +#define OR_FCM_SCY_5 0x00000050 +#define OR_FCM_SCY_6 0x00000060 +#define OR_FCM_SCY_7 0x00000070 +#define OR_FCM_RST 0x00000008 +#define OR_FCM_RST_SHIFT 3 +#define OR_FCM_TRLX 0x00000004 +#define OR_FCM_TRLX_SHIFT 2 +#define OR_FCM_EHTR 0x00000002 +#define OR_FCM_EHTR_SHIFT 1 + +#define OR_UPM_AM 0xFFFF8000 +#define OR_UPM_AM_SHIFT 15 +#define OR_UPM_XAM 0x00006000 +#define OR_UPM_XAM_SHIFT 13 +#define OR_UPM_BCTLD 0x00001000 +#define OR_UPM_BCTLD_SHIFT 12 +#define OR_UPM_BI 0x00000100 +#define OR_UPM_BI_SHIFT 8 +#define OR_UPM_TRLX 0x00000004 +#define OR_UPM_TRLX_SHIFT 2 +#define OR_UPM_EHTR 0x00000002 +#define OR_UPM_EHTR_SHIFT 1 +#define OR_UPM_EAD 0x00000001 +#define OR_UPM_EAD_SHIFT 0 + +#define OR_SDRAM_AM 0xFFFF8000 +#define OR_SDRAM_AM_SHIFT 15 +#define OR_SDRAM_XAM 0x00006000 +#define OR_SDRAM_XAM_SHIFT 13 +#define OR_SDRAM_COLS 0x00001C00 +#define OR_SDRAM_COLS_SHIFT 10 +#define OR_SDRAM_ROWS 0x000001C0 +#define OR_SDRAM_ROWS_SHIFT 6 +#define OR_SDRAM_PMSEL 0x00000020 +#define OR_SDRAM_PMSEL_SHIFT 5 +#define OR_SDRAM_EAD 0x00000001 +#define OR_SDRAM_EAD_SHIFT 0 + +#define OR_AM_32KB 0xFFFF8000 +#define OR_AM_64KB 0xFFFF0000 +#define OR_AM_128KB 0xFFFE0000 +#define OR_AM_256KB 0xFFFC0000 +#define OR_AM_512KB 0xFFF80000 +#define OR_AM_1MB 0xFFF00000 +#define OR_AM_2MB 0xFFE00000 +#define OR_AM_4MB 0xFFC00000 +#define OR_AM_8MB 0xFF800000 +#define OR_AM_16MB 0xFF000000 +#define OR_AM_32MB 0xFE000000 +#define OR_AM_64MB 0xFC000000 +#define OR_AM_128MB 0xF8000000 +#define OR_AM_256MB 0xF0000000 +#define OR_AM_512MB 0xE0000000 +#define OR_AM_1GB 0xC0000000 +#define OR_AM_2GB 0x80000000 +#define OR_AM_4GB 0x00000000 + #ifndef __ASSEMBLY__ typedef struct { -- 1.5.5.1

7 14

[U-Boot-Users] [RFC/PATCH 1/6] Move definition of container_of() to common.h
by Haavard Skinnemoen 05 Jun '08

05 Jun '08

AVR32 and AT91SAM9 both have their own identical definitions of container_of() taken from the Linux kernel. Move it to common.h so that all architectures can use it. container_of() is already used by some drivers, and will be used extensively by the new and improved SPI API. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- include/asm-arm/arch-at91sam9/hardware.h | 11 ----------- include/asm-avr32/u-boot.h | 11 ----------- include/common.h | 11 +++++++++++ 3 files changed, 11 insertions(+), 22 deletions(-) diff --git a/include/asm-arm/arch-at91sam9/hardware.h b/include/asm-arm/arch-at91sam9/hardware.h index d2fe453..fba3908 100644 --- a/include/asm-arm/arch-at91sam9/hardware.h +++ b/include/asm-arm/arch-at91sam9/hardware.h @@ -42,15 +42,4 @@ #error "Unsupported AT91 processor" #endif -/* - * container_of - cast a member of a structure out to the containing structure - * - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - */ -#define container_of(ptr, type, member) ({ \ - const typeof(((type *)0)->member) *__mptr = (ptr); \ - (type *)((char *)__mptr - offsetof(type, member)); }) - #endif diff --git a/include/asm-avr32/u-boot.h b/include/asm-avr32/u-boot.h index 71dfcaf..85ef008 100644 --- a/include/asm-avr32/u-boot.h +++ b/include/asm-avr32/u-boot.h @@ -42,15 +42,4 @@ typedef struct bd_info { #define bi_memstart bi_dram[0].start #define bi_memsize bi_dram[0].size -/** - * container_of - cast a member of a structure out to the containing structure - * - * @ptr: the pointer to the member. - * @type: the type of the container struct this is embedded in. - * @member: the name of the member within the struct. - */ -#define container_of(ptr, type, member) ({ \ - const typeof( ((type *)0)->member ) *__mptr = (ptr); \ - (type *)( (char *)__mptr - offsetof(type,member) );}) - #endif /* __ASM_U_BOOT_H__ */ diff --git a/include/common.h b/include/common.h index d0f5704..26e1b46 100644 --- a/include/common.h +++ b/include/common.h @@ -176,6 +176,17 @@ typedef void (interrupt_handler_t)(void *); (__x > __y) ? __x : __y; }) +/** + * container_of - cast a member of a structure out to the containing structure + * @ptr: the pointer to the member. + * @type: the type of the container struct this is embedded in. + * @member: the name of the member within the struct. + * + */ +#define container_of(ptr, type, member) ({ \ + const typeof( ((type *)0)->member ) *__mptr = (ptr); \ + (type *)( (char *)__mptr - offsetof(type,member) );}) + /* * Function Prototypes */ -- 1.5.4.3

5 19

[U-Boot-Users] From: Sergei Poselenov <sposelenov@emcraft.com>
by Wolfgang Denk 05 Jun '08

05 Jun '08

Signed-off-by: Sergei Poselenov <sposelenov(a)emcraft.com> --- board/socrates/socrates.c | 13 +++++++++++-- include/configs/socrates.h | 3 ++- 2 files changed, 13 insertions(+), 3 deletions(-) diff --git a/board/socrates/socrates.c b/board/socrates/socrates.c index cb58994..15c6478 100644 --- a/board/socrates/socrates.c +++ b/board/socrates/socrates.c @@ -45,6 +45,9 @@ ulong flash_get_size (ulong base, int banknum); int checkboard (void) { + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + char *src; + int f; char *s = getenv("serial#"); puts("Board: Socrates"); @@ -55,8 +58,14 @@ int checkboard (void) putc('\n'); #ifdef CONFIG_PCI - printf ("PCI1: 32 bit, %d MHz (compiled)\n", - CONFIG_SYS_CLK_FREQ / 1000000); + if (gur->porpllsr & (1<<15)) { + src = "SYSCLK"; + f = CONFIG_SYS_CLK_FREQ; + } else { + src = "PCI_CLK"; + f = CONFIG_PCI_CLK_FREQ; + } + printf ("PCI1: 32 bit, %d MHz (%s)\n", f/1000000, src); #else printf ("PCI1: disabled\n"); #endif diff --git a/include/configs/socrates.h b/include/configs/socrates.h index 00c0dab..028a772 100644 --- a/include/configs/socrates.h +++ b/include/configs/socrates.h @@ -227,7 +227,8 @@ */ #define CFG_PCI_PHYS 0x80000000 /* 1G PCI TLB */ - +/* PCI is clocked by the external source at 33 MHz */ +#define CONFIG_PCI_CLK_FREQ 33000000 #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -- 1.5.4.2

5 7

[U-Boot-Users] [PATCH] Fix incorrect switch for IF_TYPE in part.c
by Tor Krill 05 Jun '08

05 Jun '08

Use correct field in block_dev_desc_t when writing interface type in dev_print. Error introduced in 574b319512b13e10800f0045e39b993f4ca25e42. Signed-off-by: Tor Krill <tor(a)excito.com> --- disk/part.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/disk/part.c b/disk/part.c index 316e254..6a1b1f8 100644 --- a/disk/part.c +++ b/disk/part.c @@ -109,7 +109,7 @@ void dev_print (block_dev_desc_t *dev_desc) lbaint_t lba512; #endif - switch (dev_desc->type) { + switch (dev_desc->if_type) { case IF_TYPE_SCSI: printf ("(%d:%d) Vendor: %s Prod.: %s Rev: %s\n", dev_desc->target,dev_desc->lun, -- 1.5.5.1

3 3