May 2008 - U-Boot

[U-Boot-Users] [PATCH] MMC: Consolidate MMC/SD command definitions
by Haavard Skinnemoen 13 Jul '08

13 Jul '08

This moves the MMC and SD Card command definitions from include/asm/arch/mmc.h into include/mmc.h. These definitions are given by the MMC and SD Card standards, not by any particular architecture. There's a lot more room for consolidation in the MMC drivers which I'm hoping to get done eventually, but this patch is a start. Compile-tested for all avr32 boards as well as lpc2292sodimm and lubbock. This should cover all three mmc drivers in the tree. Signed-off-by: Haavard Skinnemoen <haavard.skinnemoen(a)atmel.com> --- cpu/at32ap/atmel_mci.c | 4 ++-- cpu/pxa/mmc.c | 8 ++++---- include/asm-arm/arch-pxa/mmc.h | 17 ----------------- include/asm-avr32/arch-at32ap700x/mmc.h | 19 ------------------- include/mmc.h | 24 ++++++++++++++++++++++++ 5 files changed, 30 insertions(+), 42 deletions(-) diff --git a/cpu/at32ap/atmel_mci.c b/cpu/at32ap/atmel_mci.c index f59dfb5..92f5a28 100644 --- a/cpu/at32ap/atmel_mci.c +++ b/cpu/at32ap/atmel_mci.c @@ -350,7 +350,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) mmc_idle_cards(); for (i = 0; i < 1000; i++) { - ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, + ret = mmc_acmd(SD_CMD_APP_SEND_OP_COND, CFG_MMC_OP_COND, resp, R3 | NID); if (ret || (resp[0] & 0x80000000)) break; @@ -368,7 +368,7 @@ static int sd_init_card(struct mmc_cid *cid, int verbose) mmc_dump_cid(cid); /* Get RCA of the card that responded */ - ret = mmc_cmd(MMC_CMD_SD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); + ret = mmc_cmd(SD_CMD_SEND_RELATIVE_ADDR, 0, resp, R6 | NCR); if (ret) return ret; diff --git a/cpu/pxa/mmc.c b/cpu/pxa/mmc.c index 039ce0f..bf48954 100644 --- a/cpu/pxa/mmc.c +++ b/cpu/pxa/mmc.c @@ -119,7 +119,7 @@ mmc_block_read(uchar * dst, ulong src, ulong len) MMC_RDTO = 0xffff; MMC_NOB = 1; MMC_BLKLEN = len; - mmc_cmd(MMC_CMD_READ_BLOCK, argh, argl, + mmc_cmd(MMC_CMD_READ_SINGLE_BLOCK, argh, argl, MMC_CMDAT_R1 | MMC_CMDAT_READ | MMC_CMDAT_BLOCK | MMC_CMDAT_DATA_EN); @@ -568,7 +568,7 @@ mmc_init(int verbose) MMC_SPI = MMC_SPI_DISABLE; /* reset */ - mmc_cmd(MMC_CMD_RESET, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); + mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, 0, MMC_CMDAT_INIT | MMC_CMDAT_R0); udelay(200000); retries = 3; while (retries--) { @@ -578,7 +578,7 @@ mmc_init(int verbose) break; } - resp = mmc_cmd(SD_CMD_APP_OP_COND, 0x0020, 0, MMC_CMDAT_R3 | (retries < 2 ? 0 : MMC_CMDAT_INIT)); /* Select 3.2-3.3 and 3.3-3.4V */ + resp = mmc_cmd(SD_CMD_APP_SEND_OP_COND, 0x0020, 0, MMC_CMDAT_R3 | (retries < 2 ? 0 : MMC_CMDAT_INIT)); /* Select 3.2-3.3 and 3.3-3.4V */ if (resp[0] & 0x80000000) { mmc_dev.if_type = IF_TYPE_SD; debug("Detected SD card\n"); @@ -616,7 +616,7 @@ mmc_init(int verbose) memcpy(cid_resp, resp, sizeof(cid_resp)); /* MMC exists, get CSD too */ - resp = mmc_cmd(MMC_CMD_SET_RCA, 0, 0, MMC_CMDAT_R1); + resp = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, 0, 0, MMC_CMDAT_R1); if (IF_TYPE_SD == mmc_dev.if_type) rca = ((resp[0] & 0xffff0000) >> 16); resp = mmc_cmd(MMC_CMD_SEND_CSD, rca, 0, MMC_CMDAT_R2); diff --git a/include/asm-arm/arch-pxa/mmc.h b/include/asm-arm/arch-pxa/mmc.h index b9304b1..9954680 100644 --- a/include/asm-arm/arch-pxa/mmc.h +++ b/include/asm-arm/arch-pxa/mmc.h @@ -110,23 +110,6 @@ #define MMC_DEFAULT_RCA 1 #define MMC_BLOCK_SIZE 512 -#define MMC_CMD_RESET 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RCA 3 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_BLOCK 17 -#define MMC_CMD_RD_BLK_MULTI 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -#define SD_CMD_APP_SET_BUS_WIDTH 6 -#define SD_CMD_APP_OP_COND 41 - #define MMC_MAX_BLOCK_SIZE 512 #define MMC_R1_IDLE_STATE 0x01 diff --git a/include/asm-avr32/arch-at32ap700x/mmc.h b/include/asm-avr32/arch-at32ap700x/mmc.h index fcfbbb3..9caba91 100644 --- a/include/asm-avr32/arch-at32ap700x/mmc.h +++ b/include/asm-avr32/arch-at32ap700x/mmc.h @@ -71,25 +71,6 @@ struct mmc_csd u8 one:1; }; -/* MMC Command numbers */ -#define MMC_CMD_GO_IDLE_STATE 0 -#define MMC_CMD_SEND_OP_COND 1 -#define MMC_CMD_ALL_SEND_CID 2 -#define MMC_CMD_SET_RELATIVE_ADDR 3 -#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 -#define MMC_CMD_SET_DSR 4 -#define MMC_CMD_SELECT_CARD 7 -#define MMC_CMD_SEND_CSD 9 -#define MMC_CMD_SEND_CID 10 -#define MMC_CMD_SEND_STATUS 13 -#define MMC_CMD_SET_BLOCKLEN 16 -#define MMC_CMD_READ_SINGLE_BLOCK 17 -#define MMC_CMD_READ_MULTIPLE_BLOCK 18 -#define MMC_CMD_WRITE_BLOCK 24 -#define MMC_CMD_APP_CMD 55 - -#define MMC_ACMD_SD_SEND_OP_COND 41 - #define R1_ILLEGAL_COMMAND (1 << 22) #define R1_APP_CMD (1 << 5) diff --git a/include/mmc.h b/include/mmc.h index a271695..268f27e 100644 --- a/include/mmc.h +++ b/include/mmc.h @@ -25,6 +25,30 @@ #define _MMC_H_ #include <asm/arch/mmc.h> +/* MMC command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_APP_CMD 55 + +/* SD Card command numbers */ +#define SD_CMD_SEND_RELATIVE_ADDR 3 +#define SD_CMD_SWITCH 6 +#define SD_CMD_SEND_IF_COND 8 + +#define SD_CMD_APP_SET_BUS_WIDTH 6 +#define SD_CMD_APP_SEND_OP_COND 41 + int mmc_init(int verbose); int mmc_read(ulong src, uchar *dst, int size); int mmc_write(uchar *src, ulong dst, int size); -- 1.5.5.1

5 14

[U-Boot-Users] [PATCH] Fix boot from NOR due to incorrect reset delay.
by Stelian Pop 10 Jul '08

10 Jul '08

AT91 RSTC registers are battery-backuped, so their values are not reset across power cycles. One of those registers, the AT91_RSTC_MR register, is being modified by U-Boot, in the ethernet initialisation routine, to generate a 500ms user reset. Unfortunately, this value is not being restored afterwards, causing subsequent resets to also last for 500ms. This long reset sequence causes problems (at least) in the boot sequence from NOR: by the time the CPU tries to load a program from the NOR flash, the latter is still in reset and not yet available. Additionaly, this patch fixes a bug in the original code which caused the reset delay to last for 2s instead of 500ms. Signed-off-by: Stelian Pop <stelian(a)popies.net> --- This patch applies on top of the latest AT91 patches, as integrated in the testing-V2 branch of the u-boot-at91 repository. board/atmel/at91cap9adk/at91cap9adk.c | 7 ++++++- board/atmel/at91sam9260ek/at91sam9260ek.c | 4 ++-- board/atmel/at91sam9263ek/at91sam9263ek.c | 7 ++++++- 3 files changed, 14 insertions(+), 4 deletions(-) diff --git a/board/atmel/at91cap9adk/at91cap9adk.c b/board/atmel/at91cap9adk/at91cap9adk.c index a3eaf19..c5082a0 100644 --- a/board/atmel/at91cap9adk/at91cap9adk.c +++ b/board/atmel/at91cap9adk/at91cap9adk.c @@ -196,7 +196,7 @@ static void at91cap9_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -204,6 +204,11 @@ static void at91cap9_macb_hw_init(void) /* Wait for end hardware reset */ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PB22) | pin_to_mask(AT91_PIN_PB25) | diff --git a/board/atmel/at91sam9260ek/at91sam9260ek.c b/board/atmel/at91sam9260ek/at91sam9260ek.c index 4635f0f..3572b16 100644 --- a/board/atmel/at91sam9260ek/at91sam9260ek.c +++ b/board/atmel/at91sam9260ek/at91sam9260ek.c @@ -149,7 +149,7 @@ static void at91sam9260ek_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -159,7 +159,7 @@ static void at91sam9260ek_macb_hw_init(void) /* Restore NRST value */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0 << 8) | + (AT91_RSTC_ERSTL & (0x0 << 8)) | AT91_RSTC_URSTEN); /* Re-enable pull-up */ diff --git a/board/atmel/at91sam9263ek/at91sam9263ek.c b/board/atmel/at91sam9263ek/at91sam9263ek.c index ba7fc71..169ee25 100644 --- a/board/atmel/at91sam9263ek/at91sam9263ek.c +++ b/board/atmel/at91sam9263ek/at91sam9263ek.c @@ -147,7 +147,7 @@ static void at91sam9263ek_macb_hw_init(void) /* Need to reset PHY -> 500ms reset */ at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | - AT91_RSTC_ERSTL | (0x0D << 8) | + (AT91_RSTC_ERSTL & (0x0D << 8)) | AT91_RSTC_URSTEN); at91_sys_write(AT91_RSTC_CR, AT91_RSTC_KEY | AT91_RSTC_EXTRST); @@ -155,6 +155,11 @@ static void at91sam9263ek_macb_hw_init(void) /* Wait for end hardware reset */ while (!(at91_sys_read(AT91_RSTC_SR) & AT91_RSTC_NRSTL)); + /* Restore NRST value */ + at91_sys_write(AT91_RSTC_MR, AT91_RSTC_KEY | + (AT91_RSTC_ERSTL & (0x0 << 8)) | + AT91_RSTC_URSTEN); + /* Re-enable pull-up */ writel(pin_to_mask(AT91_PIN_PC25), pin_to_controller(AT91_PIN_PC0) + PIO_PUER); -- 1.5.3.3

3 3

[U-Boot-Users] [PATCH 2/2] Remove prototypes of nand_init() in favor of including nand.h.
by Scott Wood 09 Jul '08

09 Jul '08

Likewise with onenand_init(). Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- lib_arm/board.c | 10 ++-------- lib_ppc/board.c | 4 +--- lib_sh/board.c | 2 +- 3 files changed, 4 insertions(+), 12 deletions(-) diff --git a/lib_arm/board.c b/lib_arm/board.c index 67506b3..5e04553 100644 --- a/lib_arm/board.c +++ b/lib_arm/board.c @@ -45,6 +45,8 @@ #include <version.h> #include <net.h> #include <serial.h> +#include <nand.h> +#include <onenand_uboot.h> #ifdef CONFIG_DRIVER_SMC91111 #include "../drivers/net/smc91111.h" @@ -55,14 +57,6 @@ DECLARE_GLOBAL_DATA_PTR; -#if defined(CONFIG_CMD_NAND) -void nand_init (void); -#endif - -#if defined(CONFIG_CMD_ONENAND) -void onenand_init(void); -#endif - ulong monitor_flash_len; #ifdef CONFIG_HAS_DATAFLASH diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 4956403..6f7242d 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -93,9 +93,7 @@ void doc_init (void); #if defined(CONFIG_HARD_SPI) #include <spi.h> #endif -#if defined(CONFIG_CMD_NAND) -void nand_init (void); -#endif +#include <nand.h> static char *failed = "*** failed ***\n"; diff --git a/lib_sh/board.c b/lib_sh/board.c index 883c381..807415c 100644 --- a/lib_sh/board.c +++ b/lib_sh/board.c @@ -76,7 +76,7 @@ static int sh_flash_init(void) } #if defined(CONFIG_CMD_NAND) -void nand_init (void); +#include <nand.h> static int sh_nand_init(void) { printf("NAND: "); -- 1.5.3

3 4

[U-Boot-Users] [PATCH] ARM: Add support for Lyrtech SFF-SDR board (ARM926EJS)
by Hugo Villeneuve 08 Jul '08

08 Jul '08

ARM: This patch adds support for the Lyrtech SFF-SDR board, based on the TI DaVinci architecture (ARM926EJS). Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> Signed-off-by: Philip Balister <philip(a)balister.org> --- MAKEALL | 1 + Makefile | 3 + board/davinci/sffsdr/Makefile | 52 +++++++++ board/davinci/sffsdr/board_init.S | 29 +++++ board/davinci/sffsdr/config.mk | 24 ++++ board/davinci/sffsdr/dv_board.c | 212 +++++++++++++++++++++++++++++++++++++ board/davinci/sffsdr/u-boot.lds | 52 +++++++++ include/asm-arm/mach-types.h | 13 +++ include/configs/davinci_sffsdr.h | 177 +++++++++++++++++++++++++++++++ 9 files changed, 563 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index 37b4334..f53ceec 100755 --- a/MAKEALL +++ b/MAKEALL @@ -496,6 +496,7 @@ LIST_ARM9=" \ voiceblue \ davinci_dvevm \ davinci_schmoogie \ + davinci_sffsdr \ davinci_sonata \ " diff --git a/Makefile b/Makefile index 6548f8e..05d90aa 100644 --- a/Makefile +++ b/Makefile @@ -2408,6 +2408,9 @@ davinci_dvevm_config : unconfig davinci_schmoogie_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs schmoogie davinci davinci +davinci_sffsdr_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm926ejs sffsdr davinci davinci + davinci_sonata_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm926ejs sonata davinci davinci diff --git a/board/davinci/sffsdr/Makefile b/board/davinci/sffsdr/Makefile new file mode 100644 index 0000000..fa00138 --- /dev/null +++ b/board/davinci/sffsdr/Makefile @@ -0,0 +1,52 @@ +# +# (C) Copyright 2000, 2001, 2002 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := dv_board.o +SOBJS := board_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak *~ .depend + +######################################################################### +# This is for $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/davinci/sffsdr/board_init.S b/board/davinci/sffsdr/board_init.S new file mode 100644 index 0000000..22d8adc --- /dev/null +++ b/board/davinci/sffsdr/board_init.S @@ -0,0 +1,29 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Board-specific low level initialization code. Called at the very end + * of cpu/arm926ejs/davinci/lowlevel_init.S. Just returns if there is no + * initialization required. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> + +.globl dv_board_init +dv_board_init: + + mov pc, lr diff --git a/board/davinci/sffsdr/config.mk b/board/davinci/sffsdr/config.mk new file mode 100644 index 0000000..e8a329c --- /dev/null +++ b/board/davinci/sffsdr/config.mk @@ -0,0 +1,24 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# David Mueller, ELSOFT AG, <d.mueller(a)elsoft.ch> +# +# Lyrtech SFF SDR board (ARM926EJS) cpu +# see http://www.lyrtech.com/ for more information on Lyrtech +# +# SFF SDR board has 1 bank of 128 MB DDR RAM +# Physical Address: +# 8000'0000 to 87FF'FFFF +# +# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 +# (mem base + reserved) +# +# Integrity kernel is expected to be at 8000'0000, entry 8000'00D0, +# up to 81FF'FFFF (uses up to 32 MB of memory for text, heap, etc). +# +# we load ourself to 8400'0000 +# +# + +# Provide at least 32MB spacing between us and the Integrity kernel image +TEXT_BASE = 0x84000000 diff --git a/board/davinci/sffsdr/dv_board.c b/board/davinci/sffsdr/dv_board.c new file mode 100644 index 0000000..0771b5b --- /dev/null +++ b/board/davinci/sffsdr/dv_board.c @@ -0,0 +1,212 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * Parts are shamelessly stolen from various TI sources, original copyright + * follows: + * ----------------------------------------------------------------- + * + * Copyright (C) 2004 Texas Instruments. + * + * ---------------------------------------------------------------------------- + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 675 Mass Ave, Cambridge, MA 02139, USA. + * ---------------------------------------------------------------------------- + */ + +#include <common.h> +#include <i2c.h> +#include <asm/arch/hardware.h> +#include <asm/arch/emac_defs.h> + +DECLARE_GLOBAL_DATA_PTR; + +extern void timer_init(void); +extern int eth_hw_init(void); +extern phy_t phy; + + +/* Works on Always On power domain only (no PD argument) */ +void lpsc_on(unsigned int id) +{ + dv_reg_p mdstat, mdctl; + + if (id >= DAVINCI_LPSC_GEM) + return; /* Don't work on DSP Power Domain */ + + mdstat = REG_P(PSC_MDSTAT_BASE + (id * 4)); + mdctl = REG_P(PSC_MDCTL_BASE + (id * 4)); + + while (REG(PSC_PTSTAT) & 0x01); + + if ((*mdstat & 0x1f) == 0x03) + return; /* Already on and enabled */ + + *mdctl |= 0x03; + + /* Special treatment for some modules as for sprue14 p.7.4.2 */ + if ((id == DAVINCI_LPSC_VPSSSLV) || + (id == DAVINCI_LPSC_EMAC) || + (id == DAVINCI_LPSC_EMAC_WRAPPER) || + (id == DAVINCI_LPSC_MDIO) || + (id == DAVINCI_LPSC_USB) || + (id == DAVINCI_LPSC_ATA) || + (id == DAVINCI_LPSC_VLYNQ) || + (id == DAVINCI_LPSC_UHPI) || + (id == DAVINCI_LPSC_DDR_EMIF) || + (id == DAVINCI_LPSC_AEMIF) || + (id == DAVINCI_LPSC_MMC_SD) || + (id == DAVINCI_LPSC_MEMSTICK) || + (id == DAVINCI_LPSC_McBSP) || + (id == DAVINCI_LPSC_GPIO)) + * mdctl |= 0x200; + + REG(PSC_PTCMD) = 0x01; + + while (REG(PSC_PTSTAT) & 0x03); + while ((*mdstat & 0x1f) != 0x03); /* Probably an overkill... */ +} + +void dsp_on(void) +{ + int i; + + if (REG(PSC_PDSTAT1) & 0x1f) + return; /* Already on */ + + REG(PSC_GBLCTL) |= 0x01; + REG(PSC_PDCTL1) |= 0x01; + REG(PSC_PDCTL1) &= ~0x100; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_GEM * 4)) &= 0xfffffeff; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) |= 0x03; + REG(PSC_MDCTL_BASE + (DAVINCI_LPSC_IMCOP * 4)) &= 0xfffffeff; + REG(PSC_PTCMD) = 0x02; + + for (i = 0; i < 100; i++) { + if (REG(PSC_EPCPR) & 0x02) + break; + } + + REG(PSC_CHP_SHRTSW) = 0x01; + REG(PSC_PDCTL1) |= 0x100; + REG(PSC_EPCCR) = 0x02; + + for (i = 0; i < 100; i++) { + if (!(REG(PSC_PTSTAT) & 0x02)) + break; + } + + REG(PSC_GBLCTL) &= ~0x1f; +} + + +int board_init(void) +{ + /* arch number of the board */ + gd->bd->bi_arch_number = MACH_TYPE_SFFSDR; + + /* address of boot parameters */ + gd->bd->bi_boot_params = LINUX_BOOT_PARAM_ADDR; + + /* Workaround for TMS320DM6446 errata 1.3.22 */ + REG(PSC_SILVER_BULLET) = 0; + + /* Power on required peripherals */ + lpsc_on(DAVINCI_LPSC_EMAC); + lpsc_on(DAVINCI_LPSC_EMAC_WRAPPER); + lpsc_on(DAVINCI_LPSC_MDIO); + lpsc_on(DAVINCI_LPSC_I2C); + lpsc_on(DAVINCI_LPSC_UART0); + lpsc_on(DAVINCI_LPSC_TIMER1); + lpsc_on(DAVINCI_LPSC_GPIO); + + /* Powerup the DSP */ + dsp_on(); + + /* Bringup UART0 out of reset */ + REG(UART0_PWREMU_MGMT) = 0x0000e003; + + /* Enable GIO3.3V cells used for EMAC */ + REG(VDD3P3V_PWDN) = 0; + + /* Enable UART0 MUX lines */ + REG(PINMUX1) |= 1; + + /* Enable EMAC and AEMIF pins */ + REG(PINMUX0) = 0x80000c1f; + + /* Enable I2C pin Mux */ + REG(PINMUX1) |= (1 << 7); + + /* Set the Bus Priority Register to appropriate value */ + REG(VBPR) = 0x20; + + timer_init(); + + return(0); +} + +int misc_init_r(void) +{ + u_int8_t tmp[20], buf[10]; + int i = 0; + int clk = 0; + + clk = ((REG(PLL2_PLLM) + 1) * 27) / ((REG(PLL2_DIV2) & 0x1f) + 1); + + printf("ARM Clock: %dMHz\n", ((REG(PLL1_PLLM) + 1) * 27) / 2); + printf("DDR Clock: %dMHz\n", (clk / 2)); + + /* Configure I2C switch (PCA9543) to enable channel 0. */ + tmp[0] = CFG_I2C_PCA9543_ENABLE_CH0; + if (i2c_write(CFG_I2C_PCA9543_ADDR, 0, + CFG_I2C_PCA9543_ADDR_LEN, tmp, 1)) + printf("Write to MUX @ 0x%02x failed\n", CFG_I2C_PCA9543_ADDR); + + /* Set Ethernet MAC address from EEPROM. + * We must read 8 bytes because data is stored in little-endian. */ + if (i2c_read(CFG_I2C_EEPROM_ADDR, 0x05A8, + CFG_I2C_EEPROM_ADDR_LEN, buf, 8)) { + printf("Read from EEPROM @ 0x%02x failed\n", + CFG_I2C_EEPROM_ADDR); + } else { + tmp[0] = 0xff; + for (i = 0; i < 6; i++) + tmp[0] &= buf[i]; + + if ((tmp[0] != 0xff) && (getenv("ethaddr") == NULL)) { + sprintf((char *)&tmp[0], + "%02x:%02x:%02x:%02x:%02x:%02x", + buf[3], buf[2], buf[1], buf[0], + buf[7], buf[6]); + setenv("ethaddr", (char *)&tmp[0]); + } + } + + if (!eth_hw_init()) { + printf("Ethernet init failed\n"); + } else { + printf("ETH PHY: %s\n", phy.name); + } + + return(0); +} + +int dram_init(void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return(0); +} diff --git a/board/davinci/sffsdr/u-boot.lds b/board/davinci/sffsdr/u-boot.lds new file mode 100644 index 0000000..a4fcd1a --- /dev/null +++ b/board/davinci/sffsdr/u-boot.lds @@ -0,0 +1,52 @@ +/* + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-littlearm", "elf32-littlearm", "elf32-littlearm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + . = ALIGN(4); + .text : + { + cpu/arm926ejs/start.o (.text) + *(.text) + } + . = ALIGN(4); + .rodata : { *(.rodata) } + . = ALIGN(4); + .data : { *(.data) } + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +} diff --git a/include/asm-arm/mach-types.h b/include/asm-arm/mach-types.h index aaf2ea2..b347857 100644 --- a/include/asm-arm/mach-types.h +++ b/include/asm-arm/mach-types.h @@ -1595,6 +1595,7 @@ extern unsigned int __machine_arch_type; #define MACH_TYPE_P300 1602 #define MACH_TYPE_XDACOMET 1603 #define MACH_TYPE_DEXFLEX2 1604 +#define MACH_TYPE_SFFSDR 1657 #ifdef CONFIG_ARCH_EBSA110 # ifdef machine_arch_type @@ -16500,6 +16501,18 @@ extern unsigned int __machine_arch_type; # define machine_is_schmoogie() (0) #endif +#ifdef CONFIG_MACH_SFFSDR +# ifdef machine_arch_type +# undef machine_arch_type +# define machine_arch_type __machine_arch_type +# else +# define machine_arch_type MACH_TYPE_SFFSDR +# endif +# define machine_is_sffsdr() (machine_arch_type == MACH_TYPE_SFFSDR) +#else +# define machine_is_sffsdr() (0) +#endif + #ifdef CONFIG_MACH_AZTOOL # ifdef machine_arch_type # undef machine_arch_type diff --git a/include/configs/davinci_sffsdr.h b/include/configs/davinci_sffsdr.h new file mode 100644 index 0000000..41a6763 --- /dev/null +++ b/include/configs/davinci_sffsdr.h @@ -0,0 +1,177 @@ +/* + * Copyright (C) 2007 Sergey Kubushyn <ksi(a)koi8.net> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H +#include <asm/sizes.h> + +/*=======*/ +/* Board */ +/*=======*/ +#define SFFSDR +#define CFG_NAND_LARGEPAGE +#define CFG_USE_NAND +/*===================*/ +/* SoC Configuration */ +/*===================*/ +#define CONFIG_ARM926EJS /* arm926ejs CPU core */ +#define CONFIG_SYS_CLK_FREQ 297000000 /* Arm Clock frequency */ +#define CFG_TIMERBASE 0x01c21400 /* use timer 0 */ +#define CFG_HZ_CLOCK 27000000 /* Timer Input clock freq */ +#define CFG_HZ 1000 +/*==================================================*/ +/* EEPROM definitions for Atmel 24LC64 EEPROM chip */ +/*==================================================*/ +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_I2C_EEPROM_ADDR 0x50 +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 20 +/*=============*/ +/* Memory Info */ +/*=============*/ +#define CFG_MALLOC_LEN (0x10000 + 256*1024) /* malloc() len */ +#define CFG_GBL_DATA_SIZE 128 /* reserved for initial data */ +#define CFG_MEMTEST_START 0x80000000 /* memtest start address */ +#define CFG_MEMTEST_END 0x81000000 /* 16MB RAM test */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define CONFIG_STACKSIZE (256*1024) /* regular stack */ +#define PHYS_SDRAM_1 0x80000000 /* DDR Start */ +#define PHYS_SDRAM_1_SIZE 0x08000000 /* DDR size 128MB */ +#define DDR_4BANKS /* 4-bank DDR2 (128MB) */ +/*====================*/ +/* Serial Driver info */ +/*====================*/ +#define CFG_NS16550 +#define CFG_NS16550_SERIAL +#define CFG_NS16550_REG_SIZE 4 /* NS16550 register size */ +#define CFG_NS16550_COM1 0x01c20000 /* Base address of UART0 */ +#define CFG_NS16550_CLK 27000000 /* Input clock to NS16550 */ +#define CONFIG_CONS_INDEX 1 /* use UART0 for console */ +#define CONFIG_BAUDRATE 115200 /* Default baud rate */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } +/*===================*/ +/* I2C Configuration */ +/*===================*/ +#define CONFIG_HARD_I2C +#define CONFIG_DRIVER_DAVINCI_I2C +#define CFG_I2C_SPEED 80000 /* 100Kbps won't work, silicon bug */ +#define CFG_I2C_SLAVE 10 /* Bogus, master-only in U-Boot */ +/*==================================*/ +/* Network & Ethernet Configuration */ +/*==================================*/ +#define CONFIG_DRIVER_TI_EMAC +#define CONFIG_MII +#define CONFIG_BOOTP_DEFAULT +#define CONFIG_BOOTP_DNS +#define CONFIG_BOOTP_DNS2 +#define CONFIG_BOOTP_SEND_HOSTNAME +#define CONFIG_NET_RETRY_COUNT 10 +#define CONFIG_OVERWRITE_ETHADDR_ONCE +/*=====================*/ +/* Flash & Environment */ +/*=====================*/ +#undef CFG_ENV_IS_IN_FLASH +#define CFG_NO_FLASH +#define CFG_ENV_IS_IN_NAND /* U-Boot env in NAND Flash */ +#define CFG_ENV_SECT_SIZE 2048 /* Env sector Size */ +#define CFG_ENV_SIZE SZ_128K +#define CONFIG_SKIP_LOWLEVEL_INIT /* U-Boot is loaded by a bootloader */ +#define CONFIG_SKIP_RELOCATE_UBOOT /* to a proper address, init done */ +#define CFG_NAND_BASE 0x02000000 +#define CFG_NAND_HW_ECC +#define CFG_MAX_NAND_DEVICE 1 /* Max number of NAND devices */ +#define NAND_MAX_CHIPS 1 +#define CFG_ENV_OFFSET 0x0 /* Block 0--not used by bootcode */ +/*=====================*/ +/* Board related stuff */ +/*=====================*/ +/*==========================================*/ +/* I2C switch definitions for PCA9543 chip */ +/* on Lyrtech SFF SDR board. */ +/* This chip has a single register. */ +/*==========================================*/ +#define CFG_I2C_PCA9543_ADDR 0x70 +#define CFG_I2C_PCA9543_ADDR_LEN 0 +#define CFG_I2C_PCA9543_ENABLE_CH0 0x01 /* Enable channel 0. */ +/*==============================*/ +/* U-Boot general configuration */ +/*==============================*/ +#undef CONFIG_USE_IRQ /* No IRQ/FIQ in U-Boot */ +#define CONFIG_MISC_INIT_R +#undef CONFIG_BOOTDELAY +#define CONFIG_BOOTFILE "uImage" /* Boot file name */ +#define CFG_PROMPT "U-Boot > " /* Monitor Command Prompt */ +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +/* Print buffer size */ +#define CFG_PBSIZE (CFG_CBSIZE + sizeof(CFG_PROMPT) + 16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ +#define CFG_LOAD_ADDR 0x80700000 /* Default Linux kernel + * load address. */ +#define CONFIG_VERSION_VARIABLE +#define CONFIG_AUTO_COMPLETE /* Won't work with hush so far, + * may be later */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING +#define CFG_LONGHELP +#define CONFIG_CRC32_VERIFY +#define CONFIG_MX_CYCLIC +/* + * Define this to load an Integrity kernel. + * +#define CONFIG_CMD_ELF + */ + +/*===================*/ +/* Linux Information */ +/*===================*/ +#define LINUX_BOOT_PARAM_ADDR 0x80000100 +#define CONFIG_CMDLINE_TAG +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_BOOTARGS \ + "mem=56M console=ttyS0,115200n8 root=/dev/hda1 rw noinitrd ip=dhcp" +#define CONFIG_BOOTCOMMAND "setenv setboot setenv bootargs \\$(bootargs) video=dm64xxfb:output=\\$(videostd);run setboot" + +/*=================*/ +/* U-Boot commands */ +/*=================*/ +#include <config_cmd_default.h> +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_I2C +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#define CONFIG_CMD_SAVES +#define CONFIG_CMD_NAND +#define CONFIG_CMD_EEPROM +#undef CONFIG_CMD_BDI +#undef CONFIG_CMD_FPGA +#undef CONFIG_CMD_SETGETDCR +#undef CONFIG_CMD_FLASH +#undef CONFIG_CMD_IMLS +/*=======================*/ +/* KGDB support (if any) */ +/*=======================*/ +#ifdef CONFIG_CMD_KGDB +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif +#endif /* __CONFIG_H */

3 5

[U-Boot-Users] PCI stopped working on MPC8343
by Andre Schwarz 08 Jul '08

08 Jul '08

Last week my PCI bus has been running fine showing all devices. Right now no devices are shown on the bus. I'm using CONFIG_83XX_GENERIC_PCI with common setup code for PCI. Nothing changed from my side during the last 2 weeks. Did I miss any changes in u-boot ? regards, Andre Schwarz Matrix Vision MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

8 18

[U-Boot-Users] [PATCH] Changes ADS5121 splash screen from hard-coded bmp to flash bmp
by Martha Marx 07 Jul '08

07 Jul '08

Signed-off-by: Martha Marx <mmarx(a)silicontkx.com> --- board/ads5121/Makefile | 1 - board/ads5121/ads5121_diu.c | 66 +++++++++++++++++++++++++++++++---- board/freescale/common/fsl_diu_fb.c | 6 +++- include/configs/ads5121.h | 2 + 4 files changed, 66 insertions(+), 9 deletions(-) diff --git a/board/ads5121/Makefile b/board/ads5121/Makefile index f4dacce..0e4de61 100644 --- a/board/ads5121/Makefile +++ b/board/ads5121/Makefile @@ -30,7 +30,6 @@ LIB = $(obj)lib$(BOARD).a COBJS-y := $(BOARD).o COBJS-${CONFIG_FSL_DIU_FB} += ads5121_diu.o COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_diu_fb.o -COBJS-${CONFIG_FSL_DIU_FB} += ../freescale/common/fsl_logo_bmp.o COBJS-$(CONFIG_PCI) += pci.o COBJS := $(COBJS-y) diff --git a/board/ads5121/ads5121_diu.c b/board/ads5121/ads5121_diu.c index 87cf0cb..a57d505 100644 --- a/board/ads5121/ads5121_diu.c +++ b/board/ads5121/ads5121_diu.c @@ -26,6 +26,7 @@ #include <common.h> #include <command.h> #include <asm/io.h> +#include <malloc.h> #ifdef CONFIG_FSL_DIU_FB @@ -61,16 +62,67 @@ void diu_set_pixel_clock(unsigned int pixclock) debug("DIU: Modified value of CLKDVDR = 0x%08x\n", *clkdvdr); } +char *valid_bmp(char *addr) +{ + unsigned long h_addr; + + h_addr = simple_strtoul(addr, NULL, 16); + if (h_addr < CFG_FLASH_BASE || + h_addr >= (CFG_FLASH_BASE + CFG_FLASH_SIZE - 1)) { + printf("bmp addr %x is not a valid flash address\n", h_addr); + return 0; + } else if ((*(char *)(h_addr) != 'B') || (*(char *)(h_addr+1) != 'M')) { + printf("bmp addr is not a bmp\n"); + return 0; + } else + return (char *)h_addr; +} + int ads5121_diu_init(void) { + int gamma_fix; unsigned int pixel_format; - - xres = 1024; - yres = 768; - pixel_format = 0x88883316; - - return fsl_diu_init(xres, pixel_format, 0, - (unsigned char *)FSL_Logo_BMP); + char *bmp_env, *bmp, *monitor_port; + unsigned char *dest; + long bmp_sz; + + debug("ads5121_diu_init\n"); + bmp_env = getenv("bmp_addr"); + if (bmp_env == NULL) { + debug("Environment Variable bmp_addr is not set \n"); + bmp = 0; + } else { + bmp = valid_bmp(bmp_env); + } + if (bmp) { + bmp_sz = (bmp[5] << 24) | (bmp[4] << 16) | + (bmp[3] << 8) | bmp[2]; + debug("bmp_sz = %u\n", bmp_sz); + if (bmp_sz > CFG_SPLASH_SIZE) { + printf("BMP exceeds size limit of %d\n", + CFG_SPLASH_SIZE); + bmp = 0; + } else { + dest = malloc(bmp_sz); + (void)memcpy((void *)dest, bmp, bmp_sz); + } + } + monitor_port = getenv("monitor_port"); + if (!strncmp(monitor_port, "LCD", 3)) { + debug("LCD Monitor port\n"); + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + gamma_fix = 1; + } else { + debug("DVI Monitor port\n"); + xres = 1024; + yres = 768; + pixel_format = 0x88883316; + gamma_fix = 0; + } + return fsl_diu_init(xres, pixel_format, gamma_fix, + (unsigned char *)bmp); } int ads5121diu_init_show_bmp(cmd_tbl_t *cmdtp, diff --git a/board/freescale/common/fsl_diu_fb.c b/board/freescale/common/fsl_diu_fb.c index 75f782e..a3bee17 100644 --- a/board/freescale/common/fsl_diu_fb.c +++ b/board/freescale/common/fsl_diu_fb.c @@ -301,11 +301,15 @@ int fsl_diu_init(int xres, debug("Fix gamma table\n"); gamma_table_base = gamma.paddr; for (i = 0; i < 256*3; i++) { +#ifdef CONFIG_ADS5121 + gamma_table_base[i] = ((gamma_table_base[i] % 4) << 6) + | (gamma_table_base[i] >> 2); +#else gamma_table_base[i] = (gamma_table_base[i] << 2) | ((gamma_table_base[i] >> 6) & 0x03); +#endif } } - debug("update-lcdc: HW - %p\n Disabling DIU\n", hw); /* Program DIU registers */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 21374e9..ae98359 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -45,6 +45,7 @@ */ #define CONFIG_E300 1 /* E300 Family */ #define CONFIG_MPC512X 1 /* MPC512X family */ +#define CONFIG_ADS5121 1 /* ADS5121 board */ #define CONFIG_FSL_DIU_FB 1 /* FSL DIU */ /* video */ @@ -222,6 +223,7 @@ #define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256 kB for Mon */ #ifdef CONFIG_FSL_DIU_FB #define CFG_MALLOC_LEN (6 * 1024 * 1024) /* Reserved for malloc */ +#define CFG_SPLASH_SIZE (2 * 1024 * 1024) #else #define CFG_MALLOC_LEN (512 * 1024) #endif -- 1.5.2.4

3 2

[U-Boot-Users] [PATCH] Feed the watchdog in u-boot for 8610 board.
by Jason Jin 07 Jul '08

07 Jul '08

The watchdog on 8610 board is enabled by setting sw[6] to on. Once enabled, the watchdog can not be disabled by software. So feed the dog in u-boot is necessary for normal operation. Signed-off-by: Jason Jin <Jason.jin(a)freescale.com> --- cpu/mpc86xx/cpu.c | 14 ++++++++++++++ cpu/mpc86xx/interrupts.c | 1 + include/asm-ppc/immap_86xx.h | 14 +++++++++++++- include/configs/MPC8610HPCD.h | 3 ++- 4 files changed, 30 insertions(+), 2 deletions(-) diff --git a/cpu/mpc86xx/cpu.c b/cpu/mpc86xx/cpu.c index bf4e651..6dd0655 100644 --- a/cpu/mpc86xx/cpu.c +++ b/cpu/mpc86xx/cpu.c @@ -213,6 +213,20 @@ get_tbclk(void) void watchdog_reset(void) { + +#if defined(CONFIG_MPC8610) +/*This actually feed the hard enabled watchdog*/ + volatile immap_t *immap = (immap_t *)CFG_IMMR; + volatile ccsr_wdt_t *wdt = &immap->im_wdt; + volatile ccsr_gur_t *gur = &immap->im_gur; + u32 tmp = gur->pordevsr; + + if(tmp & 0x4000) { + wdt->swsrr = 0x556c; + wdt->swsrr = 0xaa39; + } +#endif + } #endif /* CONFIG_WATCHDOG */ diff --git a/cpu/mpc86xx/interrupts.c b/cpu/mpc86xx/interrupts.c index d9f634f..f16744b 100644 --- a/cpu/mpc86xx/interrupts.c +++ b/cpu/mpc86xx/interrupts.c @@ -36,6 +36,7 @@ #include <command.h> #include <asm/processor.h> #include <ppc_asm.tmpl> +#include <watchdog.h> unsigned long decrementer_count; /* count value for 1e6/HZ microseconds */ unsigned long timestamp; diff --git a/include/asm-ppc/immap_86xx.h b/include/asm-ppc/immap_86xx.h index 7526061..93a4eb7 100644 --- a/include/asm-ppc/immap_86xx.h +++ b/include/asm-ppc/immap_86xx.h @@ -1304,9 +1304,19 @@ typedef struct ccsr_gur { uint lynxdcr1; /* 0xe0f08 - Lynx debug control register 1*/ int res14[6]; uint ddrioovcr; /* 0xe0f24 - DDR IO Overdrive Control register */ - char res15[61656]; + char res15[216]; } ccsr_gur_t; +/*Watchdog register block(0xe_4000-0xe_4fff)*/ +typedef struct ccsr_wdt { + uint res0; + uint swcrr; /* System watchdog control register */ + uint swcnr; /* System watchdog count register */ + char res1[2]; + ushort swsrr; /* System watchdog service register */ + char res2[4080]; +}ccsr_wdt_t; + typedef struct immap { ccsr_local_mcm_t im_local_mcm; ccsr_ddr_t im_ddr1; @@ -1330,6 +1340,8 @@ typedef struct immap { char res5[389120]; ccsr_rio_t im_rio; ccsr_gur_t im_gur; + char res6[12288]; + ccsr_wdt_t im_wdt; } immap_t; extern immap_t *immr; diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 53d6955..4d61a61 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -486,7 +486,8 @@ #endif -#undef CONFIG_WATCHDOG /* watchdog disabled */ +#define CONFIG_WATCHDOG /* watchdog enabled */ +#define CFG_WATCHDOG_FREQ 5000 /*Feed interval, 5s*/ /*DIU Configuration*/ #define DIU_CONNECT_TO_DVI /* DIU controller connects to DVI encoder*/ -- 1.5.2

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[U-Boot-Users] [PATCH] Remove duplicate code introduced by commit 597f6c26a18b389903a64692bacbf9a1ca69355b
by Hugo Villeneuve 07 Jul '08

07 Jul '08

Remove duplicate code introduced by commit 597f6c26a18b389903a64692bacbf9a1ca69355b Signed-off-by: Hugo Villeneuve <hugo.villeneuve(a)lyrtech.com> --- common/main.c | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-) diff --git a/common/main.c b/common/main.c index a17b60b..046da6f 100644 --- a/common/main.c +++ b/common/main.c @@ -940,12 +940,6 @@ int readline_into_buffer (const char *const prompt, char * buffer) int rc; static int initted = 0; - if (!initted) { - hist_init(); - initted = 1; - } - - /* * History uses a global array which is not * writable until after relocation to RAM.

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[U-Boot-Users] [PATCH 1/2] fsl_elbc_nand: workaround for hangs during nand write
by Scott Wood 07 Jul '08

07 Jul '08

From: Anton Vorontsov <avorontsov(a)ru.mvista.com> Using current driver elbc sometimes hangs during nand write. Reading back last byte helps though (thanks to Scott Wood for the idea). Signed-off-by: Anton Vorontsov <avorontsov(a)ru.mvista.com> Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- drivers/mtd/nand/fsl_elbc_nand.c | 11 ++++++++++- 1 files changed, 10 insertions(+), 1 deletions(-) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c index c1644c0..ab3e0fd 100644 --- a/drivers/mtd/nand/fsl_elbc_nand.c +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -489,7 +489,7 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) struct fsl_elbc_ctrl *ctrl = priv->ctrl; unsigned int bufsize = mtd->writesize + mtd->oobsize; - if (len < 0) { + if (len <= 0) { printf("write_buf of %d bytes", len); ctrl->status = 0; return; @@ -503,6 +503,15 @@ static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) } memcpy_toio(&ctrl->addr[ctrl->index], buf, len); + /* + * This is workaround for the weird elbc hangs during nand write, + * Scott Wood says: "...perhaps difference in how long it takes a + * write to make it through the localbus compared to a write to IMMR + * is causing problems, and sync isn't helping for some reason." + * Reading back the last byte helps though. + */ + in_8(&ctrl->addr[ctrl->index] + len - 1); + ctrl->index += len; } -- 1.5.3

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[U-Boot-Users] [PATCH] Fix lwmon5 dsp POST sequence.
by sascha.laue＠liebherr.com 07 Jul '08

07 Jul '08

From: Sascha Laue <sascha.laue(a)liebherr.com> Signed-off-by: Sascha Laue <sascha.laue(a)liebherr.com> --- post/board/lwmon5/dsp.c | 21 +++++++++++++++++++-- 1 files changed, 19 insertions(+), 2 deletions(-) diff --git a/post/board/lwmon5/dsp.c b/post/board/lwmon5/dsp.c index a96ac7d..bc12e42 100644 --- a/post/board/lwmon5/dsp.c +++ b/post/board/lwmon5/dsp.c @@ -33,20 +33,37 @@ DECLARE_GLOBAL_DATA_PTR; -#define DSP_STATUS_REG 0xC4000008 +#define DSP_STATUS_REG 0xC4000008 +#define FPGA_STATUS_REG 0xC400000C int dsp_post_test(int flags) { + uint old_value; uint read_value; int ret; + + /* momorize fpga status */ + old_value = in_be32((void *)FPGA_STATUS_REG); + /* enable outputs */ + out_be32((void *)FPGA_STATUS_REG, 0x30); + + /* generate sync signal */ + out_be32((void *)DSP_STATUS_REG, 0x300); + udelay(5); + out_be32((void *)DSP_STATUS_REG, 0); + udelay(500); + /* read status */ ret = 0; read_value = in_be32((void *)DSP_STATUS_REG) & 0x3; - if (read_value != 0x3) { + if (!(read_value & 0x3)) { post_log("\nDSP status read %08X\n", read_value); ret = 1; } + /* restore fpga status */ + out_be32((void *)FPGA_STATUS_REG, old_value); + return ret; } -- 1.5.2.4

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