May 2008 - U-Boot

[U-Boot-Users] [PATCH 2/4] PPC: Change lib_ppc/bat_rw.c to use high bats
by becky.bruce＠freescale.com 08 May '08

08 May '08

From: Becky Bruce <becky.bruce(a)freescale.com> Currently, this code only deals with BATs 0-3, which makes it useless on systems that support BATs 4-7. Add the support for these registers. Signed-off-by: Becky Bruce <Becky.bruce(a)freescale.com> --- include/asm-ppc/mmu.h | 4 ++ lib_ppc/bat_rw.c | 134 ++++++++++++++++++++++++++++++++++--------------- 2 files changed, 97 insertions(+), 41 deletions(-) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index 49d6860..f836270 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -141,6 +141,10 @@ extern void _tlbia(void); /* invalidate all TLB entries */ typedef enum { IBAT0 = 0, IBAT1, IBAT2, IBAT3, DBAT0, DBAT1, DBAT2, DBAT3 +#ifdef CONFIG_HIGH_BATS + , IBAT4, IBAT5, IBAT6, IBAT7, + DBAT4, DBAT5, DBAT6, DBAT7 +#endif } ppc_bat_t; extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c index 912efa7..6288164 100644 --- a/lib_ppc/bat_rw.c +++ b/lib_ppc/bat_rw.c @@ -28,47 +28,73 @@ int write_bat (ppc_bat_t bat, unsigned long upper, unsigned long lower) { - switch (bat) { + switch(bat) { + case DBAT0: + mtspr (DBAT0L, lower); + mtspr (DBAT0U, upper); + break; case IBAT0: mtspr (IBAT0L, lower); mtspr (IBAT0U, upper); break; - + case DBAT1: + mtspr (DBAT1L, lower); + mtspr (DBAT1U, upper); + break; case IBAT1: mtspr (IBAT1L, lower); mtspr (IBAT1U, upper); break; - + case DBAT2: + mtspr (DBAT2L, lower); + mtspr (DBAT2U, upper); + break; case IBAT2: mtspr (IBAT2L, lower); mtspr (IBAT2U, upper); break; - + case DBAT3: + mtspr (DBAT3L, lower); + mtspr (DBAT3U, upper); + break; case IBAT3: mtspr (IBAT3L, lower); mtspr (IBAT3U, upper); break; - - case DBAT0: - mtspr (DBAT0L, lower); - mtspr (DBAT0U, upper); +#ifdef CONFIG_HIGH_BATS + case DBAT4: + mtspr (DBAT4L, lower); + mtspr (DBAT3U, upper); break; - - case DBAT1: - mtspr (DBAT1L, lower); - mtspr (DBAT1U, upper); + case IBAT4: + mtspr (IBAT4L, lower); + mtspr (IBAT4U, upper); break; - - case DBAT2: - mtspr (DBAT2L, lower); - mtspr (DBAT2U, upper); + case DBAT5: + mtspr (DBAT5L, lower); + mtspr (DBAT5U, upper); break; - - case DBAT3: - mtspr (DBAT3L, lower); - mtspr (DBAT3U, upper); + case IBAT5: + mtspr (IBAT5L, lower); + mtspr (IBAT5U, upper); break; - + case DBAT6: + mtspr (DBAT6L, lower); + mtspr (DBAT6U, upper); + break; + case IBAT6: + mtspr (IBAT6L, lower); + mtspr (IBAT6U, upper); + break; + case DBAT7: + mtspr (DBAT7L, lower); + mtspr (DBAT7U, upper); + break; + case IBAT7: + mtspr (IBAT7L, lower); + mtspr (IBAT7U, upper); + break; +#endif default: return (-1); } @@ -82,46 +108,72 @@ int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) unsigned long register l; switch (bat) { + case DBAT0: + l = mfspr (DBAT0L); + u = mfspr (DBAT0U); + break; case IBAT0: l = mfspr (IBAT0L); u = mfspr (IBAT0U); break; - + case DBAT1: + l = mfspr (DBAT1L); + u = mfspr (DBAT1U); + break; case IBAT1: l = mfspr (IBAT1L); u = mfspr (IBAT1U); break; - + case DBAT2: + l = mfspr (DBAT2L); + u = mfspr (DBAT2U); + break; case IBAT2: l = mfspr (IBAT2L); u = mfspr (IBAT2U); break; - + case DBAT3: + l = mfspr (DBAT3L); + u = mfspr (DBAT3U); + break; case IBAT3: l = mfspr (IBAT3L); u = mfspr (IBAT3U); break; - - case DBAT0: - l = mfspr (DBAT0L); - u = mfspr (DBAT0U); +#ifdef CONFIG_HIGH_BATS + case DBAT4: + l = mfspr (DBAT4L); + u = mfspr (DBAT4U); break; - - case DBAT1: - l = mfspr (DBAT1L); - u = mfspr (DBAT1U); + case IBAT4: + l = mfspr (IBAT4L); + u = mfspr (IBAT4U); break; - - case DBAT2: - l = mfspr (DBAT2L); - u = mfspr (DBAT2U); + case DBAT5: + l = mfspr (DBAT5L); + u = mfspr (DBAT5U); break; - - case DBAT3: - l = mfspr (DBAT3L); - u = mfspr (DBAT3U); + case IBAT5: + l = mfspr (IBAT5L); + u = mfspr (IBAT5U); break; - + case DBAT6: + l = mfspr (DBAT6L); + u = mfspr (DBAT6U); + break; + case IBAT6: + l = mfspr (IBAT6L); + u = mfspr (IBAT6U); + break; + case DBAT7: + l = mfspr (DBAT7L); + u = mfspr (DBAT7U); + break; + case IBAT7: + l = mfspr (IBAT7L); + u = mfspr (IBAT7U); + break; +#endif default: return (-1); } -- 1.5.4.1

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[U-Boot-Users] [PATCH 1/4] PPC: Create and use CONFIG_HIGH_BATS
by becky.bruce＠freescale.com 08 May '08

08 May '08

From: Becky Bruce <becky.bruce(a)freescale.com> Change all code that conditionally operates on high bat registers (that is, BATs 4-7) to look at CONFIG_HIGH_BATS instead of the myriad ways this is done now. Define the option for every config for which high bats are supported (and enabled by early boot, on parts where they're not always enabled) Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- cpu/74xx_7xx/start.S | 6 +++--- cpu/mpc83xx/start.S | 6 +++--- include/configs/Alaska8220.h | 2 ++ include/configs/BC3450.h | 2 ++ include/configs/CPCI750.h | 2 ++ include/configs/IceCube.h | 2 ++ include/configs/MPC8313ERDB.h | 2 ++ include/configs/MPC8315ERDB.h | 1 + include/configs/MPC8323ERDB.h | 1 + include/configs/MPC832XEMDS.h | 2 ++ include/configs/MPC8349EMDS.h | 1 + include/configs/MPC8349ITX.h | 1 + include/configs/MPC8360EMDS.h | 2 ++ include/configs/MPC8360ERDK.h | 2 ++ include/configs/MPC837XEMDS.h | 1 + include/configs/MPC837XERDB.h | 2 ++ include/configs/MPC8610HPCD.h | 1 + include/configs/MPC8641HPCN.h | 1 + include/configs/PM520.h | 2 ++ include/configs/TB5200.h | 2 ++ include/configs/TOP5200.h | 2 ++ include/configs/TQM5200.h | 2 ++ include/configs/TQM834x.h | 2 ++ include/configs/Total5200.h | 2 ++ include/configs/Yukon8220.h | 2 ++ include/configs/ads5121.h | 2 ++ include/configs/aev.h | 2 ++ include/configs/canmb.h | 2 ++ include/configs/cm5200.h | 2 ++ include/configs/cpci5200.h | 2 ++ include/configs/hmi1001.h | 2 ++ include/configs/inka4x0.h | 2 ++ include/configs/jupiter.h | 2 ++ include/configs/mcc200.h | 2 ++ include/configs/mecp5200.h | 2 ++ include/configs/motionpro.h | 1 + include/configs/mpc7448hpc2.h | 2 +- include/configs/munices.h | 1 + include/configs/o2dnt.h | 2 ++ include/configs/p3mx.h | 1 + include/configs/pf5200.h | 1 + include/configs/sbc8349.h | 2 ++ include/configs/smmaco4.h | 2 ++ include/configs/sorcery.h | 2 ++ include/configs/spieval.h | 2 ++ include/configs/uc101.h | 2 ++ include/configs/v38b.h | 2 ++ 47 files changed, 84 insertions(+), 7 deletions(-) diff --git a/cpu/74xx_7xx/start.S b/cpu/74xx_7xx/start.S index b5834b9..42b0f72 100644 --- a/cpu/74xx_7xx/start.S +++ b/cpu/74xx_7xx/start.S @@ -316,7 +316,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -327,7 +327,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -414,7 +414,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#ifdef CONFIG_750FX +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l diff --git a/cpu/mpc83xx/start.S b/cpu/mpc83xx/start.S index 309eb30..c182174 100644 --- a/cpu/mpc83xx/start.S +++ b/cpu/mpc83xx/start.S @@ -557,7 +557,7 @@ invalidate_bats: mtspr IBAT1U, r0 mtspr IBAT2U, r0 mtspr IBAT3U, r0 -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr IBAT4U, r0 mtspr IBAT5U, r0 mtspr IBAT6U, r0 @@ -568,7 +568,7 @@ invalidate_bats: mtspr DBAT1U, r0 mtspr DBAT2U, r0 mtspr DBAT3U, r0 -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS mtspr DBAT4U, r0 mtspr DBAT5U, r0 mtspr DBAT6U, r0 @@ -655,7 +655,7 @@ setup_bats: mtspr DBAT3U, r3 isync -#if (CFG_HID2 & HID2_HBE) +#ifdef CONFIG_HIGH_BATS /* IBAT 4 */ addis r4, r0, CFG_IBAT4L@h ori r4, r4, CFG_IBAT4L@l diff --git a/include/configs/Alaska8220.h b/include/configs/Alaska8220.h index 3f2f614..38b962f 100644 --- a/include/configs/Alaska8220.h +++ b/include/configs/Alaska8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_ALASKA8220 1 /* ... on Alaska board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/BC3450.h b/include/configs/BC3450.h index 706c13e..b7574bf 100644 --- a/include/configs/BC3450.h +++ b/include/configs/BC3450.h @@ -61,6 +61,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/CPCI750.h b/include/configs/CPCI750.h index 48e29a2..89edbde 100644 --- a/include/configs/CPCI750.h +++ b/include/configs/CPCI750.h @@ -61,6 +61,8 @@ #undef CONFIG_ECC /* enable ECC support */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* which initialization functions to call for this board */ #define CONFIG_MISC_INIT_R #define CONFIG_BOARD_PRE_INIT diff --git a/include/configs/IceCube.h b/include/configs/IceCube.h index 38a0226..ebd5f0d 100644 --- a/include/configs/IceCube.h +++ b/include/configs/IceCube.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6eec240..482120d 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -466,6 +466,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8315ERDB.h b/include/configs/MPC8315ERDB.h index e0a887c..7a5d0aa 100644 --- a/include/configs/MPC8315ERDB.h +++ b/include/configs/MPC8315ERDB.h @@ -453,6 +453,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 32f57ac..977c041 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -468,6 +468,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index ddefa5e..dd0f256 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -483,6 +483,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 364ffac..20eec67 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -616,6 +616,7 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8349ITX.h b/include/configs/MPC8349ITX.h index be8850a..b78fc9f 100644 --- a/include/configs/MPC8349ITX.h +++ b/include/configs/MPC8349ITX.h @@ -555,6 +555,7 @@ boards, we say we have two, but don't display a message if we find only one. */ #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index 983575e..fcfbe6f 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -515,6 +515,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index a4f6af6..fe0173b 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -419,6 +419,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index e92493a..4e159a0 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -502,6 +502,7 @@ /* * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE diff --git a/include/configs/MPC837XERDB.h b/include/configs/MPC837XERDB.h index f7e6fd2..29c2490 100644 --- a/include/configs/MPC837XERDB.h +++ b/include/configs/MPC837XERDB.h @@ -524,6 +524,8 @@ * MMU Setup */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR: cache cacheable */ #define CFG_SDRAM_LOWER CFG_SDRAM_BASE #define CFG_SDRAM_UPPER (CFG_SDRAM_BASE + 0x10000000) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 585411c..a14bd30 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -55,6 +55,7 @@ #define CONFIG_NUM_DDR_CONTROLLERS 1 #define CONFIG_INTERRUPTS /* enable pci, srio, ddr interrupts */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported & enabled */ #define CONFIG_ALTIVEC 1 /* diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index a8d0077..6ff4f92 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -67,6 +67,7 @@ #define BANK_INTERLEAVING 0x22000000 #define SUPER_BANK_INTERLEAVING 0x23000000 +#define CONFIG_HIGH_BATS 1 /* High BATs supported and enabled */ #define CONFIG_ALTIVEC 1 diff --git a/include/configs/PM520.h b/include/configs/PM520.h index ad480a6..ce882e2 100644 --- a/include/configs/PM520.h +++ b/include/configs/PM520.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TB5200.h b/include/configs/TB5200.h index 6cb3022..d21783b 100644 --- a/include/configs/TB5200.h +++ b/include/configs/TB5200.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TOP5200.h b/include/configs/TOP5200.h index 1affcfd..086be90 100644 --- a/include/configs/TOP5200.h +++ b/include/configs/TOP5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM5200.h b/include/configs/TQM5200.h index bff2edf..bfb478a 100644 --- a/include/configs/TQM5200.h +++ b/include/configs/TQM5200.h @@ -47,6 +47,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index 02a16ac..7eb2d19 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -423,6 +423,8 @@ extern int tqm834x_num_flash_banks; #define CFG_HID0_FINAL CFG_HID0_INIT #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR 0 - 512M */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/Total5200.h b/include/configs/Total5200.h index 2507d77..94299b5 100644 --- a/include/configs/Total5200.h +++ b/include/configs/Total5200.h @@ -48,6 +48,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/Yukon8220.h b/include/configs/Yukon8220.h index 00c4ff0..1b4195a 100644 --- a/include/configs/Yukon8220.h +++ b/include/configs/Yukon8220.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_YUKON8220 1 /* ... on Yukon board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 30Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 30000000/* ... running at 30MHz */ diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index 81e7c1e..f8fadef 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -357,6 +357,8 @@ #define CFG_HID0_FINAL HID0_ENABLE_MACHINE_CHECK #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Internal Definitions * diff --git a/include/configs/aev.h b/include/configs/aev.h index e3f810c..c5e4759 100644 --- a/include/configs/aev.h +++ b/include/configs/aev.h @@ -41,6 +41,8 @@ #define CONFIG_AEVFIFO 1 #define CFG_MPC5XXX_CLKIN 33000000 /* ... running at 33.000000MHz */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ diff --git a/include/configs/canmb.h b/include/configs/canmb.h index 440972c..2465cda 100644 --- a/include/configs/canmb.h +++ b/include/configs/canmb.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/cm5200.h b/include/configs/cm5200.h index d554348..ef50c7c 100644 --- a/include/configs/cm5200.h +++ b/include/configs/cm5200.h @@ -31,6 +31,8 @@ #define CONFIG_MPC5200 1 /* (more precisely an MPC5200 CPU) */ #define CONFIG_CM5200 1 /* ... on CM5200 platform */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Supported commands */ diff --git a/include/configs/cpci5200.h b/include/configs/cpci5200.h index 1b30e51..fffd1fe 100644 --- a/include/configs/cpci5200.h +++ b/include/configs/cpci5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/hmi1001.h b/include/configs/hmi1001.h index e5a8897..ad7cf76 100644 --- a/include/configs/hmi1001.h +++ b/include/configs/hmi1001.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/inka4x0.h b/include/configs/inka4x0.h index c89f041..6ec92c3 100644 --- a/include/configs/inka4x0.h +++ b/include/configs/inka4x0.h @@ -40,6 +40,8 @@ #define CONFIG_MISC_INIT_F 1 /* Use misc_init_f() */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/jupiter.h b/include/configs/jupiter.h index 0ac3e7e..050feca 100644 --- a/include/configs/jupiter.h +++ b/include/configs/jupiter.h @@ -41,6 +41,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/mcc200.h b/include/configs/mcc200.h index a9c86f9..e4c3f72 100644 --- a/include/configs/mcc200.h +++ b/include/configs/mcc200.h @@ -40,6 +40,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration * diff --git a/include/configs/mecp5200.h b/include/configs/mecp5200.h index 49919fb..ccac069 100644 --- a/include/configs/mecp5200.h +++ b/include/configs/mecp5200.h @@ -50,6 +50,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/motionpro.h b/include/configs/motionpro.h index 1503598..b6843af 100644 --- a/include/configs/motionpro.h +++ b/include/configs/motionpro.h @@ -35,6 +35,7 @@ #define CONFIG_MPC5200 1 /* More exactly a MPC5200 */ #define CONFIG_MOTIONPRO 1 /* ... on Promess Motion-PRO board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * BOOTP options diff --git a/include/configs/mpc7448hpc2.h b/include/configs/mpc7448hpc2.h index f614e67..a218f75 100644 --- a/include/configs/mpc7448hpc2.h +++ b/include/configs/mpc7448hpc2.h @@ -39,7 +39,7 @@ #define CONFIG_MPC7448HPC2 #define CONFIG_74xx -#define CONFIG_750FX /* this option to enable init of extended BATs */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CONFIG_ALTIVEC /* undef to disable */ #define CFG_BOARD_NAME "MPC7448 HPC II" diff --git a/include/configs/munices.h b/include/configs/munices.h index 38b27bb..e0046ec 100644 --- a/include/configs/munices.h +++ b/include/configs/munices.h @@ -35,6 +35,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ #define CFG_CACHELINE_SIZE 32 /* For MPC5xxx CPUs */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Command line configuration. diff --git a/include/configs/o2dnt.h b/include/configs/o2dnt.h index 8dde1ef..88bdb03 100644 --- a/include/configs/o2dnt.h +++ b/include/configs/o2dnt.h @@ -37,6 +37,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index 45dc343..77f54d2 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -42,6 +42,7 @@ #if defined (CONFIG_P3M750) #define CONFIG_750FX /* 750GL/GX/FX */ +#define CONFIG_HIGH_BATS /* High BATs supported */ #define CFG_BOARD_NAME "P3M750" #define CFG_BUS_HZ 100000000 #define CFG_BUS_CLK CFG_BUS_HZ diff --git a/include/configs/pf5200.h b/include/configs/pf5200.h index 2ce39c9..c065d33 100644 --- a/include/configs/pf5200.h +++ b/include/configs/pf5200.h @@ -49,6 +49,7 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ /* * Serial console configuration */ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 0ebc674..7481556 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -570,6 +570,8 @@ #define CFG_HID2 HID2_HBE +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* DDR @ 0x00000000 */ #define CFG_IBAT0L (CFG_SDRAM_BASE | BATL_PP_10 | BATL_MEMCOHERENCE) #define CFG_IBAT0U (CFG_SDRAM_BASE | BATU_BL_256M | BATU_VS | BATU_VP) diff --git a/include/configs/smmaco4.h b/include/configs/smmaco4.h index 4578cae..3e47eb8 100644 --- a/include/configs/smmaco4.h +++ b/include/configs/smmaco4.h @@ -42,6 +42,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/sorcery.h b/include/configs/sorcery.h index b622a30..09b1af7 100644 --- a/include/configs/sorcery.h +++ b/include/configs/sorcery.h @@ -31,6 +31,8 @@ #define CONFIG_MPC8220 1 #define CONFIG_SORCERY 1 /* Sorcery board */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* Input clock running at 60Mhz, read Hid1 for the CPU multiplier to determine the CPU speed. */ #define CFG_MPC8220_CLKIN 60000000 /* ... running at 60MHz */ diff --git a/include/configs/spieval.h b/include/configs/spieval.h index 49213dc..69d2d67 100644 --- a/include/configs/spieval.h +++ b/include/configs/spieval.h @@ -44,6 +44,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/uc101.h b/include/configs/uc101.h index dc1d7e1..042750e 100644 --- a/include/configs/uc101.h +++ b/include/configs/uc101.h @@ -40,6 +40,8 @@ #define CONFIG_BOARD_EARLY_INIT_R +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ diff --git a/include/configs/v38b.h b/include/configs/v38b.h index e24d6f7..c203522 100644 --- a/include/configs/v38b.h +++ b/include/configs/v38b.h @@ -46,6 +46,8 @@ #define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ #define BOOTFLAG_WARM 0x02 /* Software reboot */ +#define CONFIG_HIGH_BATS 1 /* High BATs supported */ + /* * Serial console configuration */ -- 1.5.4.1

1 0

Re: [U-Boot-Users] drivers MMCplus for at91sam9x
by Ken.Fuchs＠bench.com 08 May '08

08 May '08

I posted the following patch under a different subject line: Re: [U-Boot-Users] [PATCH] Add eSDHC driver > > --- u-boot_at91sam9260_mmc.patch (AT91 MCI driver) --- Pierre Savary wrote: > Thanks for that... but it's my own patch ;) > > Pierre =========================================================== Pierre, I hope you like this patch better. :) The following MMC v4 patch is for u-boot-1.1.5_atmel_1.2. To the AT91SAM9261 MCI device driver it adds support for MMC v4.x chips (MoviNAND in particular). The u-boot_at91sam9260_mmc.patch, previously send to this thread 23 April 2008 must be applied to u-boot-1.1.5_atmel_1.2, prior to applying the patch below. The patch includes lines "/* Ignore */". These are simply place holders for code that was not relevant to the MCI driver or MMC code. The patch is actually of four individual source files. Please let me know of any serious problems applying the patch. It should apply cleanly, but I didn't verify this. The MCI MMC v4 features contained in this patch work perfectly on our AT91SAM9261 board, except that I never got MMC 4 bit bus working (that code is omitted from this patch). Anyone know why the AT91SAM9261-EK doesn't appear to support 4 bit MMC? This patch may not work on AT91SAM9261-EK, since we modified the AT91SAM9261-EK board definitions rather than creating a new configuration and files for our board. Sincerely, Ken Fuchs u-boot-at91sam9261-mmc-v4.patch =============================== svn diff -r21 cpu/arm926ejs/at91sam926x/atmel_mci.c Index: cpu/arm926ejs/at91sam926x/atmel_mci.c =================================================================== --- cpu/arm926ejs/at91sam926x/atmel_mci.c (revision 21) +++ cpu/arm926ejs/at91sam926x/atmel_mci.c (working copy) @@ -1,4 +1,8 @@ /* + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added MMC v4.x (MoviNAND) support + * * Copyright (C) 2004-2006 Atmel Corporation * * See file CREDITS for list of people who contributed to this @@ -34,21 +38,43 @@ #include <asm/arch/hardware.h> //klk #include "atmel_mci.h" -#undef DEBUG + +/* Ignore */ +/* Ignore */ +/* Ignore */ + +#if 0 +#define DEBUG +#else /* 0 */ +#undef DEBUG /* kf - was #undef */ +#endif /* 0 */ + #ifdef DEBUG #define pr_debug(fmt, args...) printf(fmt, ##args) #else #define pr_debug(...) do { } while(0) #endif +#undef CFG_MMC_CLK_OD +#define CFG_MMC_CLK_OD 375000 + #ifndef CFG_MMC_CLK_OD #define CFG_MMC_CLK_OD 375000 #endif +#undef CFG_MMC_CLK_PP +#define CFG_MMC_CLK_PP 20000000 + #ifndef CFG_MMC_CLK_PP #define CFG_MMC_CLK_PP 20000000 #endif +#undef CFG_MMC_OP_COND +#define CFG_MMC_OP_COND 0x80ff8000 +/* 0x80ff8080 works with 30+ sec. power off req */ +/* 0x00800000 works better, but write forever? */ +/* 0x00100000 works with 30+ sec. power off req */ + #ifndef CFG_MMC_OP_COND #define CFG_MMC_OP_COND 0x00100000 #endif @@ -74,8 +100,13 @@ bus_hz = AT91C_MASTER_CLOCK; clkdiv = (bus_hz / hz) / 2 - 1; +#if 1 + printf("mmc: setting clock %lu Hz, block size %lu\n", + hz, blklen); +#else /* 1 */ pr_debug("mmc: setting clock %lu Hz, block size %lu\n", hz, blklen); +#endif /* 1 */ if (clkdiv & ~255UL) { clkdiv = 255; @@ -84,10 +115,17 @@ } blklen &= 0xfffc; + +#if 1 /* AT91SAM9261 does not have RDPROOF and WRPROOF fields. */ mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) + | MMCI_BF(BLKLEN, blklen))); +#else /* 1 */ + mmci_writel(MR, (MMCI_BF(CLKDIV, clkdiv) | MMCI_BF(BLKLEN, blklen) | MMCI_BIT(RDPROOF) | MMCI_BIT(WRPROOF))); +#endif /* 1 */ + } #define RESP_NO_CRC 1 @@ -99,6 +137,7 @@ #define NCR MMCI_BF(MAXLAT, 1) #define TRCMD_START MMCI_BF(TRCMD, 1) #define TRDIR_READ MMCI_BF(TRDIR, 1) +#define TRDIR_WRITE MMCI_BF(TRDIR, 0) #define TRTYP_BLOCK MMCI_BF(TRTYP, 0) #define INIT_CMD MMCI_BF(SPCMD, 1) #define OPEN_DRAIN MMCI_BF(OPDCMD, 1) @@ -109,6 +148,20 @@ | MMCI_BIT(RINDE) \ | MMCI_BIT(RTOE)) +#if 0 +#define DEBUG +#else /* 0 */ +#undef DEBUG /* kf - was #undef */ +#endif /* 0 */ + +#undef pr_debug + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + static int mmc_cmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) @@ -117,7 +170,9 @@ int i, response_words = 0; unsigned long error_flags; u32 status; - +#if 1 + pr_debug("mmc_cmd: entry\n"); +#endif /* 1 */ AT91F_MMC_Hardware_Init(); pr_debug("mmc: CMD%lu 0x%lx (flags 0x%lx)\n", @@ -161,12 +216,28 @@ return 0; } +#if 0 +#define DEBUG +#else /* 0 */ +#undef DEBUG /* kf - was #undef */ +#endif /* 0 */ + +#undef pr_debug + +#ifdef DEBUG +#define pr_debug(fmt, args...) printf(fmt, ##args) +#else +#define pr_debug(...) do { } while(0) +#endif + static int mmc_acmd(unsigned long cmd, unsigned long arg, void *resp, unsigned long flags) { unsigned long aresp[4]; int ret; + pr_debug("mmc_acmd: entry\n"); + /* * Seems like the APP_CMD part of an ACMD has 64 cycles max * latency even though the ACMD part doesn't. This isn't @@ -184,7 +255,16 @@ return ret; } -static unsigned long +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + +unsigned long mmc_bread(int dev, unsigned long start, lbaint_t blkcnt, unsigned long *buffer) { @@ -193,7 +273,14 @@ unsigned long card_status, data; unsigned long wordcount; u32 status; + unsigned long *bufaddr; + pr_debug("mmc_bread: entry\n"); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", ret, card_status); + + bufaddr = buffer; + if (blkcnt == 0) return 0; @@ -202,10 +289,16 @@ /* Put the device into Transfer state */ ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", + ret, card_status); if (ret) goto fail; /* Set block length */ ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", + ret, card_status); if (ret) goto fail; pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); @@ -228,7 +321,6 @@ if (status & MMCI_BIT(RXRDY)) { data = mmci_readl(RDR); - /* pr_debug("%x\n", data); */ *buffer++ = data; wordcount++; } @@ -240,12 +332,68 @@ status = mmci_readl(SR); } while (!(status & MMCI_BIT(BLKE))); - putc('.'); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", + ret, card_status); + + if (i % 0x800 == 0x7ff) { + putc('.'); /* Display '.', after each MB xfer'ed */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + } + +#if 0 + buffer = bufaddr; + wordcount = 0; + do { + if (wordcount % 8 == 0) { + pr_debug("\n%06lx:", 4 * wordcount); + } + pr_debug(" %08lx", *buffer++); + wordcount++; + } while (4 * wordcount < mmc_blkdev.blksz); + pr_debug("\n"); +#endif /* 0 */ + } out: /* Put the device back into Standby state */ mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("mmc: bread ret = %d, card status = %08x\n", ret, card_status); + if (i >= 0x7ff) { + putc('\n'); + } return i; fail: @@ -254,8 +402,329 @@ goto out; } +unsigned long +mmc_bwrite(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + u32 status; + unsigned long *bufaddr; + + pr_debug("mmc_bwrite: entry\n"); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("en mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + + bufaddr = buffer; + + if (blkcnt == 0) + return 0; + + pr_debug("mmc_bwrite: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("sc mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("bl mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + + for (i = 0; i < blkcnt; i++, start++) { + ret = mmc_cmd(MMC_CMD_WRITE_BLOCK, + start * mmc_blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_WRITE + | TRTYP_BLOCK)); + if (ret) goto fail; + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(SR); + if (status & (ERROR_FLAGS | MMCI_BIT(UNRE))) + goto fail; + } while (!(status & MMCI_BIT(TXRDY))); + + if (status & MMCI_BIT(TXRDY)) { + data = *buffer++; + mmci_writel(TDR, data); + wordcount++; + } + } while(wordcount < (mmc_blkdev.blksz / 4)); + + pr_debug("mmc: write %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(BLKE))); + + do { + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + if ((card_status & 0x00000100) != 0x00000100) { +#if 0 + printf("lp mmc: bwrite ret = %d, ", ret); + printf("card status = %08x\n", card_status); +#endif /* 0 */ + } else { + pr_debug("lp mmc: bwrite ret = %d, ", ret); + pr_debug("card status = %08x\n", card_status); + } + } while ((card_status & 0x00000100) != 0x00000100); + + if (i % 0x800 == 0x7ff) { + putc('.'); /* Display '.', after each MB xfer'ed */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + } + +#if 0 + ret = mmc_cmd(MMC_CMD_STOP_TRANSMISSION, + 0, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + pr_debug("st mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; +#endif /* 0 */ + + } + +out: +#if 0 + ret = mmc_cmd(MMC_CMD_STOP_TRANSMISSION, + 0, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("st mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; +#endif /* 0 */ + + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("dc mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + if (i >= 0x7ff) { + putc('\n'); + } + return i; + +fail: + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("fa mmc: bwrite ret = %d, card status = %08x\n", + ret, card_status); + goto out; +} + + /* Hangs - did not attempt to debug */ +/* MMC Multiple Block Write - mmc_mbwrite() */ +unsigned long +mmc_mbwrite(int dev, unsigned long start, lbaint_t blkcnt, + unsigned long *buffer) +{ + int ret, i = 0; + unsigned long resp[4]; + unsigned long card_status, data; + unsigned long wordcount; + u32 status; + unsigned long *bufaddr; + + pr_debug("mmc_bwrite: entry\n"); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("en mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + + bufaddr = buffer; + + if (blkcnt == 0) + return 0; + + if (blkcnt > 0xffff) { /* Exceeds length supported by MoviNAND. */ + return -1; + } + + pr_debug("mmc_mbwrite: dev %d, start %lx, blkcnt %lx\n", + dev, start, blkcnt); + + /* Put the device into Transfer state */ + ret = mmc_cmd(MMC_CMD_SELECT_CARD, mmc_rca << 16, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("sc mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + /* Set block length */ + ret = mmc_cmd(MMC_CMD_SET_BLOCKLEN, mmc_blkdev.blksz, resp, R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("bl mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + pr_debug("MCI_DTOR = %08lx\n", mmci_readl(DTOR)); + + ret = mmc_cmd(MMC_CMD_SET_BLOCK_COUNT, + blkcnt, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("bc mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; + + ret = mmc_cmd(MMC_CMD_WRITE_MULTIPLE_BLOCK, + start * mmc_blkdev.blksz, resp, + (R1 | NCR | TRCMD_START | TRDIR_WRITE | TRTYP_BLOCK)); + if (ret) goto fail; + + for (i = 0; i < blkcnt; i++, start++) { + + ret = -EIO; + wordcount = 0; + do { + do { + status = mmci_readl(SR); + if (status & (ERROR_FLAGS | MMCI_BIT(UNRE))) + goto fail; + } while (!(status & MMCI_BIT(TXRDY))); + + if (status & MMCI_BIT(TXRDY)) { + data = *buffer++; + mmci_writel(TDR, data); + wordcount++; + } + } while(wordcount < (mmc_blkdev.blksz / 4)); + +#if 1 + pr_debug("mmc: write %u words, waiting for BLKE\n", wordcount); + + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(BLKE))); +#endif /* 0 */ + + do { + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, + &card_status, R1 | NCR); + if ((card_status & 0x00000100) != 0x00000100) { +#if 0 + printf("lp mmc: mbwrite ret = %d, ", ret); + printf("card status = %08x\n", card_status); +#endif /* 0 */ + } else { + pr_debug("lp mmc: mbwrite ret = %d, ", ret); + pr_debug("card status = %08x\n", card_status); + } + } while ((card_status & 0x00000100) != 0x00000100); + + if (i % 0x800 == 0x7ff) { + putc('.'); /* Display '.', after each MB xfer'ed */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + } + } + +out: +#if 0 + ret = mmc_cmd(MMC_CMD_STOP_TRANSMISSION, + 0, resp, + R1 | NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("st mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (ret) goto fail; +#endif /* 0 */ + + /* Put the device back into Standby state */ + mmc_cmd(MMC_CMD_SELECT_CARD, 0, resp, NCR); + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("dc mmc: mbwrite ret = %d, card status = %08x\n", + ret, card_status); + if (i >= 0x7ff) { + putc('\n'); + } + return i; + +fail: + mmc_cmd(MMC_CMD_SEND_STATUS, mmc_rca << 16, &card_status, R1 | NCR); + pr_debug("fa mmc: mbwrite failed, card status = %08x\n", card_status); + goto out; +} + static void mmc_parse_cid(struct mmc_cid *cid, unsigned long *resp) { + pr_debug("mmc_parse_cid: entry\n"); + cid->mid = resp[0] >> 24; cid->oid = (resp[0] >> 8) & 0xffff; cid->pnm[0] = resp[0]; @@ -272,6 +741,8 @@ static void sd_parse_cid(struct mmc_cid *cid, unsigned long *resp) { + pr_debug("sd_parse_cid: entry\n"); + cid->mid = resp[0] >> 24; cid->oid = (resp[0] >> 8) & 0xffff; cid->pnm[0] = resp[0]; @@ -288,6 +759,8 @@ static void mmc_dump_cid(const struct mmc_cid *cid) { + pr_debug("mmc_dump_cid: entry\n"); + printf("Manufacturer ID: %02lX\n", cid->mid); printf("OEM/Application ID: %04lX\n", cid->oid); printf("Product name: %s\n", cid->pnm); @@ -301,6 +774,9 @@ static void mmc_dump_csd(const struct mmc_csd *csd) { unsigned long *csd_raw = (unsigned long *)csd; + + pr_debug("mmc_dump_csd: entry\n"); + pr_debug("CSD data: %08lx %08lx %08lx %08lx\n", csd_raw[0], csd_raw[1], csd_raw[2], csd_raw[3]); pr_debug("CSD structure version: 1.%u\n", csd->csd_structure); @@ -337,6 +813,8 @@ { int ret; + pr_debug("mmc_idle_cards: entry\n"); + /* Reset and initialize all cards */ ret = mmc_cmd(MMC_CMD_GO_IDLE_STATE, 0, NULL, 0); @@ -352,6 +830,8 @@ unsigned long resp[4]; int i, ret = 0; + pr_debug("sd_init_card: entry\n"); + mmc_idle_cards(); for (i = 0; i < 1000; i++) { ret = mmc_acmd(MMC_ACMD_SD_SEND_OP_COND, CFG_MMC_OP_COND, @@ -387,10 +867,40 @@ { unsigned long resp[4]; int i, ret = 0; + u32 status; + pr_debug("mmc_init_card: entry\n"); + mmc_idle_cards(); + /* MoviNAND initialization */ for (i = 0; i < 1000; i++) { + mmci_writel(ARGR, 0xFFFFFFFF); + mmci_writel(CMDR, 0x0018113F); + do { + status = mmci_readl(SR); + } while (!(status & MMCI_BIT(CMDRDY))); + } + /* Getting the OCR value seems to prevent marginal chips from */ + /* working at all, whereas they would work fine after waiting */ + /* a full minute or more with the power off prior to booting. */ + /* Our marginal chips have date codes 0716 and 0728. */ +#if 0 + for (i = 0; i < 1000; i++) { + /* Request OCR value to determine chip's supported volt. */ + ret = mmc_cmd(MMC_CMD_SEND_OP_COND, 0, resp, + R3 | NID | OPEN_DRAIN); + if (ret || (resp[0] & 0x80000000)) + { + break; + } + ret = -ETIMEDOUT; + } + if (ret) { + return ret; + } +#endif /* 0 */ + for (i = 0; i < 1000; i++) { ret = mmc_cmd(MMC_CMD_SEND_OP_COND, CFG_MMC_OP_COND, resp, R3 | NID | OPEN_DRAIN); if (ret || (resp[0] & 0x80000000)) @@ -399,13 +909,35 @@ } ret = -ETIMEDOUT; } + pr_debug("Step 4: ret = 0x%lx\n", ret); + pr_debug("MMC_CMD_SEND_OP_COND = 0x%lx\n", MMC_CMD_SEND_OP_COND); + pr_debug("CFG_MMC_OP_COND = 0x%lx\n", CFG_MMC_OP_COND); + pr_debug("resp[0] = 0x%lx\n", resp[0]); + pr_debug("resp[1] = 0x%lx\n", resp[1]); + pr_debug("resp[2] = 0x%lx\n", resp[2]); + pr_debug("resp[3] = 0x%lx\n", resp[3]); + pr_debug("R3 = 0x%lx\n", R3); + pr_debug("NID = 0x%lx\n", NID); + pr_debug("OPEN_DRAIN = 0x%lx\n", OPEN_DRAIN); + pr_debug("4\n"); pr_debug("ret : %i\n",ret); + + pr_debug("MCI_MR = 0x%08lx\n", mmci_readl(MR)); + pr_debug("MCI_DTOR = 0x%08lx\n", mmci_readl(DTOR)); + pr_debug("MCI_SDCR = 0x%08lx\n", mmci_readl(SDCR)); + pr_debug("MCI_ARGR = 0x%08lx\n", mmci_readl(ARGR)); + /* RSPR */ + /* RDR */ + pr_debug("MCI_SR = 0x%08lx\n", mmci_readl(SR)); + pr_debug("MCI_IMR = 0x%08lx\n", mmci_readl(IMR)); + if (ret) return ret; pr_debug("5\n"); /* Get CID of all cards. FIXME: Support more than one card */ ret = mmc_cmd(MMC_CMD_ALL_SEND_CID, 0, resp, R2 | NID | OPEN_DRAIN); + pr_debug("ALL_SEND_CID ret: 0x%08lx\n", ret); if (ret) return ret; mmc_parse_cid(cid, resp); @@ -415,6 +947,7 @@ /* Set Relative Address of the card that responded */ ret = mmc_cmd(MMC_CMD_SET_RELATIVE_ADDR, mmc_rca << 16, resp, R1 | NCR | OPEN_DRAIN); + pr_debug("SET_RELATIVE_ADDR ret: 0x%08lx\n", ret); return ret; } @@ -471,23 +1004,42 @@ dtocyc << shift, dtor); } +#define DEFAULT_SECTOR_SIZE 512 + int mmc_init(int verbose) { struct mmc_cid cid; struct mmc_csd csd; unsigned int max_blksz; int ret,aux; + unsigned char buffer[DEFAULT_SECTOR_SIZE]; + pr_debug("mmc_init: entry\n"); + pr_debug("mmc_init: verbose = 0x%08lx\n", verbose); + AT91F_MMC_Hardware_Init(); pr_debug("0\n"); /* Initialize controller */ mmci_writel(CR, MMCI_BIT(SWRST)); mmci_writel(CR, MMCI_BIT(MCIEN)); + + pr_debug("MCI_MR = 0x%08lx\n", mmci_readl(MR)); + pr_debug("MCI_DTOR = 0x%08lx\n", mmci_readl(DTOR)); + pr_debug("MCI_SDCR = 0x%08lx\n", mmci_readl(SDCR)); + pr_debug("MCI_ARGR = 0x%08lx\n", mmci_readl(ARGR)); + /* RSPR */ + /* RDR */ + pr_debug("MCI_SR = 0x%08lx\n", mmci_readl(SR)); + pr_debug("MCI_IMR = 0x%08lx\n", mmci_readl(IMR)); + mmci_writel(DTOR, 0x5f); mmci_writel(IDR, ~0UL); mmci_writel(SDCR, 0x1); mci_set_mode(CFG_MMC_CLK_OD, MMC_DEFAULT_BLKLEN); +#if 0 + mmci_writel(MR, 0x02009B4A); +#endif /* 0 */ /* //mmci_writel(CR, MMCI_BIT(SWRST)); mmci_writel(CR, 0x00000001); mmci_writel(DTOR, 0x0000007F); @@ -502,6 +1054,7 @@ ret = sd_init_card(&cid, verbose); if (ret) { + pr_debug("Not SDCard, try MMC\n"); mmc_rca = MMC_DEFAULT_RCA; ret = mmc_init_card(&cid, verbose); } @@ -545,6 +1098,20 @@ mci_set_mode(CFG_MMC_CLK_PP, mmc_blkdev.blksz); #if 0 + mmc_bread(mmc_blkdev.dev, 1024, 1, (ulong *)buffer); + buffer[0] = 0x00; buffer[1] = 0x11; + buffer[2] = 0x22; buffer[3] = 0x33; + buffer[4] = 0x44; buffer[5] = 0x55; + buffer[6] = 0x66; buffer[7] = 0x77; + buffer[504] = 0x88; buffer[505] = 0x99; + buffer[506] = 0xaa; buffer[507] = 0xbb; + buffer[508] = 0xcc; buffer[509] = 0xdd; + buffer[510] = 0xee; buffer[511] = 0xff; + mmc_bwrite(mmc_blkdev.dev, 1024, 1, (ulong *)buffer); + mmc_bread(mmc_blkdev.dev, 1024, 1, (ulong *)buffer); +#endif /* 0 */ + +#if 0 if (fat_register_device(&mmc_blkdev, 1)) pr_debug("Could not register MMC fat device\n"); #else @@ -556,16 +1123,22 @@ int mmc_read(ulong src, uchar *dst, int size) { + pr_debug("mmc_read: entry\n"); + return -ENOSYS; } int mmc_write(uchar *src, ulong dst, int size) { + pr_debug("mmc_write: entry\n"); + return -ENOSYS; } int mmc2info(ulong addr) { + pr_debug("mmc2info: entry\n"); + return 0; } svn diff -r21 include/asm-arm/arch-at91sam926x/mmc.h Index: include/asm-arm/arch-at91sam926x/mmc.h =================================================================== --- include/asm-arm/arch-at91sam926x/mmc.h (revision 0) +++ include/asm-arm/arch-at91sam926x/mmc.h (revision 50) @@ -0,0 +1,103 @@ +/* + * (C) Copyright 2007 + * Benchmark Electronics, Inc. + * Added MMC v4.x (MoviNAND) support + * + * Copyright (C) 2004-2006 Atmel Corporation + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#ifndef __ASM_AT91SAM926X_MMC_H +#define __ASM_AT91SAM926X_MMC_H + +struct mmc_cid { + unsigned long psn; + unsigned short oid; + unsigned char mid; + unsigned char prv; + unsigned char mdt; + char pnm[7]; +}; + +struct mmc_csd +{ + u8 csd_structure:2, + spec_vers:4, + rsvd1:2; + u8 taac; + u8 nsac; + u8 tran_speed; + u16 ccc:12, + read_bl_len:4; + u64 read_bl_partial:1, + write_blk_misalign:1, + read_blk_misalign:1, + dsr_imp:1, + rsvd2:2, + c_size:12, + vdd_r_curr_min:3, + vdd_r_curr_max:3, + vdd_w_curr_min:3, + vdd_w_curr_max:3, + c_size_mult:3, + sector_size:5, + erase_grp_size:5, + wp_grp_size:5, + wp_grp_enable:1, + default_ecc:2, + r2w_factor:3, + write_bl_len:4, + write_bl_partial:1, + rsvd3:5; + u8 file_format_grp:1, + copy:1, + perm_write_protect:1, + tmp_write_protect:1, + file_format:2, + ecc:2; + u8 crc:7; + u8 one:1; +}; + +/* MMC Command numbers */ +#define MMC_CMD_GO_IDLE_STATE 0 +#define MMC_CMD_SEND_OP_COND 1 +#define MMC_CMD_ALL_SEND_CID 2 +#define MMC_CMD_SET_RELATIVE_ADDR 3 +#define MMC_CMD_SD_SEND_RELATIVE_ADDR 3 +#define MMC_CMD_SET_DSR 4 +#define MMC_CMD_SELECT_CARD 7 +#define MMC_CMD_SEND_CSD 9 +#define MMC_CMD_SEND_CID 10 +#define MMC_CMD_STOP_TRANSMISSION 12 +#define MMC_CMD_SEND_STATUS 13 +#define MMC_CMD_SET_BLOCKLEN 16 +#define MMC_CMD_READ_SINGLE_BLOCK 17 +#define MMC_CMD_READ_MULTIPLE_BLOCK 18 +#define MMC_CMD_SET_BLOCK_COUNT 23 +#define MMC_CMD_WRITE_BLOCK 24 +#define MMC_CMD_WRITE_MULTIPLE_BLOCK 25 +#define MMC_CMD_APP_CMD 55 + +#define MMC_ACMD_SD_SEND_OP_COND 41 + +#define R1_ILLEGAL_COMMAND (1 << 22) +#define R1_APP_CMD (1 << 5) + +#endif /* __ASM_AT91SAM926X_MMC_H */ svn diff -r21 include/configs/at91sam9261ek.h Index: include/configs/at91sam9261ek.h =================================================================== --- include/configs/at91sam9261ek.h (revision 21) +++ include/configs/at91sam9261ek.h (working copy) @@ -1,4 +1,8 @@ /* + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added MMC v4.x (MoviNAND) support + * * (C) Copyright 2005 * M. Amine SAYA ATMEL Rousset, France. * @@ -95,18 +99,24 @@ /* SPI */ #define CONFIG_SPI +/* kf - define hush (from busy box) command line interface & options */ +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#define CFG_AUTO_COMPLETE +#define CONFIG_CMDLINE_EDITING + #define CONFIG_COMMANDS \ ((CONFIG_CMD_DFL | \ CFG_CMD_NET | \ CFG_CMD_ENV | \ CFG_CMD_USB | \ CFG_CMD_FLASH | \ - CFG_CMD_NAND | \ + CFG_CMD_MMC | \ + CFG_CMD_EXT2 | \ + CFG_CMD_FAT | \ CFG_CMD_AUTOSCRIPT | \ - CFG_CMD_FAT | \ CFG_CMD_NFS | \ CFG_CMD_SPI | \ - CFG_CMD_U | \ CFG_CMD_IMI | \ CFG_CMD_PING ) & \ ~(CFG_CMD_BDI | \ @@ -296,8 +306,12 @@ #define CFG_FLASH_ERASE_TOUT (2*CFG_HZ) /* Timeout for Flash Erase */ #define CFG_FLASH_WRITE_TOUT (2*CFG_HZ) /* Timeout for Flash Write */ +#undef CFG_ENV_IS_IN_FLASH #define CFG_ENV_IS_IN_DATAFLASH 1 -#undef CFG_ENV_IS_IN_FLASH +#if 0 +#undef CFG_ENV_IS_IN_NAND +#endif /* 0 - kf */ +#undef CFG_ENV_IS_NOWHERE #ifdef CFG_ENV_IS_IN_DATAFLASH #define CFG_ENV_OFFSET 0x4000 @@ -305,6 +319,10 @@ #define CFG_ENV_SIZE 0x4000 /* 0x8000 */ #endif +#ifdef CFG_ENV_IS_NOWHERE +#define CFG_ENV_SIZE 0x4000 +#endif + #ifdef CFG_ENV_IS_IN_FLASH #ifdef CONFIG_BOOTBINFUNC #define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x60000) /* after u-boot.bin */ @@ -316,6 +334,9 @@ #endif /* Add LCD stuff */ +/* Ignore */ +/* Ignore */ + #if 0 /* No LCD */ #define CONFIG_LCD /* #undef CONFIG_LCD_LOGO */ @@ -333,8 +354,21 @@ #define CONFIG_DOS_PARTITION 1 #define LITTLEENDIAN 1 -#define CFG_LOAD_ADDR 0x23f00000 /* default load address */ +/* Add FAT filesystem configuration, other than CFG_CMD_FAT */ +#define CONFIG_SUPPORT_VFAT +/* MMC */ +#define CONFIG_MMC 1 +#define MMCI_BASE 0xFFFA8000 /* (void *)AT91C_BASE_MCI */ +/* MMC - kf - slow down speed for debug from 20000000 Hz down to ... */ +/* However, tweaking this value here causes all code to be compiled, */ +/* so we shall change the value only where needed - in atmel_mci.c. */ +#define CFG_MMC_CLK_PP 20000000 + +#define CFG_LOAD_ADDR 0x23f00000 /* default load address */ + +#define CFG_BOOTM_LEN 0x02100000 /* 33MB uncompressed max. */ + #ifdef CONFIG_BOOTBINFUNC #define CFG_BOOT_SIZE 0x00 /* 0 KBytes */ #define CFG_U_BOOT_BASE PHYS_FLASH_1 svn diff -r21 board/at91sam9261ek/at91sam9261ek.c Index: board/at91sam9261ek/at91sam9261ek.c =================================================================== --- board/at91sam9261ek/at91sam9261ek.c (revision 21) +++ board/at91sam9261ek/at91sam9261ek.c (working copy) @@ -1,4 +1,8 @@ /* + * (C) Copyright 2007-2008 + * Benchmark Electronics, Inc. + * Added specific AT91SAM9261 board support + * * (C) Copyright 2005 * M. Amine SAYA ATMEL Rousset, France. * Added AT91SAM9261EK support. @@ -28,12 +32,19 @@ #include <common.h> #include <asm/arch/hardware.h> +#include <asm/arch-at91sam926x/at91sam9261.h> #include <net.h> extern void AT91F_Spi1Init (void); extern void gpio_init(void); +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + /* ------------------------------------------------------------------------ - */ /* * Miscelaneous platform dependent initialisations @@ -107,7 +118,8 @@ *AT91C_PMC_PCER |= 1 << AT91C_ID_US0; /* enable clock */ #endif -#ifdef CONFIG_USART1 +#if 1 + /* #ifdef CONFIG_USART1 */ *AT91C_PIOB_PDR = AT91C_PC12_TXD1 | AT91C_PC13_RXD1; *AT91C_PMC_PCER |= 1 << AT91C_ID_US1; /* enable clock */ #endif @@ -118,6 +130,41 @@ #endif } +#ifdef CONFIG_MMC +#if (CONFIG_COMMANDS & CFG_CMD_MMC) +int AT91F_MMC_Hardware_Init(void) +{ +#if 0 + printf("AT91F_MMC_Hardware_Init: entry\n"); +#endif /* 0 */ + + AT91F_PIO_CfgPeriph(AT91C_BASE_PIOA, + 0, /* <- Peripheral A */ + (AT91C_PA0_MCDA0 | /* MMC NAND MCDA0 */ + AT91C_PA1_MCCDA | /* MMC NAND MCCDA */ + AT91C_PA2_MCCK | /* MMC NAND MCCK */ + AT91C_PA4_MCDA1 | /* MMC NAND MCDA1 */ + AT91C_PA5_MCDA2 | /* MMC NAND MCDA2 */ + AT91C_PA6_MCDA3 | /* MMC NAND MCDA3 */ + 0)); /* <- Peripheral B */ + +#if 1 + /* Pull up disable register */ + AT91C_BASE_PIOA->PIO_PPUDR |= + AT91C_PA0_MCDA0 | /* MMC NAND MCDA0 */ + AT91C_PA1_MCCDA | /* MMC NAND MCCDA */ + AT91C_PA2_MCCK | /* MMC NAND MCCK */ + AT91C_PA4_MCDA1 | /* MMC NAND MCDA1 */ + AT91C_PA5_MCDA2 | /* MMC NAND MCDA2 */ + AT91C_PA6_MCDA3; /* MMC NAND MCDA3 */ +#endif /* 0 */ + + AT91C_BASE_PMC->PMC_PCER = (1 << AT91C_ID_MCI); +} +#endif /* CONFIG_COMMANDS & CFG_CMD_MMC */ +#endif /* CONFIG_MMC */ + + int dram_init (void) { DECLARE_GLOBAL_DATA_PTR; @@ -148,5 +195,35 @@ gpio_init(); +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ +/* Ignore */ + return 0; }

6 8

[U-Boot-Users] [Patch 2/4] U-Boot-V2: ARM: introduce CONFIG_SKIP_RELOCATION
by Menon, Nishanth 08 May '08

08 May '08

Introduce CONFIG_SKIP_RELOCATION as alternative define. This may be desired in some conditions where U-Boot is downloaded directly into SRAM during NAND/Peripheral download mode and is not expected to be relocated. This patch also organizes SKIP_LOWLEVEL_INIT and SKIP_RELOCATION in a common arm feature dependent section. Signed-off-by: Nishanth Menon <x0nishan(a)ti.com> Index: u-boot-v2.git/arch/arm/cpu/start-arm.S =================================================================== --- u-boot-v2.git.orig/arch/arm/cpu/start-arm.S 2008-05-05 09:35:00.000000000 -0500 +++ u-boot-v2.git/arch/arm/cpu/start-arm.S 2008-05-05 09:35:05.000000000 -0500 @@ -160,6 +160,10 @@ bl board_init_lowlevel #endif + /* + * In some circumstances, we may choose not to relocate u-boot + */ +#ifndef CONFIG_SKIP_RELOCATION relocate: /* relocate U-Boot to RAM */ adr r0, _start /* r0 <- current position of code */ ldr r1, _TEXT_BASE /* test if we run from flash or RAM */ @@ -176,6 +180,7 @@ stmia r1!, {r3-r10} /* copy to target address [r1] */ cmp r0, r2 /* until source end addreee [r2] */ ble copy_loop +#endif /* Set up the stack */ stack_setup: Index: u-boot-v2.git/arch/arm/Kconfig =================================================================== --- u-boot-v2.git.orig/arch/arm/Kconfig 2008-05-05 09:34:44.000000000 -0500 +++ u-boot-v2.git/arch/arm/Kconfig 2008-05-05 09:35:25.000000000 -0500 @@ -74,6 +74,7 @@ bool select ARM926EJS + choice prompt "Select your board" @@ -140,7 +141,7 @@ The i.MX SoCs have a Pin which can output different reference frequencies. Say y here if you want to have the clko command which lets you select the frequency to output on this pin. - + source arch/arm/mach-netx/Kconfig menu "Arm specific settings " @@ -164,6 +165,27 @@ If you want to start a 2.6 kernel and use an initrd image say y here. +menu "Boot Features" + +config SKIP_LOWLEVEL_INIT + bool + default n + depends on ARM + prompt "Skip lowlevel init" + help + This entry skips the SDRAM initialising on many ARM based boards. + It enables using U-boot as a second stage bootloader. + +config SKIP_RELOCATION + bool + default n + depends on ARM + prompt "Skip U-Boot Relocation" + help + This entry skips the relocation logic on certain platforms + It enables using U-boot as a second stage bootloader. +endmenu + endmenu source common/Kconfig Index: u-boot-v2.git/common/Kconfig =================================================================== --- u-boot-v2.git.orig/common/Kconfig 2008-05-05 09:34:44.000000000 -0500 +++ u-boot-v2.git/common/Kconfig 2008-05-05 09:35:05.000000000 -0500 @@ -216,14 +216,6 @@ help Enable build of u-boot with -g. -config SKIP_LOWLEVEL_INIT - bool - depends on ARM - prompt "Skip lowlevel init" - help - This entry skips the SDRAM initialising on many ARM based boards. - It enables using U-boot as a second stage bootloader. - config ENABLE_FLASH_NOISE bool prompt "verbose flash handling"

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[U-Boot-Users] nand [read|write][.jffs2|.e|.i|.oob] ...
by Mark Craske 08 May '08

08 May '08

The 'nand read.oob' and 'nand write.oob' commands exist in U-Boot 1.3.2, but do not appear in 'help nand' output. Is this an oversight or intentional? Also the .e and .i options to 'nand read' and 'nand write' do not appear in 'help nand' output. Again, is this intentional? Looking at the source code in command/cmd_nand.c both those options seem to be treated identically to .jffs2. Have I misunderstood? Regards, Mark Craske

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[U-Boot-Users] ARM: interrupts using in standalone application
by L.Wegener 08 May '08

08 May '08

Hello, will nested interrupts be managed by u-boot or µP-core? If not how? Thanks for your help!

3 2

[U-Boot-Users] [PATCH 3/3] ppc4xx: Add fdt support to all remaining AMCC PPC4xx eval boards
by Stefan Roese 08 May '08

08 May '08

This patch adds fdt (flattened device tree) support to all remaining AMCC eval boards. Most newer boards already support device tree. With this patch, all AMCC boards now enable device tree passing from U-Boot to Linux arch/powerpc kernels. Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/bamboo.h | 6 ++++++ include/configs/bubinga.h | 5 +++++ include/configs/ebony.h | 6 ++++++ include/configs/katmai.h | 2 +- include/configs/luan.h | 5 +++++ include/configs/ocotea.h | 5 +++++ include/configs/taihu.h | 5 +++++ include/configs/taishan.h | 5 +++++ include/configs/walnut.h | 6 ++++++ include/configs/yosemite.h | 13 ++++--------- include/configs/yucca.h | 4 ++++ 11 files changed, 52 insertions(+), 10 deletions(-) diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index 4ea040b..2f0df8a 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -291,6 +291,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_HAS_ETH0 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0 /* PHY address, See schematics */ #define CONFIG_PHY1_ADDR 1 @@ -426,4 +427,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index 784e7c0..cbd74a0 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -128,6 +128,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 2 /* EMAC1 PHY address */ #define CONFIG_NET_MULTI 1 @@ -435,4 +436,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 88fd7ca..ba68fd4 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -201,6 +201,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 8 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 9 /* EMAC1 PHY address */ #define CONFIG_NET_MULTI 1 @@ -306,4 +307,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/katmai.h b/include/configs/katmai.h index d2f6b10..cce883f 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -79,7 +79,7 @@ #define CFG_ACE_BASE 0xfe000000 /* Xilinx ACE controller - Compact Flash */ #define CFG_MONITOR_BASE TEXT_BASE -#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_LEN + 1) +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) #define CFG_MALLOC_LEN (512 * 1024) /* Reserve 512 kB for malloc */ /*----------------------------------------------------------------------- diff --git a/include/configs/luan.h b/include/configs/luan.h index af237d9..37151d3 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -195,6 +195,7 @@ #define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ #define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ +#define CONFIG_HAS_ETH0 #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 1 #define CONFIG_CIS8201_PHY 1 /* Enable 'special' RGMII mode for Cicada phy */ @@ -306,4 +307,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 5a6eb4a..be2b3ec 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -330,4 +330,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/taihu.h b/include/configs/taihu.h index 7db9736..8a1ff1a 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -114,6 +114,7 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_PHY_ADDR 0x14 /* PHY address */ +#define CONFIG_HAS_ETH0 #define CONFIG_HAS_ETH1 #define CONFIG_PHY1_ADDR 0x10 /* EMAC1 PHY address */ #define CONFIG_NET_MULTI 1 @@ -433,4 +434,8 @@ unsigned char spi_read(void); #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 851a7ad..1879d38 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -331,4 +331,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index f6e99ac..adc420b 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -92,6 +92,7 @@ #define CONFIG_PHY_ADDR 1 /* PHY address */ #define CFG_RX_ETH_BUFFER 16 /* use 16 rx buffer on 405 emac */ +#define CONFIG_HAS_ETH0 1 #define CONFIG_NETCONSOLE /* include NetConsole support */ #define CONFIG_NET_MULTI /* needed for NetConsole */ @@ -346,4 +347,9 @@ #define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif + +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 3bd115a..f22e798 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -139,15 +139,6 @@ #define CFG_KBYTES_SDRAM (128 * 1024) /* 128MB */ #define CFG_SDRAM_BANKS (2) - -/*----------------------------------------------------------------------- - * Device tree support (Linux-2.6.26+) - *----------------------------------------------------------------------*/ - -/* pass open firmware flat tree */ -#define CONFIG_OF_LIBFDT 1 -#define CONFIG_OF_BOARD_SETUP 1 - /*----------------------------------------------------------------------- * I2C *----------------------------------------------------------------------*/ @@ -392,4 +383,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 1e3571e..6f9d3e3 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -541,4 +541,8 @@ /*---------------------------------------------------------------------------*/ +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ -- 1.5.5.1

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[U-Boot-Users] [PATCH 2/3] ppc4xx: Add weak default ft_board_setup() routine
by Stefan Roese 08 May '08

08 May '08

This patch adds a default ft_board_setup() routine to the 4xx fdt code. This routine is defined as weak and can be overwritten by a board specific one if needed. Signed-off-by: Stefan Roese <sr(a)denx.de> --- cpu/ppc4xx/fdt.c | 26 +++++++++++++++++++++++--- 1 files changed, 23 insertions(+), 3 deletions(-) diff --git a/cpu/ppc4xx/fdt.c b/cpu/ppc4xx/fdt.c index 02dece0..ccc73d5 100644 --- a/cpu/ppc4xx/fdt.c +++ b/cpu/ppc4xx/fdt.c @@ -1,5 +1,5 @@ /* - * (C) Copyright 2007 + * (C) Copyright 2007-2008 * Stefan Roese, DENX Software Engineering, sr(a)denx.de. * * See file CREDITS for list of people who contributed to this @@ -27,7 +27,7 @@ #include <asm/cache.h> #include <ppc4xx.h> -#if defined(CONFIG_OF_LIBFDT) +#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) #include <libfdt.h> #include <libfdt_env.h> #include <fdt_support.h> @@ -35,6 +35,26 @@ DECLARE_GLOBAL_DATA_PTR; +void __ft_board_setup(void *blob, bd_t *bd) +{ + u32 val[4]; + int rc; + + ft_cpu_setup(blob, bd); + + /* Fixup NOR mapping */ + val[0] = 0; /* chip select number */ + val[1] = 0; /* always 0 */ + val[2] = gd->bd->bi_flashstart; + val[3] = gd->bd->bi_flashsize; + rc = fdt_find_and_setprop(blob, "/plb/opb/ebc", "ranges", + val, sizeof(val), 1); + if (rc) + printf("Unable to update property NOR mapping, err=%s\n", + fdt_strerror(rc)); +} +void ft_board_setup(void *blob, bd_t *bd) __attribute__((weak, alias("__ft_board_setup"))); + /* * Fixup all PCIe nodes by setting the device_type property * to "pci-endpoint" instead is "pci" for endpoint ports. @@ -109,4 +129,4 @@ void ft_cpu_setup(void *blob, bd_t *bd) */ fdt_pcie_setup(blob); } -#endif /* CONFIG_OF_LIBFDT */ +#endif /* CONFIG_OF_LIBFDT && CONFIG_OF_BOARD_SETUP */ -- 1.5.5.1

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[U-Boot-Users] [PATCH 1/3] ppc4xx: acadia: Add fdt support and fix section overlap problem
by Stefan Roese 08 May '08

08 May '08

This patch adds fdt (flattened device tree) support to the AMCC Acadia eval board. This increases the image size and it doesn't fit anymore into 256kByte. Since we didn't want to remove features from the configuration, we decided to increase the U-Boot image size (add one flash sector). Also changed the default environment definition to make it independent of such changes. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/acadia/config.mk | 2 +- include/configs/acadia.h | 21 +++++++++++++++------ 2 files changed, 16 insertions(+), 7 deletions(-) diff --git a/board/amcc/acadia/config.mk b/board/amcc/acadia/config.mk index af5a46c..290415c 100644 --- a/board/amcc/acadia/config.mk +++ b/board/amcc/acadia/config.mk @@ -28,7 +28,7 @@ sinclude $(OBJTREE)/board/$(BOARDDIR)/config.tmp ifndef TEXT_BASE -TEXT_BASE = 0xFFFC0000 +TEXT_BASE = 0xFFF80000 endif ifeq ($(debug),1) diff --git a/include/configs/acadia.h b/include/configs/acadia.h index 3cd5ad6..bbf726d 100644 --- a/include/configs/acadia.h +++ b/include/configs/acadia.h @@ -59,16 +59,16 @@ * Base addresses -- Note these are effective addresses where the * actual resources get mapped (not physical addresses) *----------------------------------------------------------------------*/ -#define CFG_MONITOR_LEN (256 * 1024)/* Reserve 256 kB for Monitor */ -#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ - #define CFG_SDRAM_BASE 0x00000000 #define CFG_FLASH_BASE 0xfe000000 -#define CFG_MONITOR_BASE TEXT_BASE #define CFG_CPLD_BASE 0x80000000 #define CFG_NAND_ADDR 0xd0000000 #define CFG_USB_HOST 0xef603000 /* USB OHCI 1.1 controller */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MONITOR_LEN (0xFFFFFFFF - CFG_MONITOR_BASE + 1) +#define CFG_MALLOC_LEN (512 * 1024)/* Reserve 512 kB for malloc() */ + /*----------------------------------------------------------------------- * Initial RAM & stack pointer *----------------------------------------------------------------------*/ @@ -237,6 +237,7 @@ #define CONFIG_PHY_ADDR 0 /* PHY address */ #define CONFIG_NET_MULTI 1 #define CFG_RX_ETH_BUFFER 16 /* # of rx buffers & descriptors*/ +#define CONFIG_HAS_ETH0 1 #define CONFIG_NETCONSOLE /* include NetConsole support */ @@ -246,6 +247,9 @@ #undef CONFIG_BOOTARGS +#define xstr(s) str(s) +#define str(s) #s + #define CONFIG_EXTRA_ENV_SETTINGS \ "netdev=eth0\0" \ "hostname=acadia\0" \ @@ -268,8 +272,9 @@ "ramdisk_addr=fff20000\0" \ "initrd_high=30000000\0" \ "load=tftp 200000 acadia/u-boot.bin\0" \ - "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ - "cp.b ${fileaddr} fffc0000 ${filesize};" \ + "update=protect off " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "era " xstr(CFG_MONITOR_BASE) " FFFFFFFF;" \ + "cp.b ${fileaddr} " xstr(CFG_MONITOR_BASE) " ${filesize};" \ "setenv filesize;saveenv\0" \ "upd=run load update\0" \ "nload=tftp 200000 acadia/u-boot-nand.bin\0" \ @@ -501,4 +506,8 @@ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif +/* pass open firmware flat tree */ +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_OF_BOARD_SETUP 1 + #endif /* __CONFIG_H */ -- 1.5.5.1

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[U-Boot-Users] [PATCH] ppc4xx: Kilauea: Fix incorrect FPGA FIFO address
by Stefan Roese 08 May '08

08 May '08

Signed-off-by: Stefan Roese <sr(a)denx.de> --- include/configs/kilauea.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/configs/kilauea.h b/include/configs/kilauea.h index f4cf42c..57cc90a 100644 --- a/include/configs/kilauea.h +++ b/include/configs/kilauea.h @@ -490,7 +490,7 @@ * Some Kilauea stuff..., mainly fpga registers */ #define CFG_FPGA_REG_BASE CFG_FPGA_BASE -#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 11)) +#define CFG_FPGA_FIFO_BASE (in32(CFG_FPGA_BASE) | (1 << 10)) /* interrupt */ #define CFG_FPGA_SLIC0_R_DPRAM_INT 0x80000000 -- 1.5.5.1

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