May 2008 - U-Boot

[U-Boot-Users] 1.3.3-rc2 typo clean up patch
by Adrian Filipi 09 May '08

09 May '08

Hi folks, Attached is a patch for a few typos I came accross. Adrian -- Linux Software Engineer | EuroTech, Inc. | www.eurotech-inc.com

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[U-Boot-Users] [PATCH] Recognize 'powerpc' As an Alias for IH_ARCH_POWERPC
by Grant Erickson 09 May '08

09 May '08

Add support for the recognition of 'powerpc' as an alias for the PowerPC architecture type since Linux is already trending in that direction, preferring 'powerpc' to 'ppc'. Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- common/image.c | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/common/image.c b/common/image.c index 4a024d4..ecbf9d8 100644 --- a/common/image.c +++ b/common/image.c @@ -93,6 +93,7 @@ static table_entry_t uimage_arch[] = { { IH_ARCH_MIPS64, "mips64", "MIPS 64 Bit", }, { IH_ARCH_NIOS, "nios", "NIOS", }, { IH_ARCH_NIOS2, "nios2", "NIOS II", }, + { IH_ARCH_POWERPC, "powerpc", "PowerPC", }, { IH_ARCH_PPC, "ppc", "PowerPC", }, { IH_ARCH_S390, "s390", "IBM S390", }, { IH_ARCH_SH, "sh", "SuperH", }, -- 1.5.4.3

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[U-Boot-Users] [PATCH] 7450 and 86xx L2 cache invalidate bug corrections
by Wheatley Travis 09 May '08

09 May '08

The 7610 and related parts have an L2IP bit in the L2CR that is monitored to signal when the L2 cache invalidate is complete whereas the 7450 and related parts utilize L2I for this purpose. However, the current code does not account for this difference. Additionally the 86xx L2 cache invalidate code used an "andi" instruction where an "andis" instruction should have been used. This patch addresses both of these bugs. Signed-off-by: Travis Wheatley <travis.wheatley(a)freescale.com> --- cpu/74xx_7xx/cache.S | 21 ++++++++++++++++++++- cpu/mpc86xx/cache.S | 2 +- 2 files changed, 21 insertions(+), 2 deletions(-) diff --git a/cpu/74xx_7xx/cache.S b/cpu/74xx_7xx/cache.S index a793d79..db29821 100644 --- a/cpu/74xx_7xx/cache.S +++ b/cpu/74xx_7xx/cache.S @@ -329,14 +329,28 @@ _GLOBAL(dcache_status) blr /* - * Invalidate L2 cache using L2I and polling L2IP + * Invalidate L2 cache using L2I and polling L2IP or L2I */ _GLOBAL(l2cache_invalidate) sync + mfspr r3, l2cr oris r3, r3, L2CR_L2I@h sync mtspr l2cr, r3 sync + mfspr r3, PVR + sync + rlwinm r3, r3, 16,16,31 + cmpli 0,r3,0x8000 /* 7451, 7441 */ + beq 0,inv_7450 + cmpli 0,r3,0x8001 /* 7455, 7445 */ + beq 0,inv_7450 + cmpli 0,r3,0x8002 /* 7457, 7447 */ + beq 0,inv_7450 + cmpli 0,r3,0x8003 /* 7447A */ + beq 0,inv_7450 + cmpli 0,r3,0x8004 /* 7448 */ + beq 0,inv_7450 invl2: mfspr r3, l2cr andi. r3, r3, L2CR_L2IP @@ -348,6 +362,11 @@ invl2: mtspr l2cr, r3 sync blr +inv_7450: + mfspr r3, l2cr + andis. r3, r3, L2CR_L2I@h + bne inv_7450 + blr /* * Enable L2 cache diff --git a/cpu/mpc86xx/cache.S b/cpu/mpc86xx/cache.S index f316b3e..2e4ea02 100644 --- a/cpu/mpc86xx/cache.S +++ b/cpu/mpc86xx/cache.S @@ -338,7 +338,7 @@ _GLOBAL(l2cache_invalidate) invl2: mfspr r3, l2cr - andi. r3, r3, L2CR_L2I@h + andis. r3, r3, L2CR_L2I@h bne invl2 blr -- 1.5.4.5

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[U-Boot-Users] [PATCH 3/4 V2] PPC: Add print_bats() to lib_ppc/bat_rw.c
by Becky.bruce＠freescale.com 09 May '08

09 May '08

From: Becky Bruce <becky.bruce(a)freescale.com> This function prints the values of all the BAT register pairs - I needed this for debug earlier this week; adding it to lib_ppc so others can use it (and add it to reginfo commands if so desired). Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- include/asm-ppc/mmu.h | 1 + lib_ppc/bat_rw.c | 41 +++++++++++++++++++++++++++++++++++++++++ 2 files changed, 42 insertions(+), 0 deletions(-) diff --git a/include/asm-ppc/mmu.h b/include/asm-ppc/mmu.h index f836270..3af1d9c 100644 --- a/include/asm-ppc/mmu.h +++ b/include/asm-ppc/mmu.h @@ -149,6 +149,7 @@ typedef enum { extern int read_bat(ppc_bat_t bat, unsigned long *upper, unsigned long *lower); extern int write_bat(ppc_bat_t bat, unsigned long upper, unsigned long lower); +extern void print_bats(void); #endif /* __ASSEMBLY__ */ diff --git a/lib_ppc/bat_rw.c b/lib_ppc/bat_rw.c index 6288164..f317b25 100644 --- a/lib_ppc/bat_rw.c +++ b/lib_ppc/bat_rw.c @@ -183,3 +183,44 @@ int read_bat (ppc_bat_t bat, unsigned long *upper, unsigned long *lower) return (0); } + +void print_bats(void) +{ + printf("BAT registers:\n"); + + printf ("\tIBAT0L = 0x%08X ", mfspr (IBAT0L)); + printf ("\tIBAT0U = 0x%08X\n", mfspr (IBAT0U)); + printf ("\tDBAT0L = 0x%08X ", mfspr (DBAT0L)); + printf ("\tDBAT0U = 0x%08X\n", mfspr (DBAT0U)); + printf ("\tIBAT1L = 0x%08X ", mfspr (IBAT1L)); + printf ("\tIBAT1U = 0x%08X\n", mfspr (IBAT1U)); + printf ("\tDBAT1L = 0x%08X ", mfspr (DBAT1L)); + printf ("\tDBAT1U = 0x%08X\n", mfspr (DBAT1U)); + printf ("\tIBAT2L = 0x%08X ", mfspr (IBAT2L)); + printf ("\tIBAT2U = 0x%08X\n", mfspr (IBAT2U)); + printf ("\tDBAT2L = 0x%08X ", mfspr (DBAT2L)); + printf ("\tDBAT2U = 0x%08X\n", mfspr (DBAT2U)); + printf ("\tIBAT3L = 0x%08X ", mfspr (IBAT3L)); + printf ("\tIBAT3U = 0x%08X\n", mfspr (IBAT3U)); + printf ("\tDBAT3L = 0x%08X ", mfspr (DBAT3L)); + printf ("\tDBAT3U = 0x%08X\n", mfspr (DBAT3U)); + +#ifdef CONFIG_HIGH_BATS + printf ("\tIBAT4L = 0x%08X ", mfspr (IBAT4L)); + printf ("\tIBAT4U = 0x%08X\n", mfspr (IBAT4U)); + printf ("\tDBAT4L = 0x%08X ", mfspr (DBAT4L)); + printf ("\tDBAT4U = 0x%08X\n", mfspr (DBAT4U)); + printf ("\tIBAT5L = 0x%08X ", mfspr (IBAT5L)); + printf ("\tIBAT5U = 0x%08X\n", mfspr (IBAT5U)); + printf ("\tDBAT5L = 0x%08X ", mfspr (DBAT5L)); + printf ("\tDBAT5U = 0x%08X\n", mfspr (DBAT5U)); + printf ("\tIBAT6L = 0x%08X ", mfspr (IBAT6L)); + printf ("\tIBAT6U = 0x%08X\n", mfspr (IBAT6U)); + printf ("\tDBAT6L = 0x%08X ", mfspr (DBAT6L)); + printf ("\tDBAT6U = 0x%08X\n", mfspr (DBAT6U)); + printf ("\tIBAT7L = 0x%08X ", mfspr (IBAT7L)); + printf ("\tIBAT7U = 0x%08X\n", mfspr (IBAT7U)); + printf ("\tDBAT7L = 0x%08X ", mfspr (DBAT7L)); + printf ("\tDBAT7U = 0x%08X\n", mfspr (DBAT7U)); +#endif +} -- 1.5.4.1

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[U-Boot-Users] [PATCH] Remove $(VERSION_FILE) from PHONY Target List
by Grant Erickson 09 May '08

09 May '08

When building against non-local, non-disk-backed file systems (e.g. NFS, tmpfs), the u-boot build can iterate forever, attempting to re-generate "include/autoconf.mk". This occurs because $(VERSION_FILE) (aka ${ROOT}/u-boot/build/include/version_autogenerated.h) is always regarded as out-of-date because it is in the .PHONY target list, even though it's a real file and seems to need to be only created once and only once. This patch removes $(VERSION_FILE) from the .PHONY target list and has been verified to work with various flavors and builds of make-3.81 against NFS, ext2fs, ext3fs and tmpfs file systems. More detail at: http://sourceforge.net/mailarchive/message.php?msg_id=C4180895.E556%25gerick son%40nuovations.com Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- diff --git a/Makefile b/Makefile index e5b4210..50069b7 100644 --- a/Makefile +++ b/Makefile @@ -247,7 +247,7 LIBS += api/libapi.a LIBS := $(addprefix $(obj),$(LIBS)) -.PHONY : $(LIBS) $(VERSION_FILE) +.PHONY : $(LIBS) # Add GCC lib PLATFORM_LIBS += -L $(shell dirname `$(CC) $(CFLAGS) -print-libgcc-file-name`) -lgcc

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[U-Boot-Users] [PATCH] syscon3: remove redundant and unused code
by Wolfgang Denk 09 May '08

09 May '08

Remove board_early_init_r() - not used for this board. Remove ft_board_setup() - redundant as now handled by weak default routine, see commit "ppc4xx: Add weak default ft_board_setup() routine" Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- board/syscon3/syscon3.c | 35 ----------------------------------- 1 files changed, 0 insertions(+), 35 deletions(-) diff --git a/board/syscon3/syscon3.c b/board/syscon3/syscon3.c index b814bae..d4ef569 100644 --- a/board/syscon3/syscon3.c +++ b/board/syscon3/syscon3.c @@ -132,7 +132,6 @@ int misc_init_r (void) */ void local_bus_init (void) { - volatile ccsr_lbc_t *lbc = (void *)(CFG_MPC85xx_LBC_ADDR); volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); @@ -160,7 +159,6 @@ static struct pci_config_table pci_mpc85xxads_config_table[] = { }; #endif - static struct pci_controller hose = { #ifndef CONFIG_PCI_PNP config_table:pci_mpc85xxads_config_table, @@ -176,36 +174,3 @@ void pci_init_board (void) pci_mpc85xx_init (&hose); #endif /* CONFIG_PCI */ } - -#ifdef CONFIG_BOARD_EARLY_INIT_R -int board_early_init_r (void) -{ -#ifdef CONFIG_PS2MULT - ps2mult_early_init(); -#endif /* CONFIG_PS2MULT */ - return (0); -} -#endif /* CONFIG_BOARD_EARLY_INIT_R */ - -#if defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) -void -ft_board_setup(void *blob, bd_t *bd) -{ - u32 val[4]; - int rc; - - ft_cpu_setup(blob, bd); - - /* Fixup NOR mapping */ - val[0] = 0; /* chip select number */ - val[1] = 0; /* always 0 */ - val[2] = gd->bd->bi_flashstart; - val[3] = gd->bd->bi_flashsize; - - rc = fdt_find_and_setprop(blob, "/localbus", "ranges", - val, sizeof(val), 1); - if (rc) - printf("Unable to update property NOR mapping, err=%s\n", - fdt_strerror(rc)); -} -#endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -- 1.5.4.2

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[U-Boot-Users] Help needed Urgent (How to shift TEXT_BASE)
by RamaBhaskar 09 May '08

09 May '08

Hi Experts, I am new bee to u-boot. I have u-boot image running on my PPC board. I need to create dual boot loader and I have the concept working fine, except I have to change the TEXT_BASE for each image. Here are details: If I have boot loaders at 0xfff00000, looks like I have to set TEXT_BASE to 0xFFF00000. If I am going to burn it to location 0xfe000000, I need to change the TEXT_BASE to 0xFE000000. Otherwise images are not working right. Now my request to all of the experts here is: Is there a way I can have entire u-boot, with relative addressing for TEXT section. Thanks in advance RM ____________________________________________________________________________________ Be a better friend, newshound, and know-it-all with Yahoo! Mobile. Try it now. http://mobile.yahoo.com/;_ylt=Ahu06i62sR8HDtDypao8Wcj9tAcJ

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[U-Boot-Users] [PATCH] syscon3: fix second TSEC configuration (it is actually TSEC3)
by Wolfgang Denk 09 May '08

09 May '08

From: Sergei Poselenov <sposelenov(a)emcraft.com> Signed-off-by: Sergei Poselenov <sposelenov(a)emcraft.com> --- include/configs/syscon3.h | 12 ++++++------ 1 files changed, 6 insertions(+), 6 deletions(-) diff --git a/include/configs/syscon3.h b/include/configs/syscon3.h index d451a61..3f4725e 100644 --- a/include/configs/syscon3.h +++ b/include/configs/syscon3.h @@ -242,19 +242,19 @@ #define CONFIG_MII 1 /* MII PHY management */ #define CONFIG_TSEC1 1 #define CONFIG_TSEC1_NAME "TSEC0" -#define CONFIG_TSEC2 1 -#define CONFIG_TSEC2_NAME "TSEC1" +#define CONFIG_TSEC3 1 +#define CONFIG_TSEC3_NAME "TSEC1" #undef CONFIG_MPC85XX_FEC #define TSEC1_PHY_ADDR 0 -#define TSEC2_PHY_ADDR 1 +#define TSEC3_PHY_ADDR 1 #define TSEC1_PHYIDX 0 -#define TSEC2_PHYIDX 0 +#define TSEC3_PHYIDX 0 #define TSEC1_FLAGS TSEC_GIGABIT -#define TSEC2_FLAGS TSEC_GIGABIT +#define TSEC3_FLAGS TSEC_GIGABIT -/* Options are: TSEC[0-1] */ +/* Options are: TSEC[0,1] */ #define CONFIG_ETHPRIME "TSEC0" #define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ -- 1.5.4.2

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[U-Boot-Users] [Help Need Urgent]u-boot CFG_RAMBOOT (u-boot running from DDR not from NOR) mpc85xx based board
by Manish Jaggi 09 May '08

09 May '08

Hi All, This is kinda urgent. I am using a custom mpc85xx SOC based EVB and my requirement is to compile u-boot such that the image be copied to DDR and then run from there itself. This is similar to CFG_RAMBOOT in mpc83xx. I think i have to put a lot of initialization code in cpu/mpc85xx/start.S and board/xxx/init.S Can u please advice me on what all to comment out in these files, also it would be really great if you could point me to some implementation which matches my problem Thanks a ton. Manish

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[U-Boot-Users] [PATCH v2 1/3] New i.MX31 SPI driver
by Guennadi Liakhovetski 09 May '08

09 May '08

This is an SPI driver for i.MX and MXC based SoCs from Freescale. So far only implemented and tested on i.MX31, can with a modified register layout and definitions be used for i.MX27, I think, MXC CPUs have similar SPI controllers too. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: fix a copy-paste error README | 5 + drivers/spi/Makefile | 1 + drivers/spi/mxc_spi.c | 166 +++++++++++++++++++++++++++++++++ include/asm-arm/arch-mx31/mx31-regs.h | 7 +- include/spi.h | 16 +++- 5 files changed, 193 insertions(+), 2 deletions(-) create mode 100644 drivers/spi/mxc_spi.c diff --git a/README b/README index 7c16345..d201b92 100644 --- a/README +++ b/README @@ -1414,6 +1414,11 @@ The following options need to be configured: Currently supported on some MPC8xxx processors. For an example, see include/configs/mpc8349emds.h. + CONFIG_MXC_SPI + + Enables the driver for the SPI controllers on i.MX and MXC + SoCs. Currently only i.MX31 is supported. + - FPGA Support: CONFIG_FPGA Enables FPGA subsystem. diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 0b7a2df..bc8a104 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -26,6 +26,7 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a COBJS-y += mpc8xxx_spi.o +COBJS-$(CONFIG_MXC_SPI) += mxc_spi.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/spi/mxc_spi.c b/drivers/spi/mxc_spi.c new file mode 100644 index 0000000..b2e3ab9 --- /dev/null +++ b/drivers/spi/mxc_spi.c @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + */ + +#include <common.h> +#include <spi.h> +#include <asm/io.h> + +#ifdef CONFIG_MX27 +/* i.MX27 has a completely wrong register layout and register definitions in the + * datasheet, the correct one is in the Freescale's Linux driver */ + +#error "i.MX27 CSPI not supported due to drastic differences in register definisions" \ +"See linux mxc_spi driver from Freescale for details." + +#else + +#define MXC_CSPIRXDATA 0x00 +#define MXC_CSPITXDATA 0x04 +#define MXC_CSPICTRL 0x08 +#define MXC_CSPIINT 0x0C +#define MXC_CSPIDMA 0x10 +#define MXC_CSPISTAT 0x14 +#define MXC_CSPIPERIOD 0x18 +#define MXC_CSPITEST 0x1C +#define MXC_CSPIRESET 0x00 + +#define MXC_CSPICTRL_EN (1 << 0) +#define MXC_CSPICTRL_MODE (1 << 1) +#define MXC_CSPICTRL_XCH (1 << 2) +#define MXC_CSPICTRL_SMC (1 << 3) +#define MXC_CSPICTRL_POL (1 << 4) +#define MXC_CSPICTRL_PHA (1 << 5) +#define MXC_CSPICTRL_SSCTL (1 << 6) +#define MXC_CSPICTRL_SSPOL (1 << 7) +#define MXC_CSPICTRL_CHIPSELECT(x) (((x) & 0x3) << 24) +#define MXC_CSPICTRL_BITCOUNT(x) (((x) & 0x1f) << 8) +#define MXC_CSPICTRL_DATARATE(x) (((x) & 0x7) << 16) + +#define MXC_CSPIPERIOD_32KHZ (1 << 15) + +static unsigned long spi_bases[] = { + 0x43fa4000, + 0x50010000, + 0x53f84000, +}; + +static unsigned long spi_base; + +#endif + +spi_chipsel_type spi_chipsel[] = { + (spi_chipsel_type)0, + (spi_chipsel_type)1, + (spi_chipsel_type)2, + (spi_chipsel_type)3, +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +static inline u32 reg_read(unsigned long addr) +{ + return *(volatile unsigned long*)addr; +} + +static inline void reg_write(unsigned long addr, u32 val) +{ + *(volatile unsigned long*)addr = val; +} + +static u32 spi_xchg_single(u32 data, int bitlen) +{ + + unsigned int cfg_reg = reg_read(spi_base + MXC_CSPICTRL); + + if (MXC_CSPICTRL_BITCOUNT(bitlen - 1) != (cfg_reg & MXC_CSPICTRL_BITCOUNT(31))) { + cfg_reg = (cfg_reg & ~MXC_CSPICTRL_BITCOUNT(31)) | + MXC_CSPICTRL_BITCOUNT(bitlen - 1); + reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + } + + reg_write(spi_base + MXC_CSPITXDATA, data); + + cfg_reg |= MXC_CSPICTRL_XCH; + + reg_write(spi_base + MXC_CSPICTRL, cfg_reg); + + while (reg_read(spi_base + MXC_CSPICTRL) & MXC_CSPICTRL_XCH) + ; + + return reg_read(spi_base + MXC_CSPIRXDATA); +} + +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din) +{ + int n_blks = (bitlen + 31) / 32; + u32 *out_l, *in_l; + int i; + + if ((int)dout & 3 || (int)din & 3) { + printf("Error: unaligned buffers in: %p, out: %p\n", din, dout); + return 1; + } + + if (!spi_base) + spi_select(CONFIG_MXC_SPI_IFACE, (int)chipsel, SPI_MODE_2 | SPI_CS_HIGH); + + for (i = 0, in_l = (u32 *)din, out_l = (u32 *)dout; + i < n_blks; + i++, in_l++, out_l++, bitlen -= 32) + *in_l = spi_xchg_single(*out_l, bitlen); + + return 0; +} + +void spi_init(void) +{ +} + +int spi_select(unsigned int bus, unsigned int dev, unsigned long mode) +{ + unsigned int ctrl_reg; + + if (bus >= sizeof(spi_bases) / sizeof(spi_bases[0]) || + dev > 3) + return 1; + + spi_base = spi_bases[bus]; + + ctrl_reg = MXC_CSPICTRL_CHIPSELECT(dev) | + MXC_CSPICTRL_BITCOUNT(31) | + MXC_CSPICTRL_DATARATE(7) | /* FIXME: calculate data rate */ + MXC_CSPICTRL_EN | + MXC_CSPICTRL_MODE; + + if (mode & SPI_CPHA) + ctrl_reg |= MXC_CSPICTRL_PHA; + if (!(mode & SPI_CPOL)) + ctrl_reg |= MXC_CSPICTRL_POL; + if (mode & SPI_CS_HIGH) + ctrl_reg |= MXC_CSPICTRL_SSPOL; + + reg_write(spi_base + MXC_CSPIRESET, 1); + udelay(1); + reg_write(spi_base + MXC_CSPICTRL, ctrl_reg); + reg_write(spi_base + MXC_CSPIPERIOD, + MXC_CSPIPERIOD_32KHZ); + reg_write(spi_base + MXC_CSPIINT, 0); + + return 0; +} diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index 380b401..d04072e 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -37,6 +37,9 @@ #define CCM_UPCTL (CCM_BASE + 0x10) #define CCM_SPCTL (CCM_BASE + 0x18) #define CCM_COSR (CCM_BASE + 0x1C) +#define CCM_CGR0 (CCM_BASE + 0x20) +#define CCM_CGR1 (CCM_BASE + 0x24) +#define CCM_CGR2 (CCM_BASE + 0x28) #define CCMR_MDS (1 << 7) #define CCMR_SBYCS (1 << 4) @@ -118,7 +121,9 @@ #define MUX_CTL_RXD1 0x82 #define MUX_CTL_TXD1 0x83 #define MUX_CTL_CSPI2_MISO 0x84 -/* 0x85 .. 0x8a */ +#define MUX_CTL_CSPI2_SS0 0x85 +#define MUX_CTL_CSPI2_SS1 0x86 +#define MUX_CTL_CSPI2_SS2 0x87 #define MUX_CTL_CSPI2_MOSI 0x8b /* The modes a specific pin can be in diff --git a/include/spi.h b/include/spi.h index 03dc5bc..3a55a68 100644 --- a/include/spi.h +++ b/include/spi.h @@ -24,6 +24,18 @@ #ifndef _SPI_H_ #define _SPI_H_ +/* SPI mode flags */ +#define SPI_CPHA 0x01 /* clock phase */ +#define SPI_CPOL 0x02 /* clock polarity */ +#define SPI_MODE_0 (0|0) /* (original MicroWire) */ +#define SPI_MODE_1 (0|SPI_CPHA) +#define SPI_MODE_2 (SPI_CPOL|0) +#define SPI_MODE_3 (SPI_CPOL|SPI_CPHA) +#define SPI_CS_HIGH 0x04 /* chipselect active high? */ +#define SPI_LSB_FIRST 0x08 /* per-word bits-on-wire */ +#define SPI_3WIRE 0x10 /* SI/SO signals shared */ +#define SPI_LOOP 0x20 /* loopback mode */ + /* * The function call pointer type used to drive the chip select. */ @@ -68,6 +80,8 @@ void spi_init(void); * * Returns: 0 on success, not 0 on failure */ -int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); +int spi_xfer(spi_chipsel_type chipsel, int bitlen, uchar *dout, uchar *din); + +int spi_select(unsigned int bus, unsigned int dev, unsigned long mode); #endif /* _SPI_H_ */ -- 1.5.4

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