May 2008 - U-Boot

[U-Boot-Users] HIGH PRIORITY
by International Bank Of Settlement 19 May '08

19 May '08

----------------------------------------------------------------- Ce message a été créé et envoyé avec une version d'évaluation

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[U-Boot-Users] [PATCH] PPC40x: Rework CFG_INIT_DCACHE_CS Block to Avoid Machine Checks
by Grant Erickson 18 May '08

18 May '08

This patch lays the ground work for moving out-of-assembly and unifying the SDRAM initialization code for PowerPC 405EX[r]-based boards. include/ppc405.h: Wrapped casts in EBC mnemonics with a macro such that the mnemonics can be used from assembly as well as from C. cpu/ppc4xx/start.S: Reworked code to handle the primordial stack and data area initialization when CFG_INIT_DCACHE_CS is asserted. The most important change was the addition of a 'dcba' loop (per-AMCC) to preallocate data cache blocks to be used for such a purpose. In addition, other changes include replacing magic numbers with the approriate mnemonics to improve code readability and self-documentation. Tested On: AMCC "Haleakala" with: CFG_SDRAM_BASE=0x00000000 CFG_INIT_DCACHE_CS=4 CFG_INIT_RAM_ADDR=(CFG_SDRAM_BASE + (1 << 30)) CFG_INIT_RAM_END=(4 << 10) Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- include/ppc405.h | 45 +++++++++++++++++++++++++++++++++++---------- cpu/ppc4xx/start.S | 124 +++++++++++++++++++++++++++++++++++++++------------- 2 files changed, 128 insertions(+), 41 deletions(-) diff --git a/include/ppc405.h b/include/ppc405.h index 009aa68..d02eb71 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -25,6 +25,12 @@ #define PPC_REG_BITS 32 #define PPC_REG_VAL(bit, value) ((value) << ((PPC_REG_BITS - 1) - (bit))) +#ifndef __ASSEMBLY__ +#define static_cast(type, val) (type)(val) +#else +#define static_cast(type, val) (val) +#endif + #ifndef CONFIG_IOP480 #define CFG_DCACHE_SIZE (16 << 10) /* For AMCC 405 CPUs */ #else @@ -371,7 +377,8 @@ /* Bank Configuration Register */ #define EBC_BXCR_BAS_MASK PPC_REG_VAL(11, 0xFFF) -#define EBC_BXCR_BAS_ENCODE(n) ((((unsigned long)(n))&EBC_BXCR_BAS_MASK)<<0) +#define EBC_BXCR_BAS_ENCODE(n) (((static_cast(unsigned long, n)) & \ + EBC_BXCR_BAS_MASK) << 0) #define EBC_BXCR_BS_MASK PPC_REG_VAL(14, 0x7) #define EBC_BXCR_BS_1MB PPC_REG_VAL(14, 0x0) #define EBC_BXCR_BS_2MB PPC_REG_VAL(14, 0x1) @@ -394,9 +401,15 @@ /* Bank Access Parameter Register */ #define EBC_BXAP_BME_ENABLED PPC_REG_VAL(0, 0x1) #define EBC_BXAP_BME_DISABLED PPC_REG_VAL(0, 0x0) -#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, ((unsigned long)(n)) & 0xFF) -#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, ((unsigned long)(n)) & 0x1F) -#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, ((unsigned long)(n)) & 0x7) +#define EBC_BXAP_TWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0xFF) +#define EBC_BXAP_FWT_ENCODE(n) PPC_REG_VAL(5, \ + (static_cast(unsigned long, n)) \ + & 0x1F) +#define EBC_BXAP_BWT_ENCODE(n) PPC_REG_VAL(8, \ + (static_cast(unsigned long, n)) \ + & 0x7) #define EBC_BXAP_BCE_DISABLE PPC_REG_VAL(9, 0x0) #define EBC_BXAP_BCE_ENABLE PPC_REG_VAL(9, 0x1) #define EBC_BXAP_BCT_MASK PPC_REG_VAL(11, 0x3) @@ -404,11 +417,21 @@ #define EBC_BXAP_BCT_4TRANS PPC_REG_VAL(11, 0x1) #define EBC_BXAP_BCT_8TRANS PPC_REG_VAL(11, 0x2) #define EBC_BXAP_BCT_16TRANS PPC_REG_VAL(11, 0x3) -#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, ((unsigned long)(n)) & 0x3) -#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, ((unsigned long)(n)) & 0x3) -#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, ((unsigned long)(n)) & 0x3) -#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, ((unsigned long)(n)) & 0x3) -#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, ((unsigned long)(n)) & 0x7) +#define EBC_BXAP_CSN_ENCODE(n) PPC_REG_VAL(13, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_OEN_ENCODE(n) PPC_REG_VAL(15, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBN_ENCODE(n) PPC_REG_VAL(17, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_WBF_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x3) +#define EBC_BXAP_TH_ENCODE(n) PPC_REG_VAL(22, \ + (static_cast(unsigned long, n)) \ + & 0x7) #define EBC_BXAP_RE_ENABLED PPC_REG_VAL(23, 0x1) #define EBC_BXAP_RE_DISABLED PPC_REG_VAL(23, 0x0) #define EBC_BXAP_SOR_DELAYED PPC_REG_VAL(24, 0x0) @@ -453,7 +476,9 @@ #define EBC_CFG_PME_DISABLE PPC_REG_VAL(14, 0x0) #define EBC_CFG_PME_ENABLE PPC_REG_VAL(14, 0x1) #define EBC_CFG_PMT_MASK PPC_REG_VAL(19, 0x1F) -#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, ((unsigned long)(n)) & 0x1F) +#define EBC_CFG_PMT_ENCODE(n) PPC_REG_VAL(19, \ + (static_cast(unsigned long, n)) \ + & 0x1F) #define EBC_CFG_PR_MASK PPC_REG_VAL(21, 0x3) #define EBC_CFG_PR_16 PPC_REG_VAL(21, 0x0) #define EBC_CFG_PR_32 PPC_REG_VAL(21, 0x1) diff --git a/cpu/ppc4xx/start.S b/cpu/ppc4xx/start.S index a513b45..92eb925 100644 --- a/cpu/ppc4xx/start.S +++ b/cpu/ppc4xx/start.S @@ -108,6 +108,34 @@ # define PBxAP pb7ap # define PBxCR pb7cr # endif +/* + * Memory Bank x (nothingness) initialization CFG_INIT_RAM_ADDR + 64 MiB + * used as temporary stack pointer for the primordial stack + */ +# ifndef CFG_INIT_DCACHE_PBxAR +# define CFG_INIT_DCACHE_PBxAR (EBC_BXAP_BME_DISABLED | \ + EBC_BXAP_TWT_ENCODE(7) | \ + EBC_BXAP_BCE_DISABLE | \ + EBC_BXAP_BCT_2TRANS | \ + EBC_BXAP_CSN_ENCODE(0) | \ + EBC_BXAP_OEN_ENCODE(0) | \ + EBC_BXAP_WBN_ENCODE(0) | \ + EBC_BXAP_WBF_ENCODE(0) | \ + EBC_BXAP_TH_ENCODE(2) | \ + EBC_BXAP_RE_DISABLED | \ + EBC_BXAP_SOR_NONDELAYED | \ + EBC_BXAP_BEM_WRITEONLY | \ + EBC_BXAP_PEN_DISABLED) +# endif /* CFG_INIT_DCACHE_PBxAR */ +# ifndef CFG_INIT_DCACHE_PBxCR +# define CFG_INIT_DCACHE_PBxCR (EBC_BXCR_BAS_ENCODE(CFG_INIT_RAM_ADDR) | \ + EBC_BXCR_BS_64MB | \ + EBC_BXCR_BU_RW | \ + EBC_BXCR_BW_16BIT) +# endif /* CFG_INIT_DCACHE_PBxCR */ +# ifndef CFG_INIT_RAM_PATTERN +# define CFG_INIT_RAM_PATTERN 0xDEADDEAD +# endif #endif /* CFG_INIT_DCACHE_CS */ #if (defined(CFG_INIT_RAM_DCACHE) && (CFG_INIT_RAM_END > (4 << 10))) @@ -922,9 +950,9 @@ _start: #endif #if !(defined(CFG_INIT_DCACHE_CS) || defined(CFG_TEMP_STACK_OCM)) /* - * Boards like the Kilauea (405EX) don't have OCM and can't use - * DCache for init-ram. So setup stack here directly after the - * SDRAM is initialized. + * For boards that don't have OCM and can't use the data cache + * for their primordial stack, setup stack here directly after the + * SDRAM is initialized in ext_bus_cntlr_init. */ lis r1, CFG_INIT_RAM_ADDR@h ori r1,r1,CFG_INIT_SP_OFFSET /* set up the stack in SDRAM */ @@ -1043,47 +1071,81 @@ start_ram: /* Setup temporary stack in DCACHE or OCM if needed for SDRAM SPD. */ /*----------------------------------------------------------------------- */ #ifdef CFG_INIT_DCACHE_CS - /*----------------------------------------------------------------------- */ - /* Memory Bank x (nothingness) initialization 1GB+64MEG */ - /* used as temporary stack pointer for stage0 */ - /*----------------------------------------------------------------------- */ - li r4,PBxAP - mtdcr ebccfga,r4 - lis r4,0x0380 - ori r4,r4,0x0480 - mtdcr ebccfgd,r4 - - addi r4,0,PBxCR - mtdcr ebccfga,r4 - lis r4,0x400D - ori r4,r4,0xa000 - mtdcr ebccfgd,r4 + li r4, PBxAP + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxAR@h + ori r4, r4, CFG_INIT_DCACHE_PBxAR@l + mtdcr ebccfgd, r4 + + addi r4, 0, PBxCR + mtdcr ebccfga, r4 + lis r4, CFG_INIT_DCACHE_PBxCR@h + ori r4, r4, CFG_INIT_DCACHE_PBxCR@l + mtdcr ebccfgd, r4 /* turn on data cache for this region */ - lis r4,0x0080 + lis r4, 0x0080 mtdccr r4 - /* set stack pointer and clear stack to known value */ + /* + * Preallocate data cache lines to be used to avoid a subsequent + * cache miss and an ensuing machine check exception when exceptions + * are enabled. + */ + li r0, 0 - lis r1,CFG_INIT_RAM_ADDR@h - ori r1,r1,CFG_INIT_SP_OFFSET@l + lis r3, CFG_INIT_RAM_ADDR@h + ori r3, r3, CFG_INIT_RAM_ADDR@l + + lis r4, CFG_INIT_RAM_END@h + ori r4, r4, CFG_INIT_RAM_END@l + + /* + * Convert the size, in bytes, to the number of cache lines/blocks + * to preallocate. + */ + clrlwi. r5, r4, (32 - L1_CACHE_SHIFT) + srwi r5, r4, L1_CACHE_SHIFT + beq ..load_counter + addi r5, r5, 0x0001 +..load_counter: + mtctr r5 - li r4,2048 /* we store 2048 words to stack */ + /* Preallocate the computed number of cache blocks. */ +..alloc_dcache_block: + dcba r0, r3 + addi r3, r3, L1_CACHE_BYTES + bdnz ..alloc_dcache_block + sync + + /* + * Load the initial stack pointer and data area and convert the size, + * in bytes, to the number of words to initialize to a known value. + */ + lis r1, CFG_INIT_RAM_ADDR@h + ori r1, r1, CFG_INIT_SP_OFFSET@l + + lis r4, (CFG_INIT_RAM_END >> 2)@h + ori r4, r4, (CFG_INIT_RAM_END >> 2)@l mtctr r4 - lis r2,CFG_INIT_RAM_ADDR@h /* we also clear data area */ - ori r2,r2,CFG_INIT_RAM_END@l /* so cant copy value from r1 */ + lis r2, CFG_INIT_RAM_ADDR@h + ori r2, r2, CFG_INIT_RAM_END@l - lis r4,0xdead /* we store 0xdeaddead in the stack */ - ori r4,r4,0xdead + lis r4, CFG_INIT_RAM_PATTERN@h + ori r4, r4, CFG_INIT_RAM_PATTERN@l ..stackloop: - stwu r4,-4(r2) + stwu r4, -4(r2) bdnz ..stackloop - li r0, 0 /* Make room for stack frame header and */ - stwu r0, -4(r1) /* clear final stack frame so that */ - stwu r0, -4(r1) /* stack backtraces terminate cleanly */ + /* + * Make room for stack frame header and clear final stack frame so + * that stack backtraces terminate cleanly. + */ + stwu r0, -4(r1) + stwu r0, -4(r1) + /* * Set up a dummy frame to store reset vector as return address. * this causes stack underflow to reset board. -- 1.5.4.3

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[U-Boot-Users] NOKIA's BB5 boards
by Divel 18 May '08

18 May '08

Can anybody write initialisation for BB5 boards ? It based on OMAP 1710 ARM processor and NOKIA's RAP 3G

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Re: [U-Boot-Users] [PATCH] 82550_eeprom: Fix error: lvalue required as increment operand
by Wolfgang Denk 18 May '08

18 May '08

In message <010901c8b846$32bb8230$98328690$@Tjernlund@transmode.se> you wrote: > > > + return (void *)ret; > > return dst; Right. Thanks for catching. Unapplied. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de "There are three principal ways to lose money: wine, women, and en- gineers. While the first two are more pleasant, the third is by far the more certain." -- Baron Rothschild, ca. 1800

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[U-Boot-Users] [PATCH] 82550_eeprom: Fix error: lvalue required as increment operand
by Jean-Christophe PLAGNIOL-VILLARD 18 May '08

18 May '08

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> --- examples/82559_eeprom.c | 11 ++++++++--- 1 files changed, 8 insertions(+), 3 deletions(-) diff --git a/examples/82559_eeprom.c b/examples/82559_eeprom.c index 1a121d4..a56edd4 100644 --- a/examples/82559_eeprom.c +++ b/examples/82559_eeprom.c @@ -53,9 +53,14 @@ static inline unsigned short swap16(unsigned short x) static inline void *memcpy(void *dst, const void *src, unsigned int len) { - void * ret = dst; - while (len-- > 0) *((char *)dst)++ = *((char *)src)++; - return ret; + char * ret = dst; + + while (len-- > 0) { + *ret++ = *((char *)src); + src++; + } + + return (void *)ret; } /* The EEPROM commands include the alway-set leading bit. */ -- 1.5.5.1

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[U-Boot-Users] [PATCH]
by Grant Erickson 18 May '08

18 May '08

This patch continues laying the ground work for moving out-of-assembly and unifying the SDRAM initialization code for PowerPC 405EX[r]-based boards. To do so, this deduces by one the number of nearly-identical DRAM ECC initialization implementations for PowerPC 4xx processors utilizing a DDR/DDR2 SDRAM controller by merging two of them into a common, shared implementation. Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- cpu/ppc4xx/44x_spd_ddr.c | 51 ++------------------ cpu/ppc4xx/Makefile | 1 + cpu/ppc4xx/ecc.c | 117 ++++++++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/ecc.h | 42 ++++++++++++++++ cpu/ppc4xx/sdram.c | 46 +----------------- 5 files changed, 168 insertions(+), 89 deletions(-) create mode 100644 cpu/ppc4xx/ecc.c create mode 100644 cpu/ppc4xx/ecc.h diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b9cf5cb..7f04ca6 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -53,6 +53,10 @@ #include <ppc4xx.h> #include <asm/mmu.h> +#ifdef CONFIG_DDR_ECC +#include "ecc.h" +#endif + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR)) @@ -296,10 +300,6 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long num_dimm_banks); static void program_tr1(void); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes); -#endif - static unsigned long program_bxcr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -418,7 +418,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - program_ecc(total_size); + ecc_init(CFG_SDRAM_BASE, total_size); #endif return total_size; @@ -1402,45 +1402,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, return(bank_base_addr); } - -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) - address_increment = 4; - else - address_increment = 8; - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} -#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 178c5c6..800bb41 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -45,6 +45,7 @@ COBJS += cpu.o COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o +COBJS += ecc.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c new file mode 100644 index 0000000..a7755bf --- /dev/null +++ b/cpu/ppc4xx/ecc.c @@ -0,0 +1,117 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * + * Copyright (c) 2005-2007 DENX Software Engineering, GmbH + * Stefan Roese <sr(a)denx.de> + * + * Copyright (c) 2002 Artesyn Technology + * Jun Gu <jung(a)artesyncp.com> + * + * Copyright (c) 2001 Wave 7 Optics + * Bill Hunter <williamhunter(a)attbi.com>x + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements generic DRAM ECC initialization for + * PowerPC processors using a SDRAM DDR/DDR2 controller, + * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and + * 460EX/GT. + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> + +#include "ecc.h" + +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) +/* + * void ecc_init() + * + * Description: + * This routine initializes a range of DRAM ECC memory with known + * data and enables ECC checking. + * + * TO DO: + * Improve performance by utilizing cache. + * + * Input(s): + * start - A pointer to the start of memory covered by ECC requiring + * initialization. + * size - The size, in bytes, of the memory covered by ECC requiring + * initialization. + * + * Output(s): + * start - A pointer to the start of memory covered by ECC with + * CFG_ECC_PATTERN written to all locations and ECC data + * primed. + * + * Returns: + * N/A + */ +void ecc_init(unsigned long * const start, unsigned long size) +{ + const unsigned long pattern = CFG_ECC_PATTERN; + unsigned * const end = (unsigned long * const)((long)start + size); + unsigned long * current = start; + unsigned long mcopt1; + long increment; + + if (start >= end) + return; + + mfsdram(SDRAM_MCOPT1, mcopt1); + + /* Enable ECC generation without checking or reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_GEN)); + + increment = sizeof(u32); + +#if defined(CONFIG_440) + /* + * Look at the geometry of SDRAM (data width) to determine whether we + * can skip words when writing. + */ + + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32) + increment = sizeof(u64); +#endif /* defined(CONFIG_440) */ + + while (current < end) { + *current = pattern; + current = (unsigned long *)((long)current + increment); + } + + /* Wait until the writes are finished. */ + + sync(); + eieio(); + + /* Enable ECC generation with checking and no reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_CHK)); +} +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h new file mode 100644 index 0000000..da1c4fd --- /dev/null +++ b/cpu/ppc4xx/ecc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * + * Copyright (c) 2007 DENX Software Engineering, GmbH + * Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements ECC initialization for PowerPC processors + * using the SDRAM DDR2 controller, including the 405EX(r), + * 440SP(E), 460EX and 460GT. + * + */ + +#ifndef _ECC_H_ +#define _ECC_H_ + +#if !defined(CFG_ECC_PATTERN) +#define CFG_ECC_PATTERN 0x00000000 +#endif /* !defined(CFG_ECC_PATTERN) */ + +extern void ecc_init(unsigned long * const start, unsigned long size); + +#endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 2724d91..bd0a827 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -31,6 +31,9 @@ #include <ppc4xx.h> #include <asm/processor.h> #include "sdram.h" +#ifdef CONFIG_SDRAM_ECC +#include "ecc.h" +#endif #ifdef CONFIG_SDRAM_BANK0 @@ -332,49 +335,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -#ifdef CONFIG_SDRAM_ECC -static void ecc_init(ulong start, ulong size) -{ - ulong current_addr; /* current byte address */ - ulong end_addr; /* end of memory region */ - ulong addr_inc; /* address skip between writes */ - ulong cfg0_reg; /* for restoring ECC state */ - - /* - * TODO: Enable dcache before running this test (speedup) - */ - - mfsdram(mem_cfg0, cfg0_reg); - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); - - /* - * look at geometry of SDRAM (data width) to determine whether we - * can skip words when writing - */ - if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) - addr_inc = 4; - else - addr_inc = 8; - - current_addr = start; - end_addr = start + size; - - while (current_addr < end_addr) { - *((ulong *)current_addr) = 0x00000000; - current_addr += addr_inc; - } - - /* - * TODO: Flush dcache and disable it again - */ - - /* - * Enable ecc checking and parity errors - */ - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); -} -#endif - /* * Autodetect onboard DDR SDRAM on 440 platforms * -- 1.5.4.3

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[U-Boot-Users] [ppc4xx] Please pull git://www.denx.de/git/u-boot-ppc4xx.git
by Stefan Roese 18 May '08

18 May '08

The following changes since commit a38dc3ea8614f8b0c41e432b445a9959b9711295: Wolfgang Denk (1): TQM8272: fix out-of-tree building are available in the git repository at: git://www.denx.de/git/u-boot-ppc4xx.git master Stefan Roese (1): ppc4xx: Canyonlands: Disable PCIe0/SATA in dev-tree depending on selection board/amcc/canyonlands/canyonlands.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-)

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[U-Boot-Users] [PATCH V2] ppc4xx: Canyonlands: Disable PCIe0/SATA in dev-tree depending on selection
by Stefan Roese 18 May '08

18 May '08

When SATA is selected (via jumper J6) we need to disable the first PCIe node in the device tree, so that Linux doesn't initialize it. Otherwise the Linux SATA driver will fail to detect the devices. The same goes the other way around too. So if PCIe is selected we need to disable the SATA node in the device tree. This is because PCIe port 0 and SATA on 460EX share the same pins (multiplexed) and we have to configure in U-Boot which peripheral is enabled. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/canyonlands/canyonlands.c | 26 ++++++++++++++++++++++++++ 1 files changed, 26 insertions(+), 0 deletions(-) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 9986e9a..9c458b9 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -479,5 +479,31 @@ void ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); + + if (gd->board_type == BOARD_CANYONLANDS_SATA) { + /* + * When SATA is selected we need to disable the first PCIe + * node in the device tree, so that Linux doesn't initialize + * it. + */ + rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) + printf("Unable to update property status in PCIe node, err=%s\n", + fdt_strerror(rc)); + } + + if (gd->board_type == BOARD_CANYONLANDS_PCIE) { + /* + * When PCIe is selected we need to disable the SATA + * node in the device tree, so that Linux doesn't initialize + * it. + */ + rc = fdt_find_and_setprop(blob, "/plb/sata@bffd1000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) + printf("Unable to update property status in PCIe node, err=%s\n", + fdt_strerror(rc)); + } } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -- 1.5.5.1

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[U-Boot-Users] Duplicate implementations of testdram() deprecated
by Wolfgang Denk 18 May '08

18 May '08

Hello, I just noticed that 84 boards contain some function "testdram()" which (and I guess few people are surprised) in 80+ cases is basicly a verbatim copy of the same code. Allt hese boards completely ignore that we already have several implamentations of memory test code both in the mtest command (see "common/cmd_mem.c") and in the POST (see "post/drivers/memory.c"). depending on requirements these can be selected / configured to be either faster or more thorough. I hereby ask the maintainers of the following boards to clean up theirt code and get rid of the duplicated code. Please remove the "testdram()" implementation (which is disabled in all but 6 boards anyway) from your code and use for example the respective POST code instead: board/BuS/EB+MCF-EV123/EB+MCF-EV123.c board/Marvell/db64360/db64360.c board/Marvell/db64460/db64460.c board/amcc/bamboo/bamboo.c board/amcc/bubinga/bubinga.c board/amcc/ebony/ebony.c board/amcc/luan/luan.c board/amcc/ocotea/ocotea.c board/amcc/sequoia/sequoia.c board/amcc/walnut/walnut.c board/amcc/yosemite/yosemite.c board/amcc/yucca/yucca.c board/amcc/acadia/memory.c board/amcc/katmai/katmai.c board/amcc/taihu/taihu.c board/amcc/taishan/taishan.c board/amcc/kilauea/memory.c board/amcc/makalu/memory.c board/amcc/canyonlands/canyonlands.c board/cobra5272/cobra5272.c board/cray/L1/L1.c board/dave/PPChameleonEVB/PPChameleonEVB.c board/eric/eric.c board/esd/adciop/adciop.c board/esd/ar405/ar405.c board/esd/canbt/canbt.c board/esd/cpci750/cpci750.c board/esd/cpciiser4/cpciiser4.c board/esd/dasa_sim/dasa_sim.c board/esd/dp405/dp405.c board/esd/du405/du405.c board/esd/ocrtc/ocrtc.c board/esd/pci405/pci405.c board/esd/tasreg/tasreg.c board/esd/voh405/voh405.c board/fads/fads.c board/g2000/g2000.c board/gw8260/gw8260.c board/idmr/idmr.c board/jse/sdram.c board/sbc8641d/sbc8641d.c board/m5271evb/m5271evb.c board/m5272c3/m5272c3.c board/ml2/ml2.c board/freescale/m5235evb/m5235evb.c board/freescale/m5249evb/m5249evb.c board/freescale/m5253evbe/m5253evbe.c board/freescale/m5329evb/m5329evb.c board/freescale/m54455evb/m54455evb.c board/freescale/mpc8544ds/mpc8544ds.c board/freescale/mpc8641hpcn/mpc8641hpcn.c board/freescale/mpc8540ads/mpc8540ads.c board/freescale/mpc8541cds/mpc8541cds.c board/freescale/mpc8548cds/mpc8548cds.c board/freescale/mpc8555cds/mpc8555cds.c board/freescale/mpc8560ads/mpc8560ads.c board/freescale/mpc8568mds/mpc8568mds.c board/freescale/mpc8610hpcd/mpc8610hpcd.c board/freescale/mpc837xerdb/mpc837xerdb.c board/freescale/m52277evb/m52277evb.c board/freescale/m5373evb/m5373evb.c board/freescale/m547xevb/m547xevb.c board/freescale/m548xevb/m548xevb.c board/freescale/m5275evb/m5275evb.c board/mpc8540eval/mpc8540eval.c board/korat/korat.c board/mpl/common/memtst.c board/lwmon5/lwmon5.c board/pcs440ep/pcs440ep.c board/pm854/pm854.c board/pm856/pm856.c board/prodrive/alpr/alpr.c board/prodrive/p3mx/p3mx.c board/sandburst/common/sb_common.c board/sbc405/sbc405.c board/sbc8560/sbc8560.c board/stxgp3/stxgp3.c board/tqm85xx/sdram.c board/xilinx/ml300/ml300.c board/xpedite1k/xpedite1k.c board/stxssa/stxssa.c board/zeus/zeus.c board/atum8548/atum8548.c board/sbc8548/sbc8548.c Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de ADVISORY: There is an Extremely Small but Nonzero Chance That, Through a Process Know as "Tunneling," This Product May Spontaneously Disappear from Its Present Location and Reappear at Any Random Place in the Universe, Including Your Neighbor's Domicile. The Manufacturer Will Not Be Responsible for Any Damages or Inconvenience That May Result.

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[U-Boot-Users] [PATCH] ppc4xx: Canyonlands: Disable PCIe port 0 in dev-tree when SATA is selected
by Stefan Roese 18 May '08

18 May '08

When SATA is selected (via jumper J6) we need to disable the first PCIe node in the device tree, so that Linux doesn't initialize it. Otherwise the Linux SATA driver will fail to detect the devices. Signed-off-by: Stefan Roese <sr(a)denx.de> --- board/amcc/canyonlands/canyonlands.c | 13 +++++++++++++ 1 files changed, 13 insertions(+), 0 deletions(-) diff --git a/board/amcc/canyonlands/canyonlands.c b/board/amcc/canyonlands/canyonlands.c index 9986e9a..9c65e72 100644 --- a/board/amcc/canyonlands/canyonlands.c +++ b/board/amcc/canyonlands/canyonlands.c @@ -479,5 +479,18 @@ void ft_board_setup(void *blob, bd_t *bd) if (rc) printf("Unable to update property NOR mapping, err=%s\n", fdt_strerror(rc)); + + if (gd->board_type == BOARD_CANYONLANDS_SATA) { + /* + * When SATA is selected we need to disable the first PCIe + * node in the device tree, so that Linux doesn't initialize + * it. + */ + rc = fdt_find_and_setprop(blob, "/plb/pciex@d00000000", "status", + "disabled", sizeof("disabled"), 1); + if (rc) + printf("Unable to update property status in PCIe node, err=%s\n", + fdt_strerror(rc)); + } } #endif /* defined(CONFIG_OF_LIBFDT) && defined(CONFIG_OF_BOARD_SETUP) */ -- 1.5.5.1

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