May 2008 - U-Boot

[U-Boot-Users] [PATCH] mips: Use 'CFG_MIPS_CLOCK' to compute the MIPS tick timebase
by Jason McMullan 20 May '08

20 May '08

All existing MIPS boards define CFG_HZ to be the number of ticks per second for the timebase. However, CFG_HZ should be a constant 1000 for all boards. This patch set CFG_HZ to be defined as 1000 for all MIPS boards, and uses the new configuration value 'CFG_MIPS_CLOCK' to calculate the timebase. Per-board patches to board config files are included. Signed-off-by: Jason McMullan <mcmullan(a)netapp.com> --- include/configs/dbau1x00.h | 3 ++- include/configs/gth2.h | 3 ++- include/configs/incaip.h | 3 ++- include/configs/pb1x00.h | 3 ++- include/configs/purple.h | 3 ++- include/configs/qemu-mips.h | 3 ++- include/configs/tb0229.h | 3 ++- lib_mips/time.c | 17 +++++++++++++++-- 8 files changed, 29 insertions(+), 9 deletions(-) diff --git a/include/configs/dbau1x00.h b/include/configs/dbau1x00.h index b2f606f..b4cc0c2 100644 --- a/include/configs/dbau1x00.h +++ b/include/configs/dbau1x00.h @@ -148,7 +148,8 @@ #error "Invalid CPU frequency - must be multiple of 12!" #endif -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_MIPS_CLOCK (CFG_MHZ * 1000000) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/gth2.h b/include/configs/gth2.h index c2a50c1..656eccb 100644 --- a/include/configs/gth2.h +++ b/include/configs/gth2.h @@ -117,8 +117,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 #define CFG_MHZ 500 +#define CFG_MIPS_CLOCK (CFG_MHZ * 1000000) -#define CFG_HZ (CFG_MHZ * 1000000) /* FIXME causes overflow in net.c */ +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/incaip.h b/include/configs/incaip.h index 5ca00b3..c0e26f2 100644 --- a/include/configs/incaip.h +++ b/include/configs/incaip.h @@ -118,7 +118,8 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (incaip_get_cpuclk() / 2) +#define CFG_MIPS_CLOCK (incaip_get_cpuclk() / 2) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/include/configs/pb1x00.h b/include/configs/pb1x00.h index 810e0f0..5cb5069 100644 --- a/include/configs/pb1x00.h +++ b/include/configs/pb1x00.h @@ -81,7 +81,8 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ 396000000 /* FIXME causes overflow in net.c */ +#define CFG_MIPS_CLOCK 396000000 +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/purple.h b/include/configs/purple.h index 1be4e05..9fe98f2 100644 --- a/include/configs/purple.h +++ b/include/configs/purple.h @@ -114,7 +114,8 @@ #define CFG_PROMPT "PURPLE # " /* Monitor Command Prompt */ #define CFG_CBSIZE 256 /* Console I/O Buffer Size */ #define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ -#define CFG_HZ (CPU_CLOCK_RATE/2) +#define CFG_MIPS_CLOCK (CPU_CLOCK_RATE/2) +#define CFG_HZ 1000 #define CFG_MAXARGS 16 /* max number of command args*/ #define CFG_LOAD_ADDR 0x80500000 /* default load address */ diff --git a/include/configs/qemu-mips.h b/include/configs/qemu-mips.h index d6bcc8e..6889d7f 100644 --- a/include/configs/qemu-mips.h +++ b/include/configs/qemu-mips.h @@ -119,8 +119,9 @@ #define CFG_BOOTPARAMS_LEN 128*1024 #define CFG_MHZ 132 +#define CFG_MIPS_CLOCK (132 * 1000000) -#define CFG_HZ (CFG_MHZ * 1000000) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 /* Cached addr */ diff --git a/include/configs/tb0229.h b/include/configs/tb0229.h index dadf5d3..82206d5 100644 --- a/include/configs/tb0229.h +++ b/include/configs/tb0229.h @@ -122,7 +122,8 @@ #define CFG_BOOTPARAMS_LEN 128*1024 -#define CFG_HZ (CPU_TCLOCK_RATE/4) +#define CFG_MIPS_CLOCK (CPU_TCLOCK_RATE/4) +#define CFG_HZ 1000 #define CFG_SDRAM_BASE 0x80000000 diff --git a/lib_mips/time.c b/lib_mips/time.c index cd8dc72..1746160 100644 --- a/lib_mips/time.c +++ b/lib_mips/time.c @@ -23,24 +23,37 @@ #include <common.h> +/* CFG_MIPS_CLOCK is the number of ticks per second of the MIPS cpu timer. + * For MIPS processors, this is often the same as the CPU speed in HZ, + * however many embedded processors have a /2 or /4 divider. Please see + * your CPU reference manual for details. + */ +#ifndef CFG_MIPS_CLOCK +#error CFG_MIPS_CLOCK must be set in the board configuration file +#endif +/* Input is in CFG_HZ ticks */ static inline void mips_compare_set(u32 v) { + v *= (CFG_MIPS_CLOCK / CFG_HZ); asm volatile ("mtc0 %0, $11" : : "r" (v)); } +/* Input is in CFG_HZ ticks */ static inline void mips_count_set(u32 v) { + v *= (CFG_MIPS_CLOCK / CFG_HZ); asm volatile ("mtc0 %0, $9" : : "r" (v)); } +/* Returns CFG_HZ ticks */ static inline u32 mips_count_get(void) { u32 count; asm volatile ("mfc0 %0, $9" : "=r" (count) :); - return count; + return count / (CFG_MIPS_CLOCK / CFG_HZ); } /* @@ -75,7 +88,7 @@ void udelay (unsigned long usec) ulong tmo; ulong start = get_timer(0); - tmo = usec * (CFG_HZ / 1000000); + tmo = usec * CFG_HZ / 1000; while ((ulong)((mips_count_get() - start)) < tmo) /*NOP*/; } -- 1.5.4.3

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[U-Boot-Users] PXA255 code in start.S
by Amit Kumar 20 May '08

20 May '08

Hello, Kindly refer code at path UBOOT / u-boot / cpu / pxa / start.S Code: .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} /* Calling r0-r12 */ add r8, sp, #S_PC stmdb r8, {sp, lr}^ /* Calling SP, LR */ str lr, [r8, #0] /* Save calling PC */ mrs r6, spsr str r6, [r8, #4] /* Save CPSR */ str r0, [r8, #8] /* Save OLD_R0 */ mov r0, sp .endm Why there is need to save R0? If we refer ARM architecture (section what all happens when interrupt comes) there is no need to save R0. Moreover, there is no need of writing such big piece of code it can be replaced with below given four liner code: Sub lr, lr, #4 Stmfd sp! , {r0-r12, lr} MRS r1, spsr Stmfd sp! , {r1} Similarly we can write small code for restore of stack .macro irq_restore_user_regs Ldmfd sp! , {r1} MSR cpsr_c , R1 ldmfd sp!, {r0-r12, pc}^ .endm Can anybody clarify? Regards Amit Kumar **************** CAUTION - Disclaimer ***************** This e-mail contains PRIVILEGED AND CONFIDENTIAL INFORMATION intended solely for the use of the addressee(s). If you are not the intended recipient, please notify the sender by e-mail and delete the original message. Further, you are not to copy, disclose, or distribute this e-mail or its contents to any other person and any such actions are unlawful. This e-mail may contain viruses. Infosys has taken every reasonable precaution to minimize this risk, but is not liable for any damage you may sustain as a result of any virus in this e-mail. You should carry out your own virus checks before opening the e-mail or attachment. Infosys reserves the right to monitor and review the content of all messages sent to or from this e-mail address. Messages sent to or from this e-mail address may be stored on the Infosys e-mail system. ***INFOSYS******** End of Disclaimer ********INFOSYS***

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[U-Boot-Users] question about interrupt
by loody 20 May '08

20 May '08

Dear all: I have trace interrupt/Fiq vector in uboot based on smdk2410. after we save user registers, we jump to following functions I excerpted at the end of mail. But these 2 functions seems not really handle the irq/fiq, would someone please tell me where the real interrupt handler is? Is the interrupt handled in kernel? if it really is, how loader pass the vector pointer to OS? appreciate your help, miloody void do_fiq (struct pt_regs *pt_regs) { printf ("fast interrupt request\n"); show_regs (pt_regs); bad_mode (); } void do_irq (struct pt_regs *pt_regs) { #if defined (CONFIG_USE_IRQ) && defined (CONFIG_ARCH_INTEGRATOR) /* ASSUMED to be a timer interrupt */ /* Just clear it - count handled in */ /* integratorap.c */ *(volatile ulong *)(CFG_TIMERBASE + 0x0C) = 0; #else printf ("interrupt request\n"); show_regs (pt_regs); bad_mode (); #endif }

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[U-Boot-Users] [PATCH] Remove gaps and whitespaces in README file
by Hebbar 20 May '08

20 May '08

Hi, Remove gaps and whitespaces in README file Here in my company i cannot use git and hence no git-patch or git-mail. Will see if i can convince them to allow git. sorry till then Regards Gururaja Signed off by: Gururaja Hebbar <gururajakr(a)sanyo.co.in> diff -purN u-boot-1.3.3/README u-boot-1.3.3-modified/README --- u-boot-1.3.3/README 2008-05-19 03:47:11.000000000 -0700 +++ u-boot-1.3.3-modified/README 2008-05-20 13:58:47.656250000 -0700 @@ -180,15 +180,15 @@ Directory Hierarchy: - dtt Digital Thermometer and Thermostat drivers - examples Example code for standalone applications, etc. - include Header Files -- lib_arm Files generic to ARM architecture -- lib_avr32 Files generic to AVR32 architecture -- lib_generic Files generic to all architectures -- lib_i386 Files generic to i386 architecture -- lib_m68k Files generic to m68k architecture -- lib_mips Files generic to MIPS architecture -- lib_nios Files generic to NIOS architecture +- lib_arm Files generic to ARM architecture +- lib_avr32 Files generic to AVR32 architecture +- lib_generic Files generic to all architectures +- lib_i386 Files generic to i386 architecture +- lib_m68k Files generic to m68k architecture +- lib_mips Files generic to MIPS architecture +- lib_nios Files generic to NIOS architecture - lib_ppc Files generic to PowerPC architecture -- lib_sparc Files generic to SPARC architecture +- lib_sparc Files generic to SPARC architecture - libfdt Library files to support flattened device trees - net Networking code - post Power On Self Test @@ -608,7 +608,7 @@ The following options need to be configu CONFIG_CMD_NAND * NAND support CONFIG_CMD_NET bootp, tftpboot, rarpboot CONFIG_CMD_PCI * pciinfo - CONFIG_CMD_PCMCIA * PCMCIA support + CONFIG_CMD_PCMCIA * PCMCIA support CONFIG_CMD_PING * send ICMP ECHO_REQUEST to network host CONFIG_CMD_PORTIO * Port I/O @@ -618,7 +618,7 @@ The following options need to be configu CONFIG_CMD_SCSI * SCSI Support CONFIG_CMD_SDRAM * print SDRAM configuration information (requires CONFIG_CMD_I2C) - CONFIG_CMD_SETGETDCR Support for DCR Register access + CONFIG_CMD_SETGETDCR Support for DCR Register access (4xx only) CONFIG_CMD_SPI * SPI serial bus support CONFIG_CMD_USB * USB support @@ -1697,14 +1697,14 @@ The following options need to be configu Legacy uImage format: - Arg Where When + Arg Where When 1 common/cmd_bootm.c before attempting to boot an image - -1 common/cmd_bootm.c Image header has bad magic number + -1 common/cmd_bootm.c Image header has bad magic number 2 common/cmd_bootm.c Image header has correct magic number - -2 common/cmd_bootm.c Image header has bad checksum + -2 common/cmd_bootm.c Image header has bad checksum 3 common/cmd_bootm.c Image header has correct checksum - -3 common/cmd_bootm.c Image data has bad checksum - 4 common/cmd_bootm.c Image data has correct checksum + -3 common/cmd_bootm.c Image data has bad checksum + 4 common/cmd_bootm.c Image data has correct checksum -4 common/cmd_bootm.c Image is for unsupported architecture 5 common/cmd_bootm.c Architecture check OK -5 common/cmd_bootm.c Wrong Image Type (not kernel, multi) @@ -1716,11 +1716,11 @@ Legacy uImage format: -9 common/cmd_bootm.c Unsupported OS (not Linux, BSD, VxWorks, QNX) 9 common/image.c Start initial ramdisk verification - -10 common/image.c Ramdisk header has bad magic number - -11 common/image.c Ramdisk header has bad checksum + -10 common/image.c Ramdisk header has bad magic number + -11 common/image.c Ramdisk header has bad checksum 10 common/image.c Ramdisk header is OK - -12 common/image.c Ramdisk data has bad checksum - 11 common/image.c Ramdisk data has correct checksum + -12 common/image.c Ramdisk data has bad checksum + 11 common/image.c Ramdisk data has correct checksum 12 common/image.c Ramdisk verification complete, start loading -13 common/image.c Wrong Image Type (not PPC Linux Ramdisk) 13 common/image.c Start multifile image verification @@ -1762,7 +1762,7 @@ Legacy uImage format: 48 common/cmd_ide.c reading Image Header from IDE device OK -49 common/cmd_ide.c Image header has bad magic number 49 common/cmd_ide.c Image header has correct magic number - -50 common/cmd_ide.c Image header has bad checksum + -50 common/cmd_ide.c Image header has bad checksum 50 common/cmd_ide.c Image header has correct checksum -51 common/cmd_ide.c Error reading Image from IDE device 51 common/cmd_ide.c reading Image from IDE device OK http://www.nabble.com/file/p17336468/uboot-1.3.3-README_remove_whitespace.d… uboot-1.3.3-README_remove_whitespace.diff -- View this message in context: http://www.nabble.com/-PATCH--Remove-gaps-and-whitespaces-in-README-file-tp… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot-Users] Uncensored big boobs blogger
by JS 20 May '08

20 May '08

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[U-Boot-Users] help required on porting of U-boot and implementation of UBi iver U-boot.
by Akshay Srinivas 20 May '08

20 May '08

Hi all, I am new to U-boot.I want to implement UBI over U-boot and also want to port U-boot to one of our devices. Please provide some design documents and any other documents which will help me gain good understanding on U-boot.Provide me any info that will help me in understanding u-boot. Warm Regards, Akshay

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[U-Boot-Users] [PATCH 1/1] Fix 8313ERDB board configuration
by York Sun 19 May '08

19 May '08

Change LCRR clock ratio from 2 to 4 to commodate VSC7385. Correct TSEC1 vs TSEC2 assignment. Define ETHADDR and ETH1ADDR always. Signed-off-by: York Sun <yorksun(a)freescale.com> Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/configs/MPC8313ERDB.h | 14 ++++++-------- 1 files changed, 6 insertions(+), 8 deletions(-) diff --git a/include/configs/MPC8313ERDB.h b/include/configs/MPC8313ERDB.h index 6eec240..f9fa535 100644 --- a/include/configs/MPC8313ERDB.h +++ b/include/configs/MPC8313ERDB.h @@ -42,9 +42,12 @@ /* * On-board devices + * + * TSEC1 is VSC switch + * TSEC2 is SoC TSEC */ #define CONFIG_VSC7385_ENET - +#define CONFIG_TSEC2 #ifdef CFG_66MHZ #define CONFIG_83XX_CLKIN 66666667 /* in Hz */ @@ -80,7 +83,7 @@ #ifdef CONFIG_VSC7385_ENET -#define CONFIG_TSEC2 +#define CONFIG_TSEC1 /* The flash address and size of the VSC7385 firmware image */ #define CONFIG_VSC7385_IMAGE 0xFE7FE000 @@ -209,7 +212,7 @@ /* * Local Bus LCRR and LBCR regs */ -#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_2 /* 0x00010002 */ +#define CFG_LCRR LCRR_EADC_1 | LCRR_CLKDIV_4 #define CFG_LBC_LBCR ( 0x00040000 /* TODO */ \ | (0xFF << LBCR_BMT_SHIFT) \ | 0xF ) /* 0x0004ff0f */ @@ -523,13 +526,8 @@ */ #define CONFIG_ENV_OVERWRITE -#ifdef CONFIG_HAS_ETH0 #define CONFIG_ETHADDR 00:E0:0C:00:95:01 -#endif - -#ifdef CONFIG_HAS_ETH1 #define CONFIG_ETH1ADDR 00:E0:0C:00:95:02 -#endif #define CONFIG_IPADDR 10.0.0.2 #define CONFIG_SERVERIP 10.0.0.1 -- 1.5.2.2

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[U-Boot-Users] New board support patches
by Ronald Madrid 19 May '08

19 May '08

Hello, I have two questions. First, is there any particular way the patches should be created for the submission of code for supporting a new board? Second, this is a question for the Freescale maintainers, my board is based on the 8313erdb, and will only support NAND flash as its boot ROM. Is there a reason that the NAND support (patches) that was delivered with the BSP were not ever included into the u-boot project? Ron _________________________________________________________________ Change the world with e-mail. Join the i’m Initiative from Microsoft. http://im.live.com/Messenger/IM/Join/Default.aspx?source=EML_WL_ChangeWorld

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[U-Boot-Users] U-Boot 1.3.3 release
by Wolfgang Denk 19 May '08

19 May '08

Hi everybody, U-Boot v1.3.3 has been released and is available from the git repository and the FTP server. The Merge Window for v1.3.3 is open until June 03, 23:59:59 MET. Release v1.3.4 is scheduled for July 14, but you know that you better don't hold your breath. A little statistics [1] - changes since release v1.3.2: Processed 715 csets from 89 developers 36 employers found A total of 97852 lines added, 54112 removed (delta 43740) Compare v1.3.2: 858 csets from 101 developers 34 employers found A total of 180495 lines added, 55592 removed (delta 124903) Developers with the most changesets Marian Balakowicz 68 (9.5%) Wolfgang Denk 63 (8.8%) Stefan Roese 63 (8.8%) Kumar Gala 35 (4.9%) Jean-Christophe PLAGNIOL-VILLARD 28 (3.9%) Yuri Tikhonov 27 (3.8%) Mike Frysinger 21 (2.9%) Shinya Kuribayashi 20 (2.8%) Dave Liu 19 (2.7%) Guennadi Liakhovetski 18 (2.5%) ... Developers with the most changed lines Daniel Hellstrom 15355 (13.3%) Mike Frysinger 12971 (11.3%) Marian Balakowicz 11749 (10.2%) Wolfgang Denk 9460 (8.2%) Jon Loeliger 8712 (7.6%) Sascha Hauer 7498 (6.5%) Stefan Roese 4725 (4.1%) Matthias Fuchs 3942 (3.4%) Dave Liu 3574 (3.1%) Stelian Pop 3565 (3.1%) ... Developers with the most lines removed Mike Frysinger 7579 (14.0%) Matthias Fuchs 443 (0.8%) TsiChung Liew 379 (0.7%) Jason Wessel 233 (0.4%) Kim Phillips 218 (0.4%) Jerry Van Baren 186 (0.3%) David Gibson 53 (0.1%) Dirk Behme 25 (0.0%) dirk.behme(a)googlemail.com 24 (0.0%) Markus Klotzbuecher 13 (0.0%) ... Developers with the most signoffs (total 1697) Wolfgang Denk 138 (9.3%) Stefan Roese 135 (9.1%) Marian Balakowicz 134 (9.0%) Kumar Gala 85 (5.7%) Jean-Christophe PLAGNIOL-VILLARD 60 (4.0%) Guennadi Liakhovetski 59 (4.0%) Yuri Tikhonov 51 (3.4%) Shinya Kuribayashi 43 (2.9%) Kim Phillips 42 (2.8%) Bartlomiej Sieka 41 (2.8%) ... Top changeset contributors by employer DENX 223 (31.2%) Freescale 112 (15.7%) SemiHalf 90 (12.6%) (Unknown) 84 (11.7%) jcrosoft 28 (3.9%) Emcraft 28 (3.9%) ADI 21 (2.9%) MontaVista 18 (2.5%) ESD Electronics 15 (2.1%) Gaisler Research 14 (2.0%) ... Top lines changed by employer DENX 22339 (19.4%) Freescale 17140 (14.9%) Gaisler Research 15355 (13.3%) SemiHalf 13403 (11.6%) ADI 13136 (11.4%) (Unknown) 8217 (7.1%) Pengutronix 7498 (6.5%) ESD Electronics 4604 (4.0%) Renesas Technology 3133 (2.7%) Emcraft 2642 (2.3%) ... [1] See http://www.denx.de/wiki/UBoot/UbootStat_1_3_3 for full statistics, and http://www.denx.de/wiki/UBoot/ReleaseCycle for links to statistics for earlier releases. Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany As usual, this being a 1.3.x release, I haven't even compiled this kernel yet. So if it works, you should be doubly impressed. - Linus Torvalds in <199506181536.SAA10638(a)keos.cs.Helsinki.FI>

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[U-Boot-Users] [PATCH V2] PPC4xx: Unify ECC Initialization Routines
by Grant Erickson 19 May '08

19 May '08

This patch continues laying the ground work for moving out-of-assembly and unifying the SDRAM initialization code for PowerPC 405EX[r]-based boards. To do so, this deduces by one the number of nearly-identical DRAM ECC initialization implementations for PowerPC 4xx processors utilizing a DDR/DDR2 SDRAM controller by merging two of them into a common, shared implementation. The last revision of this patch failed to compile on 440ERX/GPX systems, so the appropriate preprocessor wrappers were added to address it. Signed-off-by: Grant Erickson <gerickson(a)nuovations.com> --- cpu/ppc4xx/44x_spd_ddr.c | 51 ++------------------ cpu/ppc4xx/Makefile | 1 + cpu/ppc4xx/ecc.c | 119 ++++++++++++++++++++++++++++++++++++++++++++++ cpu/ppc4xx/ecc.h | 42 ++++++++++++++++ cpu/ppc4xx/sdram.c | 46 +----------------- 5 files changed, 170 insertions(+), 89 deletions(-) create mode 100644 cpu/ppc4xx/ecc.c create mode 100644 cpu/ppc4xx/ecc.h diff --git a/cpu/ppc4xx/44x_spd_ddr.c b/cpu/ppc4xx/44x_spd_ddr.c index b9cf5cb..7f04ca6 100644 --- a/cpu/ppc4xx/44x_spd_ddr.c +++ b/cpu/ppc4xx/44x_spd_ddr.c @@ -53,6 +53,10 @@ #include <ppc4xx.h> #include <asm/mmu.h> +#ifdef CONFIG_DDR_ECC +#include "ecc.h" +#endif + #if defined(CONFIG_SPD_EEPROM) && \ (defined(CONFIG_440GP) || defined(CONFIG_440GX) || \ defined(CONFIG_440EP) || defined(CONFIG_440GR)) @@ -296,10 +300,6 @@ static void program_tr0(unsigned long *dimm_populated, unsigned long num_dimm_banks); static void program_tr1(void); -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes); -#endif - static unsigned long program_bxcr(unsigned long *dimm_populated, unsigned char *iic0_dimm_addr, unsigned long num_dimm_banks); @@ -418,7 +418,7 @@ long int spd_sdram(void) { /* * If ecc is enabled, initialize the parity bits. */ - program_ecc(total_size); + ecc_init(CFG_SDRAM_BASE, total_size); #endif return total_size; @@ -1402,45 +1402,4 @@ static unsigned long program_bxcr(unsigned long *dimm_populated, return(bank_base_addr); } - -#ifdef CONFIG_DDR_ECC -static void program_ecc(unsigned long num_bytes) -{ - unsigned long bank_base_addr; - unsigned long current_address; - unsigned long end_address; - unsigned long address_increment; - unsigned long cfg0; - - /* - * get Memory Controller Options 0 data - */ - mfsdram(mem_cfg0, cfg0); - - /* - * reset the bank_base address - */ - bank_base_addr = CFG_SDRAM_BASE; - - if ((cfg0 & SDRAM_CFG0_MCHK_MASK) != SDRAM_CFG0_MCHK_NON) { - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | SDRAM_CFG0_MCHK_GEN); - - if ((cfg0 & SDRAM_CFG0_DMWD_MASK) == SDRAM_CFG0_DMWD_32) - address_increment = 4; - else - address_increment = 8; - - current_address = (unsigned long)(bank_base_addr); - end_address = (unsigned long)(bank_base_addr) + num_bytes; - - while (current_address < end_address) { - *((unsigned long*)current_address) = 0x00000000; - current_address += address_increment; - } - - mtsdram(mem_cfg0, (cfg0 & ~SDRAM_CFG0_MCHK_MASK) | - SDRAM_CFG0_MCHK_CHK); - } -} -#endif /* CONFIG_DDR_ECC */ #endif /* CONFIG_SPD_EEPROM */ diff --git a/cpu/ppc4xx/Makefile b/cpu/ppc4xx/Makefile index 178c5c6..800bb41 100644 --- a/cpu/ppc4xx/Makefile +++ b/cpu/ppc4xx/Makefile @@ -45,6 +45,7 @@ COBJS += cpu.o COBJS += cpu_init.o COBJS += denali_data_eye.o COBJS += denali_spd_ddr2.o +COBJS += ecc.o COBJS += fdt.o COBJS += gpio.o COBJS += i2c.o diff --git a/cpu/ppc4xx/ecc.c b/cpu/ppc4xx/ecc.c new file mode 100644 index 0000000..dd45b50 --- /dev/null +++ b/cpu/ppc4xx/ecc.c @@ -0,0 +1,119 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * + * Copyright (c) 2005-2007 DENX Software Engineering, GmbH + * Stefan Roese <sr(a)denx.de> + * + * Copyright (c) 2002 Artesyn Technology + * Jun Gu <jung(a)artesyncp.com> + * + * Copyright (c) 2001 Wave 7 Optics + * Bill Hunter <williamhunter(a)attbi.com>x + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements generic DRAM ECC initialization for + * PowerPC processors using a SDRAM DDR/DDR2 controller, + * including the 405EX(r), 440GP/GX/EP/GR, 440SP(E), and + * 460EX/GT. + */ + +#include <common.h> +#include <ppc4xx.h> +#include <ppc_asm.tmpl> +#include <ppc_defs.h> +#include <asm/processor.h> + +#include "ecc.h" + +#if !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) +#if defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) +/* + * void ecc_init() + * + * Description: + * This routine initializes a range of DRAM ECC memory with known + * data and enables ECC checking. + * + * TO DO: + * Improve performance by utilizing cache. + * + * Input(s): + * start - A pointer to the start of memory covered by ECC requiring + * initialization. + * size - The size, in bytes, of the memory covered by ECC requiring + * initialization. + * + * Output(s): + * start - A pointer to the start of memory covered by ECC with + * CFG_ECC_PATTERN written to all locations and ECC data + * primed. + * + * Returns: + * N/A + */ +void ecc_init(unsigned long * const start, unsigned long size) +{ + const unsigned long pattern = CFG_ECC_PATTERN; + unsigned * const end = (unsigned long * const)((long)start + size); + unsigned long * current = start; + unsigned long mcopt1; + long increment; + + if (start >= end) + return; + + mfsdram(SDRAM_MCOPT1, mcopt1); + + /* Enable ECC generation without checking or reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_GEN)); + + increment = sizeof(u32); + +#if defined(CONFIG_440) + /* + * Look at the geometry of SDRAM (data width) to determine whether we + * can skip words when writing. + */ + + if ((mcopt1 & SDRAM_MCOPT1_DMWD_MASK) != SDRAM_MCOPT1_DMWD_32) + increment = sizeof(u64); +#endif /* defined(CONFIG_440) */ + + while (current < end) { + *current = pattern; + current = (unsigned long *)((long)current + increment); + } + + /* Wait until the writes are finished. */ + + sync(); + eieio(); + + /* Enable ECC generation with checking and no reporting */ + + mtsdram(SDRAM_MCOPT1, ((mcopt1 & ~SDRAM_MCOPT1_MCHK_MASK) | + SDRAM_MCOPT1_MCHK_CHK)); +} +#endif /* defined(CONFIG_DDR_ECC) || defined(CONFIG_SDRAM_ECC) */ +#endif /* !defined(CONFIG_440EPX) && !defined(CONFIG_440GRX) */ diff --git a/cpu/ppc4xx/ecc.h b/cpu/ppc4xx/ecc.h new file mode 100644 index 0000000..da1c4fd --- /dev/null +++ b/cpu/ppc4xx/ecc.h @@ -0,0 +1,42 @@ +/* + * Copyright (c) 2008 Nuovation System Designs, LLC + * Grant Erickson <gerickson(a)nuovations.com> + * + * Copyright (c) 2007 DENX Software Engineering, GmbH + * Stefan Roese <sr(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will abe useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Description: + * This file implements ECC initialization for PowerPC processors + * using the SDRAM DDR2 controller, including the 405EX(r), + * 440SP(E), 460EX and 460GT. + * + */ + +#ifndef _ECC_H_ +#define _ECC_H_ + +#if !defined(CFG_ECC_PATTERN) +#define CFG_ECC_PATTERN 0x00000000 +#endif /* !defined(CFG_ECC_PATTERN) */ + +extern void ecc_init(unsigned long * const start, unsigned long size); + +#endif /* _ECC_H_ */ diff --git a/cpu/ppc4xx/sdram.c b/cpu/ppc4xx/sdram.c index 2724d91..bd0a827 100644 --- a/cpu/ppc4xx/sdram.c +++ b/cpu/ppc4xx/sdram.c @@ -31,6 +31,9 @@ #include <ppc4xx.h> #include <asm/processor.h> #include "sdram.h" +#ifdef CONFIG_SDRAM_ECC +#include "ecc.h" +#endif #ifdef CONFIG_SDRAM_BANK0 @@ -332,49 +335,6 @@ static void sdram_tr1_set(int ram_address, int* tr1_value) *tr1_value = (first_good + last_bad) / 2; } -#ifdef CONFIG_SDRAM_ECC -static void ecc_init(ulong start, ulong size) -{ - ulong current_addr; /* current byte address */ - ulong end_addr; /* end of memory region */ - ulong addr_inc; /* address skip between writes */ - ulong cfg0_reg; /* for restoring ECC state */ - - /* - * TODO: Enable dcache before running this test (speedup) - */ - - mfsdram(mem_cfg0, cfg0_reg); - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_GEN); - - /* - * look at geometry of SDRAM (data width) to determine whether we - * can skip words when writing - */ - if ((cfg0_reg & SDRAM_CFG0_DRAMWDTH) == SDRAM_CFG0_DRAMWDTH_32) - addr_inc = 4; - else - addr_inc = 8; - - current_addr = start; - end_addr = start + size; - - while (current_addr < end_addr) { - *((ulong *)current_addr) = 0x00000000; - current_addr += addr_inc; - } - - /* - * TODO: Flush dcache and disable it again - */ - - /* - * Enable ecc checking and parity errors - */ - mtsdram(mem_cfg0, (cfg0_reg & ~SDRAM_CFG0_MEMCHK) | SDRAM_CFG0_MEMCHK_CHK); -} -#endif - /* * Autodetect onboard DDR SDRAM on 440 platforms * -- 1.5.4.3

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