March 2008 - U-Boot

Re: [U-Boot-Users] FPGA mess
by Stefan Roese 07 Mar '08

07 Mar '08

Andre, On Thursday 06 March 2008, Andre Schwarz wrote: > sorry for being impatient ... I'm just trying to get clean and universal > code with no need for recoding twice a year. No problem. > Stefan Roese schrieb: > > Andre, > > > > On Wednesday 05 March 2008, Andre Schwarz wrote: > >> you're listed as maintainer for the alpr board. > > > > Correct. But I didn't use this board for quite some time > > ok - no problem. I just need to start somewhere. Good. > >> It's the only board that uses the ACEX1K.c file for FPGA loading... > > > > Does it? To use this file you have to define CONFIG_FPGA_ACEX1K. I don't > > see it defined anywhere in the whole U-Boot tree. So perhaps this code is > > not used at all. > > correct - so you can kick it away. If no official board uses it and it looks broken to you, then please send a patch to remove it. > There's a include/ACEX1K.h that introduces two interfaces for obviously > the same funtionality. > The first one is specific to ACEX1K and the other one is a general > cyclone implementation as it should be. Please clean it up too. > >> I'm quite sure there are many boards with Altera FPGAs outside and can't > >> believe they have all mounted > >> platform flashes and therefore don't use u-boot for loading the FPGA. > >> Nevertheless those board don't show up in the tree. Maybe they all keep > >> their own patches like me ... > > > > Maybe. I suggest you start pushing your code to change this situation. :) > > I've been trying to submit patches for years now - there's always a > point when you give up. > If there's a will to change this and to discard unused/scrambled code > I'll provide a patch as soon as my board is up and running. As you may know, we changed our development infrastructure by adding submaintainers (custodians) for subsystems. Currently this is working not perfect, but seems to get better over the time. So we are improving here. Unfortunately we don't have a custodian for the FPGA stuff. Since it's getting more and more complex, it would be great if somebody would step up here. Any volunteers? :) > >> There are some points that doesn't seem to work out very well in > >> general. This is where some questions come up (top->down) : > >> > >> common/cmd_fpga: > >> In function do_fpga there's a used environment variable "fpgadata" that > >> obviously stores the location of the bitstream. > >> What sense does this make if the "data_size" parameter (=arg4) is _not_ > >> optional ? > >> Instead the command "fpga load 0 0x..." leads to a load function with > >> zero length. > >> The user always has to supply all 4 args (load, nr, data, size). > >> Of course the loading function could use the pre-defined bitstream size > >> from the header or the device struct... > > > > I have to admit that I don't understand what you are really asking here. > > Please ask more specific questions. Or send a patch to fix something that > > is "broken". > > ok - you'll get a patch. > The point is that it makes no sense to provide a function "fpga" > (declared in common/cmd_fpga) that accepts up to 4 args with > arg2 and arg3 being optional and arg4 not ... Right. With this description it makes sense to me. But we have to be careful here, not to change the command syntax in a non backward compatible way. > >> common/altera.c > >> What's that ACEX1K ? Isn't it a Cyclone chip and should use that > >> interface ? Why does this need special treatment throughout the > >> interface ? > > > > I didn't introduce this file. Perhaps we should ask the author who > > committed this code. > > ok - can you do this ? Yes. Steven Scholz as original author is on CC. > >> include/ACEX1K.h > >> Obviously there are some confusions about the various file formats and > >> sizes that can be output > >> from Altera's SoPC Builder. Compression is also possible with > >> de-compression on the fly during load ... > >> Of course the defined file sizes should match a raw bit file that > >> represents the true size of the device. > >> > >> Why is ACEX1K and Cyclone not merged ? > > > > No idea. If you have some fixes, please send patches. > > > >> Does _any_ real board use the Altera path ? scanning the config files > >> ... no. > > > > alpr seems to use the cyclone2.c code. > > no - it uses common/ACEX1K.c .... and common/cyclon2.c is derived from it. No, it doesn't use common/ACEX1K.c. > >> CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted > >> during preparation. This code can't work. > > > > No idea. I have to admit, that I didn't implement the FPGA booting on > > this board. But it seems to work fine. > > yes - because it's a board specific implementation with an "general" > interface. ??? > >> Is there any interest in getting this fixed ? > > > > Sure. > > But implementing the Altera path in a clean way means discarding the > ACEX1K and breaking the alpr borad. > I'm quite sure that Wolfgang will reject those changes. Yes, I will reject this too. :) > How can we solve this ? By trying to solve it in a compatible way. I added Heiko Schocher to CC too, since he was responsible for the FPGA booting implementation of the alpr board. > >> What about Liberty's Stratix code ? It's living and working ! > > > > Sorry, but I have no clue what "Liberty's Stratix code" is. > > Look out for mails from "eran.liberty". Stratix and Arria are high-end > FPGA families from Altera. > There's some work left to get those chips implemented well. Sorry, I currently don't have the time to read through this whole email thread. Please write an answer to this thread if you have some comments there. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

4 6

[U-Boot-Users] I want to port IXDP425 to another board wrv54g(IXP425 processor)
by Ajit Mittal 07 Mar '08

07 Mar '08

I want to port IXDP425(available in U-boot) to another board(linksys wrv54g(IXP425 processor) Here is the details for wrv54g Flash: It has 8Mb flash (0x50000000 - 0x50800000). Flash chip is TE28F640J3(CFI compatible)) RAM 32 MB RAM(0x00000000 - 0x02000000) GPIO 0 - Power LED (a) 1 - Internet LED 2 - Power LED (b) 3 - Factory reset button 4 - DMZ LED 5 - SPIS_N 6 - SPID 7 - SPIC 8 - LED (not populated but could be) 9 - Wireless-G LED 10 - PCI INTB 11 - PCI INTA 12 - SPIQ 13 - PCI reset 14 - PCI clock 15 - IXP expansion bus clock Pleae guide. How to modify the files in Uboot. I have downloaded the Uboot sources. Need hand in porting. Thanks Ajit

1 0

[U-Boot-Users] [PATCH] 837xEMDS: Improve the system performance
by Dave Liu 07 Mar '08

07 Mar '08

1. Make the CSB bus pipeline depth as 4, and enable the repeat mode; 2. Raise the eTSEC emergency priority; 3. Use the highest IP blocks clock. Signed-off-by: Dave Liu <daveliu(a)freescale.com> --- include/configs/MPC837XEMDS.h | 10 +++++++++- 1 files changed, 9 insertions(+), 1 deletions(-) diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 61de084..2222ef2 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -84,11 +84,19 @@ HRCWH_LDP_CLEAR) #endif +/* Arbiter Configuration Register */ +#define CFG_ACR_PIPE_DEP 3 /* Arbiter pipeline depth is 4 */ +#define CFG_ACR_RPTCNT 3 /* Arbiter repeat count is 4 */ + +/* System Priority Control Register */ +#define CFG_SPCR_TSECEP 3 /* eTSEC1/2 emergency has highest priority */ + /* - * eTSEC Clock Config + * IP blocks clock configuration */ #define CFG_SCCR_TSEC1CM 1 /* CSB:eTSEC1 = 1:1 */ #define CFG_SCCR_TSEC2CM 1 /* CSB:eTSEC2 = 1:1 */ +#define CFG_SCCR_SATACM SCCR_SATACM_1 /* CSB:SATA[0:3] = 1:1 */ /* * System IO Config -- 1.5.4.rc4

4 5

[U-Boot-Users] ARM: test_and_set_bit
by Scott McNutt 06 Mar '08

06 Mar '08

In asm-arm/bitops.h: The test_and_set_bit() function is declared, but not implemented inline as in other architectures. However, the function __test_and_set_bit() is defined (inline) but never referenced. From a practical point-of-view, this only appears to affect ext2_set_bit() as used in net/tftp.c for Multicast TFTP. Does anyone see any reason why we can't just remove the leading underscores for the __test_and_xxx_bit routines in asm-arm/bitops.h ? i.e. is this just an oversight? ... or is there some other motivation that I don't understand (yet)? ;-) Regards, --Scott

1 0

[U-Boot-Users] dcache on ads5121e
by Kenneth Johansson 06 Mar '08

06 Mar '08

Using HEAD 6bc113886d7d316df1a4e459bec8baf027518551 When I set CONFIG_CMD_CACHE and then use the command "dcache on" to turn on cache I lose the serial port. u-boot is now just spinning on the serial receive but it never gets any input. Anybody run with caches on ??

2 2

[U-Boot-Users] [PATCH] Replace "run load; run update" with conditionalized "run load update".
by Detlev Zundel 06 Mar '08

06 Mar '08

The latter version stops when "run load" fails for whatever reasons rendering the combination *a lot* more secure. Signed-off-by: Detlev Zundel <dzu(a)denx.de> --- include/configs/MPC8349EMDS.h | 2 +- include/configs/P3G4.h | 2 +- include/configs/TQM8272.h | 2 +- include/configs/TQM834x.h | 2 +- include/configs/TQM85xx.h | 2 +- include/configs/alpr.h | 2 +- include/configs/bamboo.h | 2 +- include/configs/bubinga.h | 2 +- include/configs/ebony.h | 2 +- include/configs/hcu4.h | 2 +- include/configs/hcu5.h | 2 +- include/configs/ixdpg425.h | 2 +- include/configs/katmai.h | 2 +- include/configs/korat.h | 2 +- include/configs/luan.h | 2 +- include/configs/lwmon5.h | 2 +- include/configs/ocotea.h | 2 +- include/configs/p3mx.h | 2 +- include/configs/p3p440.h | 2 +- include/configs/pcs440ep.h | 2 +- include/configs/pdnb3.h | 2 +- include/configs/sbc8349.h | 2 +- include/configs/sequoia.h | 2 +- include/configs/taihu.h | 2 +- include/configs/taishan.h | 2 +- include/configs/walnut.h | 2 +- include/configs/yosemite.h | 2 +- include/configs/yucca.h | 4 ++-- 28 files changed, 29 insertions(+), 29 deletions(-) diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index b98d8b1..07fefec 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -739,7 +739,7 @@ "load=tftp 100000 /tftpboot/mpc8349emds/u-boot.bin\0" \ "update=protect off fe000000 fe03ffff; " \ "era fe000000 fe03ffff; cp.b 100000 fe000000 ${filesize}\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "fdtaddr=400000\0" \ "fdtfile=mpc8349emds.dtb\0" \ "" diff --git a/include/configs/P3G4.h b/include/configs/P3G4.h index 74ef470..e85e1b9 100644 --- a/include/configs/P3G4.h +++ b/include/configs/P3G4.h @@ -110,7 +110,7 @@ "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ "cp.b 100000 fff00000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM8272.h b/include/configs/TQM8272.h index 9e408f4..ba0402d 100644 --- a/include/configs/TQM8272.h +++ b/include/configs/TQM8272.h @@ -87,7 +87,7 @@ "cp.b 300000 40000000 40000;" \ "setenv filesize;saveenv\0" \ "cphwib=cp.b 4003fc00 33fc00 400\0" \ - "upd=run load;run cphwib;run update\0" \ + "upd=run load cphwib update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM834x.h b/include/configs/TQM834x.h index c7b38a2..02a16ac 100644 --- a/include/configs/TQM834x.h +++ b/include/configs/TQM834x.h @@ -528,7 +528,7 @@ extern int tqm834x_num_flash_banks; "load=tftp 100000 /tftpboot/tqm834x/u-boot.bin\0" \ "update=protect off 80000000 8003ffff; " \ "era 80000000 8003ffff; cp.b 100000 80000000 40000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index dd0654b..21e8baf 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -468,7 +468,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/alpr.h b/include/configs/alpr.h index cfe08c8..38fb7c6 100644 --- a/include/configs/alpr.h +++ b/include/configs/alpr.h @@ -166,7 +166,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "ethprime=ppc_4xx_eth3\0" \ "ethact=ppc_4xx_eth3\0" \ "autoload=no\0" \ diff --git a/include/configs/bamboo.h b/include/configs/bamboo.h index f9ffa49..4ea040b 100644 --- a/include/configs/bamboo.h +++ b/include/configs/bamboo.h @@ -276,7 +276,7 @@ "update=protect off fffa0000 ffffffff;era fffa0000 ffffffff;" \ "cp.b 100000 fffa0000 60000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/bubinga.h b/include/configs/bubinga.h index bec03d4..784e7c0 100644 --- a/include/configs/bubinga.h +++ b/include/configs/bubinga.h @@ -111,7 +111,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" diff --git a/include/configs/ebony.h b/include/configs/ebony.h index 3e4aee4..88fd7ca 100644 --- a/include/configs/ebony.h +++ b/include/configs/ebony.h @@ -184,7 +184,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/hcu4.h b/include/configs/hcu4.h index e29cfe7..5a85feb 100644 --- a/include/configs/hcu4.h +++ b/include/configs/hcu4.h @@ -192,7 +192,7 @@ "load=tftp 100000 hcu4/u-boot.bin\0" \ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \ "cp.b 100000 FFFB0000 50000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "vx_rom=hcu4/hcu4_vx_rom\0" \ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ diff --git a/include/configs/hcu5.h b/include/configs/hcu5.h index 8c26613..2ed8530 100644 --- a/include/configs/hcu5.h +++ b/include/configs/hcu5.h @@ -199,7 +199,7 @@ "load=tftp 100000 hcu5/u-boot.bin\0" \ "update=protect off FFFB0000 FFFFFFFF;era FFFB0000 FFFFFFFF;" \ "cp.b 100000 FFFB0000 50000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "vx_rom=hcu5/hcu5_vx_rom\0" \ "vx=tftp ${loadaddr} ${vx_rom};run vxargs; bootvx\0" \ "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ diff --git a/include/configs/ixdpg425.h b/include/configs/ixdpg425.h index 465eaa2..a3be0b5 100644 --- a/include/configs/ixdpg425.h +++ b/include/configs/ixdpg425.h @@ -168,7 +168,7 @@ "update=protect off 50000000 5003ffff;era 50000000 5003ffff;" \ "cp.b 100000 50000000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" diff --git a/include/configs/katmai.h b/include/configs/katmai.h index b28236b..21b2604 100644 --- a/include/configs/katmai.h +++ b/include/configs/katmai.h @@ -209,7 +209,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b ${fileaddr} fffc0000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "kozio=bootm ffc60000\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:RP:RP\0" \ diff --git a/include/configs/korat.h b/include/configs/korat.h index 88e50d7..dcec9b0 100644 --- a/include/configs/korat.h +++ b/include/configs/korat.h @@ -202,7 +202,7 @@ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 200000 FFFA0000 60000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/luan.h b/include/configs/luan.h index 051252e..af237d9 100644 --- a/include/configs/luan.h +++ b/include/configs/luan.h @@ -182,7 +182,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/lwmon5.h b/include/configs/lwmon5.h index 97e8bf1..c3f10c7 100644 --- a/include/configs/lwmon5.h +++ b/include/configs/lwmon5.h @@ -219,7 +219,7 @@ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ "update=protect off FFF80000 FFFFFFFF;era FFF80000 FFFFFFFF;" \ "cp.b 200000 FFF80000 80000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "lwe_env=tftp 200000 /tftpboot.dev/lwmon5/env_uboot.bin;" \ "autoscr 200000\0" \ "" diff --git a/include/configs/ocotea.h b/include/configs/ocotea.h index 9f67993..5a6eb4a 100644 --- a/include/configs/ocotea.h +++ b/include/configs/ocotea.h @@ -199,7 +199,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/p3mx.h b/include/configs/p3mx.h index bec442d..45dc343 100644 --- a/include/configs/p3mx.h +++ b/include/configs/p3mx.h @@ -219,7 +219,7 @@ "update=protect off fff00000 fff3ffff;era fff00000 fff3ffff;" \ "cp.b 100000 fff00000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "serverip=11.0.0.152\0" #if defined (CONFIG_P3M750) diff --git a/include/configs/p3p440.h b/include/configs/p3p440.h index 139175e..82f2391 100644 --- a/include/configs/p3p440.h +++ b/include/configs/p3p440.h @@ -147,7 +147,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "unlock=yes\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" diff --git a/include/configs/pcs440ep.h b/include/configs/pcs440ep.h index b666964..893924b 100644 --- a/include/configs/pcs440ep.h +++ b/include/configs/pcs440ep.h @@ -172,7 +172,7 @@ "load=tftp 100000 /tftpboot/pcs440ep/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 100000 FFFA0000 60000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/pdnb3.h b/include/configs/pdnb3.h index 9d598fe..ed41b2f 100644 --- a/include/configs/pdnb3.h +++ b/include/configs/pdnb3.h @@ -170,7 +170,7 @@ "update=protect off 50000000 5007dfff;era 50000000 5007dfff;" \ "cp.b 100000 50000000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "ipaddr=10.0.0.233\0" \ "serverip=10.0.0.152\0" \ "netmask=255.255.0.0\0" \ diff --git a/include/configs/sbc8349.h b/include/configs/sbc8349.h index 2498b3e..d00c22f 100644 --- a/include/configs/sbc8349.h +++ b/include/configs/sbc8349.h @@ -688,7 +688,7 @@ "load=tftp 100000 /tftpboot/sbc8349/u-boot.bin\0" \ "update=protect off fff00000 fff3ffff; " \ "era fff00000 fff3ffff; cp.b 100000 fff00000 ${filesize}\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "fdtaddr=400000\0" \ "fdtfile=sbc8349.dtb\0" \ "" diff --git a/include/configs/sequoia.h b/include/configs/sequoia.h index 92f1ee4..cc910de 100644 --- a/include/configs/sequoia.h +++ b/include/configs/sequoia.h @@ -284,7 +284,7 @@ "load=tftp 200000 /tftpboot/${hostname}/u-boot.bin\0" \ "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ "cp.b 200000 FFFA0000 60000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/taihu.h b/include/configs/taihu.h index a450c5b..7db9736 100644 --- a/include/configs/taihu.h +++ b/include/configs/taihu.h @@ -99,7 +99,7 @@ "load=tftp 200000 /tftpboot/taihu/u-boot.bin\0" \ "update=protect off FFFC0000 FFFFFFFF;era FFFC0000 FFFFFFFF;" \ "cp.b 200000 FFFC0000 40000\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/taishan.h b/include/configs/taishan.h index 7662169..851a7ad 100644 --- a/include/configs/taishan.h +++ b/include/configs/taishan.h @@ -194,7 +194,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "fixedip=setenv bootargs $(bootargs) ip=$(ipaddr):$(serverip):" \ "$(gatewayip):$(netmask):$(hostname):$(netdev):off panic=1\0" \ "dhcp=setenv bootargs $(bootargs) ip=dhcp\0" \ diff --git a/include/configs/walnut.h b/include/configs/walnut.h index b83660c..f6e99ac 100644 --- a/include/configs/walnut.h +++ b/include/configs/walnut.h @@ -73,7 +73,7 @@ "update=protect off fffc0000 ffffffff;era fffc0000 ffffffff;" \ "cp.b 100000 fffc0000 40000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run net_nfs" diff --git a/include/configs/yosemite.h b/include/configs/yosemite.h index 225308f..c9323f6 100644 --- a/include/configs/yosemite.h +++ b/include/configs/yosemite.h @@ -209,7 +209,7 @@ "update=protect off fff80000 ffffffff;era fff80000 ffffffff;" \ "cp.b 200000 fff80000 80000;" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "" #define CONFIG_BOOTCOMMAND "run flash_self" diff --git a/include/configs/yucca.h b/include/configs/yucca.h index 9538c0d..1e3571e 100644 --- a/include/configs/yucca.h +++ b/include/configs/yucca.h @@ -175,7 +175,7 @@ "bootm ${kernel_addr} ${ramdisk_addr}\0" \ "net_nfs=tftp 200000 ${bootfile};run nfsargs addip addtty;" \ "bootm\0" \ - "rootpath=/opt/eldk/ppc_4xx\0" \ + "rootpath=/opt/eldk/ppc_4xx\0" \ "bootfile=yucca/uImage\0" \ "kernel_addr=E7F10000\0" \ "ramdisk_addr=E7F20000\0" \ @@ -184,7 +184,7 @@ "update=protect off 2:4-7;era 2:4-7;" \ "cp.b ${fileaddr} FFFB0000 ${filesize};" \ "setenv filesize;saveenv\0" \ - "upd=run load;run update\0" \ + "upd=run load update\0" \ "pciconfighost=1\0" \ "pcie_mode=RP:EP:EP\0" \ "" -- 1.5.4.2

3 4

[U-Boot-Users] [PATCH] new PHY @ e1000 - 2nd try
by Andre Schwarz 06 Mar '08

06 Mar '08

Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom. Signed-off-by: Andre Schwarz <andre.schwarz(a)matrix-vision.de> --- MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner diff --git a/README b/README index 491397a..d59d9b3 100644 --- a/README +++ b/README @@ -731,6 +731,9 @@ The following options need to be configured: CONFIG_E1000 Support for Intel 8254x gigabit chips. + CONFIG_E1000_FALLBACK_MAC + default MAC for empty eeprom after production. + CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index f0741da..4b1a39a 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1,5 +1,5 @@ /************************************************************************** -Inter Pro 1000 for ppcboot/das-u-boot +Intel Pro 1000 for ppcboot/das-u-boot Drivers are port from Intel's Linux driver e1000-4.3.15 and from Etherboot pro 1000 driver by mrakes at vivato dot net tested on both gig copper and gig fiber boards @@ -82,6 +82,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, }; /* Function forward declarations */ @@ -512,6 +513,11 @@ e1000_read_mac_addr(struct eth_device *nic) /* Invert the last bit if this is the second device */ nic->enetaddr[5] += 1; } +#ifdef CONFIG_E1000_FALLBACK_MAC + if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) + for ( i=0; i < NODE_ADDRESS_SIZE; i++ ) + nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff; +#endif #else /* * The AP1000's e1000 has no eeprom; the MAC address is stored in the @@ -639,6 +645,9 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_82546EB_FIBER: hw->mac_type = e1000_82546; break; + case E1000_DEV_ID_82541ER: + hw->mac_type = e1000_82541_rev_2; + break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; @@ -2485,6 +2494,36 @@ e1000_phy_reset(struct e1000_hw *hw) return 0; } +static int +e1000_set_phy_type(struct e1000_hw *hw) +{ + DEBUGFUNC(); + + if(hw->mac_type == e1000_undefined) + return -E1000_ERR_PHY_TYPE; + + switch(hw->phy_id) { + case M88E1000_E_PHY_ID: + case M88E1000_I_PHY_ID: + case M88E1011_I_PHY_ID: + hw->phy_type = e1000_phy_m88; + break; + case IGP01E1000_I_PHY_ID: + if(hw->mac_type == e1000_82541 || + hw->mac_type == e1000_82541_rev_2) { + hw->phy_type = e1000_phy_igp; + break; + } + /* Fall Through */ + default: + /* Should never have loaded on this device */ + hw->phy_type = e1000_phy_undefined; + return -E1000_ERR_PHY_TYPE; + } + + return E1000_SUCCESS; +} + /****************************************************************************** * Probes the expected PHY address for known PHY IDs * @@ -2493,6 +2532,7 @@ e1000_phy_reset(struct e1000_hw *hw) static int e1000_detect_gig_phy(struct e1000_hw *hw) { + int32_t phy_init_status; uint16_t phy_id_high, phy_id_low; int match = FALSE; @@ -2526,11 +2566,19 @@ e1000_detect_gig_phy(struct e1000_hw *hw) if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; break; + case e1000_82541_rev_2: + if(hw->phy_id == IGP01E1000_I_PHY_ID) + match = TRUE; + + break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); return -E1000_ERR_CONFIG; } - if (match) { + + phy_init_status = e1000_set_phy_type(hw); + + if ((match) && (phy_init_status == E1000_SUCCESS)) { DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); return 0; } @@ -2985,7 +3033,7 @@ e1000_initialize(bd_t * bis) free(nic); return 0; } -#ifndef CONFIG_AP1000 +#if !(defined(CONFIG_AP1000) || defined(CONFIG_MVBC_1G)) if (e1000_validate_eeprom_checksum(nic) < 0) { printf("The EEPROM Checksum Is Not Valid\n"); free(hw); diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 0fbdc90..c72517c 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -71,6 +71,8 @@ typedef enum { e1000_82540, e1000_82545, e1000_82546, + e1000_82541, + e1000_82541_rev_2, e1000_num_macs } e1000_mac_type; @@ -168,6 +170,13 @@ typedef enum { e1000_1000t_rx_status_undefined = 0xFF } e1000_1000t_rx_status; +typedef enum { + e1000_phy_m88 = 0, + e1000_phy_igp, + e1000_phy_igp_2, + e1000_phy_undefined = 0xFF +} e1000_phy_type; + struct e1000_phy_info { e1000_cable_length cable_length; e1000_10bt_ext_dist_enable extended_10bt_distance; @@ -184,14 +193,19 @@ struct e1000_phy_stats { }; /* Error Codes */ -#define E1000_SUCCESS 0 -#define E1000_ERR_EEPROM 1 -#define E1000_ERR_PHY 2 -#define E1000_ERR_CONFIG 3 -#define E1000_ERR_PARAM 4 -#define E1000_ERR_MAC_TYPE 5 -#define E1000_ERR_NOLINK 6 -#define E1000_ERR_TIMEOUT 7 +#define E1000_SUCCESS 0 +#define E1000_ERR_EEPROM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_TYPE 5 +#define E1000_ERR_PHY_TYPE 6 +#define E1000_ERR_NOLINK 7 +#define E1000_ERR_TIMEOUT 8 +#define E1000_ERR_RESET 9 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11 +#define E1000_BLK_PHY_RESET 12 /* PCI Device IDs */ #define E1000_DEV_ID_82542 0x1000 @@ -207,7 +221,8 @@ struct e1000_phy_stats { #define E1000_DEV_ID_82545EM_FIBER 0x1011 #define E1000_DEV_ID_82546EB_COPPER 0x1010 #define E1000_DEV_ID_82546EB_FIBER 0x1012 -#define NUM_DEV_IDS 13 +#define E1000_DEV_ID_82541ER 0x1078 +#define NUM_DEV_IDS 14 #define NODE_ADDRESS_SIZE 6 #define ETH_LENGTH_OF_ADDRESS 6 @@ -799,6 +814,8 @@ struct e1000_hw { pci_dev_t pdev; uint8_t *hw_addr; e1000_mac_type mac_type; + e1000_phy_type phy_type; + uint32_t phy_init_script; e1000_media_type media_type; e1000_lan_loc lan_loc; e1000_fc_type fc; @@ -1517,7 +1534,22 @@ struct e1000_hw { #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ -#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ + +/* IGP01E1000 specifics */ +#define IGP01E1000_IEEE_REGS_PAGE 0x0000 +#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 +#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 + +/* IGP01E1000 Specific Registers */ +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ +#define IGP02E1000_PHY_POWER_MGMT 0x19 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ /* PHY Control Register */ #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ @@ -1729,6 +1761,7 @@ struct e1000_hw { #define M88E1011_I_PHY_ID 0x01410C20 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID +#define IGP01E1000_I_PHY_ID 0x02A80380 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF diff --git a/include/pci_ids.h b/include/pci_ids.h index 3b10452..723583c 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1810,6 +1810,7 @@ #define PCI_DEVICE_ID_INTEL_82434 0x04a3 #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82542 0x1000 #define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001 #define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004

1 0

[U-Boot-Users] [PATCH] new PHY @ e1000
by Andre Schwarz 06 Mar '08

06 Mar '08

Add 82541ER device with latest integrated IGP2 PHY. Introduced CONFIG_E1000_FALLBACK_MAC for NIC bring-up with empty eeprom. regards, Andre Schwarz MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner diff --git a/README b/README index 491397a..d59d9b3 100644 --- a/README +++ b/README @@ -731,6 +731,9 @@ The following options need to be configured: CONFIG_E1000 Support for Intel 8254x gigabit chips. + CONFIG_E1000_FALLBACK_MAC + default MAC for empty eeprom after production. + CONFIG_EEPRO100 Support for Intel 82557/82559/82559ER chips. Optional CONFIG_EEPRO100_SROM_WRITE enables eeprom diff --git a/drivers/net/e1000.c b/drivers/net/e1000.c index f0741da..47f1bb0 100644 --- a/drivers/net/e1000.c +++ b/drivers/net/e1000.c @@ -1,5 +1,5 @@ /************************************************************************** -Inter Pro 1000 for ppcboot/das-u-boot +Intel Pro 1000 for ppcboot/das-u-boot Drivers are port from Intel's Linux driver e1000-4.3.15 and from Etherboot pro 1000 driver by mrakes at vivato dot net tested on both gig copper and gig fiber boards @@ -82,6 +82,7 @@ static struct pci_device_id supported[] = { {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82545EM_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82546EB_FIBER}, {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82540EM_LOM}, + {PCI_VENDOR_ID_INTEL, PCI_DEVICE_ID_INTEL_82541ER}, }; /* Function forward declarations */ @@ -512,6 +513,11 @@ e1000_read_mac_addr(struct eth_device *nic) /* Invert the last bit if this is the second device */ nic->enetaddr[5] += 1; } +#ifdef CONFIG_E1000_FALLBACK_MAC + if ( *(u32*)(nic->enetaddr) == 0 || *(u32*)(nic->enetaddr) == ~0 ) + for ( i=0; i < NODE_ADDRESS_SIZE; i++ ) + nic->enetaddr[i] = (CONFIG_E1000_FALLBACK_MAC >> (8*(5-i))) & 0xff; +#endif #else /* * The AP1000's e1000 has no eeprom; the MAC address is stored in the @@ -639,6 +645,9 @@ e1000_set_mac_type(struct e1000_hw *hw) case E1000_DEV_ID_82546EB_FIBER: hw->mac_type = e1000_82546; break; + case E1000_DEV_ID_82541ER: + hw->mac_type = e1000_82541_rev_2; + break; default: /* Should never have loaded on this device */ return -E1000_ERR_MAC_TYPE; @@ -2485,6 +2494,36 @@ e1000_phy_reset(struct e1000_hw *hw) return 0; } +static int +e1000_set_phy_type(struct e1000_hw *hw) +{ + DEBUGFUNC(); + + if(hw->mac_type == e1000_undefined) + return -E1000_ERR_PHY_TYPE; + + switch(hw->phy_id) { + case M88E1000_E_PHY_ID: + case M88E1000_I_PHY_ID: + case M88E1011_I_PHY_ID: + hw->phy_type = e1000_phy_m88; + break; + case IGP01E1000_I_PHY_ID: + if(hw->mac_type == e1000_82541 || + hw->mac_type == e1000_82541_rev_2) { + hw->phy_type = e1000_phy_igp; + break; + } + /* Fall Through */ + default: + /* Should never have loaded on this device */ + hw->phy_type = e1000_phy_undefined; + return -E1000_ERR_PHY_TYPE; + } + + return E1000_SUCCESS; +} + /****************************************************************************** * Probes the expected PHY address for known PHY IDs * @@ -2493,6 +2532,7 @@ e1000_phy_reset(struct e1000_hw *hw) static int e1000_detect_gig_phy(struct e1000_hw *hw) { + int32_t phy_init_status; uint16_t phy_id_high, phy_id_low; int match = FALSE; @@ -2526,11 +2566,19 @@ e1000_detect_gig_phy(struct e1000_hw *hw) if (hw->phy_id == M88E1011_I_PHY_ID) match = TRUE; break; + case e1000_82541_rev_2: + if(hw->phy_id == IGP01E1000_I_PHY_ID) + match = TRUE; + + break; default: DEBUGOUT("Invalid MAC type %d\n", hw->mac_type); return -E1000_ERR_CONFIG; } - if (match) { + + phy_init_status = e1000_set_phy_type(hw); + + if ((match) && (phy_init_status == E1000_SUCCESS)) { DEBUGOUT("PHY ID 0x%X detected\n", hw->phy_id); return 0; } diff --git a/drivers/net/e1000.h b/drivers/net/e1000.h index 0fbdc90..c72517c 100644 --- a/drivers/net/e1000.h +++ b/drivers/net/e1000.h @@ -71,6 +71,8 @@ typedef enum { e1000_82540, e1000_82545, e1000_82546, + e1000_82541, + e1000_82541_rev_2, e1000_num_macs } e1000_mac_type; @@ -168,6 +170,13 @@ typedef enum { e1000_1000t_rx_status_undefined = 0xFF } e1000_1000t_rx_status; +typedef enum { + e1000_phy_m88 = 0, + e1000_phy_igp, + e1000_phy_igp_2, + e1000_phy_undefined = 0xFF +} e1000_phy_type; + struct e1000_phy_info { e1000_cable_length cable_length; e1000_10bt_ext_dist_enable extended_10bt_distance; @@ -184,14 +193,19 @@ struct e1000_phy_stats { }; /* Error Codes */ -#define E1000_SUCCESS 0 -#define E1000_ERR_EEPROM 1 -#define E1000_ERR_PHY 2 -#define E1000_ERR_CONFIG 3 -#define E1000_ERR_PARAM 4 -#define E1000_ERR_MAC_TYPE 5 -#define E1000_ERR_NOLINK 6 -#define E1000_ERR_TIMEOUT 7 +#define E1000_SUCCESS 0 +#define E1000_ERR_EEPROM 1 +#define E1000_ERR_PHY 2 +#define E1000_ERR_CONFIG 3 +#define E1000_ERR_PARAM 4 +#define E1000_ERR_MAC_TYPE 5 +#define E1000_ERR_PHY_TYPE 6 +#define E1000_ERR_NOLINK 7 +#define E1000_ERR_TIMEOUT 8 +#define E1000_ERR_RESET 9 +#define E1000_ERR_MASTER_REQUESTS_PENDING 10 +#define E1000_ERR_HOST_INTERFACE_COMMAND 11 +#define E1000_BLK_PHY_RESET 12 /* PCI Device IDs */ #define E1000_DEV_ID_82542 0x1000 @@ -207,7 +221,8 @@ struct e1000_phy_stats { #define E1000_DEV_ID_82545EM_FIBER 0x1011 #define E1000_DEV_ID_82546EB_COPPER 0x1010 #define E1000_DEV_ID_82546EB_FIBER 0x1012 -#define NUM_DEV_IDS 13 +#define E1000_DEV_ID_82541ER 0x1078 +#define NUM_DEV_IDS 14 #define NODE_ADDRESS_SIZE 6 #define ETH_LENGTH_OF_ADDRESS 6 @@ -799,6 +814,8 @@ struct e1000_hw { pci_dev_t pdev; uint8_t *hw_addr; e1000_mac_type mac_type; + e1000_phy_type phy_type; + uint32_t phy_init_script; e1000_media_type media_type; e1000_lan_loc lan_loc; e1000_fc_type fc; @@ -1517,7 +1534,22 @@ struct e1000_hw { #define M88E1000_EXT_PHY_SPEC_CTRL 0x14 /* Extended PHY Specific Control */ #define M88E1000_RX_ERR_CNTR 0x15 /* Receive Error Counter */ -#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ +#define MAX_PHY_REG_ADDRESS 0x1F /* 5 bit address bus (0-0x1F) */ + +/* IGP01E1000 specifics */ +#define IGP01E1000_IEEE_REGS_PAGE 0x0000 +#define IGP01E1000_IEEE_RESTART_AUTONEG 0x3300 +#define IGP01E1000_IEEE_FORCE_GIGA 0x0140 + +/* IGP01E1000 Specific Registers */ +#define IGP01E1000_PHY_PORT_CONFIG 0x10 /* PHY Specific Port Config Register */ +#define IGP01E1000_PHY_PORT_STATUS 0x11 /* PHY Specific Status Register */ +#define IGP01E1000_PHY_PORT_CTRL 0x12 /* PHY Specific Control Register */ +#define IGP01E1000_PHY_LINK_HEALTH 0x13 /* PHY Link Health Register */ +#define IGP01E1000_GMII_FIFO 0x14 /* GMII FIFO Register */ +#define IGP01E1000_PHY_CHANNEL_QUALITY 0x15 /* PHY Channel Quality Register */ +#define IGP02E1000_PHY_POWER_MGMT 0x19 +#define IGP01E1000_PHY_PAGE_SELECT 0x1F /* PHY Page Select Core Register */ /* PHY Control Register */ #define MII_CR_SPEED_SELECT_MSB 0x0040 /* bits 6,13: 10=1000, 01=100, 00=10 */ @@ -1729,6 +1761,7 @@ struct e1000_hw { #define M88E1011_I_PHY_ID 0x01410C20 #define M88E1000_12_PHY_ID M88E1000_E_PHY_ID #define M88E1000_14_PHY_ID M88E1000_E_PHY_ID +#define IGP01E1000_I_PHY_ID 0x02A80380 /* Miscellaneous PHY bit definitions. */ #define PHY_PREAMBLE 0xFFFFFFFF diff --git a/include/pci_ids.h b/include/pci_ids.h index 3b10452..723583c 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1810,6 +1810,7 @@ #define PCI_DEVICE_ID_INTEL_82434 0x04a3 #define PCI_DEVICE_ID_INTEL_I960 0x0960 #define PCI_DEVICE_ID_INTEL_I960RM 0x0962 +#define PCI_DEVICE_ID_INTEL_82541ER 0x1078 #define PCI_DEVICE_ID_INTEL_82542 0x1000 #define PCI_DEVICE_ID_INTEL_82543GC_FIBER 0x1001 #define PCI_DEVICE_ID_INTEL_82543GC_COPPER 0x1004

2 1

[U-Boot-Users] [Fwd: Re: FPGA mess]
by André Schwarz 06 Mar '08

06 Mar '08

forgot "cc" to list... Stefan, sorry for being impatient ... I'm just trying to get clean and universal code with no need for recoding twice a year. Stefan Roese schrieb: > Andre, > > On Wednesday 05 March 2008, Andre Schwarz wrote: > >> you're listed as maintainer for the alpr board. >> > > Correct. But I didn't use this board for quite some time > ok - no problem. I just need to start somewhere. >> It's the only board that uses the ACEX1K.c file for FPGA loading... >> > > Does it? To use this file you have to define CONFIG_FPGA_ACEX1K. I don't see > it defined anywhere in the whole U-Boot tree. So perhaps this code is not > used at all. > > correct - so you can kick it away. There's a include/ACEX1K.h that introduces two interfaces for obviously the same funtionality. The first one is specific to ACEX1K and the other one is a general cyclone implementation as it should be. >> I'm quite sure there are many boards with Altera FPGAs outside and can't >> believe they have all mounted >> platform flashes and therefore don't use u-boot for loading the FPGA. >> Nevertheless those board don't show up in the tree. Maybe they all keep >> their own patches like me ... >> > > Maybe. I suggest you start pushing your code to change this situation. :) > I've been trying to submit patches for years now - there's always a point when you give up. If there's a will to change this and to discard unused/scrambled code I'll provide a patch as soon as my board is up and running. > >> There are some points that doesn't seem to work out very well in general. >> This is where some questions come up (top->down) : >> >> common/cmd_fpga: >> In function do_fpga there's a used environment variable "fpgadata" that >> obviously stores the location of the bitstream. >> What sense does this make if the "data_size" parameter (=arg4) is _not_ >> optional ? >> Instead the command "fpga load 0 0x..." leads to a load function with >> zero length. >> The user always has to supply all 4 args (load, nr, data, size). >> Of course the loading function could use the pre-defined bitstream size >> from the header or the device struct... >> > > I have to admit that I don't understand what you are really asking here. > Please ask more specific questions. Or send a patch to fix something that > is "broken". > > ok - you'll get a patch. The point is that it makes no sense to provide a function "fpga" (declared in common/cmd_fpga) that accepts up to 4 args with arg2 and arg3 being optional and arg4 not ... >> common/altera.c >> What's that ACEX1K ? Isn't it a Cyclone chip and should use that interface >> ? Why does this need special treatment throughout the interface ? >> > > I didn't introduce this file. Perhaps we should ask the author who committed > this code. > > ok - can you do this ? >> include/ACEX1K.h >> Obviously there are some confusions about the various file formats and >> sizes that can be output >> from Altera's SoPC Builder. Compression is also possible with >> de-compression on the fly during load ... >> Of course the defined file sizes should match a raw bit file that >> represents the true size of the device. >> >> Why is ACEX1K and Cyclone not merged ? >> > > No idea. If you have some fixes, please send patches. > > >> Does _any_ real board use the Altera path ? scanning the config files >> ... no. >> > > alpr seems to use the cyclone2.c code. > > no - it uses common/ACEX1K.c .... and common/cyclon2.c is derived from it. >> CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted >> during preparation. This code can't work. >> > > No idea. I have to admit, that I didn't implement the FPGA booting on this > board. But it seems to work fine. > > yes - because it's a board specific implementation with an "general" interface. >> Is there any interest in getting this fixed ? >> > > Sure. > > But implementing the Altera path in a clean way means discarding the ACEX1K and breaking the alpr borad. I'm quite sure that Wolfgang will reject those changes. How can we solve this ? >> What about Liberty's Stratix code ? It's living and working ! >> > > Sorry, but I have no clue what "Liberty's Stratix code" is. > Look out for mails from "eran.liberty". Stratix and Arria are high-end FPGA families from Altera. There's some work left to get those chips implemented well. > Best regards, > Stefan > > ===================================================================== > DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel > HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany > Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de > ===================================================================== > MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

1 0

[U-Boot-Users] FPGA mess
by Andre Schwarz 06 Mar '08

06 Mar '08

Stefan, you're listed as maintainer for the alpr board. It's the only board that uses the ACEX1K.c file for FPGA loading... I'm quite sure there are many boards with Altera FPGAs outside and can't believe they have all mounted platform flashes and therefore don't use u-boot for loading the FPGA. Nevertheless those board don't show up in the tree. Maybe they all keep their own patches like me ... There are some points that doesn't seem to work out very well in general. This is where some questions come up (top->down) : common/cmd_fpga: In function do_fpga there's a used environment variable "fpgadata" that obviously stores the location of the bitstream. What sense does this make if the "data_size" parameter (=arg4) is _not_ optional ? Instead the command "fpga load 0 0x..." leads to a load function with zero length. The user always has to supply all 4 args (load, nr, data, size). Of course the loading function could use the pre-defined bitstream size from the header or the device struct... common/altera.c What's that ACEX1K ? Isn't it a Cyclone chip and should use that interface ? Why does this need special treatment throughout the interface ? include/ACEX1K.h Obviously there are some confusions about the various file formats and sizes that can be output from Altera's SoPC Builder. Compression is also possible with de-compression on the fly during load ... Of course the defined file sizes should match a raw bit file that represents the true size of the device. Why is ACEX1K and Cyclone not merged ? Does _any_ real board use the Altera path ? scanning the config files ... no. CYC2_ps_load in common/cyclon2.c the nCONFIG pin is never de-asserted during preparation. This code can't work. Is there any interest in getting this fixed ? What about Liberty's Stratix code ? It's living and working ! regards, Andre Schwarz MATRIX VISION GmbH, Talstraße 16, DE-71570 Oppenweiler - Registergericht: Amtsgericht Stuttgart, HRB 271090 Geschäftsführer: Gerhard Thullner, Werner Armingeon, Uwe Furtner

2 1