March 2008 - U-Boot

[U-Boot-Users] [PATCH] Add apollon board MAINTAINERS entry
by Kyungmin Park 14 Apr '08

14 Apr '08

Add apollon board MAINTAINERS entry Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/MAINTAINERS b/MAINTAINERS index e31ea06..35e532d 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -554,6 +554,10 @@ Richard Woodruff <r-woodruff2(a)ti.com> omap2420h4 ARM1136EJS +Kyungmin Park <kyungmin.park(a)samsung.com> + + apollon ARM1136EJS + Alex Z�pke <azu(a)sysgo.de> lart SA1100 diff --git a/include/configs/apollon.h b/include/configs/apollon.h index f101206..294cd26 100755 --- a/include/configs/apollon.h +++ b/include/configs/apollon.h @@ -1,5 +1,5 @@ /* - * (C) Copyright 2005-2007 + * (C) Copyright 2005-2008 * Samsung Electronics, * Kyungmin Park <kyungmin.park(a)samsung.com> * @@ -158,6 +158,7 @@ "norboot=cp32 0x18040000 0x80008000 0x200000; go 0x80008000\0" \ "oneboot=onenand read 0x80008000 0x40000 0x200000; go 0x80008000\0"\ "onesyncboot=run syncmode oneboot\0" \ + "updateb=tftp 0x80180000 u-boot-onenand.bin; onenand erase 0x0 0x20000; onenand write 0x80180000 0x0 0x20000\0" \ "bootcmd=run uboot\0" /*

2 1

[U-Boot-Users] [PATCH] Allow use of ARCH=powerpc when building
by Kumar Gala 14 Apr '08

14 Apr '08

The linux kernel is now mostly ARCH=powerpc, so to make life easier allow use to use ARCH=powerpc and convert it to ARCH=ppc. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- Identical to the patch 'Allow use to use ARCH=powerpc when building', but this one the subject makes a bit more sense. Makefile | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/Makefile b/Makefile index 4255cf5..46c4125 100644 --- a/Makefile +++ b/Makefile @@ -123,6 +123,10 @@ unexport CDPATH ######################################################################### +ifeq ($(ARCH),powerpc) +ARCH = ppc +endif + ifeq ($(obj)include/config.mk,$(wildcard $(obj)include/config.mk)) # load ARCH, BOARD, and CPU configuration -- 1.5.4.1

2 1

[U-Boot-Users] [PATCH] Fix OneNAND erase command
by Kyungmin Park 14 Apr '08

14 Apr '08

It mis-calculates the block address. Also fix DECLARE_GLOBAL_DATA_PTR in env_onenand. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/common/cmd_onenand.c b/common/cmd_onenand.c index dcda099..aff11d1 100644 --- a/common/cmd_onenand.c +++ b/common/cmd_onenand.c @@ -44,14 +44,28 @@ int do_onenand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) default: /* At least 4 args */ if (strncmp(argv[1], "erase", 5) == 0) { - struct erase_info instr; + struct erase_info instr = { + .callback = NULL, + }; ulong start, end; ulong block; - - start = simple_strtoul(argv[2], NULL, 10); - end = simple_strtoul(argv[3], NULL, 10); - start -= (unsigned long)onenand_chip.base; - end -= (unsigned long)onenand_chip.base; + char *endtail; + + if (strncmp(argv[2], "block", 5) == 0) { + start = simple_strtoul(argv[3], NULL, 10); + endtail = strchr(argv[3], '-'); + end = simple_strtoul(endtail + 1, NULL, 10); + } else { + start = simple_strtoul(argv[2], NULL, 10); + end = simple_strtoul(argv[3], NULL, 10); + start -= (unsigned long)onenand_chip.base; + end -= (unsigned long)onenand_chip.base; + + start >>= onenand_chip.erase_shift; + end >>= onenand_chip.erase_shift; + /* Don't include the end block */ + end--; + } if (!end || end < 0) end = start; diff --git a/common/env_onenand.c b/common/env_onenand.c index 5888f75..ac8a8c1 100644 --- a/common/env_onenand.c +++ b/common/env_onenand.c @@ -52,22 +52,21 @@ static unsigned char onenand_env[MAX_ONENAND_PAGESIZE]; env_t *env_ptr = (env_t *) onenand_env; #endif /* ENV_IS_EMBEDDED */ +DECLARE_GLOBAL_DATA_PTR; + uchar env_get_char_spec(int index) { - DECLARE_GLOBAL_DATA_PTR; - return (*((uchar *) (gd->env_addr + index))); } void env_relocate_spec(void) { - DECLARE_GLOBAL_DATA_PTR; unsigned long env_addr; int use_default = 0; size_t retlen; env_addr = CFG_ENV_ADDR; - env_addr -= (unsigned long)onenand_chip.base; + env_addr -= (unsigned long) onenand_chip.base; /* Check OneNAND exist */ if (onenand_mtd.oobblock) @@ -95,7 +94,9 @@ void env_relocate_spec(void) int saveenv(void) { unsigned long env_addr = CFG_ENV_ADDR; - struct erase_info instr; + struct erase_info instr = { + .callback = NULL, + }; size_t retlen; instr.len = CFG_ENV_SIZE; @@ -108,7 +109,7 @@ int saveenv(void) /* update crc */ env_ptr->crc = - crc32(0, env_ptr->data, onenand_mtd.oobblock - ENV_HEADER_SIZE); + crc32(0, env_ptr->data, ONENAND_ENV_SIZE(onenand_mtd)); env_addr -= (unsigned long)onenand_chip.base; if (onenand_write(&onenand_mtd, env_addr, onenand_mtd.oobblock, &retlen, @@ -122,8 +123,6 @@ int saveenv(void) int env_init(void) { - DECLARE_GLOBAL_DATA_PTR; - /* use default */ gd->env_addr = (ulong) & default_environment[0]; gd->env_valid = 1;

2 1

[U-Boot-Users] [PATCH] Fix OneNAND read
by Kyungmin Park 14 Apr '08

14 Apr '08

It should access with 16-bit instead of 8-bit Now it uses the generic memcpy with 8-bit access. It means it reads wrong data from OneNAND. Signed-off-by: Kyungmin Park <kyungmin.park(a)samsung.com> --- diff --git a/drivers/mtd/onenand/onenand_base.c b/drivers/mtd/onenand/onenand_base.c index 3b828fb..174384e 100644 --- a/drivers/mtd/onenand/onenand_base.c +++ b/drivers/mtd/onenand/onenand_base.c @@ -20,6 +20,19 @@ #include <asm/io.h> #include <asm/errno.h> +/* It should access 16-bit instead of 8-bit */ +static inline void *memcpy(void *dst, const void *src, unsigned int len) +{ + void *ret = dst; + short *d = dst; + const short *s = src; + + len >>= 1; + while (len-- > 0) + *d++ = *s++; + return ret; +} + static const unsigned char ffchars[] = { 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, 0xff, /* 16 */

2 1

[U-Boot-Users] [PATCH] Add CONFIG_MII_INIT support to related boards
by Tsi-Chung Liew 14 Apr '08

14 Apr '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> Replace CONFIG_8xx and CONFIG_MCF532x to CONFIG_MII_INIT in cmd_init.c. Add CONFIG_MII_INIT to board configuration files that use mii_init() in cmd_init.c. Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- board/fads/fads.h | 1 + common/cmd_mii.c | 2 +- include/configs/Adder.h | 1 + include/configs/EB+MCF-EV123.h | 1 + include/configs/EP88x.h | 1 + include/configs/GEN860T.h | 1 + include/configs/M5235EVB.h | 1 + include/configs/M5271EVB.h | 1 + include/configs/M5275EVB.h | 1 + include/configs/M5282EVB.h | 1 + include/configs/M5329EVB.h | 1 + include/configs/M5373EVB.h | 1 + include/configs/M54455EVB.h | 4 ++-- include/configs/M5475EVB.h | 1 + include/configs/M5485EVB.h | 1 + include/configs/NETPHONE.h | 1 + include/configs/NETTA.h | 1 + include/configs/NETTA2.h | 1 + include/configs/TK885D.h | 2 ++ include/configs/TOP860.h | 1 + include/configs/TQM885D.h | 1 + include/configs/cobra5272.h | 1 + include/configs/idmr.h | 3 ++- include/configs/spc1920.h | 1 + include/configs/stxxtc.h | 1 + include/configs/uc100.h | 1 + 26 files changed, 29 insertions(+), 4 deletions(-) diff --git a/board/fads/fads.h b/board/fads/fads.h index dea8a0d..b217068 100644 --- a/board/fads/fads.h +++ b/board/fads/fads.h @@ -96,6 +96,7 @@ #ifdef CONFIG_FEC_ENET #define CFG_DISCOVER_PHY +#define CONFIG_MII_INIT 1 #endif diff --git a/common/cmd_mii.c b/common/cmd_mii.c index fa753dd..bcbd7aa 100644 --- a/common/cmd_mii.c +++ b/common/cmd_mii.c @@ -306,7 +306,7 @@ int do_mii (cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) return 1; } -#if defined(CONFIG_8xx) || defined(CONFIG_MCF532x) || defined(CONFIG_MII_INIT) +#if defined(CONFIG_MII_INIT) mii_init (); #endif diff --git a/include/configs/Adder.h b/include/configs/Adder.h index 7919991..8a76c26 100644 --- a/include/configs/Adder.h +++ b/include/configs/Adder.h @@ -42,6 +42,7 @@ #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY +#define CONFIG_MII_INIT 1 #define FEC_ENET #endif /* CONFIG_ETHER_ON_FEC || CONFIG_ETHER_ON_FEC2 */ diff --git a/include/configs/EB+MCF-EV123.h b/include/configs/EB+MCF-EV123.h index ea49a5d..5ba7585 100644 --- a/include/configs/EB+MCF-EV123.h +++ b/include/configs/EB+MCF-EV123.h @@ -88,6 +88,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/EP88x.h b/include/configs/EP88x.h index 89e0eeb..c2ab18a 100644 --- a/include/configs/EP88x.h +++ b/include/configs/EP88x.h @@ -42,6 +42,7 @@ #define CONFIG_ETHER_ON_FEC2 /* Enable Ethernet on FEC2 */ #if defined(CONFIG_ETHER_ON_FEC1) || defined(CONFIG_ETHER_ON_FEC2) #define CFG_DISCOVER_PHY +#define CONFIG_MII_INIT 1 #define FEC_ENET #endif /* CONFIG_FEC_ENET */ diff --git a/include/configs/GEN860T.h b/include/configs/GEN860T.h index 3eb3131..c8b5a6d 100644 --- a/include/configs/GEN860T.h +++ b/include/configs/GEN860T.h @@ -147,6 +147,7 @@ #define CONFIG_FEC_ENET #define CFG_DISCOVER_PHY #define CONFIG_MII +#define CONFIG_MII_INIT 1 #define CONFIG_PHY_ADDR 0 /* diff --git a/include/configs/M5235EVB.h b/include/configs/M5235EVB.h index 3b4bff3..3ee2b39 100644 --- a/include/configs/M5235EVB.h +++ b/include/configs/M5235EVB.h @@ -77,6 +77,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5271EVB.h b/include/configs/M5271EVB.h index 47e1e03..e1cc720 100644 --- a/include/configs/M5271EVB.h +++ b/include/configs/M5271EVB.h @@ -88,6 +88,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5275EVB.h b/include/configs/M5275EVB.h index 599f8dc..283c873 100644 --- a/include/configs/M5275EVB.h +++ b/include/configs/M5275EVB.h @@ -89,6 +89,7 @@ #ifdef CONFIG_MCFFEC #define CONFIG_NET_MULTI 1 #define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 #define CFG_DISCOVER_PHY #define CFG_RX_ETH_BUFFER 8 #define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5282EVB.h b/include/configs/M5282EVB.h index 7bb9f60..826778c 100644 --- a/include/configs/M5282EVB.h +++ b/include/configs/M5282EVB.h @@ -75,6 +75,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5329EVB.h b/include/configs/M5329EVB.h index 1a15c77..42692d6 100644 --- a/include/configs/M5329EVB.h +++ b/include/configs/M5329EVB.h @@ -70,6 +70,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5373EVB.h b/include/configs/M5373EVB.h index da4156c..3b9da17 100644 --- a/include/configs/M5373EVB.h +++ b/include/configs/M5373EVB.h @@ -70,6 +70,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M54455EVB.h b/include/configs/M54455EVB.h index a3c71e3..3a022af 100644 --- a/include/configs/M54455EVB.h +++ b/include/configs/M54455EVB.h @@ -83,9 +83,9 @@ /* Network configuration */ #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC -# define CONFIG_NET_MULTI 1 +# define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 -# define CONFIG_CF_DOMII +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/M5475EVB.h b/include/configs/M5475EVB.h index a4e6c5d..6bb4619 100644 --- a/include/configs/M5475EVB.h +++ b/include/configs/M5475EVB.h @@ -69,6 +69,7 @@ #ifdef CONFIG_FSLDMAFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CONFIG_HAS_ETH1 # define CFG_DISCOVER_PHY diff --git a/include/configs/M5485EVB.h b/include/configs/M5485EVB.h index 9121023..cba51c8 100644 --- a/include/configs/M5485EVB.h +++ b/include/configs/M5485EVB.h @@ -69,6 +69,7 @@ #ifdef CONFIG_FSLDMAFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CONFIG_HAS_ETH1 # define CFG_DISCOVER_PHY diff --git a/include/configs/NETPHONE.h b/include/configs/NETPHONE.h index bb3d19d..e3c6fd3 100644 --- a/include/configs/NETPHONE.h +++ b/include/configs/NETPHONE.h @@ -101,6 +101,7 @@ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 diff --git a/include/configs/NETTA.h b/include/configs/NETTA.h index 945f47f..20404a3 100644 --- a/include/configs/NETTA.h +++ b/include/configs/NETTA.h @@ -97,6 +97,7 @@ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY /* do not discover phys */ #define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 #define CONFIG_RMII 1 /* use RMII interface */ #if defined(CONFIG_NETTA_ISDN) diff --git a/include/configs/NETTA2.h b/include/configs/NETTA2.h index fb8085d..cf66e04 100644 --- a/include/configs/NETTA2.h +++ b/include/configs/NETTA2.h @@ -102,6 +102,7 @@ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 #define CONFIG_RMII 1 /* use RMII interface */ #define CONFIG_ETHER_ON_FEC1 1 diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h index 50f1c63..7310abf 100644 --- a/include/configs/TK885D.h +++ b/include/configs/TK885D.h @@ -510,6 +510,8 @@ #define CONFIG_FEC2_PHY 2 #endif +#define CONFIG_MII_INIT 1 + #define CONFIG_NET_RETRY_COUNT 3 #define CONFIG_ETHPRIME "FEC ETHERNET" diff --git a/include/configs/TOP860.h b/include/configs/TOP860.h index 66f7a11..8237ba1 100644 --- a/include/configs/TOP860.h +++ b/include/configs/TOP860.h @@ -205,6 +205,7 @@ #define FEC_ENET 1 /* eth.c needs it that way... */ #define CFG_DISCOVER_PHY 1 #define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 #define CONFIG_PHY_ADDR 31 /*----------------------------------------------------------------------- diff --git a/include/configs/TQM885D.h b/include/configs/TQM885D.h index a254bcd..f075442 100644 --- a/include/configs/TQM885D.h +++ b/include/configs/TQM885D.h @@ -497,6 +497,7 @@ #if defined(CONFIG_CMD_MII) #define CFG_DISCOVER_PHY +#define CONFIG_MII_INIT 1 #endif #define CONFIG_NET_RETRY_COUNT 1 /* reduce max. timeout before diff --git a/include/configs/cobra5272.h b/include/configs/cobra5272.h index 104d94e..c7e3899 100644 --- a/include/configs/cobra5272.h +++ b/include/configs/cobra5272.h @@ -158,6 +158,7 @@ #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 # define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/idmr.h b/include/configs/idmr.h index a15f69a..2ed51f7 100644 --- a/include/configs/idmr.h +++ b/include/configs/idmr.h @@ -156,7 +156,8 @@ #define CONFIG_MCFFEC #ifdef CONFIG_MCFFEC # define CONFIG_NET_MULTI 1 -#define CONFIG_MII 1 +# define CONFIG_MII 1 +# define CONFIG_MII_INIT 1 # define CFG_DISCOVER_PHY # define CFG_RX_ETH_BUFFER 8 # define CFG_FAULT_ECHO_LINK_DOWN diff --git a/include/configs/spc1920.h b/include/configs/spc1920.h index 2efc8f1..729f3c0 100644 --- a/include/configs/spc1920.h +++ b/include/configs/spc1920.h @@ -31,6 +31,7 @@ #undef CONFIG_8xx_CONS_NONE #define CONFIG_MII +#define CONFIG_MII_INIT 1 #undef CONFIG_ETHER_ON_FEC1 #define CONFIG_ETHER_ON_FEC2 #define FEC_ENET diff --git a/include/configs/stxxtc.h b/include/configs/stxxtc.h index f12765d..a3ab798 100644 --- a/include/configs/stxxtc.h +++ b/include/configs/stxxtc.h @@ -97,6 +97,7 @@ #define FEC_ENET 1 /* eth.c needs it that way... */ #undef CFG_DISCOVER_PHY #define CONFIG_MII 1 +#define CONFIG_MII_INIT 1 #undef CONFIG_RMII #define CONFIG_ETHER_ON_FEC1 1 diff --git a/include/configs/uc100.h b/include/configs/uc100.h index c1c2e03..3c2de40 100644 --- a/include/configs/uc100.h +++ b/include/configs/uc100.h @@ -510,6 +510,7 @@ #define CONFIG_FEC_ENET 1 /* use FEC ethernet */ #define FEC_ENET #define CONFIG_MII +#define CONFIG_MII_INIT 1 #define CFG_DISCOVER_PHY 1 #endif /* __CONFIG_H */ -- 1.5.4.1

3 2

[U-Boot-Users] [PATCH] Fix 8xx build to conditionally compile fdt.o
by Jerry Van Baren 14 Apr '08

14 Apr '08

Change to COBJS-y method so that the fdt.o library can be properly conditionally compiled. Without this change, the mpc8xx boards that don't use CONFIG_OF_LIBFDT still build the fdt.o, causing code bloat and compile warnings. Signed-off-by: Gerald Van Baren <vanbaren(a)cideas.com> --- Hi Wolfgang, Commit a6f5f317cd074bbbfa2aab4fca05904c811c19fb added fdt.o unconditionally. 8xx : Add OF support to Adder875 board port - resubmit I don't have any 8xx boards (especially no Adder boards) so I cannot verify the patch doesn't break the boards, but it does compile cleanly both with and w/o CONFIG_OF_LIBFDT. Best regards, gvb cpu/mpc8xx/Makefile | 24 +++++++++++++++++++----- 1 files changed, 19 insertions(+), 5 deletions(-) diff --git a/cpu/mpc8xx/Makefile b/cpu/mpc8xx/Makefile index dbdc2e0..a800210 100644 --- a/cpu/mpc8xx/Makefile +++ b/cpu/mpc8xx/Makefile @@ -28,14 +28,28 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o kgdb.o -COBJS = bedbug_860.o commproc.o cpu.o cpu_init.o \ - fec.o fdt.o i2c.o interrupts.o lcd.o scc.o \ - serial.o speed.o spi.o \ - traps.o upatch.o video.o + +COBJS-y += bedbug_860.o +COBJS-y += commproc.o +COBJS-y += cpu.o +COBJS-y += cpu_init.o +COBJS-y += fec.o +COBJS-y += i2c.o +COBJS-y += lcd.o +COBJS-y += interrupts.o +COBJS-y += scc.o +COBJS-y += serial.o +COBJS-y += speed.o +COBJS-y += spi.o +COBJS-y += traps.o +COBJS-y += upatch.o +COBJS-y += video.o +COBJS-$(CONFIG_OF_LIBFDT) += fdt.o + SOBJS = plprcr_write.o SRCS := $(START:.o=.S) $(SOBJS:.o=.S) $(COBJS:.o=.c) -OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) +OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS-y)) START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) -- 1.5.4.1

2 2

[U-Boot-Users] [PATCH v2 4/7] add SMSC LAN9x1x Network driver
by Guennadi Liakhovetski 14 Apr '08

14 Apr '08

From: Sascha Hauer <s.hauer(a)pengutronix.de> This patch adds a driver for the following smsc network controllers: LAN9115 LAN9116 LAN9117 LAN9215 LAN9216 LAN9217 Signed-off-by: Sascha Hauer <s.hauer(a)pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: Removed C++ style comments drivers/net/Makefile | 1 + drivers/net/smc911x.c | 668 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 669 insertions(+), 0 deletions(-) create mode 100644 drivers/net/smc911x.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 320dc3e..9482398 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -54,6 +54,7 @@ COBJS-y += rtl8139.o COBJS-y += rtl8169.o COBJS-y += s3c4510b_eth.o COBJS-y += smc91111.o +COBJS-y += smc911x.o COBJS-y += tigon3.o COBJS-y += tsec.o COBJS-y += tsi108_eth.o diff --git a/drivers/net/smc911x.c b/drivers/net/smc911x.c new file mode 100644 index 0000000..5830368 --- /dev/null +++ b/drivers/net/smc911x.c @@ -0,0 +1,667 @@ +/* + * SMSC LAN9[12]1[567] Network driver + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#ifdef CONFIG_DRIVER_SMC911X + +#include <command.h> +#include <net.h> +#include <miiphy.h> + +#define mdelay(n) udelay((n)*1000) + +#define __REG(x) (*((volatile u32 *)(x))) + +/* Below are the register offsets and bit definitions + * of the Lan911x memory space + */ +#define RX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x00) + +#define TX_DATA_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x20) +#define TX_CMD_A_INT_ON_COMP (0x80000000) +#define TX_CMD_A_INT_BUF_END_ALGN (0x03000000) +#define TX_CMD_A_INT_4_BYTE_ALGN (0x00000000) +#define TX_CMD_A_INT_16_BYTE_ALGN (0x01000000) +#define TX_CMD_A_INT_32_BYTE_ALGN (0x02000000) +#define TX_CMD_A_INT_DATA_OFFSET (0x001F0000) +#define TX_CMD_A_INT_FIRST_SEG (0x00002000) +#define TX_CMD_A_INT_LAST_SEG (0x00001000) +#define TX_CMD_A_BUF_SIZE (0x000007FF) +#define TX_CMD_B_PKT_TAG (0xFFFF0000) +#define TX_CMD_B_ADD_CRC_DISABLE (0x00002000) +#define TX_CMD_B_DISABLE_PADDING (0x00001000) +#define TX_CMD_B_PKT_BYTE_LENGTH (0x000007FF) + +#define RX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x40) +#define RX_STS_PKT_LEN (0x3FFF0000) +#define RX_STS_ES (0x00008000) +#define RX_STS_BCST (0x00002000) +#define RX_STS_LEN_ERR (0x00001000) +#define RX_STS_RUNT_ERR (0x00000800) +#define RX_STS_MCAST (0x00000400) +#define RX_STS_TOO_LONG (0x00000080) +#define RX_STS_COLL (0x00000040) +#define RX_STS_ETH_TYPE (0x00000020) +#define RX_STS_WDOG_TMT (0x00000010) +#define RX_STS_MII_ERR (0x00000008) +#define RX_STS_DRIBBLING (0x00000004) +#define RX_STS_CRC_ERR (0x00000002) +#define RX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x44) +#define TX_STATUS_FIFO __REG(CONFIG_DRIVER_SMC911X_BASE + 0x48) +#define TX_STS_TAG (0xFFFF0000) +#define TX_STS_ES (0x00008000) +#define TX_STS_LOC (0x00000800) +#define TX_STS_NO_CARR (0x00000400) +#define TX_STS_LATE_COLL (0x00000200) +#define TX_STS_MANY_COLL (0x00000100) +#define TX_STS_COLL_CNT (0x00000078) +#define TX_STS_MANY_DEFER (0x00000004) +#define TX_STS_UNDERRUN (0x00000002) +#define TX_STS_DEFERRED (0x00000001) +#define TX_STATUS_FIFO_PEEK __REG(CONFIG_DRIVER_SMC911X_BASE + 0x4C) +#define ID_REV __REG(CONFIG_DRIVER_SMC911X_BASE + 0x50) +#define ID_REV_CHIP_ID (0xFFFF0000) /* RO */ +#define ID_REV_REV_ID (0x0000FFFF) /* RO */ + +#define INT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x54) +#define INT_CFG_INT_DEAS (0xFF000000) /* R/W */ +#define INT_CFG_INT_DEAS_CLR (0x00004000) +#define INT_CFG_INT_DEAS_STS (0x00002000) +#define INT_CFG_IRQ_INT (0x00001000) /* RO */ +#define INT_CFG_IRQ_EN (0x00000100) /* R/W */ +#define INT_CFG_IRQ_POL (0x00000010) /* R/W Not Affected by SW Reset */ +#define INT_CFG_IRQ_TYPE (0x00000001) /* R/W Not Affected by SW Reset */ + +#define INT_STS __REG(CONFIG_DRIVER_SMC911X_BASE + 0x58) +#define INT_STS_SW_INT (0x80000000) /* R/WC */ +#define INT_STS_TXSTOP_INT (0x02000000) /* R/WC */ +#define INT_STS_RXSTOP_INT (0x01000000) /* R/WC */ +#define INT_STS_RXDFH_INT (0x00800000) /* R/WC */ +#define INT_STS_RXDF_INT (0x00400000) /* R/WC */ +#define INT_STS_TX_IOC (0x00200000) /* R/WC */ +#define INT_STS_RXD_INT (0x00100000) /* R/WC */ +#define INT_STS_GPT_INT (0x00080000) /* R/WC */ +#define INT_STS_PHY_INT (0x00040000) /* RO */ +#define INT_STS_PME_INT (0x00020000) /* R/WC */ +#define INT_STS_TXSO (0x00010000) /* R/WC */ +#define INT_STS_RWT (0x00008000) /* R/WC */ +#define INT_STS_RXE (0x00004000) /* R/WC */ +#define INT_STS_TXE (0x00002000) /* R/WC */ +/*#define INT_STS_ERX (0x00001000)*/ /* R/WC */ +#define INT_STS_TDFU (0x00000800) /* R/WC */ +#define INT_STS_TDFO (0x00000400) /* R/WC */ +#define INT_STS_TDFA (0x00000200) /* R/WC */ +#define INT_STS_TSFF (0x00000100) /* R/WC */ +#define INT_STS_TSFL (0x00000080) /* R/WC */ +/*#define INT_STS_RXDF (0x00000040)*/ /* R/WC */ +#define INT_STS_RDFO (0x00000040) /* R/WC */ +#define INT_STS_RDFL (0x00000020) /* R/WC */ +#define INT_STS_RSFF (0x00000010) /* R/WC */ +#define INT_STS_RSFL (0x00000008) /* R/WC */ +#define INT_STS_GPIO2_INT (0x00000004) /* R/WC */ +#define INT_STS_GPIO1_INT (0x00000002) /* R/WC */ +#define INT_STS_GPIO0_INT (0x00000001) /* R/WC */ +#define INT_EN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x5C) +#define INT_EN_SW_INT_EN (0x80000000) /* R/W */ +#define INT_EN_TXSTOP_INT_EN (0x02000000) /* R/W */ +#define INT_EN_RXSTOP_INT_EN (0x01000000) /* R/W */ +#define INT_EN_RXDFH_INT_EN (0x00800000) /* R/W */ +/*#define INT_EN_RXDF_INT_EN (0x00400000)*/ /* R/W */ +#define INT_EN_TIOC_INT_EN (0x00200000) /* R/W */ +#define INT_EN_RXD_INT_EN (0x00100000) /* R/W */ +#define INT_EN_GPT_INT_EN (0x00080000) /* R/W */ +#define INT_EN_PHY_INT_EN (0x00040000) /* R/W */ +#define INT_EN_PME_INT_EN (0x00020000) /* R/W */ +#define INT_EN_TXSO_EN (0x00010000) /* R/W */ +#define INT_EN_RWT_EN (0x00008000) /* R/W */ +#define INT_EN_RXE_EN (0x00004000) /* R/W */ +#define INT_EN_TXE_EN (0x00002000) /* R/W */ +/*#define INT_EN_ERX_EN (0x00001000)*/ /* R/W */ +#define INT_EN_TDFU_EN (0x00000800) /* R/W */ +#define INT_EN_TDFO_EN (0x00000400) /* R/W */ +#define INT_EN_TDFA_EN (0x00000200) /* R/W */ +#define INT_EN_TSFF_EN (0x00000100) /* R/W */ +#define INT_EN_TSFL_EN (0x00000080) /* R/W */ +/*#define INT_EN_RXDF_EN (0x00000040)*/ /* R/W */ +#define INT_EN_RDFO_EN (0x00000040) /* R/W */ +#define INT_EN_RDFL_EN (0x00000020) /* R/W */ +#define INT_EN_RSFF_EN (0x00000010) /* R/W */ +#define INT_EN_RSFL_EN (0x00000008) /* R/W */ +#define INT_EN_GPIO2_INT (0x00000004) /* R/W */ +#define INT_EN_GPIO1_INT (0x00000002) /* R/W */ +#define INT_EN_GPIO0_INT (0x00000001) /* R/W */ + +#define BYTE_TEST __REG(CONFIG_DRIVER_SMC911X_BASE + 0x64) +#define FIFO_INT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x68) +#define FIFO_INT_TX_AVAIL_LEVEL (0xFF000000) /* R/W */ +#define FIFO_INT_TX_STS_LEVEL (0x00FF0000) /* R/W */ +#define FIFO_INT_RX_AVAIL_LEVEL (0x0000FF00) /* R/W */ +#define FIFO_INT_RX_STS_LEVEL (0x000000FF) /* R/W */ + +#define RX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x6C) +#define RX_CFG_RX_END_ALGN (0xC0000000) /* R/W */ +#define RX_CFG_RX_END_ALGN4 (0x00000000) /* R/W */ +#define RX_CFG_RX_END_ALGN16 (0x40000000) /* R/W */ +#define RX_CFG_RX_END_ALGN32 (0x80000000) /* R/W */ +#define RX_CFG_RX_DMA_CNT (0x0FFF0000) /* R/W */ +#define RX_CFG_RX_DUMP (0x00008000) /* R/W */ +#define RX_CFG_RXDOFF (0x00001F00) /* R/W */ +/*#define RX_CFG_RXBAD (0x00000001)*/ /* R/W */ + +#define TX_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x70) +/*#define TX_CFG_TX_DMA_LVL (0xE0000000)*/ /* R/W */ +/*#define TX_CFG_TX_DMA_CNT (0x0FFF0000)*/ /* R/W Self Clearing */ +#define TX_CFG_TXS_DUMP (0x00008000) /* Self Clearing */ +#define TX_CFG_TXD_DUMP (0x00004000) /* Self Clearing */ +#define TX_CFG_TXSAO (0x00000004) /* R/W */ +#define TX_CFG_TX_ON (0x00000002) /* R/W */ +#define TX_CFG_STOP_TX (0x00000001) /* Self Clearing */ + +#define HW_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x74) +#define HW_CFG_TTM (0x00200000) /* R/W */ +#define HW_CFG_SF (0x00100000) /* R/W */ +#define HW_CFG_TX_FIF_SZ (0x000F0000) /* R/W */ +#define HW_CFG_TR (0x00003000) /* R/W */ +#define HW_CFG_PHY_CLK_SEL (0x00000060) /* R/W */ +#define HW_CFG_PHY_CLK_SEL_INT_PHY (0x00000000) /* R/W */ +#define HW_CFG_PHY_CLK_SEL_EXT_PHY (0x00000020) /* R/W */ +#define HW_CFG_PHY_CLK_SEL_CLK_DIS (0x00000040) /* R/W */ +#define HW_CFG_SMI_SEL (0x00000010) /* R/W */ +#define HW_CFG_EXT_PHY_DET (0x00000008) /* RO */ +#define HW_CFG_EXT_PHY_EN (0x00000004) /* R/W */ +#define HW_CFG_32_16_BIT_MODE (0x00000004) /* RO */ +#define HW_CFG_SRST_TO (0x00000002) /* RO */ +#define HW_CFG_SRST (0x00000001) /* Self Clearing */ + +#define RX_DP_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x78) +#define RX_DP_CTRL_RX_FFWD (0x80000000) /* R/W */ +#define RX_DP_CTRL_FFWD_BUSY (0x80000000) /* RO */ + +#define RX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x7C) +#define RX_FIFO_INF_RXSUSED (0x00FF0000) /* RO */ +#define RX_FIFO_INF_RXDUSED (0x0000FFFF) /* RO */ + +#define TX_FIFO_INF __REG(CONFIG_DRIVER_SMC911X_BASE + 0x80) +#define TX_FIFO_INF_TSUSED (0x00FF0000) /* RO */ +#define TX_FIFO_INF_TDFREE (0x0000FFFF) /* RO */ + +#define PMT_CTRL __REG(CONFIG_DRIVER_SMC911X_BASE + 0x84) +#define PMT_CTRL_PM_MODE (0x00003000) /* Self Clearing */ +#define PMT_CTRL_PHY_RST (0x00000400) /* Self Clearing */ +#define PMT_CTRL_WOL_EN (0x00000200) /* R/W */ +#define PMT_CTRL_ED_EN (0x00000100) /* R/W */ +#define PMT_CTRL_PME_TYPE (0x00000040) /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_WUPS (0x00000030) /* R/WC */ +#define PMT_CTRL_WUPS_NOWAKE (0x00000000) /* R/WC */ +#define PMT_CTRL_WUPS_ED (0x00000010) /* R/WC */ +#define PMT_CTRL_WUPS_WOL (0x00000020) /* R/WC */ +#define PMT_CTRL_WUPS_MULTI (0x00000030) /* R/WC */ +#define PMT_CTRL_PME_IND (0x00000008) /* R/W */ +#define PMT_CTRL_PME_POL (0x00000004) /* R/W */ +#define PMT_CTRL_PME_EN (0x00000002) /* R/W Not Affected by SW Reset */ +#define PMT_CTRL_READY (0x00000001) /* RO */ + +#define GPIO_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x88) +#define GPIO_CFG_LED3_EN (0x40000000) /* R/W */ +#define GPIO_CFG_LED2_EN (0x20000000) /* R/W */ +#define GPIO_CFG_LED1_EN (0x10000000) /* R/W */ +#define GPIO_CFG_GPIO2_INT_POL (0x04000000) /* R/W */ +#define GPIO_CFG_GPIO1_INT_POL (0x02000000) /* R/W */ +#define GPIO_CFG_GPIO0_INT_POL (0x01000000) /* R/W */ +#define GPIO_CFG_EEPR_EN (0x00700000) /* R/W */ +#define GPIO_CFG_GPIOBUF2 (0x00040000) /* R/W */ +#define GPIO_CFG_GPIOBUF1 (0x00020000) /* R/W */ +#define GPIO_CFG_GPIOBUF0 (0x00010000) /* R/W */ +#define GPIO_CFG_GPIODIR2 (0x00000400) /* R/W */ +#define GPIO_CFG_GPIODIR1 (0x00000200) /* R/W */ +#define GPIO_CFG_GPIODIR0 (0x00000100) /* R/W */ +#define GPIO_CFG_GPIOD4 (0x00000010) /* R/W */ +#define GPIO_CFG_GPIOD3 (0x00000008) /* R/W */ +#define GPIO_CFG_GPIOD2 (0x00000004) /* R/W */ +#define GPIO_CFG_GPIOD1 (0x00000002) /* R/W */ +#define GPIO_CFG_GPIOD0 (0x00000001) /* R/W */ + +#define GPT_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0x8C) +#define GPT_CFG_TIMER_EN (0x20000000) /* R/W */ +#define GPT_CFG_GPT_LOAD (0x0000FFFF) /* R/W */ + +#define GPT_CNT __REG(CONFIG_DRIVER_SMC911X_BASE + 0x90) +#define GPT_CNT_GPT_CNT (0x0000FFFF) /* RO */ + +#define ENDIAN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x98) +#define FREE_RUN __REG(CONFIG_DRIVER_SMC911X_BASE + 0x9C) +#define RX_DROP __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA0) +#define MAC_CSR_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA4) +#define MAC_CSR_CMD_CSR_BUSY (0x80000000) /* Self Clearing */ +#define MAC_CSR_CMD_R_NOT_W (0x40000000) /* R/W */ +#define MAC_CSR_CMD_CSR_ADDR (0x000000FF) /* R/W */ + +#define MAC_CSR_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xA8) +#define AFC_CFG __REG(CONFIG_DRIVER_SMC911X_BASE + 0xAC) +#define AFC_CFG_AFC_HI (0x00FF0000) /* R/W */ +#define AFC_CFG_AFC_LO (0x0000FF00) /* R/W */ +#define AFC_CFG_BACK_DUR (0x000000F0) /* R/W */ +#define AFC_CFG_FCMULT (0x00000008) /* R/W */ +#define AFC_CFG_FCBRD (0x00000004) /* R/W */ +#define AFC_CFG_FCADD (0x00000002) /* R/W */ +#define AFC_CFG_FCANY (0x00000001) /* R/W */ + +#define E2P_CMD __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB0) +#define E2P_CMD_EPC_BUSY (0x80000000) /* Self Clearing */ +#define E2P_CMD_EPC_CMD (0x70000000) /* R/W */ +#define E2P_CMD_EPC_CMD_READ (0x00000000) /* R/W */ +#define E2P_CMD_EPC_CMD_EWDS (0x10000000) /* R/W */ +#define E2P_CMD_EPC_CMD_EWEN (0x20000000) /* R/W */ +#define E2P_CMD_EPC_CMD_WRITE (0x30000000) /* R/W */ +#define E2P_CMD_EPC_CMD_WRAL (0x40000000) /* R/W */ +#define E2P_CMD_EPC_CMD_ERASE (0x50000000) /* R/W */ +#define E2P_CMD_EPC_CMD_ERAL (0x60000000) /* R/W */ +#define E2P_CMD_EPC_CMD_RELOAD (0x70000000) /* R/W */ +#define E2P_CMD_EPC_TIMEOUT (0x00000200) /* RO */ +#define E2P_CMD_MAC_ADDR_LOADED (0x00000100) /* RO */ +#define E2P_CMD_EPC_ADDR (0x000000FF) /* R/W */ + +#define E2P_DATA __REG(CONFIG_DRIVER_SMC911X_BASE + 0xB4) +#define E2P_DATA_EEPROM_DATA (0x000000FF) /* R/W */ +/* end of LAN register offsets and bit definitions */ + +/* MAC Control and Status registers */ +#define MAC_CR (0x01) /* R/W */ + +/* MAC_CR - MAC Control Register */ +#define MAC_CR_RXALL (0x80000000) +/* TODO: delete this bit? It is not described in the data sheet. */ +#define MAC_CR_HBDIS (0x10000000) +#define MAC_CR_RCVOWN (0x00800000) +#define MAC_CR_LOOPBK (0x00200000) +#define MAC_CR_FDPX (0x00100000) +#define MAC_CR_MCPAS (0x00080000) +#define MAC_CR_PRMS (0x00040000) +#define MAC_CR_INVFILT (0x00020000) +#define MAC_CR_PASSBAD (0x00010000) +#define MAC_CR_HFILT (0x00008000) +#define MAC_CR_HPFILT (0x00002000) +#define MAC_CR_LCOLL (0x00001000) +#define MAC_CR_BCAST (0x00000800) +#define MAC_CR_DISRTY (0x00000400) +#define MAC_CR_PADSTR (0x00000100) +#define MAC_CR_BOLMT_MASK (0x000000C0) +#define MAC_CR_DFCHK (0x00000020) +#define MAC_CR_TXEN (0x00000008) +#define MAC_CR_RXEN (0x00000004) + +#define ADDRH (0x02) /* R/W mask 0x0000FFFFUL */ +#define ADDRL (0x03) /* R/W mask 0xFFFFFFFFUL */ +#define HASHH (0x04) /* R/W */ +#define HASHL (0x05) /* R/W */ + +#define MII_ACC (0x06) /* R/W */ +#define MII_ACC_PHY_ADDR (0x0000F800) +#define MII_ACC_MIIRINDA (0x000007C0) +#define MII_ACC_MII_WRITE (0x00000002) +#define MII_ACC_MII_BUSY (0x00000001) + +#define MII_DATA (0x07) /* R/W mask 0x0000FFFFUL */ + +#define FLOW (0x08) /* R/W */ +#define FLOW_FCPT (0xFFFF0000) +#define FLOW_FCPASS (0x00000004) +#define FLOW_FCEN (0x00000002) +#define FLOW_FCBSY (0x00000001) + +#define VLAN1 (0x09) /* R/W mask 0x0000FFFFUL */ +#define VLAN1_VTI1 (0x0000ffff) + +#define VLAN2 (0x0A) /* R/W mask 0x0000FFFFUL */ +#define VLAN2_VTI2 (0x0000ffff) + +#define WUFF (0x0B) /* WO */ + +#define WUCSR (0x0C) /* R/W */ +#define WUCSR_GUE (0x00000200) +#define WUCSR_WUFR (0x00000040) +#define WUCSR_MPR (0x00000020) +#define WUCSR_WAKE_EN (0x00000004) +#define WUCSR_MPEN (0x00000002) + +/* Chip ID values */ +#define CHIP_9115 0x115 +#define CHIP_9116 0x116 +#define CHIP_9117 0x117 +#define CHIP_9118 0x118 +#define CHIP_9215 0x115a +#define CHIP_9216 0x116a +#define CHIP_9217 0x117a +#define CHIP_9218 0x118a + +struct chip_id { + u16 id; + char *name; +}; + +static const struct chip_id chip_ids[] = { + { CHIP_9115, "LAN9115" }, + { CHIP_9116, "LAN9116" }, + { CHIP_9117, "LAN9117" }, + { CHIP_9118, "LAN9118" }, + { CHIP_9215, "LAN9215" }, + { CHIP_9216, "LAN9216" }, + { CHIP_9217, "LAN9217" }, + { CHIP_9218, "LAN9218" }, + { 0, NULL }, +}; + +#define DRIVERNAME "smc911x" + +u32 smc911x_get_mac_csr(u8 reg) +{ + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); + MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | MAC_CSR_CMD_R_NOT_W | reg; + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); + + return MAC_CSR_DATA; +} + +void smc911x_set_mac_csr(u8 reg, u32 data) +{ + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); + MAC_CSR_DATA = data; + MAC_CSR_CMD = MAC_CSR_CMD_CSR_BUSY | reg; + while (MAC_CSR_CMD & MAC_CSR_CMD_CSR_BUSY); +} + +static int smx911x_handle_mac_address(bd_t *bd) +{ + unsigned long addrh, addrl; + unsigned char *m = bd->bi_enetaddr; + + /* if the environment has a valid mac address then use it */ + if ((m[0] | m[1] | m[2] | m[3] | m[4] | m[5])) { + addrl = m[0] | m[1] << 8 | m[2] << 16 | m[3] << 24; + addrh = m[4] | m[5] << 8; + smc911x_set_mac_csr(ADDRH, addrh); + smc911x_set_mac_csr(ADDRL, addrl); + } else { + /* if not, try to get one from the eeprom */ + addrh = smc911x_get_mac_csr(ADDRH); + addrl = smc911x_get_mac_csr(ADDRL); + + m[0] = (addrl ) & 0xff; + m[1] = (addrl >> 8 ) & 0xff; + m[2] = (addrl >> 16 ) & 0xff; + m[3] = (addrl >> 24 ) & 0xff; + m[4] = (addrh ) & 0xff; + m[5] = (addrh >> 8 ) & 0xff; + + /* we get 0xff when there is no eeprom connected */ + if ((m[0] & m[1] & m[2] & m[3] & m[4] & m[5]) == 0xff) { + printf(DRIVERNAME ": no valid mac address in environment " + "and no eeprom found\n"); + return -1; + } + } + + printf(DRIVERNAME ": MAC %02x:%02x:%02x:%02x:%02x:%02x\n", + m[0], m[1], m[2], m[3], m[4], m[5]); + + return 0; +} + +static int smc911x_miiphy_read(u8 phy, u8 reg, u16 *val) +{ + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + + smc911x_set_mac_csr( MII_ACC, phy << 11 | reg << 6 | MII_ACC_MII_BUSY); + + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + + *val = smc911x_get_mac_csr(MII_DATA); + + return 0; +} + +static int smc911x_miiphy_write(u8 phy, u8 reg, u16 val) +{ + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + + smc911x_set_mac_csr(MII_DATA, val); + smc911x_set_mac_csr(MII_ACC, + phy << 11 | reg << 6 | MII_ACC_MII_BUSY | MII_ACC_MII_WRITE); + + while (smc911x_get_mac_csr(MII_ACC) & MII_ACC_MII_BUSY); + return 0; +} + +static int smc911x_phy_reset(void) +{ + u32 reg; + + reg = PMT_CTRL; + reg &= ~0xfffff030; + reg |= PMT_CTRL_PHY_RST; + PMT_CTRL = reg; + + mdelay(100); + + return 0; +} + +static void smc911x_phy_configure(void) +{ + int timeout; + u16 status; + + smc911x_phy_reset(); + + smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_RESET); + mdelay(1); + smc911x_miiphy_write(1, PHY_ANAR, 0x01e1); + smc911x_miiphy_write(1, PHY_BMCR, PHY_BMCR_AUTON | PHY_BMCR_RST_NEG); + + timeout = 5000; + do { + mdelay(1); + if ((timeout--) == 0) + goto err_out; + + if (smc911x_miiphy_read(1, PHY_BMSR, &status) != 0) + goto err_out; + } while (!(status & PHY_BMSR_LS)); + + printf(DRIVERNAME ": phy initialized\n"); + + return; + +err_out: + printf(DRIVERNAME ": autonegotiation timed out\n"); +} + +static void smc911x_reset(void) +{ + int timeout; + + /* Take out of PM setting first */ + if (PMT_CTRL & PMT_CTRL_READY) { + /* Write to the bytetest will take out of powerdown */ + BYTE_TEST = 0x0; + + timeout = 10; + + while ( timeout-- && !(PMT_CTRL & PMT_CTRL_READY)) + udelay(10); + if (!timeout) { + printf(DRIVERNAME + ": timeout waiting for PM restore\n"); + return; + } + } + + /* Disable interrupts */ + INT_EN = 0; + + HW_CFG = HW_CFG_SRST; + + timeout = 1000; + while (timeout-- && E2P_CMD & E2P_CMD_EPC_BUSY) + udelay(10); + + if(!timeout) { + printf(DRIVERNAME ": reset timeout\n"); + return; + } + + /* Reset the FIFO level and flow control settings */ + smc911x_set_mac_csr(FLOW, FLOW_FCPT | FLOW_FCEN); + AFC_CFG = 0x0050287F; + + /* Set to LED outputs */ + GPIO_CFG = 0x70070000; +} + +static void smc911x_enable(void) +{ + /* Enable TX */ + HW_CFG = 8 << 16 | HW_CFG_SF; + + GPT_CFG = GPT_CFG_TIMER_EN | 10000; + + TX_CFG = TX_CFG_TX_ON; + + /* no padding to start of packets */ + RX_CFG = 0; + + smc911x_set_mac_csr(MAC_CR, MAC_CR_TXEN | MAC_CR_RXEN | MAC_CR_HBDIS); + +} + +int eth_init(bd_t *bd) +{ + unsigned long val, i; + + printf(DRIVERNAME ": initializing\n"); + + val = BYTE_TEST; + if(val != 0x87654321) { + printf(DRIVERNAME ": Invalid chip endian 0x08%x\n", val); + goto err_out; + } + + val = ID_REV >> 16; + for(i = 0; chip_ids[i].id != 0; i++) { + if (chip_ids[i].id == val) break; + } + if (!chip_ids[i].id) { + printf(DRIVERNAME ": Unknown chip ID %04x\n", val); + goto err_out; + } + + printf(DRIVERNAME ": detected %s controller\n", chip_ids[i].name); + + smc911x_reset(); + + /* Configure the PHY, initialize the link state */ + smc911x_phy_configure(); + + if (smx911x_handle_mac_address(bd)) + goto err_out; + + /* Turn on Tx + Rx */ + smc911x_enable(); + + return 0; + +err_out: + return -1; +} + +int eth_send(volatile void *packet, int length) +{ + u32 *data = (u32*)packet; + u32 tmplen; + u32 status; + + TX_DATA_FIFO = TX_CMD_A_INT_FIRST_SEG | TX_CMD_A_INT_LAST_SEG | length; + TX_DATA_FIFO = length; + + tmplen = (length + 3) / 4; + + while(tmplen--) + TX_DATA_FIFO = *data++; + + /* wait for transmission */ + while (!((TX_FIFO_INF & TX_FIFO_INF_TSUSED) >> 16)); + + /* get status. Ignore 'no carrier' error, it has no meaning for + * full duplex operation + */ + status = TX_STATUS_FIFO & (TX_STS_LOC | TX_STS_LATE_COLL | + TX_STS_MANY_COLL | TX_STS_MANY_DEFER | TX_STS_UNDERRUN); + + if(!status) + return 0; + + printf(DRIVERNAME ": failed to send packet: %s%s%s%s%s\n", + status & TX_STS_LOC ? "TX_STS_LOC " : "", + status & TX_STS_LATE_COLL ? "TX_STS_LATE_COLL " : "", + status & TX_STS_MANY_COLL ? "TX_STS_MANY_COLL " : "", + status & TX_STS_MANY_DEFER ? "TX_STS_MANY_DEFER " : "", + status & TX_STS_UNDERRUN ? "TX_STS_UNDERRUN" : ""); + + return -1; +} + +void eth_halt(void) +{ + smc911x_reset(); +} + +int eth_rx(void) +{ + u32 *data = (u32 *)NetRxPackets[0]; + u32 pktlen, tmplen; + u32 status; + + if((RX_FIFO_INF & RX_FIFO_INF_RXSUSED) >> 16) { + status = RX_STATUS_FIFO; + pktlen = (status & RX_STS_PKT_LEN) >> 16; + + RX_CFG = 0; + + tmplen = (pktlen + 2+ 3) / 4; + while(tmplen--) + *data++ = RX_DATA_FIFO; + + if(status & RX_STS_ES) + printf(DRIVERNAME + ": dropped bad packet. Status: 0x%08x\n", + status); + else + NetReceive(NetRxPackets[0], pktlen); + } + + return 0; +} + +#endif /* CONFIG_DRIVER_SMC911X */ -- 1.5.4

7 13

[U-Boot-Users] [PATCH v2] Introduce phys_size_t and move phys_addr_t into asm/types.h
by Kumar Gala 14 Apr '08

14 Apr '08

Also add CONFIG_PHYS_64BIT on powerpc to deal with 32-bit ppc's that have larger physical addresses like 44x, 85xx, and 86xx. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- include/asm-arm/io.h | 2 -- include/asm-arm/types.h | 3 +++ include/asm-avr32/io.h | 2 -- include/asm-avr32/types.h | 3 +++ include/asm-blackfin/io.h | 2 -- include/asm-blackfin/types.h | 3 +++ include/asm-i386/io.h | 2 -- include/asm-i386/types.h | 3 +++ include/asm-m68k/io.h | 2 -- include/asm-m68k/types.h | 3 +++ include/asm-microblaze/io.h | 2 -- include/asm-microblaze/types.h | 3 +++ include/asm-mips/io.h | 2 -- include/asm-mips/types.h | 8 ++++++++ include/asm-nios/io.h | 2 -- include/asm-nios/types.h | 3 +++ include/asm-nios2/io.h | 2 -- include/asm-ppc/io.h | 2 -- include/asm-ppc/types.h | 8 ++++++++ include/asm-sh/io.h | 2 -- include/asm-sh/types.h | 3 +++ 21 files changed, 40 insertions(+), 22 deletions(-) diff --git a/include/asm-arm/io.h b/include/asm-arm/io.h index 029b7f9..c33b9e8 100644 --- a/include/asm-arm/io.h +++ b/include/asm-arm/io.h @@ -38,8 +38,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-arm/types.h b/include/asm-arm/types.h index e56f19d..71dc049 100644 --- a/include/asm-arm/types.h +++ b/include/asm-arm/types.h @@ -45,6 +45,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif diff --git a/include/asm-avr32/io.h b/include/asm-avr32/io.h index ba14674..d030c26 100644 --- a/include/asm-avr32/io.h +++ b/include/asm-avr32/io.h @@ -101,8 +101,6 @@ static inline void sync(void) * This implementation works for memory below 512MiB (flash, etc.) as * well as above 3.5GiB (internal peripherals.) */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (1 << 7) #define MAP_WRBACK (MAP_WRCOMBINE | (1 << 9)) diff --git a/include/asm-avr32/types.h b/include/asm-avr32/types.h index 2dbea4b..c303e3c 100644 --- a/include/asm-avr32/types.h +++ b/include/asm-avr32/types.h @@ -71,6 +71,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #ifdef CONFIG_LBD typedef u64 sector_t; #define HAVE_SECTOR_T diff --git a/include/asm-blackfin/io.h b/include/asm-blackfin/io.h index 2149685..da58914 100644 --- a/include/asm-blackfin/io.h +++ b/include/asm-blackfin/io.h @@ -45,8 +45,6 @@ extern void cf_outb(unsigned char val, volatile unsigned char *addr); * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-blackfin/types.h b/include/asm-blackfin/types.h index 9fd8e03..2160ba0 100644 --- a/include/asm-blackfin/types.h +++ b/include/asm-blackfin/types.h @@ -78,6 +78,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif #endif diff --git a/include/asm-i386/io.h b/include/asm-i386/io.h index db4f442..2c57140 100644 --- a/include/asm-i386/io.h +++ b/include/asm-i386/io.h @@ -210,8 +210,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-i386/types.h b/include/asm-i386/types.h index bdbde41..9a40e38 100644 --- a/include/asm-i386/types.h +++ b/include/asm-i386/types.h @@ -45,6 +45,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif diff --git a/include/asm-m68k/io.h b/include/asm-m68k/io.h index 33c454a..1fccc12 100644 --- a/include/asm-m68k/io.h +++ b/include/asm-m68k/io.h @@ -232,8 +232,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-m68k/types.h b/include/asm-m68k/types.h index e944d3f..44b4ca5 100644 --- a/include/asm-m68k/types.h +++ b/include/asm-m68k/types.h @@ -44,6 +44,9 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-microblaze/io.h b/include/asm-microblaze/io.h index 90d1842..aa37a60 100644 --- a/include/asm-microblaze/io.h +++ b/include/asm-microblaze/io.h @@ -134,8 +134,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-microblaze/types.h b/include/asm-microblaze/types.h index 3895dc4..77094f6 100644 --- a/include/asm-microblaze/types.h +++ b/include/asm-microblaze/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* _ASM_TYPES_H */ diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index e27d1f1..7137072 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -470,8 +470,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-mips/types.h b/include/asm-mips/types.h index f49a217..d4bb859 100644 --- a/include/asm-mips/types.h +++ b/include/asm-mips/types.h @@ -78,8 +78,16 @@ typedef unsigned long long u64; #if (defined(CONFIG_HIGHMEM) && defined(CONFIG_64BIT_PHYS_ADDR)) \ || defined(CONFIG_64BIT) typedef u64 dma_addr_t; + +typedef u64 phys_addr_t; +typedef u64 phys_size_t; + #else typedef u32 dma_addr_t; + +typedef u32 phys_addr_t; +typedef u32 phys_size_t; + #endif typedef u64 dma64_addr_t; diff --git a/include/asm-nios/io.h b/include/asm-nios/io.h index 6fc339f..12a0bd9 100644 --- a/include/asm-nios/io.h +++ b/include/asm-nios/io.h @@ -114,8 +114,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-nios/types.h b/include/asm-nios/types.h index 24c98a8..636e12f 100644 --- a/include/asm-nios/types.h +++ b/include/asm-nios/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; /* Dma addresses are 32-bits wide. */ typedef u32 dma_addr_t; + +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; #endif /* __KERNEL__ */ #endif /* _NIOS_TYPES_H */ diff --git a/include/asm-nios2/io.h b/include/asm-nios2/io.h index a52b95c..2f1ec26 100644 --- a/include/asm-nios2/io.h +++ b/include/asm-nios2/io.h @@ -34,8 +34,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-ppc/io.h b/include/asm-ppc/io.h index 91c9c1e..00b7ec5 100644 --- a/include/asm-ppc/io.h +++ b/include/asm-ppc/io.h @@ -243,8 +243,6 @@ extern inline void out_be32(volatile unsigned __iomem *addr, int val) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-ppc/types.h b/include/asm-ppc/types.h index 7adf145..864391f 100644 --- a/include/asm-ppc/types.h +++ b/include/asm-ppc/types.h @@ -44,6 +44,14 @@ typedef unsigned long long u64; /* DMA addresses are 32-bits wide */ typedef u32 dma_addr_t; +#ifdef CONFIG_PHYS_64BIT +typedef unsigned long long phys_addr_t; +typedef unsigned long long phys_size_t; +#else +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; +#endif + #endif /* __KERNEL__ */ #endif /* __ASSEMBLY__ */ diff --git a/include/asm-sh/io.h b/include/asm-sh/io.h index 51fd10b..7400293 100644 --- a/include/asm-sh/io.h +++ b/include/asm-sh/io.h @@ -233,8 +233,6 @@ static inline void sync(void) * that can be used to access the memory range with the caching * properties specified by "flags". */ -typedef unsigned long phys_addr_t; - #define MAP_NOCACHE (0) #define MAP_WRCOMBINE (0) #define MAP_WRBACK (0) diff --git a/include/asm-sh/types.h b/include/asm-sh/types.h index 7ba69d9..aed4a6e 100644 --- a/include/asm-sh/types.h +++ b/include/asm-sh/types.h @@ -52,6 +52,9 @@ typedef unsigned long long u64; typedef u32 dma_addr_t; +typedef unsigned long phys_addr_t; +typedef unsigned long phys_size_t; + #endif /* __ASSEMBLY__ */ #endif /* __KERNEL__ */ -- 1.5.4.1

2 1

[U-Boot-Users] [PATCH] Fix host tool build breakage, take two
by Bartlomiej Sieka 14 Apr '08

14 Apr '08

Revert commit 87c8431f and fix build breakage so that the build continues to work on FC systems. Signed-off-by: Bartlomiej Sieka <tur(a)semihalf.com> --- Patch tested on FC and kubuntu. Could people that reported Haavard's patch fixing the build for them try this one out and report back? diff --git a/include/fdt.h b/include/fdt.h index 39beada..48ccfd9 100644 --- a/include/fdt.h +++ b/include/fdt.h @@ -3,10 +3,6 @@ #ifndef __ASSEMBLY__ -#ifdef USE_HOSTCC -#include <stdint.h> -#endif - struct fdt_header { uint32_t magic; /* magic word FDT_MAGIC */ uint32_t totalsize; /* total size of DT block */ diff --git a/include/libfdt_env.h b/include/libfdt_env.h index 98c522a..ab5c301 100644 --- a/include/libfdt_env.h +++ b/include/libfdt_env.h @@ -21,15 +21,16 @@ #ifndef _LIBFDT_ENV_H #define _LIBFDT_ENV_H -#include <stddef.h> -#include <linux/types.h> -#include <asm/byteorder.h> #ifdef USE_HOSTCC +#include <stdint.h> #include <string.h> #else #include <linux/string.h> +#include <linux/types.h> #endif /* USE_HOSTCC */ +#include <stddef.h> +#include <asm/byteorder.h> extern struct fdt_header *fdt; /* Pointer to the working fdt */ #define fdt32_to_cpu(x) __be32_to_cpu(x)

10 24

[U-Boot-Users] [PATCH] Add support for setting the I2C bus speed in fsl_i2c.c
by Timur Tabi 14 Apr '08

14 Apr '08

Add support to the Freescale I2C driver (fsl_i2c.c) for setting and querying the I2C bus speed. Current 8[356]xx boards define the CFG_I2C_SPEED macro, but fsl_i2c.c ignores it and uses conservative value when programming the I2C bus speed. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- This patch is for U-Boot 1.3.3. It affects 83xx, 85xx, and 86xx. drivers/i2c/fsl_i2c.c | 114 +++++++++++++++++++++++++++++++++++++++++++++---- 1 files changed, 105 insertions(+), 9 deletions(-) diff --git a/drivers/i2c/fsl_i2c.c b/drivers/i2c/fsl_i2c.c index 22485ea..dde0571 100644 --- a/drivers/i2c/fsl_i2c.c +++ b/drivers/i2c/fsl_i2c.c @@ -32,6 +32,8 @@ #define I2C_READ_BIT 1 #define I2C_WRITE_BIT 0 +DECLARE_GLOBAL_DATA_PTR; + /* Initialize the bus pointer to whatever one the SPD EEPROM is on. * Default is bus 0. This is necessary because the DDR initialization * runs from ROM, and we can't switch buses because we can't modify @@ -43,24 +45,111 @@ static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = CFG_SPD_BUS static unsigned int i2c_bus_num __attribute__ ((section ("data"))) = 0; #endif -static volatile struct fsl_i2c *i2c_dev[2] = { +static unsigned int i2c_bus_speed[2] = {CFG_I2C_SPEED, CFG_I2C_SPEED}; + +static const struct fsl_i2c *i2c_dev[2] = { (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET), #ifdef CFG_I2C2_OFFSET (struct fsl_i2c *) (CFG_IMMR + CFG_I2C2_OFFSET) #endif }; +/* I2C speed map for a DFSR value of 1 */ + +/* + * Map I2C frequency dividers to FDR and DFSR values + * + * This structure is used to define the elements of a table that maps I2C + * frequency divider (I2C clock rate divided by I2C bus speed) to a value to be + * programmed into the Frequency Divider Ratio (FDR) and Digital Filter + * Sampling Rate (DFSR) registers. + * + * The actual table should be defined in the board file, and it must be called + * fsl_i2c_speed_map[]. + * + * The last entry of the table must have a value of {-1, X}, where X is same + * FDR/DFSR values as the second-to-last entry. This guarantees that any + * search through the array will always find a match. + * + * The values of the divider must be in increasing numerical order, i.e. + * fsl_i2c_speed_map[x+1].divider > fsl_i2c_speed_map[x].divider. + * + * For this table, the values are based on a value of 1 for the DFSR + * register. See the application note AN2919 "Determining the I2C Frequency + * Divider Ratio for SCL" + */ +static const struct { + unsigned short divider; + u8 dfsr; + u8 fdr; +} fsl_i2c_speed_map[] = { + {160, 1, 32}, {192, 1, 33}, {224, 1, 34}, {256, 1, 35}, + {288, 1, 0}, {320, 1, 1}, {352, 6, 1}, {384, 1, 2}, {416, 6, 2}, + {448, 1, 38}, {480, 1, 3}, {512, 1, 39}, {544, 11, 3}, {576, 1, 4}, + {608, 22, 3}, {640, 1, 5}, {672, 32, 3}, {704, 11, 5}, {736, 43, 3}, + {768, 1, 6}, {800, 54, 3}, {832, 11, 6}, {896, 1, 42}, {960, 1, 7}, + {1024, 1, 43}, {1088, 22, 7}, {1152, 1, 8}, {1216, 43, 7}, {1280, 1, 9}, + {1408, 22, 9}, {1536, 1, 10}, {1664, 22, 10}, {1792, 1, 46}, + {1920, 1, 11}, {2048, 1, 47}, {2176, 43, 11}, {2304, 1, 12}, + {2560, 1, 13}, {2816, 43, 13}, {3072, 1, 14}, {3328, 43, 14}, + {3584, 1, 50}, {3840, 1, 15}, {4096, 1, 51}, {4608, 1, 16}, + {5120, 1, 17}, {6144, 1, 18}, {7168, 1, 54}, {7680, 1, 19}, + {8192, 1, 55}, {9216, 1, 20}, {10240, 1, 21}, {12288, 1, 22}, + {14336, 1, 58}, {15360, 1, 23}, {16384, 1, 59}, {18432, 1, 24}, + {20480, 1, 25}, {24576, 1, 26}, {28672, 1, 62}, {30720, 1, 27}, + {32768, 1, 63}, {36864, 1, 28}, {40960, 1, 29}, {49152, 1, 30}, + {61440, 1, 31}, {-1, 1, 31} +}; + +/** + * Set the I2C bus speed for a given I2C device + * + * @param dev: the I2C device + * @i2c_clk: I2C bus clock frequency + * @speed: the desired speed of the bus + * + * The I2C device must be stopped before calling this function. + * + * The return value is the actual bus speed that is set. + */ +static unsigned int set_i2c_bus_speed(const struct fsl_i2c *dev, + unsigned int i2c_clk, unsigned int speed) +{ + unsigned short divider = min(i2c_clk / speed, (unsigned short) -1); + unsigned int i; + u8 fdr, dfsr; + + /* + * We want to choose an FDR/DFSR that generates an I2C bus speed that + * is equal to or lower than the requested speed. That means that we + * want the first divider that is equal to or greater than the + * calculated divider. + */ + + for (i = 0; i < ARRAY_SIZE(fsl_i2c_speed_map); i++) + if (fsl_i2c_speed_map[i].divider >= divider) { + dfsr = fsl_i2c_speed_map[i].dfsr; + fdr = fsl_i2c_speed_map[i].fdr; + speed = i2c_clk / fsl_i2c_speed_map[i].divider; + break; + } + + writeb(fdr, &dev->fdr); /* set bus speed */ + writeb(dfsr, &dev->dfsrr); /* set default filter */ + + return speed; +} + void i2c_init(int speed, int slaveadd) { - volatile struct fsl_i2c *dev; + struct fsl_i2c *dev; dev = (struct fsl_i2c *) (CFG_IMMR + CFG_I2C_OFFSET); writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ - writeb(0x3F, &dev->fdr); /* set bus speed */ - writeb(0x3F, &dev->dfsrr); /* set default filter */ + i2c_bus_speed[0] = set_i2c_bus_speed(dev, gd->i2c1_clk, speed); writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ @@ -70,12 +159,11 @@ i2c_init(int speed, int slaveadd) writeb(0, &dev->cr); /* stop I2C controller */ udelay(5); /* let it shutdown in peace */ - writeb(0x3F, &dev->fdr); /* set bus speed */ - writeb(0x3F, &dev->dfsrr); /* set default filter */ + i2c_bus_speed[1] = set_i2c_bus_speed(dev, gd->i2c2_clk, speed); writeb(slaveadd << 1, &dev->adr); /* write slave address */ writeb(0x0, &dev->sr); /* clear status register */ writeb(I2C_CR_MEN, &dev->cr); /* start I2C controller */ -#endif /* CFG_I2C2_OFFSET */ +#endif } static __inline__ int @@ -279,7 +367,14 @@ int i2c_set_bus_num(unsigned int bus) int i2c_set_bus_speed(unsigned int speed) { - return -1; + unsigned int i2c_clk = (i2c_bus_num == 1) ? gd->i2c2_clk : gd->i2c1_clk; + + writeb(0, &i2c_dev[i2c_bus_num]->cr); /* stop controller */ + i2c_bus_speed[i2c_bus_num] = + set_i2c_bus_speed(i2c_dev[i2c_bus_num], i2c_clk, speed); + writeb(I2C_CR_MEN, &i2c_dev[i2c_bus_num]->cr); /* start controller */ + + return 0; } unsigned int i2c_get_bus_num(void) @@ -289,7 +384,8 @@ unsigned int i2c_get_bus_num(void) unsigned int i2c_get_bus_speed(void) { - return 0; + return i2c_bus_speed[i2c_bus_num]; } + #endif /* CONFIG_HARD_I2C */ #endif /* CONFIG_FSL_I2C */ -- 1.5.4

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