March 2008 - U-Boot

[U-Boot-Users] [PATCH v2 7/7] Support for the MX31ADS evaluation board from Freescale
by Guennadi Liakhovetski 20 Apr '08

20 Apr '08

This patch adds support for the MX31ADS evaluation board from Freescale, initialization code is copied from RedBoot sources, also provided by Freescale. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Changes since v1: removed C++ style comments, disabled CONFIG_FIT, fixed patch format damage MAKEALL | 1 + Makefile | 3 + board/mx31ads/Makefile | 47 +++++ board/{imx31_litekit => mx31ads}/config.mk | 0 board/mx31ads/lowlevel_init.S | 281 +++++++++++++++++++++++++++ board/mx31ads/mx31ads.c | 95 +++++++++ board/{imx31_litekit => mx31ads}/u-boot.lds | 0 include/asm-arm/arch-mx31/mx31-regs.h | 14 ++ include/configs/mx31ads.h | 157 +++++++++++++++ 9 files changed, 598 insertions(+), 0 deletions(-) create mode 100644 board/mx31ads/Makefile copy board/{imx31_litekit => mx31ads}/config.mk (100%) create mode 100644 board/mx31ads/lowlevel_init.S create mode 100644 board/mx31ads/mx31ads.c copy board/{imx31_litekit => mx31ads}/u-boot.lds (100%) create mode 100644 include/configs/mx31ads.h diff --git a/MAKEALL b/MAKEALL index 0ca866f..d192ed2 100755 --- a/MAKEALL +++ b/MAKEALL @@ -504,6 +504,7 @@ LIST_ARM11=" \ apollon \ imx31_litekit \ imx31_phycore \ + mx31ads \ " ######################################################################### diff --git a/Makefile b/Makefile index b3cbb20..207f5bc 100644 --- a/Makefile +++ b/Makefile @@ -2601,6 +2601,9 @@ imx31_litekit_config : unconfig imx31_phycore_config : unconfig @$(MKCONFIG) $(@:_config=) arm arm1136 imx31_phycore NULL mx31 +mx31ads_config : unconfig + @$(MKCONFIG) $(@:_config=) arm arm1136 mx31ads NULL mx31 + #======================================================================== # i386 #======================================================================== diff --git a/board/mx31ads/Makefile b/board/mx31ads/Makefile new file mode 100644 index 0000000..dfadd96 --- /dev/null +++ b/board/mx31ads/Makefile @@ -0,0 +1,47 @@ +# +# Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := mx31ads.o +SOBJS := lowlevel_init.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) $(SOBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(SOBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/imx31_litekit/config.mk b/board/mx31ads/config.mk similarity index 100% copy from board/imx31_litekit/config.mk copy to board/mx31ads/config.mk diff --git a/board/mx31ads/lowlevel_init.S b/board/mx31ads/lowlevel_init.S new file mode 100644 index 0000000..099a7ca --- /dev/null +++ b/board/mx31ads/lowlevel_init.S @@ -0,0 +1,281 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <asm/arch/mx31-regs.h> + +.macro REG reg, val + ldr r2, =\reg + ldr r3, =\val + str r3, [r2] +.endm + +.macro REG8 reg, val + ldr r2, =\reg + ldr r3, =\val + strb r3, [r2] +.endm + +.macro DELAY loops + ldr r2, =\loops +1: + subs r2, r2, #1 + nop + bcs 1b +.endm + +/* RedBoot: AIPS setup - Only setup MPROTx registers. + * The PACR default values are good.*/ +.macro init_aips + /* + * Set all MPROTx to be non-bufferable, trusted for R/W, + * not forced to user-mode. + */ + ldr r0, =0x43F00000 + ldr r1, =0x77777777 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + ldr r0, =0x53F00000 + str r1, [r0, #0x00] + str r1, [r0, #0x04] + + /* + * Clear the on and off peripheral modules Supervisor Protect bit + * for SDMA to access them. Did not change the AIPS control registers + * (offset 0x20) access type + */ + ldr r0, =0x43F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] + + ldr r0, =0x53F00000 + ldr r1, =0x0 + str r1, [r0, #0x40] + str r1, [r0, #0x44] + str r1, [r0, #0x48] + str r1, [r0, #0x4C] + ldr r1, [r0, #0x50] + and r1, r1, #0x00FFFFFF + str r1, [r0, #0x50] +.endm /* init_aips */ + +/* RedBoot: MAX (Multi-Layer AHB Crossbar Switch) setup */ +.macro init_max + ldr r0, =0x43F04000 + /* MPR - priority is M4 > M2 > M3 > M5 > M0 > M1 */ + ldr r1, =0x00302154 + str r1, [r0, #0x000] /* for S0 */ + str r1, [r0, #0x100] /* for S1 */ + str r1, [r0, #0x200] /* for S2 */ + str r1, [r0, #0x300] /* for S3 */ + str r1, [r0, #0x400] /* for S4 */ + /* SGPCR - always park on last master */ + ldr r1, =0x10 + str r1, [r0, #0x010] /* for S0 */ + str r1, [r0, #0x110] /* for S1 */ + str r1, [r0, #0x210] /* for S2 */ + str r1, [r0, #0x310] /* for S3 */ + str r1, [r0, #0x410] /* for S4 */ + /* MGPCR - restore default values */ + ldr r1, =0x0 + str r1, [r0, #0x800] /* for M0 */ + str r1, [r0, #0x900] /* for M1 */ + str r1, [r0, #0xA00] /* for M2 */ + str r1, [r0, #0xB00] /* for M3 */ + str r1, [r0, #0xC00] /* for M4 */ + str r1, [r0, #0xD00] /* for M5 */ +.endm /* init_max */ + +/* RedBoot: M3IF setup */ +.macro init_m3if + /* Configure M3IF registers */ + ldr r1, =0xB8003000 + /* + * M3IF Control Register (M3IFCTL) + * MRRP[0] = L2CC0 not on priority list (0 << 0) = 0x00000000 + * MRRP[1] = L2CC1 not on priority list (0 << 0) = 0x00000000 + * MRRP[2] = MBX not on priority list (0 << 0) = 0x00000000 + * MRRP[3] = MAX1 not on priority list (0 << 0) = 0x00000000 + * MRRP[4] = SDMA not on priority list (0 << 0) = 0x00000000 + * MRRP[5] = MPEG4 not on priority list (0 << 0) = 0x00000000 + * MRRP[6] = IPU1 on priority list (1 << 6) = 0x00000040 + * MRRP[7] = IPU2 not on priority list (0 << 0) = 0x00000000 + * ------------ + * 0x00000040 + */ + ldr r0, =0x00000040 + str r0, [r1] /* M3IF control reg */ +.endm /* init_m3if */ + +/* RedBoot: To support 133MHz DDR */ +.macro init_drive_strength + /* + * Disable maximum drive strength SDRAM/DDR lines by clearing DSE1 bits + * in SW_PAD_CTL registers + */ + + /* SDCLK */ + ldr r1, =0x43FAC200 + ldr r0, [r1, #0x6C] + bic r0, r0, #(1 << 12) + str r0, [r1, #0x6C] + + /* CAS */ + ldr r0, [r1, #0x70] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x70] + + /* RAS */ + ldr r0, [r1, #0x74] + bic r0, r0, #(1 << 2) + str r0, [r1, #0x74] + + /* CS2 (CSD0) */ + ldr r0, [r1, #0x7C] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x7C] + + /* DQM3 */ + ldr r0, [r1, #0x84] + bic r0, r0, #(1 << 22) + str r0, [r1, #0x84] + + /* DQM2, DQM1, DQM0, SD31-SD0, A25-A0, MA10 (0x288..0x2DC) */ + ldr r2, =22 /* (0x2E0 - 0x288) / 4 = 22 */ +pad_loop: + ldr r0, [r1, #0x88] + bic r0, r0, #(1 << 22) + bic r0, r0, #(1 << 12) + bic r0, r0, #(1 << 2) + str r0, [r1, #0x88] + add r1, r1, #4 + subs r2, r2, #0x1 + bne pad_loop +.endm /* init_drive_strength */ + +/* CPLD on CS4 setup */ +.macro init_cs4 + ldr r0, =WEIM_BASE + ldr r1, =0x0000D843 + str r1, [r0, #0x40] + ldr r1, =0x22252521 + str r1, [r0, #0x44] + ldr r1, =0x22220A00 + str r1, [r0, #0x48] +.endm /* init_cs4 */ + +.globl lowlevel_init +lowlevel_init: + + /* Redboot initializes very early AIPS, what for? + * Then it also initializes Multi-Layer AHB Crossbar Switch, + * M3IF */ + /* Also setup the Peripheral Port Remap register inside the core */ + ldr r0, =0x40000015 /* start from AIPS 2GB region */ + mcr p15, 0, r0, c15, c2, 4 + + init_aips + + init_max + + init_m3if + + init_drive_strength + + init_cs4 + + /* Image Processing Unit: */ + /* Too early to switch display on? */ + REG IPU_CONF, IPU_CONF_DI_EN /* Switch on Display Interface */ + /* Clock Control Module: */ + REG CCM_CCMR, 0x074B0BF5 /* Use CKIH, MCU PLL off */ + + DELAY 0x40000 + + REG CCM_CCMR, 0x074B0BF5 | CCMR_MPE /* MCU PLL on */ + REG CCM_CCMR, (0x074B0BF5 | CCMR_MPE) & ~CCMR_MDS /* Switch to MCU PLL */ + + /* PBC CPLD on CS4 */ + mov r1, #CS4_BASE + ldrh r1, [r1, #0x2] + /* Is 27MHz switch set? */ + ands r1, r1, #0x16 + + /* 532-133-66.5 */ + ldr r0, =CCM_BASE + ldr r1, =0xFF871D58 + /* PDR0 */ + str r1, [r0, #0x4] + ldreq r1, MPCTL_PARAM_532 + ldrne r1, MPCTL_PARAM_532_27 + /* MPCTL */ + str r1, [r0, #0x10] + + /* Set UPLL=240MHz, USB=60MHz */ + ldr r1, =0x49FCFE7F + /* PDR1 */ + str r1, [r0, #0x8] + ldreq r1, UPCTL_PARAM_240 + ldrne r1, UPCTL_PARAM_240_27 + /* UPCTL */ + str r1, [r0, #0x14] + /* default CLKO to 1/8 of the ARM core */ + mov r1, #0x000002C0 + add r1, r1, #0x00000006 + /* COSR */ + str r1, [r0, #0x1c] + + /* RedBoot sets 0x1ff, 7, 3, 5, 1, 3, 0 */ +/* REG CCM_PDR0, PDR0_CSI_PODF(0x1ff) | PDR0_PER_PODF(7) | PDR0_HSP_PODF(2) | PDR0_NFC_PODF(6) | PDR0_IPG_PODF(1) | PDR0_MAX_PODF(2) | PDR0_MCU_PODF(0)*/ + + /* Redboot: 0, 51, 10, 12 / 0, 14, 9, 13 */ +/* REG CCM_MPCTL, PLL_PD(0) | PLL_MFD(0x33) | PLL_MFI(7) | PLL_MFN(0x23)*/ + /* Default: 1, 4, 12, 1 */ + REG CCM_SPCTL, PLL_PD(1) | PLL_MFD(4) | PLL_MFI(12) | PLL_MFN(1) + + /* B8xxxxxx - NAND, 8xxxxxxx - CSD0 RAM */ + REG 0xB8001010, 0x00000004 + REG 0xB8001004, 0x006ac73a + REG 0xB8001000, 0x92100000 + REG 0x80000f00, 0x12344321 + REG 0xB8001000, 0xa2100000 + REG 0x80000000, 0x12344321 + REG 0x80000000, 0x12344321 + REG 0xB8001000, 0xb2100000 + REG8 0x80000033, 0xda + REG8 0x81000000, 0xff + REG 0xB8001000, 0x82226080 + REG 0x80000000, 0xDEADBEEF + REG 0xB8001010, 0x0000000c + + mov pc, lr + +MPCTL_PARAM_532: + .word (((1-1) << 26) + ((52-1) << 16) + (10 << 10) + (12 << 0)) +MPCTL_PARAM_532_27: + .word (((1-1) << 26) + ((15-1) << 16) + (9 << 10) + (13 << 0)) +UPCTL_PARAM_240: + .word (((2-1) << 26) + ((13-1) << 16) + (9 << 10) + (3 << 0)) +UPCTL_PARAM_240_27: + .word (((2-1) << 26) + ((9 -1) << 16) + (8 << 10) + (8 << 0)) diff --git a/board/mx31ads/mx31ads.c b/board/mx31ads/mx31ads.c new file mode 100644 index 0000000..a92adb7 --- /dev/null +++ b/board/mx31ads/mx31ads.c @@ -0,0 +1,94 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/io.h> +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +DECLARE_GLOBAL_DATA_PTR; + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return 0; +} + +int board_init (void) +{ + int i; +#if 0 + /* CS0: Nor Flash */ + /* + * These are values from the RedBoot sources by Freescale. However, + * under U-Boot with this configuration 32-bit accesses don't work, + * lower 16 bits of data are read twice for each 32-bit read. + */ + __REG(CSCR_U(0)) = 0x23524E80; + __REG(CSCR_L(0)) = 0x10000D03; /* WRAP bit (1) is suspicious here, but + * disabling it doesn't help either */ + __REG(CSCR_A(0)) = 0x00720900; +#endif + + /* setup pins for UART1 */ + mx31_gpio_mux(MUX_RXD1__UART1_RXD_MUX); + mx31_gpio_mux(MUX_TXD1__UART1_TXD_MUX); + mx31_gpio_mux(MUX_RTS1__UART1_RTS_B); + mx31_gpio_mux(MUX_RTS1__UART1_CTS_B); + + /* PBC setup */ + /* Enable UART transceivers also reset the Ethernet/external UART */ + readw(CS4_BASE + 4); + + writew(0x8023, CS4_BASE + 4); + + /* RedBoot also has an empty loop with 100000 iterations here - + * clock doesn't run yet */ + for (i = 0; i < 100000; i++) + ; + + /* Clear the reset, toggle the LEDs */ + writew(0xDF, CS4_BASE + 6); + + /* clock still doesn't run */ + for (i = 0; i < 100000; i++) + ; + + /* See 1.5.4 in IMX31ADSE_PERI_BUS_CNTRL_CPLD_RM.pdf */ + readb(CS4_BASE + 8); + readb(CS4_BASE + 7); + readb(CS4_BASE + 8); + readb(CS4_BASE + 7); + + gd->bd->bi_arch_number = 447; /* board id for linux */ + gd->bd->bi_boot_params = 0x80000100; /* adress of boot parameters */ + + return 0; +} + +int checkboard (void) +{ + printf("Board: MX31ADS\n"); + return 0; +} diff --git a/board/imx31_litekit/u-boot.lds b/board/mx31ads/u-boot.lds similarity index 100% copy from board/imx31_litekit/u-boot.lds copy to board/mx31ads/u-boot.lds diff --git a/include/asm-arm/arch-mx31/mx31-regs.h b/include/asm-arm/arch-mx31/mx31-regs.h index c004478..e9c7671 100644 --- a/include/asm-arm/arch-mx31/mx31-regs.h +++ b/include/asm-arm/arch-mx31/mx31-regs.h @@ -133,6 +133,20 @@ #define MUX_CSPI2_MOSI__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MOSI) #define MUX_CSPI2_MISO__I2C2_SCL ((MUX_CTL_ALT1 << 8) | MUX_CTL_CSPI2_MISO) +/* + * Memory regions and CS + */ +#define IPU_MEM_BASE 0x70000000 +#define CSD0_BASE 0x80000000 +#define CSD1_BASE 0x90000000 +#define CS0_BASE 0xA0000000 +#define CS1_BASE 0xA8000000 +#define CS2_BASE 0xB0000000 +#define CS3_BASE 0xB2000000 +#define CS4_BASE 0xB4000000 +#define CS4_PSRAM_BASE 0xB5000000 +#define CS5_BASE 0xB6000000 +#define PCMCIA_MEM_BASE 0xC0000000 #endif /* __ASM_ARCH_MX31_REGS_H */ diff --git a/include/configs/mx31ads.h b/include/configs/mx31ads.h new file mode 100644 index 0000000..49e733b --- /dev/null +++ b/include/configs/mx31ads.h @@ -0,0 +1,166 @@ +/* + * Copyright (C) 2008, Guennadi Liakhovetski <lg(a)denx.de> + * + * Configuration settings for the MX31ADS Freescale board. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#include <asm/arch/mx31-regs.h> + + /* High Level Configuration Options */ +#define CONFIG_ARM1136 1 /* This is an arm1136 CPU core */ +#define CONFIG_MX31 1 /* in a mx31 */ +#define CONFIG_MX31_HCLK_FREQ 26000000 /* RedBoot says 26MHz */ +#define CONFIG_MX31_CLK32 32000 + +#define CONFIG_DISPLAY_CPUINFO +#define CONFIG_DISPLAY_BOARDINFO + +/* + * Disabled for now due to build problems under Debian and a significant increase + * in the final file size: 144260 vs. 109536 Bytes. + */ +#if 0 +#define CONFIG_OF_LIBFDT 1 +#define CONFIG_FIT 1 +#define CONFIG_FIT_VERBOSE 1 +#endif + +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128 * 1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* + * Hardware drivers + */ + +#define CONFIG_MX31_UART 1 +#define CFG_MX31_UART1 1 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE +#define CONFIG_CONS_INDEX 1 +#define CONFIG_BAUDRATE 115200 +#define CFG_BAUDRATE_TABLE {9600, 19200, 38400, 57600, 115200} + +/*********************************************************** + * Command definition + ***********************************************************/ + +#include <config_cmd_default.h> + +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING + +#define CONFIG_BOOTDELAY 3 + +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.23.168 +#define CONFIG_SERVERIP 192.168.23.2 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "bootargs_base=setenv bootargs console=ttymxc0,115200\0" \ + "bootargs_nfs=setenv bootargs $(bootargs) root=/dev/nfs ip=dhcp nfsroot=$(serverip):$(nfsrootfs),v3,tcp\0" \ + "bootcmd=run bootcmd_net\0" \ + "bootcmd_net=run bootargs_base bootargs_mtd bootargs_nfs; tftpboot 0x80000000 uImage-mx31; bootm\0" \ + "prg_uboot=tftpboot 0x80000000 u-boot-mx31ads.bin; protect off 0xa0000000 0xa001ffff; erase 0xa0000000 0xa001ffff; cp.b 0x80000000 0xa0000000 $(filesize)\0" + + +#define CONFIG_DRIVER_CS8900 1 +#define CS8900_BASE 0xb4020300 +#define CS8900_BUS16 1 /* the Linux driver does accesses as shorts */ + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0 /* memtest works on */ +#define CFG_MEMTEST_END 0x10000 + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR CSD0_BASE /* default load address */ + +#define CFG_HZ 32000 + +#define CONFIG_CMDLINE_EDITING 1 + +/*----------------------------------------------------------------------- + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ + +/*----------------------------------------------------------------------- + * Physical Memory Map + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 CSD0_BASE +#define PHYS_SDRAM_1_SIZE (128 * 1024 * 1024) + +/*----------------------------------------------------------------------- + * FLASH and environment organization + */ +#define CFG_FLASH_BASE CS0_BASE +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 262 /* max number of sectors on one chip */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE /* Monitor at beginning of flash */ +#define CFG_MONITOR_LEN (128 * 1024) /* Reserve 128KiB */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SECT_SIZE (32 * 1024) +#define CFG_ENV_SIZE CFG_ENV_SECT_SIZE +/* S29WS256N NOR flash has 4 32KiB small sectors at the beginning and at the end. + * The rest of 32MiB is in 128KiB big sectors. U-Boot occupies the low 4 sectors, + * if we put environment next to it, we will have to occupy 128KiB for it. + * Putting it at the top of flash we use only 32KiB. */ +#define CFG_ENV_ADDR (CFG_MONITOR_BASE + 32 * 1024 * 1024 - CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * CFI FLASH driver setup + */ +#define CFG_FLASH_CFI 1 /* Flash memory is CFI compliant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use drivers/cfi_flash.c */ +#if 0 /* Doesn't work yet, work in progress */ +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* Use buffered writes (~10x faster) */ +#endif +#define CFG_FLASH_PROTECTION 1 /* Use hardware sector protection */ + +/* + * JFFS2 partitions + */ +#undef CONFIG_JFFS2_CMDLINE +#define CONFIG_JFFS2_DEV "nor0" + +#endif /* __CONFIG_H */ -- 1.5.4

2 3

[U-Boot-Users] [PATCH] Add support for u-boot in svn and localversion-* files
by Mike Frysinger 20 Apr '08

20 Apr '08

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/setlocalversion | 14 ++++++++++++++ 1 files changed, 14 insertions(+), 0 deletions(-) diff --git a/tools/setlocalversion b/tools/setlocalversion index 9a23825..5ff7f2e 100755 --- a/tools/setlocalversion +++ b/tools/setlocalversion @@ -19,4 +19,18 @@ if head=`git rev-parse --verify HEAD 2>/dev/null`; then if git diff-files | read dummy; then printf '%s' -dirty fi + + # Is this git on svn? + if git config --get svn-remote.svn.url >/dev/null; then + printf -- '-svn%s' "`git-svn find-rev $head`" + fi fi + +# Check for svn and a svn repo. +if rev=`svn info 2>/dev/null` ; then + rev=`echo "${rev}" | grep '^Revision' | awk '{print $NF}'` + printf -- '-svn%s' $rev +fi + +# Check for any localversion-* files +printf '%s' "`cat localversion-* 2>/dev/null`" -- 1.5.3.8

5 9

[U-Boot-Users] U-Boot WinCE booting support?
by Stefan Roese 19 Apr '08

19 Apr '08

Hi, I'm wondering what may be needed to boot WinCE (6.0) images from U-Boot. Searching the web leads to some pages that mention booting WinCE is possible. But my understanding is that some additional patches are necessary and the official U-Boot doesn't support this currently. Does anybody have experience with this? Any hints appreciated. Thanks. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

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[U-Boot-Users] [PATCH v2 2/2] Freescale eLBC FCM NAND driver
by Scott Wood 18 Apr '08

18 Apr '08

This is a driver for the Flash Control Machine of the enhanched Local Bus Controller found on some Freescale chips (such as the mpc8313 and the mpc8379). Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- Fixed one instance of trailing whitespace, moved the conditional to the makefile, and increased the hardware timeout to the maximum after receiving a report that some boards need higher that the old setting. drivers/mtd/nand/Makefile | 1 + drivers/mtd/nand/fsl_elbc_nand.c | 759 ++++++++++++++++++++++++++++++++++++++ 2 files changed, 760 insertions(+), 0 deletions(-) create mode 100644 drivers/mtd/nand/fsl_elbc_nand.c diff --git a/drivers/mtd/nand/Makefile b/drivers/mtd/nand/Makefile index 244fa09..10ad247 100644 --- a/drivers/mtd/nand/Makefile +++ b/drivers/mtd/nand/Makefile @@ -32,6 +32,7 @@ COBJS-y += nand_ecc.o COBJS-y += nand_bbt.o COBJS-y += nand_util.o +COBJS-$(CONFIG_NAND_FSL_ELBC) += fsl_elbc_nand.o COBJS-y += fsl_upm.o COBJS := $(COBJS-y) diff --git a/drivers/mtd/nand/fsl_elbc_nand.c b/drivers/mtd/nand/fsl_elbc_nand.c new file mode 100644 index 0000000..c1644c0 --- /dev/null +++ b/drivers/mtd/nand/fsl_elbc_nand.c @@ -0,0 +1,759 @@ +/* Freescale Enhanced Local Bus Controller FCM NAND driver + * + * Copyright (c) 2006-2008 Freescale Semiconductor + * + * Authors: Nick Spence <nick.spence(a)freescale.com>, + * Scott Wood <scottwood(a)freescale.com> + * + * This program is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> + +#include <linux/mtd/mtd.h> +#include <linux/mtd/nand.h> +#include <linux/mtd/nand_ecc.h> + +#include <asm/io.h> +#include <asm/errno.h> + +#ifdef VERBOSE_DEBUG +#define DEBUG_ELBC +#define vdbg(format, arg...) printf("DEBUG: " format, ##arg) +#else +#define vdbg(format, arg...) do {} while (0) +#endif + +/* Can't use plain old DEBUG because the linux mtd + * headers define it as a macro. + */ +#ifdef DEBUG_ELBC +#define dbg(format, arg...) printf("DEBUG: " format, ##arg) +#else +#define dbg(format, arg...) do {} while (0) +#endif + +#define MAX_BANKS 8 +#define ERR_BYTE 0xFF /* Value returned for read bytes when read failed */ +#define FCM_TIMEOUT_MSECS 10 /* Maximum number of mSecs to wait for FCM */ + +#define LTESR_NAND_MASK (LTESR_FCT | LTESR_PAR | LTESR_CC) + +struct fsl_elbc_ctrl; + +/* mtd information per set */ + +struct fsl_elbc_mtd { + struct mtd_info mtd; + struct nand_chip chip; + struct fsl_elbc_ctrl *ctrl; + + struct device *dev; + int bank; /* Chip select bank number */ + u8 __iomem *vbase; /* Chip select base virtual address */ + int page_size; /* NAND page size (0=512, 1=2048) */ + unsigned int fmr; /* FCM Flash Mode Register value */ +}; + +/* overview of the fsl elbc controller */ + +struct fsl_elbc_ctrl { + struct nand_hw_control controller; + struct fsl_elbc_mtd *chips[MAX_BANKS]; + + /* device info */ + lbus83xx_t *regs; + u8 __iomem *addr; /* Address of assigned FCM buffer */ + unsigned int page; /* Last page written to / read from */ + unsigned int read_bytes; /* Number of bytes read during command */ + unsigned int column; /* Saved column from SEQIN */ + unsigned int index; /* Pointer to next byte to 'read' */ + unsigned int status; /* status read from LTESR after last op */ + unsigned int mdr; /* UPM/FCM Data Register value */ + unsigned int use_mdr; /* Non zero if the MDR is to be set */ + unsigned int oob; /* Non zero if operating on OOB data */ + uint8_t *oob_poi; /* Place to write ECC after read back */ +}; + +/* These map to the positions used by the FCM hardware ECC generator */ + +/* Small Page FLASH with FMR[ECCM] = 0 */ +static struct nand_ecclayout fsl_elbc_oob_sp_eccm0 = { + .eccbytes = 3, + .eccpos = {6, 7, 8}, + .oobfree = { {0, 5}, {9, 7} }, + .oobavail = 12, +}; + +/* Small Page FLASH with FMR[ECCM] = 1 */ +static struct nand_ecclayout fsl_elbc_oob_sp_eccm1 = { + .eccbytes = 3, + .eccpos = {8, 9, 10}, + .oobfree = { {0, 5}, {6, 2}, {11, 5} }, + .oobavail = 12, +}; + +/* Large Page FLASH with FMR[ECCM] = 0 */ +static struct nand_ecclayout fsl_elbc_oob_lp_eccm0 = { + .eccbytes = 12, + .eccpos = {6, 7, 8, 22, 23, 24, 38, 39, 40, 54, 55, 56}, + .oobfree = { {1, 5}, {9, 13}, {25, 13}, {41, 13}, {57, 7} }, + .oobavail = 48, +}; + +/* Large Page FLASH with FMR[ECCM] = 1 */ +static struct nand_ecclayout fsl_elbc_oob_lp_eccm1 = { + .eccbytes = 12, + .eccpos = {8, 9, 10, 24, 25, 26, 40, 41, 42, 56, 57, 58}, + .oobfree = { {1, 7}, {11, 13}, {27, 13}, {43, 13}, {59, 5} }, + .oobavail = 48, +}; + +/*=================================*/ + +/* + * Set up the FCM hardware block and page address fields, and the fcm + * structure addr field to point to the correct FCM buffer in memory + */ +static void set_addr(struct mtd_info *mtd, int column, int page_addr, int oob) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + int buf_num; + + ctrl->page = page_addr; + + out_be32(&lbc->fbar, + page_addr >> (chip->phys_erase_shift - chip->page_shift)); + + if (priv->page_size) { + out_be32(&lbc->fpar, + ((page_addr << FPAR_LP_PI_SHIFT) & FPAR_LP_PI) | + (oob ? FPAR_LP_MS : 0) | column); + buf_num = (page_addr & 1) << 2; + } else { + out_be32(&lbc->fpar, + ((page_addr << FPAR_SP_PI_SHIFT) & FPAR_SP_PI) | + (oob ? FPAR_SP_MS : 0) | column); + buf_num = page_addr & 7; + } + + ctrl->addr = priv->vbase + buf_num * 1024; + ctrl->index = column; + + /* for OOB data point to the second half of the buffer */ + if (oob) + ctrl->index += priv->page_size ? 2048 : 512; + + vdbg("set_addr: bank=%d, ctrl->addr=0x%p (0x%p), " + "index %x, pes %d ps %d\n", + buf_num, ctrl->addr, priv->vbase, ctrl->index, + chip->phys_erase_shift, chip->page_shift); +} + +/* + * execute FCM command and wait for it to complete + */ +static int fsl_elbc_run_command(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + long long end_tick; + u32 ltesr; + + /* Setup the FMR[OP] to execute without write protection */ + out_be32(&lbc->fmr, priv->fmr | 3); + if (ctrl->use_mdr) + out_be32(&lbc->mdr, ctrl->mdr); + + vdbg("fsl_elbc_run_command: fmr=%08x fir=%08x fcr=%08x\n", + in_be32(&lbc->fmr), in_be32(&lbc->fir), in_be32(&lbc->fcr)); + vdbg("fsl_elbc_run_command: fbar=%08x fpar=%08x " + "fbcr=%08x bank=%d\n", + in_be32(&lbc->fbar), in_be32(&lbc->fpar), + in_be32(&lbc->fbcr), priv->bank); + + /* execute special operation */ + out_be32(&lbc->lsor, priv->bank); + + /* wait for FCM complete flag or timeout */ + end_tick = usec2ticks(FCM_TIMEOUT_MSECS * 1000) + get_ticks(); + + ltesr = 0; + while (end_tick > get_ticks()) { + ltesr = in_be32(&lbc->ltesr); + if (ltesr & LTESR_CC) + break; + } + + ctrl->status = ltesr & LTESR_NAND_MASK; + out_be32(&lbc->ltesr, ctrl->status); + out_be32(&lbc->lteatr, 0); + + /* store mdr value in case it was needed */ + if (ctrl->use_mdr) + ctrl->mdr = in_be32(&lbc->mdr); + + ctrl->use_mdr = 0; + + vdbg("fsl_elbc_run_command: stat=%08x mdr=%08x fmr=%08x\n", + ctrl->status, ctrl->mdr, in_be32(&lbc->fmr)); + + /* returns 0 on success otherwise non-zero) */ + return ctrl->status == LTESR_CC ? 0 : -EIO; +} + +static void fsl_elbc_do_read(struct nand_chip *chip, int oob) +{ + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + + if (priv->page_size) { + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_CW1 << FIR_OP3_SHIFT) | + (FIR_OP_RBW << FIR_OP4_SHIFT)); + + out_be32(&lbc->fcr, (NAND_CMD_READ0 << FCR_CMD0_SHIFT) | + (NAND_CMD_READSTART << FCR_CMD1_SHIFT)); + } else { + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_RBW << FIR_OP3_SHIFT)); + + if (oob) + out_be32(&lbc->fcr, + NAND_CMD_READOOB << FCR_CMD0_SHIFT); + else + out_be32(&lbc->fcr, NAND_CMD_READ0 << FCR_CMD0_SHIFT); + } +} + +/* cmdfunc send commands to the FCM */ +static void fsl_elbc_cmdfunc(struct mtd_info *mtd, unsigned int command, + int column, int page_addr) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + + ctrl->use_mdr = 0; + + /* clear the read buffer */ + ctrl->read_bytes = 0; + if (command != NAND_CMD_PAGEPROG) + ctrl->index = 0; + + switch (command) { + /* READ0 and READ1 read the entire buffer to use hardware ECC. */ + case NAND_CMD_READ1: + column += 256; + + /* fall-through */ + case NAND_CMD_READ0: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_READ0, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + + out_be32(&lbc->fbcr, 0); /* read entire page to enable ECC */ + set_addr(mtd, 0, page_addr, 0); + + ctrl->read_bytes = mtd->writesize + mtd->oobsize; + ctrl->index += column; + + fsl_elbc_do_read(chip, 0); + fsl_elbc_run_command(mtd); + return; + + /* READOOB reads only the OOB because no ECC is performed. */ + case NAND_CMD_READOOB: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_READOOB, page_addr:" + " 0x%x, column: 0x%x.\n", page_addr, column); + + out_be32(&lbc->fbcr, mtd->oobsize - column); + set_addr(mtd, column, page_addr, 1); + + ctrl->read_bytes = mtd->writesize + mtd->oobsize; + + fsl_elbc_do_read(chip, 1); + fsl_elbc_run_command(mtd); + + return; + + /* READID must read all 5 possible bytes while CEB is active */ + case NAND_CMD_READID: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_READID.\n"); + + out_be32(&lbc->fir, (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_UA << FIR_OP1_SHIFT) | + (FIR_OP_RBW << FIR_OP2_SHIFT)); + out_be32(&lbc->fcr, NAND_CMD_READID << FCR_CMD0_SHIFT); + /* 5 bytes for manuf, device and exts */ + out_be32(&lbc->fbcr, 5); + ctrl->read_bytes = 5; + ctrl->use_mdr = 1; + ctrl->mdr = 0; + + set_addr(mtd, 0, 0, 0); + fsl_elbc_run_command(mtd); + return; + + /* ERASE1 stores the block and page address */ + case NAND_CMD_ERASE1: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE1, " + "page_addr: 0x%x.\n", page_addr); + set_addr(mtd, 0, page_addr, 0); + return; + + /* ERASE2 uses the block and page address from ERASE1 */ + case NAND_CMD_ERASE2: + vdbg("fsl_elbc_cmdfunc: NAND_CMD_ERASE2.\n"); + + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_PA << FIR_OP1_SHIFT) | + (FIR_OP_CM1 << FIR_OP2_SHIFT)); + + out_be32(&lbc->fcr, + (NAND_CMD_ERASE1 << FCR_CMD0_SHIFT) | + (NAND_CMD_ERASE2 << FCR_CMD1_SHIFT)); + + out_be32(&lbc->fbcr, 0); + ctrl->read_bytes = 0; + + fsl_elbc_run_command(mtd); + return; + + /* SEQIN sets up the addr buffer and all registers except the length */ + case NAND_CMD_SEQIN: { + u32 fcr; + vdbg("fsl_elbc_cmdfunc: NAND_CMD_SEQIN/PAGE_PROG, " + "page_addr: 0x%x, column: 0x%x.\n", + page_addr, column); + + ctrl->column = column; + ctrl->oob = 0; + + if (priv->page_size) { + fcr = (NAND_CMD_SEQIN << FCR_CMD0_SHIFT) | + (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT); + + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CA << FIR_OP1_SHIFT) | + (FIR_OP_PA << FIR_OP2_SHIFT) | + (FIR_OP_WB << FIR_OP3_SHIFT) | + (FIR_OP_CW1 << FIR_OP4_SHIFT)); + } else { + fcr = (NAND_CMD_PAGEPROG << FCR_CMD1_SHIFT) | + (NAND_CMD_SEQIN << FCR_CMD2_SHIFT); + + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_CM2 << FIR_OP1_SHIFT) | + (FIR_OP_CA << FIR_OP2_SHIFT) | + (FIR_OP_PA << FIR_OP3_SHIFT) | + (FIR_OP_WB << FIR_OP4_SHIFT) | + (FIR_OP_CW1 << FIR_OP5_SHIFT)); + + if (column >= mtd->writesize) { + /* OOB area --> READOOB */ + column -= mtd->writesize; + fcr |= NAND_CMD_READOOB << FCR_CMD0_SHIFT; + ctrl->oob = 1; + } else if (column < 256) { + /* First 256 bytes --> READ0 */ + fcr |= NAND_CMD_READ0 << FCR_CMD0_SHIFT; + } else { + /* Second 256 bytes --> READ1 */ + fcr |= NAND_CMD_READ1 << FCR_CMD0_SHIFT; + } + } + + out_be32(&lbc->fcr, fcr); + set_addr(mtd, column, page_addr, ctrl->oob); + return; + } + + /* PAGEPROG reuses all of the setup from SEQIN and adds the length */ + case NAND_CMD_PAGEPROG: { + int full_page; + vdbg("fsl_elbc_cmdfunc: NAND_CMD_PAGEPROG " + "writing %d bytes.\n", ctrl->index); + + /* if the write did not start at 0 or is not a full page + * then set the exact length, otherwise use a full page + * write so the HW generates the ECC. + */ + if (ctrl->oob || ctrl->column != 0 || + ctrl->index != mtd->writesize + mtd->oobsize) { + out_be32(&lbc->fbcr, ctrl->index); + full_page = 0; + } else { + out_be32(&lbc->fbcr, 0); + full_page = 1; + } + + fsl_elbc_run_command(mtd); + + /* Read back the page in order to fill in the ECC for the + * caller. Is this really needed? + */ + if (full_page && ctrl->oob_poi) { + out_be32(&lbc->fbcr, 3); + set_addr(mtd, 6, page_addr, 1); + + ctrl->read_bytes = mtd->writesize + 9; + + fsl_elbc_do_read(chip, 1); + fsl_elbc_run_command(mtd); + + memcpy_fromio(ctrl->oob_poi + 6, + &ctrl->addr[ctrl->index], 3); + ctrl->index += 3; + } + + ctrl->oob_poi = NULL; + return; + } + + /* CMD_STATUS must read the status byte while CEB is active */ + /* Note - it does not wait for the ready line */ + case NAND_CMD_STATUS: + out_be32(&lbc->fir, + (FIR_OP_CM0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT)); + out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); + out_be32(&lbc->fbcr, 1); + set_addr(mtd, 0, 0, 0); + ctrl->read_bytes = 1; + + fsl_elbc_run_command(mtd); + + /* The chip always seems to report that it is + * write-protected, even when it is not. + */ + out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); + return; + + /* RESET without waiting for the ready line */ + case NAND_CMD_RESET: + dbg("fsl_elbc_cmdfunc: NAND_CMD_RESET.\n"); + out_be32(&lbc->fir, FIR_OP_CM0 << FIR_OP0_SHIFT); + out_be32(&lbc->fcr, NAND_CMD_RESET << FCR_CMD0_SHIFT); + fsl_elbc_run_command(mtd); + return; + + default: + printf("fsl_elbc_cmdfunc: error, unsupported command 0x%x.\n", + command); + } +} + +static void fsl_elbc_select_chip(struct mtd_info *mtd, int chip) +{ + /* The hardware does not seem to support multiple + * chips per bank. + */ +} + +/* + * Write buf to the FCM Controller Data Buffer + */ +static void fsl_elbc_write_buf(struct mtd_info *mtd, const u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + unsigned int bufsize = mtd->writesize + mtd->oobsize; + + if (len < 0) { + printf("write_buf of %d bytes", len); + ctrl->status = 0; + return; + } + + if ((unsigned int)len > bufsize - ctrl->index) { + printf("write_buf beyond end of buffer " + "(%d requested, %u available)\n", + len, bufsize - ctrl->index); + len = bufsize - ctrl->index; + } + + memcpy_toio(&ctrl->addr[ctrl->index], buf, len); + ctrl->index += len; +} + +/* + * read a byte from either the FCM hardware buffer if it has any data left + * otherwise issue a command to read a single byte. + */ +static u8 fsl_elbc_read_byte(struct mtd_info *mtd) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + + /* If there are still bytes in the FCM, then use the next byte. */ + if (ctrl->index < ctrl->read_bytes) + return in_8(&ctrl->addr[ctrl->index++]); + + printf("read_byte beyond end of buffer\n"); + return ERR_BYTE; +} + +/* + * Read from the FCM Controller Data Buffer + */ +static void fsl_elbc_read_buf(struct mtd_info *mtd, u8 *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + int avail; + + if (len < 0) + return; + + avail = min((unsigned int)len, ctrl->read_bytes - ctrl->index); + memcpy_fromio(buf, &ctrl->addr[ctrl->index], avail); + ctrl->index += avail; + + if (len > avail) + printf("read_buf beyond end of buffer " + "(%d requested, %d available)\n", + len, avail); +} + +/* + * Verify buffer against the FCM Controller Data Buffer + */ +static int fsl_elbc_verify_buf(struct mtd_info *mtd, + const u_char *buf, int len) +{ + struct nand_chip *chip = mtd->priv; + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + int i; + + if (len < 0) { + printf("write_buf of %d bytes", len); + return -EINVAL; + } + + if ((unsigned int)len > ctrl->read_bytes - ctrl->index) { + printf("verify_buf beyond end of buffer " + "(%d requested, %u available)\n", + len, ctrl->read_bytes - ctrl->index); + + ctrl->index = ctrl->read_bytes; + return -EINVAL; + } + + for (i = 0; i < len; i++) + if (in_8(&ctrl->addr[ctrl->index + i]) != buf[i]) + break; + + ctrl->index += len; + return i == len && ctrl->status == LTESR_CC ? 0 : -EIO; +} + +/* This function is called after Program and Erase Operations to + * check for success or failure. + */ +static int fsl_elbc_wait(struct mtd_info *mtd, struct nand_chip *chip) +{ + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + lbus83xx_t *lbc = ctrl->regs; + + if (ctrl->status != LTESR_CC) + return NAND_STATUS_FAIL; + + /* Use READ_STATUS command, but wait for the device to be ready */ + ctrl->use_mdr = 0; + out_be32(&lbc->fir, + (FIR_OP_CW0 << FIR_OP0_SHIFT) | + (FIR_OP_RBW << FIR_OP1_SHIFT)); + out_be32(&lbc->fcr, NAND_CMD_STATUS << FCR_CMD0_SHIFT); + out_be32(&lbc->fbcr, 1); + set_addr(mtd, 0, 0, 0); + ctrl->read_bytes = 1; + + fsl_elbc_run_command(mtd); + + if (ctrl->status != LTESR_CC) + return NAND_STATUS_FAIL; + + /* The chip always seems to report that it is + * write-protected, even when it is not. + */ + out_8(ctrl->addr, in_8(ctrl->addr) | NAND_STATUS_WP); + return fsl_elbc_read_byte(mtd); +} + +static int fsl_elbc_read_page(struct mtd_info *mtd, + struct nand_chip *chip, + uint8_t *buf) +{ + fsl_elbc_read_buf(mtd, buf, mtd->writesize); + fsl_elbc_read_buf(mtd, chip->oob_poi, mtd->oobsize); + + if (fsl_elbc_wait(mtd, chip) & NAND_STATUS_FAIL) + mtd->ecc_stats.failed++; + + return 0; +} + +/* ECC will be calculated automatically, and errors will be detected in + * waitfunc. + */ +static void fsl_elbc_write_page(struct mtd_info *mtd, + struct nand_chip *chip, + const uint8_t *buf) +{ + struct fsl_elbc_mtd *priv = chip->priv; + struct fsl_elbc_ctrl *ctrl = priv->ctrl; + + fsl_elbc_write_buf(mtd, buf, mtd->writesize); + fsl_elbc_write_buf(mtd, chip->oob_poi, mtd->oobsize); + + ctrl->oob_poi = chip->oob_poi; +} + +static struct fsl_elbc_ctrl *elbc_ctrl; + +static void fsl_elbc_ctrl_init(void) +{ + immap_t *im = (immap_t *)CFG_IMMR; + + elbc_ctrl = kzalloc(sizeof(*elbc_ctrl), GFP_KERNEL); + if (!elbc_ctrl) + return; + + elbc_ctrl->regs = &im->lbus; + + /* clear event registers */ + out_be32(&elbc_ctrl->regs->ltesr, LTESR_NAND_MASK); + out_be32(&elbc_ctrl->regs->lteatr, 0); + + /* Enable interrupts for any detected events */ + out_be32(&elbc_ctrl->regs->lteir, LTESR_NAND_MASK); + + elbc_ctrl->read_bytes = 0; + elbc_ctrl->index = 0; + elbc_ctrl->addr = NULL; +} + +int board_nand_init(struct nand_chip *nand) +{ + struct fsl_elbc_mtd *priv; + uint32_t br, or; + + if (!elbc_ctrl) { + fsl_elbc_ctrl_init(); + if (!elbc_ctrl) + return -1; + } + + priv = kzalloc(sizeof(*priv), GFP_KERNEL); + if (!priv) + return -ENOMEM; + + priv->ctrl = elbc_ctrl; + priv->vbase = nand->IO_ADDR_R; + + /* Find which chip select it is connected to. It'd be nice + * if we could pass more than one datum to the NAND driver... + */ + for (priv->bank = 0; priv->bank < MAX_BANKS; priv->bank++) { + br = in_be32(&elbc_ctrl->regs->bank[priv->bank].br); + or = in_be32(&elbc_ctrl->regs->bank[priv->bank].or); + + if ((br & BR_V) && (br & BR_MSEL) == BR_MS_FCM && + (br & or & BR_BA) == (phys_addr_t)nand->IO_ADDR_R) + break; + } + + if (priv->bank >= MAX_BANKS) { + printf("fsl_elbc_nand: address did not match any " + "chip selects\n"); + return -ENODEV; + } + + elbc_ctrl->chips[priv->bank] = priv; + + /* fill in nand_chip structure */ + /* set up function call table */ + nand->read_byte = fsl_elbc_read_byte; + nand->write_buf = fsl_elbc_write_buf; + nand->read_buf = fsl_elbc_read_buf; + nand->verify_buf = fsl_elbc_verify_buf; + nand->select_chip = fsl_elbc_select_chip; + nand->cmdfunc = fsl_elbc_cmdfunc; + nand->waitfunc = fsl_elbc_wait; + + /* set up nand options */ + nand->options = NAND_NO_READRDY | NAND_NO_AUTOINCR; + + nand->controller = &elbc_ctrl->controller; + nand->priv = priv; + + nand->ecc.read_page = fsl_elbc_read_page; + nand->ecc.write_page = fsl_elbc_write_page; + + /* If CS Base Register selects full hardware ECC then use it */ + if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + nand->ecc.mode = NAND_ECC_HW; + + nand->ecc.layout = (priv->fmr & FMR_ECCM) ? + &fsl_elbc_oob_sp_eccm1 : + &fsl_elbc_oob_sp_eccm0; + + nand->ecc.size = 512; + nand->ecc.bytes = 3; + nand->ecc.steps = 1; + } else { + /* otherwise fall back to default software ECC */ + nand->ecc.mode = NAND_ECC_SOFT; + } + + priv->fmr = (15 << FMR_CWTO_SHIFT) | (2 << FMR_AL_SHIFT); + + /* adjust Option Register and ECC to match Flash page size */ + if (or & OR_FCM_PGS) { + priv->page_size = 1; + + /* adjust ecc setup if needed */ + if ((br & BR_DECC) == BR_DECC_CHK_GEN) { + nand->ecc.steps = 4; + nand->ecc.layout = (priv->fmr & FMR_ECCM) ? + &fsl_elbc_oob_lp_eccm1 : + &fsl_elbc_oob_lp_eccm0; + } + } + + return 0; +} -- 1.5.3

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[U-Boot-Users] [PATCH 1/2] Don't panic if a controller driver does ecc its own way.
by Scott Wood 18 Apr '08

18 Apr '08

Some hardware, such as the enhanced local bus controller used on some mpc83xx chips, does ecc transparently when reading and writing data, rather than providing a generic calculate/correct mechanism that can be exported to the nand subsystem. The subsystem should not BUG() when calculate, correct, or hwctl are missing, if the methods that call them have been overridden. Signed-off-by: Scott Wood <scottwood(a)freescale.com> --- This patch applies to the mtd-2.6.22.1 branch of the nand tree. drivers/mtd/nand/nand_base.c | 8 ++++++-- 1 files changed, 6 insertions(+), 2 deletions(-) diff --git a/drivers/mtd/nand/nand_base.c b/drivers/mtd/nand/nand_base.c index 576b0db..319696d 100644 --- a/drivers/mtd/nand/nand_base.c +++ b/drivers/mtd/nand/nand_base.c @@ -2593,8 +2593,12 @@ int nand_scan_tail(struct mtd_info *mtd) chip->ecc.write_oob = nand_write_oob_std; case NAND_ECC_HW_SYNDROME: - if (!chip->ecc.calculate || !chip->ecc.correct || - !chip->ecc.hwctl) { + if ((!chip->ecc.calculate || !chip->ecc.correct || + !chip->ecc.hwctl) && + (!chip->ecc.read_page || + chip->ecc.read_page == nand_read_page_hwecc || + !chip->ecc.write_page || + chip->ecc.write_page == nand_write_page_hwecc)) { printk(KERN_WARNING "No ECC functions supplied, " "Hardware ECC not possible\n"); BUG(); -- 1.5.3

3 6

[U-Boot-Users] [PATCH] Move init_sequence table into code.
by Joakim Tjernlund 18 Apr '08

18 Apr '08

Global variables are not ideal before relocation to RAM. --- I hope this still applies. lib_ppc/board.c | 144 +++++++++++++++++++++++++----------------------------- 1 files changed, 67 insertions(+), 77 deletions(-) diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 8a18350..c64bbd5 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -288,124 +288,114 @@ static int init_func_watchdog_reset (void) ************************************************************************ */ -init_fnc_t *init_sequence[] = { +/************************************************************************ + * + * This is the first part of the initialization sequence that is + * implemented in C, but still running from ROM. + * + * The main purpose is to provide a (serial) console interface as + * soon as possible (so we can see any error messages), and to + * initialize the RAM so that we can relocate the monitor code to + * RAM. + * + * Be aware of the restrictions: global data is read-only, BSS is not + * initialized, and stack space is limited to a few kB. + * + ************************************************************************ + */ + +void board_init_f (ulong bootflag) +{ + bd_t *bd; + ulong len, addr, addr_sp; + ulong *s; + gd_t *id; + init_fnc_t **init_fnc_ptr; +#ifdef CONFIG_PRAM + int i; + ulong reg; + uchar tmp[64]; /* long enough for environment variables */ +#endif + + /* Pointer is writable since we allocated a register for it */ + gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); + /* compiler optimization barrier needed for GCC >= 3.4 */ + __asm__ __volatile__("": : :"memory"); + +#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) + /* Clear initial global data */ + memset ((void *) gd, 0, sizeof (gd_t)); +#endif #if defined(CONFIG_BOARD_EARLY_INIT_F) - board_early_init_f, + board_early_init_f(); #endif #if !defined(CONFIG_8xx_CPUCLK_DEFAULT) - get_clocks, /* get CPU and bus clocks (etc.) */ + get_clocks(); /* get CPU and bus clocks (etc.) */ #if defined(CONFIG_TQM8xxL) && !defined(CONFIG_TQM866M) \ && !defined(CONFIG_TQM885D) - adjust_sdram_tbs_8xx, + adjust_sdram_tbs_8xx(); #endif - init_timebase, + init_timebase(); #endif #ifdef CFG_ALLOC_DPRAM #if !defined(CONFIG_CPM2) - dpram_init, + dpram_init(); #endif #endif #if defined(CONFIG_BOARD_POSTCLK_INIT) - board_postclk_init, + board_postclk_init(); #endif - env_init, + env_init(); #if defined(CONFIG_8xx_CPUCLK_DEFAULT) - get_clocks_866, /* get CPU and bus clocks according to the environment variable */ - sdram_adjust_866, /* adjust sdram refresh rate according to the new clock */ - init_timebase, -#endif - init_baudrate, - serial_init, - console_init_f, - display_options, + get_clocks_866(); /* get CPU and bus clocks according to the environment variable */ + sdram_adjust_866(); /* adjust sdram refresh rate according to the new clock */ + init_timebase(); +#endif + init_baudrate(); + serial_init(); + console_init_f(); + display_options(); #if defined(CONFIG_8260) - prt_8260_rsr, - prt_8260_clks, + prt_8260_rsr(); + prt_8260_clks(); #endif /* CONFIG_8260 */ #if defined(CONFIG_MPC83XX) - prt_83xx_rsr, + prt_83xx_rsr(); #endif - checkcpu, + checkcpu(); #if defined(CONFIG_MPC5xxx) - prt_mpc5xxx_clks, + prt_mpc5xxx_clks(); #endif /* CONFIG_MPC5xxx */ #if defined(CONFIG_MPC8220) - prt_mpc8220_clks, + prt_mpc8220_clks(); #endif - checkboard, + checkboard(); INIT_FUNC_WATCHDOG_INIT #if defined(CONFIG_MISC_INIT_F) - misc_init_f, + misc_init_f(); #endif INIT_FUNC_WATCHDOG_RESET #if defined(CONFIG_HARD_I2C) || defined(CONFIG_SOFT_I2C) - init_func_i2c, + init_func_i2c(); #endif #if defined(CONFIG_HARD_SPI) - init_func_spi, + init_func_spi(); #endif #if defined(CONFIG_DTT) /* Digital Thermometers and Thermostats */ - dtt_init, + dtt_init(); #endif #ifdef CONFIG_POST - post_init_f, + post_init_f(); #endif INIT_FUNC_WATCHDOG_RESET - init_func_ram, + init_func_ram(); #if defined(CFG_DRAM_TEST) - testdram, + testdram(); #endif /* CFG_DRAM_TEST */ INIT_FUNC_WATCHDOG_RESET - NULL, /* Terminate this list */ -}; - -/************************************************************************ - * - * This is the first part of the initialization sequence that is - * implemented in C, but still running from ROM. - * - * The main purpose is to provide a (serial) console interface as - * soon as possible (so we can see any error messages), and to - * initialize the RAM so that we can relocate the monitor code to - * RAM. - * - * Be aware of the restrictions: global data is read-only, BSS is not - * initialized, and stack space is limited to a few kB. - * - ************************************************************************ - */ - -void board_init_f (ulong bootflag) -{ - bd_t *bd; - ulong len, addr, addr_sp; - ulong *s; - gd_t *id; - init_fnc_t **init_fnc_ptr; -#ifdef CONFIG_PRAM - int i; - ulong reg; - uchar tmp[64]; /* long enough for environment variables */ -#endif - - /* Pointer is writable since we allocated a register for it */ - gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); - /* compiler optimization barrier needed for GCC >= 3.4 */ - __asm__ __volatile__("": : :"memory"); - -#if !defined(CONFIG_CPM2) && !defined(CONFIG_MPC83XX) - /* Clear initial global data */ - memset ((void *) gd, 0, sizeof (gd_t)); -#endif - - for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { - if ((*init_fnc_ptr) () != 0) { - hang (); - } - } /* * Now that we have DRAM mapped and working, we can -- 1.5.4.3

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[U-Boot-Users] [PATCH 1/2] Additional PCI IDs for IDE and network controllers
by Guennadi Liakhovetski 18 Apr '08

18 Apr '08

These PCI IDs are required by the Linkstation platforms. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- Sorry for a last minute submission... Woould be good to get this and the following patch in for 1.3.3. Haven't found a PCI custodian, so, CC-ing Wolfgang. include/pci_ids.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/pci_ids.h b/include/pci_ids.h index 3b10452..638d3d8 100644 --- a/include/pci_ids.h +++ b/include/pci_ids.h @@ -1472,6 +1472,8 @@ #define PCI_DEVICE_ID_ITE_IT8172G 0x8172 #define PCI_DEVICE_ID_ITE_IT8172G_AUDIO 0x0801 #define PCI_DEVICE_ID_ITE_IT8181 0x8181 +#define PCI_DEVICE_ID_ITE_8211 0x8211 +#define PCI_DEVICE_ID_ITE_8212 0x8212 #define PCI_DEVICE_ID_ITE_8872 0x8872 #define PCI_DEVICE_ID_ITE_IT8330G_0 0xe886 @@ -2073,3 +2075,5 @@ #define PCI_DEVICE_ID_MPC8641D 0x7011 #define PCI_DEVICE_ID_MPC8610 0x7018 +#define PCI_VENDOR_ID_ADMTEK 0x1317 +#define PCI_DEVICE_ID_ADMTEK_AN983B 0x985 -- 1.5.4

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[U-Boot-Users] [GIT PULL] Please pull u-boot-arm
by Peter Pearse 17 Apr '08

17 Apr '08

Wolfgang Please pull from git://www.denx.de/git/u-boot-arm.git master. These are the patches: [PATCH v2] ARM: Davinci: Fix DM644x timer overflow handling and cleanup [PATCH] DM644x: This patch removes all boardspecific code from the arch part for DM644x (DaVinci) boards [PATCH] DM644x: (2nd try) This adds support fortheProdrivePMDRA board, based on a DM6441 [PATCH 0/7] Respin of Sascha Hauer's i.MX31support plus MX31ADS AFAIK there are no outstanding patches for git://www.denx.de/git/u-boot-arm.git for this merge window. I have dropped [PATCH] ixp: Support for NSLU2 [PATCH] Altera Stratix II support as per previous mails Regards Peter --- The following changes since commit 74d1e66d22dac91388bc538b2fe19f735edc5b82: Bartlomiej Sieka (1): Fix host tool build breakage, take two are available in the git repository at: git://www.denx.de/git/u-boot-arm.git master Dirk Behme (1): - Remove *_masked() functions as noted by Wolfgang Guennadi Liakhovetski (1): Support for the MX31ADS evaluation board from Freescale Peter Pearse (2): Add pmdra into MAKEALL Bracket READ_TIMER macro in cpu/arm1136/omap24xx/interrupts.c Pieter Voorthuijsen (2): Removes all board specific code from the arch. part for DM644x (DaVinci) boards Adds support for the Prodrive PMDRA board, based on a DM6441 Sascha Hauer (6): Separate omap24xx specific code from arm1136 core support for Freescale mx31 add an i2c driver for mx31 add SMSC LAN9x1x Network driver mx31 litekit support Phytec Phycore-i.MX31 support MAKEALL | 4 + Makefile | 16 +- board/imx31_litekit/Makefile | 50 ++ board/imx31_litekit/config.mk | 1 + board/imx31_litekit/imx31_litekit.c | 65 ++ board/imx31_litekit/lowlevel_init.S | 103 +++ board/imx31_litekit/u-boot.lds | 59 ++ board/imx31_phycore/Makefile | 49 ++ board/imx31_phycore/config.mk | 1 + board/imx31_phycore/imx31_phycore.c | 73 +++ board/imx31_phycore/lowlevel_init.S | 105 +++ board/imx31_phycore/u-boot.lds | 59 ++ board/mx31ads/Makefile | 52 ++ board/mx31ads/config.mk | 1 + board/mx31ads/lowlevel_init.S | 288 +++++++++ board/mx31ads/mx31ads.c | 94 +++ board/mx31ads/u-boot.lds | 59 ++ board/prodrive/pmdra/Makefile | 50 ++ board/prodrive/pmdra/board_init.S | 29 + board/prodrive/pmdra/config.mk | 39 ++ board/prodrive/pmdra/pmdra.c | 189 ++++++ board/prodrive/pmdra/u-boot.lds | 52 ++ cpu/arm1136/Makefile | 2 +- cpu/arm1136/cpu.c | 11 +- cpu/arm1136/mx31/Makefile | 44 ++ cpu/arm1136/mx31/generic.c | 99 +++ cpu/arm1136/mx31/interrupts.c | 113 ++++ cpu/arm1136/mx31/serial.c | 230 +++++++ cpu/arm1136/omap24xx/Makefile | 46 ++ cpu/arm1136/{ => omap24xx}/interrupts.c | 109 ++-- cpu/arm1136/omap24xx/start.S | 42 ++ cpu/arm1136/start.S | 21 - cpu/arm926ejs/davinci/lowlevel_init.S | 79 ++- cpu/arm926ejs/davinci/nand.c | 41 +- cpu/arm926ejs/davinci/timer.c | 69 +-- drivers/i2c/Makefile | 1 + drivers/i2c/mxc_i2c.c | 207 ++++++ drivers/net/Makefile | 1 + drivers/net/smc911x.c | 680 ++++++++++++++++++++ include/asm-arm/arch-davinci/hardware.h | 2 + include/asm-arm/arch-mx31/mx31-regs.h | 151 +++++ include/asm-arm/arch-mx31/mx31.h | 32 + .../asm-arm/{arch-arm1136 => arch-omap24xx}/bits.h | 0 .../{arch-arm1136 => arch-omap24xx}/clocks.h | 0 .../asm-arm/{arch-arm1136 => arch-omap24xx}/i2c.h | 0 .../asm-arm/{arch-arm1136 => arch-omap24xx}/mem.h | 0 .../asm-arm/{arch-arm1136 => arch-omap24xx}/mux.h | 0 .../{arch-arm1136 => arch-omap24xx}/omap2420.h | 0 .../{arch-arm1136 => arch-omap24xx}/sizes.h | 0 .../{arch-arm1136 => arch-omap24xx}/sys_info.h | 0 .../{arch-arm1136 => arch-omap24xx}/sys_proto.h | 0 include/configs/davinci_dvevm.h | 44 +- include/configs/davinci_schmoogie.h | 19 +- include/configs/davinci_sonata.h | 18 + include/configs/imx31_litekit.h | 167 +++++ include/configs/imx31_phycore.h | 190 ++++++ include/configs/mx31ads.h | 170 +++++ include/configs/pmdra.h | 186 ++++++ 58 files changed, 4013 insertions(+), 199 deletions(-) create mode 100644 board/imx31_litekit/Makefile create mode 100644 board/imx31_litekit/config.mk create mode 100644 board/imx31_litekit/imx31_litekit.c create mode 100644 board/imx31_litekit/lowlevel_init.S create mode 100644 board/imx31_litekit/u-boot.lds create mode 100644 board/imx31_phycore/Makefile create mode 100644 board/imx31_phycore/config.mk create mode 100644 board/imx31_phycore/imx31_phycore.c create mode 100644 board/imx31_phycore/lowlevel_init.S create mode 100644 board/imx31_phycore/u-boot.lds create mode 100644 board/mx31ads/Makefile create mode 100644 board/mx31ads/config.mk create mode 100644 board/mx31ads/lowlevel_init.S create mode 100644 board/mx31ads/mx31ads.c create mode 100644 board/mx31ads/u-boot.lds create mode 100644 board/prodrive/pmdra/Makefile create mode 100644 board/prodrive/pmdra/board_init.S create mode 100644 board/prodrive/pmdra/config.mk create mode 100644 board/prodrive/pmdra/pmdra.c create mode 100644 board/prodrive/pmdra/u-boot.lds create mode 100644 cpu/arm1136/mx31/Makefile create mode 100644 cpu/arm1136/mx31/generic.c create mode 100644 cpu/arm1136/mx31/interrupts.c create mode 100644 cpu/arm1136/mx31/serial.c create mode 100644 cpu/arm1136/omap24xx/Makefile rename cpu/arm1136/{ => omap24xx}/interrupts.c (50%) mode change 100644 => 100755 create mode 100644 cpu/arm1136/omap24xx/start.S create mode 100644 drivers/i2c/mxc_i2c.c create mode 100644 drivers/net/smc911x.c create mode 100644 include/asm-arm/arch-mx31/mx31-regs.h create mode 100644 include/asm-arm/arch-mx31/mx31.h rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/bits.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/clocks.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/i2c.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/mem.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/mux.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/omap2420.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/sizes.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/sys_info.h (100%) rename include/asm-arm/{arch-arm1136 => arch-omap24xx}/sys_proto.h (100%) create mode 100644 include/configs/imx31_litekit.h create mode 100644 include/configs/imx31_phycore.h create mode 100644 include/configs/mx31ads.h create mode 100644 include/configs/pmdra.h

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[U-Boot-Users] [PATCH v2 3/7] add an i2c driver for mx31
by Guennadi Liakhovetski 15 Apr '08

15 Apr '08

From: Sascha Hauer <s.hauer(a)pengutronix.de> This patch adds an i2c driver for Freescale i.MX processors Signed-off-by: Sascha Hauer <s.hauer(a)pengutronix.de> Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- No changes wrt v1 drivers/i2c/Makefile | 1 + drivers/i2c/mxc_i2c.c | 202 +++++++++++++++++++++++++++++++++++++++++++++++++ 2 files changed, 203 insertions(+), 0 deletions(-) create mode 100644 drivers/i2c/mxc_i2c.c diff --git a/drivers/i2c/Makefile b/drivers/i2c/Makefile index 29d6c03..071ef00 100644 --- a/drivers/i2c/Makefile +++ b/drivers/i2c/Makefile @@ -29,6 +29,7 @@ COBJS-y += fsl_i2c.o COBJS-y += omap1510_i2c.o COBJS-y += omap24xx_i2c.o COBJS-y += tsi108_i2c.o +COBJS-y += mxc_i2c.o COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c) diff --git a/drivers/i2c/mxc_i2c.c b/drivers/i2c/mxc_i2c.c new file mode 100644 index 0000000..a218329 --- /dev/null +++ b/drivers/i2c/mxc_i2c.c @@ -0,0 +1,202 @@ +/* + * i2c driver for Freescale mx31 + * + * (c) 2007 Pengutronix, Sascha Hauer <s.hauer(a)pengutronix.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if defined(CONFIG_HARD_I2C) && defined (CONFIG_I2C_MXC) + +#include <asm/arch/mx31.h> +#include <asm/arch/mx31-regs.h> + +#define IADR 0x00 +#define IFDR 0x04 +#define I2CR 0x08 +#define I2SR 0x0c +#define I2DR 0x10 + +#define I2CR_IEN (1 << 7) +#define I2CR_IIEN (1 << 6) +#define I2CR_MSTA (1 << 5) +#define I2CR_MTX (1 << 4) +#define I2CR_TX_NO_AK (1 << 3) +#define I2CR_RSTA (1 << 2) + +#define I2SR_ICF (1 << 7) +#define I2SR_IBB (1 << 5) +#define I2SR_IIF (1 << 1) +#define I2SR_RX_NO_AK (1 << 0) + +#ifdef CFG_I2C_MX31_PORT1 +#define I2C_BASE 0x43f80000 +#elif defined (CFG_I2C_MX31_PORT2) +#define I2C_BASE 0x43f98000 +#elif defined (CFG_I2C_MX31_PORT3) +#define I2C_BASE 0x43f84000 +#else +#error "define CFG_I2C_MX31_PORTx to use the mx31 I2C driver" +#endif + +#ifdef DEBUG +#define DPRINTF(args...) printf(args) +#else +#define DPRINTF(args...) +#endif + +static u16 div[] = { 30, 32, 36, 42, 48, 52, 60, 72, 80, 88, 104, 128, 144, + 160, 192, 240, 288, 320, 384, 480, 576, 640, 768, 960, + 1152, 1280, 1536, 1920, 2304, 2560, 3072, 3840}; + +void i2c_init(int speed, int unused) +{ + int freq = mx31_get_ipg_clk(); + int i; + + for (i = 0; i < 0x1f; i++) + if (freq / div[i] <= speed) + break; + + DPRINTF("%s: speed: %d\n",__FUNCTION__, speed); + + __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ + __REG16(I2C_BASE + IFDR) = i; + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + __REG16(I2C_BASE + I2SR) = 0; +} + +static int wait_busy(void) +{ + int timeout = 10000; + + while (!(__REG16(I2C_BASE + I2SR) & I2SR_IIF) && --timeout) + udelay(1); + __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + + return timeout; +} + +static int tx_byte(u8 byte) +{ + __REG16(I2C_BASE + I2DR) = byte; + + if (!wait_busy() || __REG16(I2C_BASE + I2SR) & I2SR_RX_NO_AK) + return -1; + return 0; +} + +static int rx_byte(void) +{ + if (!wait_busy()) + return -1; + + return __REG16(I2C_BASE + I2DR); +} + +int i2c_probe(uchar chip) +{ + int ret; + + __REG16(I2C_BASE + I2CR) = 0; /* Reset module */ + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + ret = tx_byte(chip << 1); + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MTX; + + return ret; +} + +static int i2c_addr(uchar chip, uint addr, int alen) +{ + __REG16(I2C_BASE + I2SR) = 0; /* clear interrupt */ + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX; + + if (tx_byte(chip << 1)) + return -1; + + while (alen--) + if (tx_byte((addr >> (alen * 8)) & 0xff)) + return -1; + return 0; +} + +int i2c_read(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int timeout = 10000; + int ret; + + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + + if (i2c_addr(chip, addr, alen)) { + printf("i2c_addr failed\n"); + return -1; + } + + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_MTX | I2CR_RSTA; + + if (tx_byte(chip << 1 | 1)) + return -1; + + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | ((len == 1) ? I2CR_TX_NO_AK : 0); + + ret = __REG16(I2C_BASE + I2DR); + + while (len--) { + if ((ret = rx_byte()) < 0) + return -1; + *buf++ = ret; + if (len <= 1) + __REG16(I2C_BASE + I2CR) = I2CR_IEN | I2CR_MSTA | I2CR_TX_NO_AK; + } + + wait_busy(); + + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + udelay(1); + + return 0; +} + +int i2c_write(uchar chip, uint addr, int alen, uchar *buf, int len) +{ + int timeout = 10000; + DPRINTF("%s chip: 0x%02x addr: 0x%04x alen: %d len: %d\n",__FUNCTION__, chip, addr, alen, len); + + if (i2c_addr(chip, addr, alen)) + return -1; + + while (len--) + if (tx_byte(*buf++)) + return -1; + + __REG16(I2C_BASE + I2CR) = I2CR_IEN; + + while (__REG16(I2C_BASE + I2SR) & I2SR_IBB && --timeout) + udelay(1); + + return 0; +} + +#endif /* CONFIG_HARD_I2C */ -- 1.5.4

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[U-Boot-Users] [PATCH] Use `ln -sf` rather than `rm -f && ln -s`
by Mike Frysinger 14 Apr '08

14 Apr '08

Signed-off-by: Mike Frysinger <vapier(a)gentoo.org> --- tools/Makefile | 9 +++------ 1 files changed, 3 insertions(+), 6 deletions(-) diff --git a/tools/Makefile b/tools/Makefile index af0de47..22d9dae 100644 --- a/tools/Makefile +++ b/tools/Makefile @@ -203,19 +203,16 @@ else endif $(obj)environment.c: - @rm -f $(obj)environment.c - ln -s $(src)../common/environment.c $(obj)environment.c + ln -s -f $(src)../common/environment.c $(obj)environment.c $(obj)environment.o: $(obj)environment.c $(CC) -g $(HOST_ENVIRO_CFLAGS) $(CPPFLAGS) -c -o $@ $< $(obj)crc32.c: - @rm -f $(obj)crc32.c - ln -s $(src)../lib_generic/crc32.c $(obj)crc32.c + ln -s -f $(src)../lib_generic/crc32.c $(obj)crc32.c $(obj)sha1.c: - @rm -f $(obj)sha1.c - ln -s $(src)../lib_generic/sha1.c $(obj)sha1.c + ln -s -f $(src)../lib_generic/sha1.c $(obj)sha1.c $(LOGO_H): $(obj)bmp_logo $(LOGO_BMP) $(obj)./bmp_logo $(LOGO_BMP) >$@ -- 1.5.3.8

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