February 2008 - U-Boot

[U-Boot-Users] Your Friend and Lover
by emartino＠dhs.gov 05 Feb '08

05 Feb '08

You're my Dream http://69.148.78.93/

1 0

[U-Boot-Users] [PATCH] MPC85xx KGDB support
by Chen Gong 05 Feb '08

05 Feb '08

--- cpu/mpc85xx/Makefile | 4 +- drivers/serial.c | 28 +++++++++++++++++++ include/configs/MPC8548CDS.h | 3 +- lib_ppc/kgdb.c | 62 +++++++++++++++++++++++++++++++++--------- 4 files changed, 81 insertions(+), 16 deletions(-) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 32091fa..f5cb148 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o resetvec.o +START = start.o resetvec.o kgdb.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o @@ -39,7 +39,7 @@ START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o ######################################################################### diff --git a/drivers/serial.c b/drivers/serial.c index 76425d8..42585d7 100644 --- a/drivers/serial.c +++ b/drivers/serial.c @@ -307,6 +307,34 @@ serial_setbrg(void) } #endif +#if defined(CONFIG_CMD_KGDB) +void kgdb_serial_init (void) +{ + /* here presume you have been initialzed appropriate COM# */ + _serial_puts("[on serial] ",CONFIG_KGDB_SER_INDEX); +} + +void putDebugChar (int c) +{ + _serial_putc(c, CONFIG_KGDB_SER_INDEX); +} + +void putDebugStr (const char *str) +{ + _serial_puts(str, CONFIG_KGDB_SER_INDEX); +} + +int getDebugChar (void) +{ + return _serial_getc(CONFIG_KGDB_SER_INDEX); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif + #if defined(CONFIG_SERIAL_MULTI) DECLARE_ESERIAL_FUNCTIONS(1); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 6083715..396feeb 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -482,6 +482,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_KGDB #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -529,7 +530,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_WARM 0x02 /* Software reboot */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/lib_ppc/kgdb.c b/lib_ppc/kgdb.c index 78c2f0c..7acdebc 100644 --- a/lib_ppc/kgdb.c +++ b/lib_ppc/kgdb.c @@ -60,20 +60,46 @@ static struct hard_trap_info unsigned int tt; /* Trap type code for powerpc */ unsigned char signo; /* Signal that we map this trap into */ } hard_trap_info[] = { - { 0x200, SIGSEGV }, /* machine check */ - { 0x300, SIGSEGV }, /* address error (store) */ - { 0x400, SIGBUS }, /* instruction bus error */ - { 0x500, SIGINT }, /* interrupt */ - { 0x600, SIGBUS }, /* alingment */ - { 0x700, SIGTRAP }, /* breakpoint trap */ - { 0x800, SIGFPE }, /* fpu unavail */ - { 0x900, SIGALRM }, /* decrementer */ - { 0xa00, SIGILL }, /* reserved */ - { 0xb00, SIGILL }, /* reserved */ - { 0xc00, SIGCHLD }, /* syscall */ - { 0xd00, SIGTRAP }, /* single-step/watch */ - { 0xe00, SIGFPE }, /* fp assist */ +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + { 0x100, SIGINT }, /* critical input interrupt */ + { 0x200, SIGSEGV }, /* machine check */ + { 0x300, SIGSEGV }, /* data storage */ + { 0x400, SIGBUS }, /* instruction storage */ + { 0x500, SIGINT }, /* interrupt */ + { 0x600, SIGBUS }, /* alignment */ + { 0x700, SIGILL }, /* program */ + { 0x800, SIGILL }, /* reserved */ + { 0x900, SIGILL }, /* reserved */ + { 0xa00, SIGILL }, /* reserved */ + { 0xb00, SIGILL }, /* reserved */ + { 0xc00, SIGCHLD }, /* syscall */ + { 0xd00, SIGILL }, /* reserved */ + { 0xe00, SIGILL }, /* reserved */ + { 0xf00, SIGILL }, /* reserved */ + /* + * 0x1000 PIT + * 0x1010 FIT + * 0x1020 watchdog + * 0x1100 data TLB miss + * 0x1200 instruction TLB miss + */ + { 0x2002, SIGTRAP}, /* debug */ +#else + { 0x200, SIGSEGV }, /* machine check */ + { 0x300, SIGSEGV }, /* address error (store) */ + { 0x400, SIGBUS }, /* instruction bus error */ + { 0x500, SIGINT }, /* interrupt */ + { 0x600, SIGBUS }, /* alingment */ + { 0x700, SIGTRAP }, /* breakpoint trap */ + { 0x800, SIGFPE }, /* fpu unavail */ + { 0x900, SIGALRM }, /* decrementer */ + { 0xa00, SIGILL }, /* reserved */ + { 0xb00, SIGILL }, /* reserved */ + { 0xc00, SIGCHLD }, /* syscall */ + { 0xd00, SIGTRAP }, /* single-step/watch */ + { 0xe00, SIGFPE }, /* fp assist */ { 0, 0} /* Must be last */ +#endif }; static int @@ -100,7 +126,12 @@ kgdb_enter(struct pt_regs *regs, kgdb_data *kdp) /* Skip over breakpoint trap insn */ regs->nip += 4; } +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR_IC); + regs->msr &= ~MSR_DE; +#else regs->msr &= ~MSR_SE; +#endif /* reply to host that an exception has occurred */ kdp->sigval = computeSignal(regs->trap); @@ -130,7 +161,12 @@ kgdb_exit(struct pt_regs *regs, kgdb_data *kdp) break; case KGDBEXIT_SINGLE: +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR_IC); + regs->msr |= MSR_DE; +#else regs->msr |= MSR_SE; +#endif #if 0 set_msr(msr | MSR_SE); #endif -- 1.5.2

4 3

[U-Boot-Users] Increase your pen1s size naturally with enlargement pills made from 100% herbal ingredients
by kyle Jermaine 05 Feb '08

05 Feb '08

Want to be well hung, with a thick, muscular tool? Now you can

1 0

[U-Boot-Users] [PATCH] ColdFire: Fix missing code flash size for M5485EVB
by Tsi-Chung Liew 05 Feb '08

05 Feb '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: James Mahan <kmahan(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 0f6cc59..30fda62 100644 --- a/Makefile +++ b/Makefile @@ -1912,7 +1912,7 @@ M5485HFE_config : unconfig M5485EFE_config) BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \ M5485FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \ M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5485HFE_config) BOOT=2;CODE=;VID=1;USB=0;RAM=64;RAM1=0;; \ + M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \ esac; \ >include/config.h ; \ echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \ -- 1.5.2

3 3

Re: [U-Boot-Users] NAND driver question
by Craig Millen 05 Feb '08

05 Feb '08

>I may have noted this before, but I suggest you move the CFG_NAND_ADDR to 0x90000000 as done on Bamboo, since 0xd0000000 is reserved for PCI memory on 440EP. I have done this and it didn't make any difference, same exception >How is SDR0_CUST0 configured. Please read is in a running system and send me the value. And how is the GPIO/multiplexing configured? a0200004 >BTW: It would be much easier to help you here, if you board port was available in the official U-Boot repository. I suggest you submit this support soon. I would love to, but I am not sure how to add all of our code to the repository because it is rather heavily customized and there are a lot of files that would conflict with what is in the u-boot git repository. >> We have noticed however that when reading from the nand in u-boot, >> that the /CE line is never deasserted between page reads, but in the >> linux kernel user mode, it is. We have yet to figure out why this is. >That's possible. Could be that the U-Boot NAND driver doesn't deassert the CE line. This turned out to be the culprit. The NAND data sheet stipulates that the CE line "should" deassert after a sequential read for 100ns. I ported the code from the NDFC drive in linux and added it to ndfc.c and we no longer see any missed bytes even on huge files (80Mb). I would highly suggest merging it into the u-boot ndfc driver. Perhaps the NAND chips that you are testing on aren't susceptible to this, but there are some that are. static void ndfc_select_chip(struct mtd_info *mtdinfo, int chip) { uint32_t ccr; struct nand_chip *this = mtdinfo->priv; ulong base = (ulong) this->IO_ADDR_W & 0xfffffffc; int cs = (ulong)this->IO_ADDR_W & 0x00000003; ccr = in_be32((u32 *)(base + NDFC_CCR)); if (chip >= 0) { ccr &= ~NDFC_CCR_BS_MASK; ccr |= NDFC_CCR_BS(chip + cs); } else ccr |= NDFC_CCR_RESET_CE; out_be32((u32 *)(base + NDFC_CCR), ccr); } Then in board_nand_init add the "select_chip" pointer to point to the ndfc_select_chip function int board_nand_init(struct nand_chip *nand) { int cs = (ulong)nand->IO_ADDR_W & 0x00000003; ulong base = (ulong)nand->IO_ADDR_W & 0xfffffffc; nand->hwcontrol = ndfc_hwcontrol; nand->read_byte = ndfc_read_byte; nand->read_buf = ndfc_read_buf; nand->write_byte = ndfc_write_byte; nand->dev_ready = ndfc_dev_ready; nand->select_chip = ndfc_select_chip; ... ... All of the code to actually use the "selec_chip" is already there in nand_base.c >What frequency is your EBC clocked? Did you try lower access speeds, something >like: We use a 66MHz EBC clock > out_be32((u32 *)(base + NDFC_BCFG0 + (cs << 2)), 0x80007777); Yes, I did try this and it gave me a machine check exception as well. This doesn't change the EBC frequency though, it is just "supposed" to change the number of EBC ticks that it waits for. Best regards, Stefan ===================================================================== DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: +49-8142-66989-0 Fax: +49-8142-66989-80 Email: office(a)denx.de =====================================================================

2 1

[U-Boot-Users] Dream of You
by west＠djsunshine.com 05 Feb '08

05 Feb '08

Your Friend and Lover http://213.60.136.120/

1 0

[U-Boot-Users] [PATCH 1/3] ppc4xx: PPC405GPr add missing EIRR register
by Niklaus Giger 05 Feb '08

05 Feb '08

Signed-off-by: Niklaus Giger <niklaus.giger(a)netstal.com> --- include/ppc405.h | 4 ++++ 1 files changed, 4 insertions(+), 0 deletions(-) diff --git a/include/ppc405.h b/include/ppc405.h index b5ad38f..fbfb681 100644 --- a/include/ppc405.h +++ b/include/ppc405.h @@ -784,6 +784,10 @@ #define reset (CNTRL_DCR_BASE+0x3) /* reset register */ #define strap (CNTRL_DCR_BASE+0x4) /* strap register */ +#ifdef CONFIG_405GPr +#define eirr (CNTRL_DCR_BASE+0x6) /* external interrupt routing register */ +#endif + #define ecr (0xaa) /* edge conditioner register (405gpr) */ /* Bit definitions */ -- 1.5.2.5

3 8

[U-Boot-Users] mpc83xx_spi.c breaks non-ppc ports
by Mike Frysinger 05 Feb '08

05 Feb '08

Commit 04a9e1180ac76a7bacc15a6fcd95ad839d65bddb introduced the mpc83xx_spi.c driver which gets compiled for everyone, but this obviously only builds for the ppc port. I haven't been following the latest build updates, but the attached patch is one way to fix things. Signed-off-by: Mike Frysinger <vapier(a)gentoo.org --- diff --git a/drivers/spi/Makefile b/drivers/spi/Makefile index 0b7a2df..1fdfb38 100644 --- a/drivers/spi/Makefile +++ b/drivers/spi/Makefile @@ -25,7 +25,9 @@ include $(TOPDIR)/config.mk LIB := $(obj)libspi.a -COBJS-y += mpc8xxx_spi.o +COBJS-ppc += mpc8xxx_spi.o + +COBJS-y += $(COBJS-$(ARCH)) COBJS := $(COBJS-y) SRCS := $(COBJS:.o=.c)

2 2

[U-Boot-Users] [PATCH] 85xx: Added support for multicore boot mechanism
by Kumar Gala 05 Feb '08

05 Feb '08

Added the cpu command that provides a generic mechanism to get status, reset, and release secondary cores in multicore processors. Added support for using the ePAPR defined spin-table mechanism on 85xx. Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- as usually, this is in the mpc85xx branch of my git tree. common/Makefile | 1 + common/cmd_mp.c | 96 +++++++++++++++++++++ cpu/mpc85xx/Makefile | 3 + cpu/mpc85xx/cpu_init.c | 4 + cpu/mpc85xx/fdt.c | 53 ++++++++++++ cpu/mpc85xx/mp.c | 190 ++++++++++++++++++++++++++++++++++++++++++ cpu/mpc85xx/mp.h | 8 ++ cpu/mpc85xx/release.S | 148 ++++++++++++++++++++++++++++++++ include/asm-ppc/immap_85xx.h | 4 + include/common.h | 7 ++ 10 files changed, 514 insertions(+), 0 deletions(-) create mode 100644 common/cmd_mp.c create mode 100644 cpu/mpc85xx/mp.c create mode 100644 cpu/mpc85xx/mp.h create mode 100644 cpu/mpc85xx/release.S diff --git a/common/Makefile b/common/Makefile index fbfa536..346d403 100644 --- a/common/Makefile +++ b/common/Makefile @@ -132,6 +132,7 @@ COBJS-y += crc16.o COBJS-y += xyzModem.o COBJS-y += cmd_mac.o COBJS-$(CONFIG_CMD_MFSL) += cmd_mfsl.o +COBJS-$(CONFIG_MP) += cmd_mp.o COBJS := $(COBJS-y) SRCS := $(AOBJS:.o=.S) $(COBJS:.o=.c) diff --git a/common/cmd_mp.c b/common/cmd_mp.c new file mode 100644 index 0000000..d96e6a3 --- /dev/null +++ b/common/cmd_mp.c @@ -0,0 +1,96 @@ +/* + * Copyright 2008 Freescale Semiconductor, Inc. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> + +int +cpu_cmd(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + unsigned long cpuid, val = 0; + + if (argc < 3) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + cpuid = simple_strtoul(argv[1], NULL, 10); + if (cpuid >= CONFIG_NR_CPUS) { + printf ("Core num: %d is out of range[0..%d]\n", + cpuid, CONFIG_NR_CPUS - 1); + return 1; + } + + + if (argc == 3) { + if (strncmp(argv[2], "reset", 5) == 0) { + cpu_reset(cpuid); + } else if (strncmp(argv[2], "status", 6) == 0) { + cpu_status(cpuid); + } else { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + return 0; + } + + /* 4 or greater, make sure its release */ + if (strncmp(argv[2], "release", 7) != 0) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + val = simple_strtoul(argv[3], NULL, 16); + + if (cpu_release(cpuid, val, argc - 4, argv + 4)) { + printf ("Usage:\n%s\n", cmdtp->usage); + return 1; + } + + return 0; +} + +#ifdef CONFIG_PPC +#define CPU_ARCH_HELP \ + " [args] : <pir> <r3> <r4> <r6> <r7>\n" \ + " pir - processor id (if writeable)\n" \ + " r3 - value for gpr 3\n" \ + " r4 - value for gpr 4\n" \ + " r6 - value for gpr 6\n" \ + " r7 - value for gpr 7\n" \ + "\n" \ + " Use '-' for any arg if you want the default value.\n" \ + " Default for r3, r4, r7 is 0, r6 is 0x65504150\n" \ + "\n" \ + " When cpu <num> is released r5 = 0 per the ePAPR spec.\n" +#endif + +U_BOOT_CMD( + cpu, CFG_MAXARGS, 1, cpu_cmd, + "cpu - Multiprocessor CPU boot manipulation and release\n", + "<num> reset - Reset cpu <num>\n" + "cpu <num> status - Status of cpu <num>\n" + "cpu <num> release <addr> [args] - Release cpu <num> at <addr> with [args]\n" +#ifdef CPU_ARCH_HELP + CPU_ARCH_HELP +#endif + ); diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 2205dca..adbc585 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -29,6 +29,9 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a START = start.o resetvec.o +SOBJS-$(CONFIG_MP) += release.o +SOBJS = $(SOBJS-y) +COBJS-$(CONFIG_MP) += mp.o COBJS-$(CONFIG_OF_LIBFDT) += fdt.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o tlb.o \ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o \ diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index 5f02e0e..fce0c48 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -33,6 +33,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -328,5 +329,8 @@ int cpu_init_r(void) qe_reset(); #endif +#if defined(CONFIG_MP) + setup_mp(); +#endif return 0; } diff --git a/cpu/mpc85xx/fdt.c b/cpu/mpc85xx/fdt.c index 0ce17e7..bd54428 100644 --- a/cpu/mpc85xx/fdt.c +++ b/cpu/mpc85xx/fdt.c @@ -27,6 +27,55 @@ #include <libfdt.h> #include <fdt_support.h> +#ifdef CONFIG_MP +#include "mp.h" +DECLARE_GLOBAL_DATA_PTR; + +void ft_fixup_cpu(void *blob, u64 memory_limit) +{ + int off; + ulong spin_tbl_addr = get_spin_addr(); + u32 bootpg, id = get_my_id(); + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + off = fdt_node_offset_by_prop_value(blob, -1, "device_type", "cpu", 4); + while (off != -FDT_ERR_NOTFOUND) { + u32 *reg = (u32 *)fdt_getprop(blob, off, "reg", 0); + + if (reg) { + if (*reg == id) { + fdt_setprop_string(blob, off, "status", "okay"); + } else { + u32 val = *reg * 24 + spin_tbl_addr; + val = cpu_to_fdt32(val); + fdt_setprop_string(blob, off, "status", + "disabled"); + fdt_setprop_string(blob, off, "enable-method", + "spin-table"); + fdt_setprop(blob, off, "cpu-release-addr", + &val, sizeof(val)); + } + } else { + printf ("cpu NULL\n"); + } + off = fdt_node_offset_by_prop_value(blob, off, + "device_type", "cpu", 4); + } + + /* Reserve the boot page so OSes dont use it */ + if ((u64)bootpg < memory_limit) { + off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); + if (off < 0) + printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); + } +} +#endif + void ft_cpu_setup(void *blob, bd_t *bd) { #if defined(CONFIG_HAS_ETH0) || defined(CONFIG_HAS_ETH1) ||\ @@ -64,4 +113,8 @@ void ft_cpu_setup(void *blob, bd_t *bd) #endif fdt_fixup_memory(blob, (u64)bd->bi_memstart, (u64)bd->bi_memsize); + +#ifdef CONFIG_MP + ft_fixup_cpu(blob, (u64)bd->bi_memstart + (u64)bd->bi_memsize); +#endif } diff --git a/cpu/mpc85xx/mp.c b/cpu/mpc85xx/mp.c new file mode 100644 index 0000000..aa91cea --- /dev/null +++ b/cpu/mpc85xx/mp.c @@ -0,0 +1,190 @@ +/* + * Copyright 2008 Freescale Semiconductor. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <asm/processor.h> +#include <ioports.h> +#include <asm/io.h> +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +#define BOOT_ENTRY_ADDR 0 +#define BOOT_ENTRY_PIR 1 +#define BOOT_ENTRY_R3 2 +#define BOOT_ENTRY_R4 3 +#define BOOT_ENTRY_R6 4 +#define BOOT_ENTRY_R7 5 +#define NUM_BOOT_ENTRY 6 + +u32 get_my_id() +{ + return mfspr(SPRN_PIR); +} + +int cpu_reset(int nr) +{ + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + out_be32(&pic->pir, 1 << nr); + (void)in_be32(&pic->pir); + out_be32(&pic->pir, 0x0); + + return 0; +} + +int cpu_status(int nr) +{ + u32 *table, id = get_my_id(); + + if (nr == id) { + table = (u32 *)get_spin_addr(); + printf("table base @ 0x%08x\n", table); + } else { + table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + printf("Running on cpu %d\n", id); + printf("\n"); + printf("table @ 0x%08x:\n", table); + printf(" addr - 0x%08x\n", table[BOOT_ENTRY_ADDR]); + printf(" pir - 0x%08x\n", table[BOOT_ENTRY_PIR]); + printf(" r3 - 0x%08x\n", table[BOOT_ENTRY_R3]); + printf(" r4 - 0x%08x\n", table[BOOT_ENTRY_R4]); + printf(" r6 - 0x%08x\n", table[BOOT_ENTRY_R6]); + printf(" r7 - 0x%08x\n", table[BOOT_ENTRY_R7]); + } + + return 0; +} + +int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]) +{ + u32 i, val, *table = (u32 *)get_spin_addr() + nr * NUM_BOOT_ENTRY; + + if (nr == get_my_id()) { + printf("Invalid to release the boot core.\n\n"); + return 1; + } + + if (argc != 5) { + printf("Invalid number of arguments to release.\n\n"); + return 1; + } + + /* handle pir, r3, r4, r6, r7 */ + for (i = 0; i < 5; i++) { + if (argv[i][0] != '-') { + val = simple_strtoul(argv[i], NULL, 16); + table[i+BOOT_ENTRY_PIR] = val; + } + } + + table[BOOT_ENTRY_ADDR] = boot_addr; + + return 0; +} + +ulong get_spin_addr(void) +{ + extern ulong __secondary_start_page; + extern ulong __spin_table; + + ulong addr = + (ulong)&__spin_table - (ulong)&__secondary_start_page; + addr += 0xfffff000; + + return addr; +} + +static void pq3_mp_up(unsigned long bootpg) +{ + u32 up, cpu_up_mask, whoami; + u32 *table = (u32 *)get_spin_addr(); + volatile u32 bpcr; + volatile ccsr_local_ecm_t *ecm = (void *)(CFG_MPC85xx_ECM_ADDR); + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile ccsr_pic_t *pic = (void *)(CFG_MPC85xx_PIC_ADDR); + u32 devdisr; + int timeout = 10; + + whoami = in_be32(&pic->whoami); + out_be32(&ecm->bptr, 0x80000000 | (bootpg >> 12)); + + /* disable time base at the platform */ + devdisr = in_be32(&gur->devdisr); + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB0; + else + devdisr |= MPC85xx_DEVDISR_TB1; + out_be32(&gur->devdisr, devdisr); + + /* release the hounds */ + up = ((1 << CONFIG_NR_CPUS) - 1); + bpcr = in_be32(&ecm->eebpcr); + bpcr |= (up << 24); + out_be32(&ecm->eebpcr, bpcr); + asm("sync; isync; msync"); + + cpu_up_mask = 1 << whoami; + /* wait for everyone */ + while (timeout) { + int i; + for (i = 1; i < CONFIG_NR_CPUS; i++) { + if (table[i * NUM_BOOT_ENTRY]) + cpu_up_mask |= (1 << i); + }; + + if ((cpu_up_mask & up) == up) + break; + + udelay(100); + timeout--; + } + + /* enable time base at the platform */ + if (whoami) + devdisr |= MPC85xx_DEVDISR_TB1; + else + devdisr |= MPC85xx_DEVDISR_TB0; + out_be32(&gur->devdisr, devdisr); + mtspr(SPRN_TBWU, 0); + mtspr(SPRN_TBWL, 0); + + devdisr &= ~(MPC85xx_DEVDISR_TB0 | MPC85xx_DEVDISR_TB1); + out_be32(&gur->devdisr, devdisr); +} + +void setup_mp(void) +{ + extern ulong __secondary_start_page; + ulong fixup = (ulong)&__secondary_start_page; + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-4k */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfffff000; + else + bootpg = gd->ram_size - 4096; + + memcpy((void *)bootpg, (void *)fixup, 4096); + flush_cache(bootpg, 4096); + + pq3_mp_up(bootpg); +} diff --git a/cpu/mpc85xx/mp.h b/cpu/mpc85xx/mp.h new file mode 100644 index 0000000..d9fbb82 --- /dev/null +++ b/cpu/mpc85xx/mp.h @@ -0,0 +1,8 @@ +#ifndef __MPC85XX_MP_H_ +#define __MPC85XX_MP_H_ + +ulong get_spin_addr(void); +void setup_mp(void); +u32 get_my_id(void); + +#endif diff --git a/cpu/mpc85xx/release.S b/cpu/mpc85xx/release.S new file mode 100644 index 0000000..fe1775c --- /dev/null +++ b/cpu/mpc85xx/release.S @@ -0,0 +1,148 @@ +#include <config.h> +#include <mpc85xx.h> +#include <version.h> + +#define _LINUX_CONFIG_H 1 /* avoid reading Linux autoconf.h file */ + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +/* To boot secondary cpus, we need a place for them to start up. + * Normally, they start at 0xfffffffc, but that's usually the + * firmware, and we don't want to have to run the firmware again. + * Instead, the primary cpu will set the BPTR to point here to + * this page. We then set up the core, and head to + * start_secondary. Note that this means that the code below + * must never exceed 1023 instructions (the branch at the end + * would then be the 1024th). + */ + .globl __secondary_start_page + .align 12 +__secondary_start_page: +/* First do some preliminary setup */ + lis r3, HID0_EMCP@h /* enable machine check */ + ori r3,r3,HID0_TBEN@l /* enable Timebase */ +#ifdef CONFIG_PHYS_64BIT + ori r3,r3,HID0_ENMAS7@l /* enable MAS7 updates */ +#endif + mtspr SPRN_HID0,r3 + + li r3,(HID1_ASTME|HID1_ABE)@l /* Addr streaming & broadcast */ + mtspr SPRN_HID1,r3 + + /* Enable branch prediction */ + li r3,0x201 + mtspr SPRN_BUCSR,r3 + + /* Enable/invalidate the I-Cache */ + mfspr r0,SPRN_L1CSR1 + ori r0,r0,(L1CSR1_ICFI|L1CSR1_ICE) + mtspr SPRN_L1CSR1,r0 + isync + + /* Enable/invalidate the D-Cache */ + mfspr r0,SPRN_L1CSR0 + ori r0,r0,(L1CSR0_DCFI|L1CSR0_DCE) + msync + isync + mtspr SPRN_L1CSR0,r0 + isync + +#define toreset(x) (x - __secondary_start_page + 0xfffff000) + + /* get our PIR to figure out our table entry */ + lis r3,toreset(__spin_table)@h + ori r3,r3,toreset(__spin_table)@l + + /* r9 has the base address for the entry */ + mfspr r0,SPRN_PIR + mr r4,r0 + slwi r8,r4,4 + slwi r9,r4,3 + add r8,r8,r9 + add r9,r3,r8 + +#define EPAPR_MAGIC (0x65504150) +#define ENTRY_ADDR 0 +#define ENTRY_PIR 4 +#define ENTRY_R3 8 +#define ENTRY_R4 12 +#define ENTRY_R6 16 +#define ENTRY_R7 20 + + /* setup the entry */ + li r4,0 + li r8,1 + lis r6,EPAPR_MAGIC@h + ori r6,r6,EPAPR_MAGIC@l + stw r0,ENTRY_PIR(r9) + stw r8,ENTRY_ADDR(r9) + stw r4,ENTRY_R3(r9) + stw r4,ENTRY_R4(r9) + stw r6,ENTRY_R6(r9) + stw r4,ENTRY_R7(r9) + + /* spin waiting for addr */ +1: lwz r4,ENTRY_ADDR(r9) + andi. r11,r4,1 + bne 1b + + /* setup branch addr */ + mtctr r4 + + /* mark the entry as released */ + li r8,3 + stw r8,ENTRY_ADDR(r9) + + /* mask by ~64M to setup our tlb we will jump to */ + rlwinm r8,r4,0,0,5 + + /* setup r3, r5, r6, r7 */ + lwz r3,ENTRY_R3(r9) + lwz r4,ENTRY_R4(r9) + li r5,0 + lwz r6,ENTRY_R6(r9) + lwz r7,ENTRY_R7(r9) + + /* load up the pir */ + lwz r0,ENTRY_PIR(r9) + mtspr SPRN_PIR,r0 + mfspr r0,SPRN_PIR + stw r0,ENTRY_PIR(r9) + +/* + * Coming here, we know the cpu has one TLB mapping in TLB1[0] + * which maps 0xfffff000-0xffffffff one-to-one. We set up a + * second mapping that maps addr 1:1 for 64M, and then we jump to + * addr + */ + lis r9,(MAS0_TLBSEL(1)|MAS0_ESEL(1))@h + mtspr SPRN_MAS0,r9 + lis r9,(MAS1_VALID|MAS1_IPROT)@h + ori r9,r9,(MAS1_TSIZE(BOOKE_PAGESZ_64M))@l + mtspr SPRN_MAS1,r9 + /* WIMGE = 0b00000 for now */ + mtspr SPRN_MAS2,r8 + ori r8,r8,(MAS3_SX|MAS3_SW|MAS3_SR) + mtspr SPRN_MAS3,r8 + tlbwe + +/* Now we have another mapping for this page, so we jump to that + * mapping + */ + bctr + + .align 3 + .globl __spin_table +__spin_table: + .space CONFIG_NR_CPUS*24 + + /* Fill in the empty space. The actual reset vector is + * the last word of the page */ +__secondary_start_code_end: + .space 4092 - (__secondary_start_code_end - __secondary_start_page) +__secondary_reset_vector: + b __secondary_start_page diff --git a/include/asm-ppc/immap_85xx.h b/include/asm-ppc/immap_85xx.h index d769d70..712a078 100644 --- a/include/asm-ppc/immap_85xx.h +++ b/include/asm-ppc/immap_85xx.h @@ -1578,7 +1578,11 @@ typedef struct ccsr_gur { #define MPC85xx_DEVDISR_RMSG 0x00040000 #define MPC85xx_DEVDISR_DDR 0x00010000 #define MPC85xx_DEVDISR_CPU 0x00008000 +#define MPC85xx_DEVDISR_CPU0 MPC85xx_DEVDISR_CPU #define MPC85xx_DEVDISR_TB 0x00004000 +#define MPC85xx_DEVDISR_TB0 MPC85xx_DEVDISR_TB +#define MPC85xx_DEVDISR_CPU1 0x00002000 +#define MPC85xx_DEVDISR_TB1 0x00001000 #define MPC85xx_DEVDISR_DMA 0x00000400 #define MPC85xx_DEVDISR_TSEC1 0x00000080 #define MPC85xx_DEVDISR_TSEC2 0x00000040 diff --git a/include/common.h b/include/common.h index 54083f1..bae9f4b 100644 --- a/include/common.h +++ b/include/common.h @@ -663,4 +663,11 @@ void inline show_boot_progress (int val); #error Read section CONFIG_SKIP_LOWLEVEL_INIT in README. #endif +/* Multicore arch functions */ +#ifdef CONFIG_MP +int cpu_status(int nr); +int cpu_reset(int nr); +int cpu_release(int nr, unsigned long boot_addr, int argc, char *argv[]); +#endif + #endif /* __COMMON_H_ */ -- 1.5.3.8

2 1

[U-Boot-Users] [PATCH] 85xx: Add the concept of CFG_CCSRBAR_PHYS
by Kumar Gala 05 Feb '08

05 Feb '08

When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- This is in the mpc85xx branch of my git tree. - k board/atum8548/tlb.c | 2 +- board/freescale/mpc8540ads/tlb.c | 2 +- board/freescale/mpc8541cds/tlb.c | 2 +- board/freescale/mpc8544ds/tlb.c | 2 +- board/freescale/mpc8548cds/tlb.c | 2 +- board/freescale/mpc8555cds/tlb.c | 2 +- board/freescale/mpc8560ads/tlb.c | 2 +- board/freescale/mpc8568mds/tlb.c | 2 +- board/mpc8540eval/tlb.c | 2 +- board/pm854/tlb.c | 2 +- board/pm856/tlb.c | 2 +- board/sbc8548/tlb.c | 2 +- board/sbc8560/tlb.c | 2 +- board/stxgp3/tlb.c | 2 +- board/stxssa/tlb.c | 2 +- board/tqm85xx/tlb.c | 2 +- cpu/mpc85xx/cpu_init.c | 6 +++--- include/configs/ATUM8548.h | 1 + include/configs/MPC8540ADS.h | 1 + include/configs/MPC8540EVAL.h | 1 + include/configs/MPC8541CDS.h | 1 + include/configs/MPC8544DS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/MPC8568MDS.h | 1 + include/configs/PM854.h | 1 + include/configs/PM856.h | 1 + include/configs/SBC8540.h | 1 + include/configs/TQM85xx.h | 1 + include/configs/sbc8548.h | 1 + include/configs/sbc8560.h | 1 + include/configs/stxgp3.h | 1 + include/configs/stxssa.h | 1 + 34 files changed, 36 insertions(+), 19 deletions(-) diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c index bb6ce76..1ef4de4 100644 --- a/board/atum8548/tlb.c +++ b/board/atum8548/tlb.c @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), }; diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 3eaff01..4fe2862 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index 92f759b..c5434a0 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index 34cfb38..61fc609 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe100_0000 255M PCI IO range */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index b21f71b..ab99af7 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c index 92f759b..c5434a0 100644 --- a/board/freescale/mpc8555cds/tlb.c +++ b/board/freescale/mpc8555cds/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 3eaff01..4fe2862 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 225fc94..a866c52 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -74,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_64M, 1), diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c index f041236..1003bf6 100644 --- a/board/mpc8540eval/tlb.c +++ b/board/mpc8540eval/tlb.c @@ -27,7 +27,7 @@ #include <asm/mmu.h> struct fsl_e_tlb_entry tlb_table[] = { - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index 5d87537..a7f3813 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index 5d87537..a7f3813 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 8d6625e..6314005 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c index 155ff64..d073399 100644 --- a/board/sbc8560/tlb.c +++ b/board/sbc8560/tlb.c @@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB for CCSRBAR (IMMR) */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c index 529f230..d410416 100644 --- a/board/stxgp3/tlb.c +++ b/board/stxgp3/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c index 46b1440..86cbd11 100644 --- a/board/stxssa/tlb.c +++ b/board/stxssa/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c index a178cfe..ad26cae 100644 --- a/board/tqm85xx/tlb.c +++ b/board/tqm85xx/tlb.c @@ -91,7 +91,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c0ff1d5..5f02e0e 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -127,12 +127,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR, + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) { u32 temp; @@ -141,7 +141,7 @@ void cpu_init_early_f(void) 1, 1, BOOKE_PAGESZ_4K, 0); temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CFG_CCSRBAR); } diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c14376e..0d644da 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -96,6 +96,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5ea7b25..85934d7 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -100,6 +100,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index bf64f27..04276a4 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -83,6 +83,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7334088..f1a86e6 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a894209..c83d9e2 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a3db9f4..2d44df4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -96,6 +96,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 93877ae..fa0f7b3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 08884b3..e30302c 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -95,6 +95,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a12d193..7bb20e5 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 819bee7..bd058fc 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -92,6 +92,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 8902f42..38a26dc 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -94,6 +94,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 2bbfe9a..946b3c2 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -99,6 +99,7 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index dd0654b..1239bd3 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -89,6 +89,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 0a7a904..a8fe689 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -87,6 +87,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index f9ede5f..81a1e07 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -93,6 +93,7 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 047e1cf..fc5d0cc 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -114,6 +114,7 @@ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index e09dd71..15f690a 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -127,6 +127,7 @@ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -- 1.5.3.8

2 1