December 2008 - U-Boot

Re: [U-Boot] hush shell script commands(eval)
by rudresh 24 Dec '08

24 Dec '08

Hi All Mary Christmas . Happy New Year. I have some query on hush shell script language. I'm using hush shell script to automate the testing for command exists in U-boot. The scripts is as follows echo -------------------------------------- echo Target Test: setenv check 'if imi FE7E0000; then val=1; else val=0; fi' print check run check echo -------------------------- echo FRAM Command Test echo -------------------------------------- setenv check 'if fram; then val_fram=1; else val_fram=0; fi' print check run check echo -------------------------------------- echo $val echo $val_fram echo ------------------------------------ setenv check 'if $val; then echo imi command executes Success; else echo imi commd Fails; fi' print check run check echo >>>>>>>>>>>>>>>>>>>>>>>> setenv check 'if $val_fram; then echo fram command executes Success; else echo fram commd Fails; fi' print check run check echo END Test If i execute this string I’m getting this error. check=if ($val); then echo command executes Success; else echo imi commd Fails; fi Unknown command '(0)' - try 'help' imi commd Fails >>>>>>>>>>>>>>>>>>>>>>>> check= if $val_fram; then echo fram command executes Success; else echo fram commd Fails; fi Unknown command '1' - try 'help' I’m not able to fix this error. is it not support the constant value in if then else fi statement?. Is there any alternate method? I also trying to use the standalone application, is there any command like system("command") in u-boot. i want to run command in U-boot using standalone application. please help me. Thanks & Regards, Rudresh -- View this message in context: http://www.nabble.com/Re%3Ahush-shell-script-commands%28eval%29-tp21156593p… Sent from the Uboot - Users mailing list archive at Nabble.com.

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[U-Boot] Debugging U-Boot with BDI2000
by Tommy Wang 23 Dec '08

23 Dec '08

Hi, I'm having trouble debugging U-Boot (version 2008.10) with a BDI2000 on an Embedded Planet EP8248 board (MPC8248 processor). According to "Embedded Linux Primer" by Christopher Hanin, early U-Boot debugging must be done using hardware breakpoints, because it is running out of flash at that point in time. Following along his example, I have connected to the BDI2000 via remote GDB and issued a 'mon break hard' command to enable hardware breakpoints. Upon continuing, I get the errors from the BDI that all hardware breakpoints are in use. Clearing breakpoints have no effect. Looking in my CPU reference manual, it does mention two instruction address breakpoint registers, as well as two data address breakpoint registers (IABR1, IABR2, DABR1, DABR2). It does not mention (at least that I could find) what is necessary to set these registers up and use them. Any tips on how to proceed would be appreciated. I have attached my BDI configuration, as well as the error message. Thank you! GDB Session: ~/u-boot/build% ppc-linux-gdb u-boot GNU gdb Red Hat Linux (6.7-1rh) Copyright (C) 2007 Free Software Foundation, Inc. License GPLv3+: GNU GPL version 3 or later <http://gnu.org/licenses/gpl.html> This is free software: you are free to change and redistribute it. There is NO WARRANTY, to the extent permitted by law. Type "show copying" and "show warranty" for details. This GDB was configured as "--host=i686-pc-linux-gnu --target=ppc-linux". The target architecture is set automatically (currently powerpc:common) .. (gdb) target remote 192.168.100.130:2001 Remote debugging using 192.168.100.130:2001 _start () at start.S:163 163 li r21, BOOTFLAG_COLD /* Normal Power-On: Boot from FLASH*/ Current language: auto; currently asm (gdb) mon break hard (gdb) b board_init_f Breakpoint 1 at 0xfff049b0: file board.c, line 405. (gdb) c Continuing. Warning: Cannot insert breakpoint 1. Error accessing memory address 0xfff049b0: Unknown error 4294967295. BDI Session: - TARGET: processing power-up delay - TARGET: processing user reset request - BDI asserts HRESET - Reset JTAG controller passed - Bypass check: 0x000000001 => 0x00000001 - Bypass check: 0x000000001 => 0x00000001 - JTAG exists check passed - COP status is 0x01 - Check running state passed - BDI scans COP freeze command - BDI removes HRESET - Target PVR is 0x80822014 - COP status is 0x05 - Check stopped state passed - Check LSRL length passed - BDI sets breakpoint at 0xFFF00100 - BDI resumes program execution - Waiting for target stop passed - TARGET: Target PVR is 0x80822014 - TARGET: resetting target passed - TARGET: processing target startup .... - TARGET: processing target startup passed - TARGET: stepped *** TARGET: all hardware breakpoints in use BDI Configuration File: ;EP8248 16M of psdram config script ;---------------------------------- ;written by Greg Davis ;based on the EP8260 BDI2000 script written by Steve Blakeslee ; ; [INIT] ; ;************************************************************* ; program the SYPCR - disable the watchdog timer ;************************************************************* WM32 0x10004 0xFFFF0681 ; ;************************************************************* ; program the bcr - Bus cfg reg ;************************************************************* WM32 0x10024 0x00908010 ; ;************************************************************* ; program the SIUMCR - ;************************************************************* WM32 0x10000 0x01240200 ; ;************************************************************* ; program the SCCR - disable PCI mode & set clock divider to 16 ;************************************************************* WM32 0x10c80 0x00000001 ; ;************************************************************* ; load IMMR register with the new base address (0x04700000) ; Warning: this assumes that the IMMR is located at 0xf0101A8 ; due to the reset configuration. If the reset config words ; in boot Flash/ROM are set for a different address, then you ; must update this script to use the new IMMR address! ;************************************************************* WM32 0x101A8 0xF0000000 ; ;************************************************************* ; initialize the memory controller registers... ;************************************************************* ; ;************************************************************* ; initialize - FLASH BR0 & OR0 (8 Mbyte) ;************************************************************* ;WM32 0xf0010100 0xFC001801 ;WM32 0xf0010104 0xFC0008B2 ; ;************************************************************* ; initialize - PSDRAM BR1 & OR1 (16 Mbyte) ;************************************************************* WM32 0xf0010108 0x00001841 WM32 0xf001010c 0xFF0030C0 ; ;************************************************************* ; initialize - BCSR BR2 & OR2 ;************************************************************* WM32 0xf0010110 0xFA000801 WM32 0xf0010114 0xFFC80864 ; ;************************************************************* ; program the MPTPR - ;************************************************************* WM16 0xf0010184 0x1300 ; ;************************************************************* ; SDRAM Initialization ;************************************************************* ;wait 100us before accessing ; ;************************************************************* ; initialize - PSDRAM mode reg (PSDMR) ; ; C2672522 ; C267FF33 (slow timing) ; ;************************************************************* WM32 0xf0010190 0xC267FF33 ; ;************************************************************* ; program PSRT - PSDRAM refresh timer ; ; 0x4B ; ;************************************************************* WM8 0xf001019C 0x4B ; ;************************************************************* ; SDRAM Initialization ;************************************************************* ;wait 100us before accessing ; ;Precharge all banks SMMR[OP]=101 WM8 0xf0010190 0xea WM8 0x00000110 0xff ; ;Issue 8 CBR_Refresh commands SMMR[OP]=001 WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0xf0010190 0xca WM8 0x00000110 0xff ; ;Issue Mode set command SMMR[OP]=011 WM8 0xf0010190 0xda WM8 0x00000110 0xff ; ;set PSDMR for normal operation WM8 0xf0010190 0xc2 ; ;clear MRS WREG MSR 0x00000000 ; ; [TARGET] CPUTYPE 8240 ;the CPU type (603EV,750,8240,8260) JTAGCLOCK 0 ;use 16 MHz JTAG clock ;WORKSPACE 0x00000000 ;workspace in target RAM for fast download BDIMODE AGENT ;the BDI working mode (LOADONLY | AGENT | GATEWAY) BREAKMODE HARD ;SOFT or HARD, HARD uses PPC hardware breakpoints VECTOR CATCH ;catch unhandled exceptions DCACHE NOFLUSH ;data cache flushing (FLUSH | NOFLUSH) SIO 7 9600 ; ; ;Not really using this ; [FLASH] ;CHIPTYPE AM29F ;Flash type (AM29F | AM29BX8 | AM29BX16 | I28BX8 | I28BX16) ;CHIPSIZE 0x200000 ;The size of one flash chip in bytes (e.g. AM29F010 = 0x20000) ;BUSWIDTH 8 ;The width of the flash memory bus in bits (8 | 16 | 32 | 64) ; ; [HOST] IP 192.168.100.3 FILE pcl82xx120.ep FORMAT SREC ;START 0x80020 ;only needed for RAM booloader LOAD MANUAL ;load code MANUAL or AUTO after reset ; ; [REGS] DMM1 0xF0000000 FILE reg8272.def Tommy Wang 5605 N. MacArthur Blvd. Suite 1100 Irving, TX 75038 601.594.9864 twang(a)dtims.com Diversified Technology, Inc. 1.800.443.2667 http://www.diversifiedtechnology.com Providing a Cohesive Approach to Embedded Solutions Both the individual sending this e-mail and Diversified Technology, Inc. intend that this electronic message be used exclusively by the individual or entity to which it is addressed. This message may contain information that is privileged or confidential and thereby exempt and protected from unauthorized disclosure under applicable law. If the reader of this message is not the intended recipient, be aware that any disclosure, dissemination, distribution or copying of this communication, or the use of its contents, is not authorized and is strictly prohibited. If you have received this communication and are not the intended recipient, notify the sender immediately, permanently delete the original message from your e-mail system and do not keep a hard copy of the message.

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Re: [U-Boot] [PATCH v2 2/6] usb : musb : Adding host controller driver for Mentor USB controller
by Bryan Wu 23 Dec '08

23 Dec '08

Hi Thomas and Ajay, I just noticed you guys are adding the musb davinci to u-boot, so I guess I don't need to reinvent wheels. As I subscribed to u-boot mail list recently, I missed your original email. I copy & paste your code to this email and add some comments. Thanks a lot -Bryan ----- +/* + * This function configures the endpoint configuration. The musb hcd or musb + * device implementation can use this function to configure the Endpoints + * and set the FIFO sizes. Note: The summation of FIFO sizes of all endpoints + * should not be more than the available FIFO size. + * + * epinfo - Pointer to EP configuration table + * cnt - Number of entries in the EP conf table. + */ +void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt) +{ + u16 csr; + u16 fifoaddr = 64; /* First 64 bytes of FIFO reserved for EP0 */ + u32 fifosize; + u8 idx; + + while (cnt--) { + /* prepare fifosize to write to register */ + fifosize = epinfo->epsize >> 3; + idx = ffs(fifosize) - 1; + + musb_writeb(MUSB_INDEX, epinfo->epnum); + if (epinfo->epdir) { + /* Configure fifo size and fifo base address */ + musb_writeb(MUSB_TXFIFOSZ, idx); + musb_writew(MUSB_TXFIFOADD, fifoaddr >> 3); + [Bryan]: As there is no such {TX|RX}FIFOSZ and {TX|RX}FIFOADD registers on Blackfin, we need to use #ifndef CONFIG_USB_BLACKFIN to embrace them. And Blackfin also missed some HUB and PORT registers. +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr | MUSB_TXCSR_CLRDATATOG); +#endif + + /* Flush fifo if required */ + if (csr & MUSB_TXCSR_TXPKTRDY) { + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr | MUSB_TXCSR_FLUSHFIFO); + } + } else { + /* Configure fifo size and fifo base address */ + musb_writeb(MUSB_RXFIFOSZ, idx); + musb_writew(MUSB_RXFIFOADD, fifoaddr >> 3); + [Bryan]: ditto +#if defined(CONFIG_MUSB_HCD) + /* clear the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr | MUSB_RXCSR_CLRDATATOG); +#endif + + /* Flush fifo if required */ + if (csr & MUSB_RXCSR_RXPKTRDY) { + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr | MUSB_RXCSR_FLUSHFIFO); + } + } + fifoaddr += epinfo->epsize; + epinfo++; + } +} + +/* + * This function writes data to endpoint fifo + * + * ep - Endpoint number + * length - Number of bytes to write to FIFO + * fifo_data - Pointer to data buffer that contains the data to write + */ +void write_fifo(u8 ep, u32 length, void *fifo_data) +{ + u32 address; + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + musb_writeb(MUSB_INDEX, ep); [Bryan]: IMO, we don't need to set the INDEX register here, right? + address = MUSB_FIFO_OFFSET(ep); + + /* write the data to the fifo */ + while (length--) + musb_writeb(address, *data++); +} + [Bryan]: On Blackfin, we can only use a fixed transfer size of half words (16-bits) So maybe this function should move out to davinci_usb.c and we can provide blackfin version. +/* + * This function reads data from endpoint fifo + * + * ep - Endpoint number + * length - Number of bytes to read from FIFO + * fifo_data - Pointer to data buffer into which data is read + */ +void read_fifo(u8 ep, u32 length, void *fifo_data) +{ + u32 address; + u8 *data = (u8 *)fifo_data; + + /* select the endpoint index */ + musb_writeb(MUSB_INDEX, ep); + address = MUSB_FIFO_OFFSET(ep); + + /* read the data to the fifo */ + while (length--) + *data++ = musb_readb(address); +} + [Bryan]: ditto +#endif /* CONFIG_MUSB_HCD */ + + + diff --git a/drivers/usb/musb_core.h b/drivers/usb/musb_core.h new file mode 100644 index 0000000..d5fba54 --- /dev/null +++ b/drivers/usb/musb_core.h @@ -0,0 +1,322 @@ +/****************************************************************** + * Copyright 2005 Mentor Graphics Corporation + * Copyright (C) 2005-2006 by Texas Instruments + * + * This file is part of the Inventra Controller Driver for Linux. + * + * The Inventra Controller Driver for Linux is free software; you + * can redistribute it and/or modify it under the terms of the GNU + * General Public License version 2 as published by the Free Software + * Foundation. + * + * The Inventra Controller Driver for Linux is distributed in + * the hope that it will be useful, but WITHOUT ANY WARRANTY; + * without even the implied warranty of MERCHANTABILITY or + * FITNESS FOR A PARTICULAR PURPOSE. See the GNU General Public + * License for more details. + * + * You should have received a copy of the GNU General Public License + * along with The Inventra Controller Driver for Linux ; if not, + * write to the Free Software Foundation, Inc., 59 Temple Place, + * Suite 330, Boston, MA 02111-1307 USA + * + * ANY DOWNLOAD, USE, REPRODUCTION, MODIFICATION OR DISTRIBUTION + * OF THIS DRIVER INDICATES YOUR COMPLETE AND UNCONDITIONAL ACCEPTANCE + * OF THOSE TERMS.THIS DRIVER IS PROVIDED "AS IS" AND MENTOR GRAPHICS + * MAKES NO WARRANTIES, EXPRESS OR IMPLIED, RELATED TO THIS DRIVER. + * MENTOR GRAPHICS SPECIFICALLY DISCLAIMS ALL IMPLIED WARRANTIES + * OF MERCHANTABILITY; FITNESS FOR A PARTICULAR PURPOSE AND + * NON-INFRINGEMENT. MENTOR GRAPHICS DOES NOT PROVIDE SUPPORT + * SERVICES OR UPDATES FOR THIS DRIVER, EVEN IF YOU ARE A MENTOR + * GRAPHICS SUPPORT CUSTOMER. + ******************************************************************/ + +#ifndef __MUSB_HDRC_DEFS_H__ +#define __MUSB_HDRC_DEFS_H__ + +#include <usb.h> +#include <usb_defs.h> + +#define MUSB_EP0_FIFOSIZE 64 /* This is non-configurable */ + +/* + * Common USB registers + */ + +#define MUSB_FADDR 0x00 /* 8-bit */ +#define MUSB_POWER 0x01 /* 8-bit */ + +#define MUSB_INTRTX 0x02 /* 16-bit */ +#define MUSB_INTRRX 0x04 +#define MUSB_INTRTXE 0x06 +#define MUSB_INTRRXE 0x08 +#define MUSB_INTRUSB 0x0A /* 8 bit */ +#define MUSB_INTRUSBE 0x0B /* 8 bit */ +#define MUSB_FRAME 0x0C +#define MUSB_INDEX 0x0E /* 8 bit */ +#define MUSB_TESTMODE 0x0F /* 8 bit */ + +/* Get offset for a given FIFO from musb->mregs */ +#define MUSB_FIFO_OFFSET(epnum) (0x20 + ((epnum) * 4)) + +/* + * Additional Control Registers + */ +#define MUSB_DEVCTL 0x60 /* 8 bit */ + +/* These are always controlled through the INDEX register */ +#define MUSB_TXFIFOSZ 0x62 /* 8-bit (see masks) */ +#define MUSB_RXFIFOSZ 0x63 /* 8-bit (see masks) */ +#define MUSB_TXFIFOADD 0x64 /* 16-bit offset shifted right 3 */ +#define MUSB_RXFIFOADD 0x66 /* 16-bit offset shifted right 3 */ + +/* REVISIT: vctrl/vstatus: optional vendor utmi+phy register at 0x68 */ +#define MUSB_HWVERS 0x6C /* 8 bit */ + +#define MUSB_EPINFO 0x78 /* 8 bit */ +#define MUSB_RAMINFO 0x79 /* 8 bit */ +#define MUSB_LINKINFO 0x7a /* 8 bit */ +#define MUSB_VPLEN 0x7b /* 8 bit */ +#define MUSB_HS_EOF1 0x7c /* 8 bit */ +#define MUSB_FS_EOF1 0x7d /* 8 bit */ +#define MUSB_LS_EOF1 0x7e /* 8 bit */ + +/* Offsets to endpoint registers */ +#define MUSB_TXMAXP 0x00 +#define MUSB_TXCSR 0x02 +#define MUSB_CSR0 MUSB_TXCSR /* Re-used for EP0 */ +#define MUSB_RXMAXP 0x04 +#define MUSB_RXCSR 0x06 +#define MUSB_RXCOUNT 0x08 +#define MUSB_COUNT0 MUSB_RXCOUNT /* Re-used for EP0 */ +#define MUSB_TXTYPE 0x0A +#define MUSB_TYPE0 MUSB_TXTYPE /* Re-used for EP0 */ +#define MUSB_TXINTERVAL 0x0B +#define MUSB_NAKLIMIT0 MUSB_TXINTERVAL /* Re-used for EP0 */ +#define MUSB_RXTYPE 0x0C +#define MUSB_RXINTERVAL 0x0D +#define MUSB_FIFOSIZE 0x0F +#define MUSB_CONFIGDATA MUSB_FIFOSIZE /* Re-used for EP0 */ + +/* Offsets to endpoint registers in indexed model (using INDEX register) */ +#define MUSB_INDEXED_OFFSET(_offset) \ + (0x10 + (_offset)) + +/* Offsets to endpoint registers in flat models */ +#define MUSB_FLAT_OFFSET(_epnum, _offset) \ + (0x100 + (0x10*(_epnum)) + (_offset)) + +/* "bus control"/target registers, for host side multipoint (external hubs) */ +#define MUSB_TXFUNCADDR 0x00 +#define MUSB_TXHUBADDR 0x02 +#define MUSB_TXHUBPORT 0x03 + +#define MUSB_RXFUNCADDR 0x04 +#define MUSB_RXHUBADDR 0x06 +#define MUSB_RXHUBPORT 0x07 + +#define MUSB_BUSCTL_OFFSET(_epnum, _offset) \ + (0x80 + (8*(_epnum)) + (_offset)) + [Bryan]: I will provide the Blackfin register map later. +/* + * MUSB Register bits + */ + +/* POWER */ +#define MUSB_POWER_ISOUPDATE 0x80 +#define MUSB_POWER_SOFTCONN 0x40 +#define MUSB_POWER_HSENAB 0x20 +#define MUSB_POWER_HSMODE 0x10 +#define MUSB_POWER_RESET 0x08 +#define MUSB_POWER_RESUME 0x04 +#define MUSB_POWER_SUSPENDM 0x02 +#define MUSB_POWER_ENSUSPEND 0x01 +#define MUSB_POWER_HSMODE_SHIFT 4 + + +/* INTRUSB */ +#define MUSB_INTR_SUSPEND 0x01 +#define MUSB_INTR_RESUME 0x02 +#define MUSB_INTR_RESET 0x04 +#define MUSB_INTR_BABBLE 0x04 +#define MUSB_INTR_SOF 0x08 +#define MUSB_INTR_CONNECT 0x10 +#define MUSB_INTR_DISCONNECT 0x20 +#define MUSB_INTR_SESSREQ 0x40 +#define MUSB_INTR_VBUSERROR 0x80 /* For SESSION end */ + +/* DEVCTL */ +#define MUSB_DEVCTL_BDEVICE 0x80 +#define MUSB_DEVCTL_FSDEV 0x40 +#define MUSB_DEVCTL_LSDEV 0x20 +#define MUSB_DEVCTL_VBUS 0x18 +#define MUSB_DEVCTL_VBUS_SHIFT 3 +#define MUSB_DEVCTL_HM 0x04 +#define MUSB_DEVCTL_HR 0x02 +#define MUSB_DEVCTL_SESSION 0x01 + +/* TESTMODE */ +#define MUSB_TEST_FORCE_HOST 0x80 +#define MUSB_TEST_FIFO_ACCESS 0x40 +#define MUSB_TEST_FORCE_FS 0x20 +#define MUSB_TEST_FORCE_HS 0x10 +#define MUSB_TEST_PACKET 0x08 +#define MUSB_TEST_K 0x04 +#define MUSB_TEST_J 0x02 +#define MUSB_TEST_SE0_NAK 0x01 + +/* Allocate for double-packet buffering (effectively doubles assigned _SIZE) */ +#define MUSB_FIFOSZ_DPB 0x10 +/* Allocation size (8, 16, 32, ... 4096) */ +#define MUSB_FIFOSZ_SIZE 0x0f + +/* CSR0 */ +#define MUSB_CSR0_FLUSHFIFO 0x0100 +#define MUSB_CSR0_TXPKTRDY 0x0002 +#define MUSB_CSR0_RXPKTRDY 0x0001 + +/* CSR0 in Peripheral mode */ +#define MUSB_CSR0_P_SVDSETUPEND 0x0080 +#define MUSB_CSR0_P_SVDRXPKTRDY 0x0040 +#define MUSB_CSR0_P_SENDSTALL 0x0020 +#define MUSB_CSR0_P_SETUPEND 0x0010 +#define MUSB_CSR0_P_DATAEND 0x0008 +#define MUSB_CSR0_P_SENTSTALL 0x0004 + +/* CSR0 in Host mode */ +#define MUSB_CSR0_H_DIS_PING 0x0800 +#define MUSB_CSR0_H_WR_DATATOGGLE 0x0400 /* Set to allow setting: */ +#define MUSB_CSR0_H_DATATOGGLE 0x0200 /* Data toggle control */ +#define MUSB_CSR0_H_NAKTIMEOUT 0x0080 +#define MUSB_CSR0_H_STATUSPKT 0x0040 +#define MUSB_CSR0_H_REQPKT 0x0020 +#define MUSB_CSR0_H_ERROR 0x0010 +#define MUSB_CSR0_H_SETUPPKT 0x0008 +#define MUSB_CSR0_H_RXSTALL 0x0004 + +/* CSR0 bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_CSR0_P_WZC_BITS \ + (MUSB_CSR0_P_SENTSTALL) +#define MUSB_CSR0_H_WZC_BITS \ + (MUSB_CSR0_H_NAKTIMEOUT | MUSB_CSR0_H_RXSTALL \ + | MUSB_CSR0_RXPKTRDY) + +/* TxType/RxType */ +#define MUSB_TYPE_SPEED 0xc0 +#define MUSB_TYPE_SPEED_SHIFT 6 +#define MUSB_TYPE_SPEED_HIGH 1 +#define MUSB_TYPE_SPEED_FULL 2 +#define MUSB_TYPE_SPEED_LOW 3 +#define MUSB_TYPE_PROTO 0x30 /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_SHIFT 4 +#define MUSB_TYPE_REMOTE_END 0xf /* Implicitly zero for ep0 */ +#define MUSB_TYPE_PROTO_BULK 2 + +/* CONFIGDATA */ +#define MUSB_CONFIGDATA_MPRXE 0x80 /* Auto bulk pkt combining */ +#define MUSB_CONFIGDATA_MPTXE 0x40 /* Auto bulk pkt splitting */ +#define MUSB_CONFIGDATA_BIGENDIAN 0x20 +#define MUSB_CONFIGDATA_HBRXE 0x10 /* HB-ISO for RX */ +#define MUSB_CONFIGDATA_HBTXE 0x08 /* HB-ISO for TX */ +#define MUSB_CONFIGDATA_DYNFIFO 0x04 /* Dynamic FIFO sizing */ +#define MUSB_CONFIGDATA_SOFTCONE 0x02 /* SoftConnect */ +#define MUSB_CONFIGDATA_UTMIDW 0x01 /* Data width 0/1 => 8/16bits */ + +/* TXCSR in Peripheral and Host mode */ +#define MUSB_TXCSR_AUTOSET 0x8000 +#define MUSB_TXCSR_MODE 0x2000 +#define MUSB_TXCSR_DMAENAB 0x1000 +#define MUSB_TXCSR_FRCDATATOG 0x0800 +#define MUSB_TXCSR_DMAMODE 0x0400 +#define MUSB_TXCSR_CLRDATATOG 0x0040 +#define MUSB_TXCSR_FLUSHFIFO 0x0008 +#define MUSB_TXCSR_FIFONOTEMPTY 0x0002 +#define MUSB_TXCSR_TXPKTRDY 0x0001 + +/* TXCSR in Peripheral mode */ +#define MUSB_TXCSR_P_ISO 0x4000 +#define MUSB_TXCSR_P_INCOMPTX 0x0080 +#define MUSB_TXCSR_P_SENTSTALL 0x0020 +#define MUSB_TXCSR_P_SENDSTALL 0x0010 +#define MUSB_TXCSR_P_UNDERRUN 0x0004 + +/* TXCSR in Host mode */ +#define MUSB_TXCSR_H_WR_DATATOGGLE 0x0200 +#define MUSB_TXCSR_H_DATATOGGLE 0x0100 +#define MUSB_TXCSR_H_NAKTIMEOUT 0x0080 +#define MUSB_TXCSR_H_RXSTALL 0x0020 +#define MUSB_TXCSR_H_ERROR 0x0004 +#define MUSB_TXCSR_H_DATATOGGLE_SHIFT 8 + + +/* TXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_TXCSR_P_WZC_BITS \ + (MUSB_TXCSR_P_INCOMPTX | MUSB_TXCSR_P_SENTSTALL \ + | MUSB_TXCSR_P_UNDERRUN | MUSB_TXCSR_FIFONOTEMPTY) +#define MUSB_TXCSR_H_WZC_BITS \ + (MUSB_TXCSR_H_NAKTIMEOUT | MUSB_TXCSR_H_RXSTALL \ + | MUSB_TXCSR_H_ERROR | MUSB_TXCSR_FIFONOTEMPTY) + +/* RXCSR in Peripheral and Host mode */ +#define MUSB_RXCSR_AUTOCLEAR 0x8000 +#define MUSB_RXCSR_DMAENAB 0x2000 +#define MUSB_RXCSR_DISNYET 0x1000 +#define MUSB_RXCSR_PID_ERR 0x1000 +#define MUSB_RXCSR_DMAMODE 0x0800 +#define MUSB_RXCSR_INCOMPRX 0x0100 +#define MUSB_RXCSR_CLRDATATOG 0x0080 +#define MUSB_RXCSR_FLUSHFIFO 0x0010 +#define MUSB_RXCSR_DATAERROR 0x0008 +#define MUSB_RXCSR_FIFOFULL 0x0002 +#define MUSB_RXCSR_RXPKTRDY 0x0001 + +/* RXCSR in Peripheral mode */ +#define MUSB_RXCSR_P_ISO 0x4000 +#define MUSB_RXCSR_P_SENTSTALL 0x0040 +#define MUSB_RXCSR_P_SENDSTALL 0x0020 +#define MUSB_RXCSR_P_OVERRUN 0x0004 + +/* RXCSR in Host mode */ +#define MUSB_RXCSR_H_AUTOREQ 0x4000 +#define MUSB_RXCSR_H_WR_DATATOGGLE 0x0400 +#define MUSB_RXCSR_H_DATATOGGLE 0x0200 +#define MUSB_RXCSR_H_RXSTALL 0x0040 +#define MUSB_RXCSR_H_REQPKT 0x0020 +#define MUSB_RXCSR_H_ERROR 0x0004 +#define MUSB_S_RXCSR_H_DATATOGGLE 9 + +/* RXCSR bits to avoid zeroing (write zero clears, write 1 ignored) */ +#define MUSB_RXCSR_P_WZC_BITS \ + (MUSB_RXCSR_P_SENTSTALL | MUSB_RXCSR_P_OVERRUN \ + | MUSB_RXCSR_RXPKTRDY) +#define MUSB_RXCSR_H_WZC_BITS \ + (MUSB_RXCSR_H_RXSTALL | MUSB_RXCSR_H_ERROR \ + | MUSB_RXCSR_DATAERROR | MUSB_RXCSR_RXPKTRDY) + +/* HUBADDR */ +#define MUSB_HUBADDR_MULTI_TT 0x80 + +/* Endpoint configuration information. Note: The value of endpoint fifo size + * element should be either 8,16,32,64,128,256,512,1024,2048 or 4096. Other + * values are not supported + */ +struct musb_epinfo { + u8 epnum; /* Endpoint number */ + u8 epdir; /* Endpoint direction */ + u16 epsize; /* Endpoint FIFO size */ +}; + +/* exported functions */ +extern void musb_start(void); +extern void musb_configure_ep(struct musb_epinfo *epinfo, u8 cnt); +extern void write_fifo(u8 ep, u32 length, void *fifo_data); +extern void read_fifo(u8 ep, u32 length, void *fifo_data); + +/* extern functions */ +extern inline void musb_writew(u32 offset, u16 value); +extern inline void musb_writeb(u32 offset, u8 value); +extern inline u16 musb_readw(u32 offset); +extern inline u8 musb_readb(u32 offset); + +#endif /* __MUSB_HDRC_DEFS_H__ */ + diff --git a/drivers/usb/musb_hcd.c b/drivers/usb/musb_hcd.c new file mode 100644 index 0000000..ed93075 --- /dev/null +++ b/drivers/usb/musb_hcd.c @@ -0,0 +1,708 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham <at> ti.com, Texas Instruments + */ + +#include <common.h> + +#ifdef CONFIG_MUSB_HCD +#include "musb_hcd.h" + +/* MSC control transfers */ +#define USB_MSC_BBB_RESET 0xFF +#define USB_MSC_BBB_GET_MAX_LUN 0xFE + +/* speed negotiated with the connected device */ +static u8 musb_speed; + +/* Endpoint configuration information */ +static struct musb_epinfo epinfo[2] = { + {MUSB_BULK_EP, 1, 512}, /* EP1 - Bluk Out - 512 Bytes */ + {MUSB_BULK_EP, 0, 512} /* EP1 - Bluk In - 512 Bytes */ +}; + [Bryan]: Davinci will set MUSB_BULK_EP as endpoint 1. While on Blackfin, it should be endpoint 5, 6 or 7, because for endpoint 1, 2, 3, 4, FIFO size is 128, for endpoint 5, 6, 7 FIFO size is 1024. +/* + * This function writes the data toggle value. + */ +static void write_toggle(struct usb_device *dev, u8 ep, u8 dir_out) +{ + u16 toggle = usb_gettoggle(dev, ep, dir_out); + u16 csr; + + if (dir_out) { + if (!toggle) + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + MUSB_TXCSR_CLRDATATOG); + else { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + csr |= MUSB_TXCSR_H_WR_DATATOGGLE; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), csr); + csr |= (toggle << MUSB_TXCSR_H_DATATOGGLE_SHIFT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), csr); + } + } else { + if (!toggle) + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + MUSB_RXCSR_CLRDATATOG); + else { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + csr |= MUSB_RXCSR_H_WR_DATATOGGLE; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), csr); + csr |= (toggle << MUSB_S_RXCSR_H_DATATOGGLE); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), csr); + } + } +} + +/* + * This function checks if RxStall has occured on the endpoint. If a RxStall + * has occured, the RxStall is cleared and 1 is returned. If RxStall has + * not occured, 0 is returned. + */ +static u8 check_stall(u8 ep, u8 dir_out) +{ + u16 csr; + + /* For endpoint 0 */ + if (!ep) { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + if (csr & MUSB_CSR0_H_RXSTALL) { + csr &= ~MUSB_CSR0_H_RXSTALL; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + return 1; + } + } else { /* For non-ep0 */ + if (dir_out) { /* is it tx ep */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + if (csr & MUSB_TXCSR_H_RXSTALL) { + csr &= ~MUSB_TXCSR_H_RXSTALL; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr); + return 1; + } + } else { /* is it rx ep */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + if (csr & MUSB_RXCSR_H_RXSTALL) { + csr &= ~MUSB_RXCSR_H_RXSTALL; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr); + return 1; + } + } + } + return 0; +} + + +/* + * waits until ep0 is ready. Returns 0 if ep is ready, -1 for timeout + * error and -2 for stall. + */ +static int wait_until_ep0_ready(struct usb_device *dev, u32 bit_mask) +{ + u16 csr; + int result = 1; + + while (result > 0) { + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + if (csr & MUSB_CSR0_H_ERROR) { + csr &= ~MUSB_CSR0_H_ERROR; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + dev->status = USB_ST_CRC_ERR; + result = -1; + break; + } + + switch (bit_mask) { + case MUSB_CSR0_TXPKTRDY: + if (!(csr & MUSB_CSR0_TXPKTRDY)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + + case MUSB_CSR0_RXPKTRDY: + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + if (csr & MUSB_CSR0_RXPKTRDY) + result = 0; + break; + + case MUSB_CSR0_H_REQPKT: + if (!(csr & MUSB_CSR0_H_REQPKT)) { + if (check_stall(MUSB_CONTROL_EP, 0)) { + dev->status = USB_ST_STALLED; + result = -2; + } else + result = 0; + } + break; + } + } + return result; +} + +/* + * waits until tx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_txep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 1)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + if (csr & MUSB_TXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (csr & MUSB_TXCSR_TXPKTRDY); + return 1; +} + +/* + * waits until rx ep is ready. Returns 1 when ep is ready and 0 on error. + */ +static u8 wait_until_rxep_ready(struct usb_device *dev, u8 ep) +{ + u16 csr; + + do { + if (check_stall(ep, 0)) { + dev->status = USB_ST_STALLED; + return 0; + } + + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + if (csr & MUSB_RXCSR_H_ERROR) { + dev->status = USB_ST_CRC_ERR; + return 0; + } + } while (!(csr & MUSB_RXCSR_RXPKTRDY)); + return 1; +} + +/* + * This function performs the setup phase of the control transfer + */ +static int ctrlreq_setup_phase(struct usb_device *dev, struct devrequest *setup) +{ + int result; + u16 csr; + + /* write the control request to ep0 fifo */ + write_fifo(MUSB_CONTROL_EP, sizeof(struct devrequest), (void *)setup); + + /* enable transfer of setup packet */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr |= (MUSB_CSR0_TXPKTRDY|MUSB_CSR0_H_SETUPPKT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + + /* wait until the setup packet is transmitted */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + dev->act_len = 0; + return result; +} + +/* + * This function handles the control transfer in data phase + */ +static int ctrlreq_in_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 rxlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *rxbuff = (u8 *)buffer; + u8 rxedlength; + int result; + + while (rxlen < len) { + /* Determine the next read length */ + nextlen = ((len-rxlen) > maxpktsize) ? maxpktsize : (len-rxlen); + + /* Set the ReqPkt bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), + csr | MUSB_CSR0_H_REQPKT); + + result = wait_until_ep0_ready(dev, MUSB_CSR0_RXPKTRDY); + if (result < 0) + return result; + + /* Actual number of bytes received by usb */ + rxedlength = musb_readb(MUSB_INDEXED_OFFSET(MUSB_COUNT0)); + + /* Read the data from the RxFIFO */ + read_fifo(MUSB_CONTROL_EP, rxedlength, &rxbuff[rxlen]); + + /* Clear the RxPktRdy Bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr &= ~MUSB_CSR0_RXPKTRDY; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + + /* short packet? */ + if (rxedlength != nextlen) { + dev->act_len += rxedlength; + break; + } + rxlen += nextlen; + dev->act_len = rxlen; + } + return 0; +} + +/* + * This function handles the control transfer out data phase + */ +static int ctrlreq_out_data_phase(struct usb_device *dev, u32 len, void *buffer) +{ + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 maxpktsize = (1 << dev->maxpacketsize) * 8; + u8 *txbuff = (u8 *)buffer; + int result = 0; + + while (txlen < len) { + /* Determine the next write length */ + nextlen = ((len-txlen) > maxpktsize) ? maxpktsize : (len-txlen); + + /* Load the data to send in FIFO */ + write_fifo(MUSB_CONTROL_EP, txlen, &txbuff[txlen]); + + /* Set TXPKTRDY bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), + csr | MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY); + + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + if (result < 0) + break; + + txlen += nextlen; + dev->act_len = txlen; + } + return result; +} + + +/* + * This function handles the control transfer out status phase + */ +static int ctrlreq_out_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr |= (MUSB_CSR0_H_DIS_PING | MUSB_CSR0_TXPKTRDY | + MUSB_CSR0_H_STATUSPKT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + + /* Wait until TXPKTRDY bit is cleared */ + result = wait_until_ep0_ready(dev, MUSB_CSR0_TXPKTRDY); + return result; +} + + +/* + * This function handles the control transfer in status phase + */ +static int ctrlreq_in_status_phase(struct usb_device *dev) +{ + u16 csr; + int result; + + /* Set the StatusPkt bit and ReqPkt bit */ + csr = MUSB_CSR0_H_DIS_PING | MUSB_CSR0_H_REQPKT | MUSB_CSR0_H_STATUSPKT; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + result = wait_until_ep0_ready(dev, MUSB_CSR0_H_REQPKT); + + /* clear StatusPkt bit and RxPktRdy bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + csr &= ~(MUSB_CSR0_RXPKTRDY | MUSB_CSR0_H_STATUSPKT); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_CSR0), csr); + return result; +} + + +/* + * determines the speed of the device (High/Full/Slow) + */ +static u8 get_dev_speed(struct usb_device *dev) +{ + return (dev->speed & USB_SPEED_HIGH) ? MUSB_TYPE_SPEED_HIGH : + ((dev->speed & USB_SPEED_LOW) ? MUSB_TYPE_SPEED_LOW : + MUSB_TYPE_SPEED_FULL); +} + +/* + * configure the hub address and the port address. + */ +static void config_hub_port(struct usb_device *dev, u8 ep) +{ + u8 chid; + u8 hub; + + /* Find out the nearest parent which is high speed */ + while (dev->parent->parent != NULL) + if (get_dev_speed(dev->parent) != MUSB_TYPE_SPEED_HIGH) + dev = dev->parent; + else + break; + + /* determine the port address at that hub */ + hub = dev->parent->devnum; + for (chid = 0; chid < USB_MAXCHILDREN; chid++) + if (dev->parent->children[chid] == dev) + break; + + /* configure the hub address and the port address */ + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_TXHUBADDR), hub); + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_TXHUBPORT), (chid + 1)); + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_RXHUBADDR), hub); + musb_writeb(MUSB_BUSCTL_OFFSET(ep, MUSB_RXHUBPORT), (chid + 1)); +} [Bryan]: should add #ifdef here. + +/* + * do a control transfer + */ +int submit_control_msg(struct usb_device *dev, unsigned long pipe, void *buffer, + int len, struct devrequest *setup) +{ + int devnum = usb_pipedevice(pipe); + u16 csr; + u8 devspeed; + + /* select control endpoint */ + musb_writeb(MUSB_INDEX, MUSB_CONTROL_EP); + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_CSR0)); + + /* target addr and (for multipoint) hub addr/port */ + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, MUSB_TXFUNCADDR), + devnum); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, MUSB_RXFUNCADDR), + devnum); + [Bryan]: ditto + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + config_hub_port(dev, MUSB_CONTROL_EP); + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_TYPE0), devspeed << 6); + } else { + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_TYPE0), musb_speed << 6); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_TXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_TXHUBPORT), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_RXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_CONTROL_EP, + MUSB_RXHUBPORT), 0); [Bryan]: ditto + } + + /* Control transfer setup phase */ + if (ctrlreq_setup_phase(dev, setup) < 0) + return 0; + + switch (setup->request) { + case USB_REQ_GET_DESCRIPTOR: + case USB_REQ_GET_CONFIGURATION: + case USB_REQ_GET_INTERFACE: + case USB_REQ_GET_STATUS: + case USB_MSC_BBB_GET_MAX_LUN: + /* control transfer in-data-phase */ + if (ctrlreq_in_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer out-status-phase */ + if (ctrlreq_out_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_ADDRESS: + case USB_REQ_SET_CONFIGURATION: + case USB_REQ_SET_FEATURE: + case USB_REQ_SET_INTERFACE: + case USB_REQ_CLEAR_FEATURE: + case USB_MSC_BBB_RESET: + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + case USB_REQ_SET_DESCRIPTOR: + /* control transfer out data phase */ + if (ctrlreq_out_data_phase(dev, len, buffer) < 0) + return 0; + /* control transfer in status phase */ + if (ctrlreq_in_status_phase(dev) < 0) + return 0; + break; + + default: + /* unhandled control transfer */ + return -1; + } + + dev->status = 0; + dev->act_len = len; + return len; +} + +/* + * do a bulk transfer + */ +int submit_bulk_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len) +{ + int dir_out = usb_pipeout(pipe); + int ep = usb_pipeendpoint(pipe); + int devnum = usb_pipedevice(pipe); + u8 type; + u16 csr; + u32 txlen = 0; + u32 nextlen = 0; + u8 devspeed; + + /* select bulk endpoint */ + musb_writeb(MUSB_INDEX, MUSB_BULK_EP); + + /* write the address of the device */ + if (dir_out) + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_TXFUNCADDR), devnum); + else + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_RXFUNCADDR), devnum); + + /* configure the hub address and the port number as required */ + devspeed = get_dev_speed(dev); + if ((musb_ishighspeed()) && (dev->parent != NULL) && + (devspeed != MUSB_TYPE_SPEED_HIGH)) { + /* + * MUSB is in high speed and the destination device is full + * speed device. So configure the hub address and port + * address registers. + */ + config_hub_port(dev, MUSB_BULK_EP); + } else { + if (dir_out) { + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_TXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_TXHUBPORT), 0); + } else { + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_RXHUBADDR), 0); + musb_writeb(MUSB_BUSCTL_OFFSET(MUSB_BULK_EP, + MUSB_RXHUBPORT), 0); + } [Bryan]: ditto + devspeed = musb_speed; + } + + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + if (dir_out) { /* bulk-out transfer */ + /* Program the TxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); [Bryan]: I think this is a bug. It should be (MUSB_BULK_EP & MUSB_TYPE_REMOTE_END); On Blackfin, we will use endpoint 5 instead of endpoint 1 on Davinci. + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_TXTYPE), type); + + /* Write maximum packet size to the TxMaxp register */ + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXMAXP), + dev->epmaxpacketout[ep]); + + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketout[ep]) ? + (len-txlen) : dev->epmaxpacketout[ep]; + [Bryan]: I guess you missed set the TX_COUNT register. IMO, we need it. + /* Write the data to the FIFO */ + write_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Set the TxPktRdy bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_TXCSR), + csr | MUSB_TXCSR_TXPKTRDY); + + /* Wait until the TxPktRdy bit is cleared */ + if (!wait_until_txep_ready(dev, MUSB_BULK_EP)) { + csr = musb_readw( + MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + dev->act_len = txlen; + return 0; + } + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_TXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_TXCSR_H_DATATOGGLE_SHIFT) & 1); + } else { /* bulk-in transfer */ + /* Write the saved toggle bit value */ + write_toggle(dev, ep, dir_out); + + /* Program the RxType register */ + type = (devspeed << MUSB_TYPE_SPEED_SHIFT) | + (MUSB_TYPE_PROTO_BULK << MUSB_TYPE_PROTO_SHIFT) | + (ep & MUSB_TYPE_REMOTE_END); [Bryan]: the same as TX. + musb_writeb(MUSB_INDEXED_OFFSET(MUSB_RXTYPE), type); + + /* Write the maximum packet size to the RxMaxp register */ + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXMAXP), + dev->epmaxpacketin[ep]); + + while (txlen < len) { + nextlen = ((len-txlen) < dev->epmaxpacketin[ep]) ? + (len-txlen) : dev->epmaxpacketin[ep]; + + /* Set the ReqPkt bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + MUSB_RXCSR_H_REQPKT); + + /* Wait until the RxPktRdy bit is set */ + if (!wait_until_rxep_ready(dev, MUSB_BULK_EP)) { + csr = musb_readw( + MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + csr &= ~MUSB_RXCSR_RXPKTRDY; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), + csr); + dev->act_len = txlen; + return 0; + } + [Bryan]: do we need to set RX_COUNT register? + /* Read the data from the FIFO */ + read_fifo(MUSB_BULK_EP, nextlen, + (void *)(((u8 *)buffer) + txlen)); + + /* Clear the RxPktRdy bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + csr &= ~MUSB_RXCSR_RXPKTRDY; + musb_writew(MUSB_INDEXED_OFFSET(MUSB_RXCSR), csr); + txlen += nextlen; + } + + /* Keep a copy of the data toggle bit */ + csr = musb_readw(MUSB_INDEXED_OFFSET(MUSB_RXCSR)); + usb_settoggle(dev, ep, dir_out, + (csr >> MUSB_S_RXCSR_H_DATATOGGLE) & 1); + } + + /* bulk transfer is complete */ + dev->status = 0; + dev->act_len = len; + return 0; +} + +/* + * This function initializes the usb controller module. + */ +int usb_lowlevel_init(void) +{ + u8 power; + u32 timeout; + + if (musb_platform_init() == -1) + return -1; + + /* Configure all the endpoint FIFO's and start usb controller */ + musb_configure_ep(&epinfo[0], + sizeof(epinfo) / sizeof(struct musb_epinfo)); + musb_start(); + + /* + * Wait until musb is enabled in host mode with a timeout. There + * should be a usb device connected. + */ + timeout = MUSB_HCD_TIMEOUT; + while (timeout--) + if (musb_readb(MUSB_DEVCTL) & MUSB_DEVCTL_HM) + break; + + /* if musb core is not in host mode, then return */ + if (!timeout) + return -1; + + /* start usb bus reset */ + power = musb_readb(MUSB_POWER); + musb_writeb(MUSB_POWER, power | MUSB_POWER_RESET); + + /* After initiating a usb reset, wait for about 20ms to 30ms */ + udelay(30000); + + /* stop usb bus reset */ + power = musb_readb(MUSB_POWER); + power &= ~MUSB_POWER_RESET; + musb_writeb(MUSB_POWER, power); + + /* Determine if the connected device is a high/full/low speed device */ + musb_speed = (musb_readb(MUSB_POWER) & MUSB_POWER_HSMODE) ? + MUSB_TYPE_SPEED_HIGH : + ((musb_readb(MUSB_DEVCTL) & MUSB_DEVCTL_FSDEV) ? + MUSB_TYPE_SPEED_FULL : MUSB_TYPE_SPEED_LOW); + return 0; +} + +/* + * This function stops the operation of the davinci usb module. + */ +int usb_lowlevel_stop(void) +{ + /* Reset the USB module */ + musb_platform_deinit(); + musb_writeb(MUSB_DEVCTL, 0); + return 0; +} + +/* + * This function supports usb interrupt transfers. Currently, usb interrupt + * transfers are not supported. + */ +int submit_int_msg(struct usb_device *dev, unsigned long pipe, + void *buffer, int len, int interval) +{ + return -1; +} + +#endif /* CONFIG_MUSB_HCD */ + + + diff --git a/drivers/usb/musb_hcd.h b/drivers/usb/musb_hcd.h new file mode 100644 index 0000000..8ca26e7 --- /dev/null +++ b/drivers/usb/musb_hcd.h @@ -0,0 +1,49 @@ +/* + * Mentor USB OTG Core host controller driver. + * + * Copyright (c) 2008 Texas Instruments + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + * + * Author: Thomas Abraham t-abraham <at> ti.com, Texas Instruments + */ + +#ifndef __MUSB_HCD_H__ +#define __MUSB_HCD_H__ + +#include "musb_core.h" + +/* The controller driver polls for changes in the state. This defines a timeout + for cases where the states do not change so the appropriate error can be + returned. */ +#define MUSB_HCD_TIMEOUT 0x3FFFFFF + +/* This defines the endpoint number used for control transfers */ +#define MUSB_CONTROL_EP 0 + +/* This defines the endpoint number used for bulk transfer */ +#define MUSB_BULK_EP 1 + [Bryan]: we need to set MUSB_BULK_EP to 5 on Blackfin +/* Determine the operating speed of MUSB core */ +#define musb_ishighspeed() \ + ((musb_readb(MUSB_POWER) & MUSB_POWER_HSMODE) \ + >> MUSB_POWER_HSMODE_SHIFT) + +/* extern functions */ +extern int musb_platform_init(void); +extern void musb_platform_deinit(void); + +#endif /* __MUSB_HCD_H__ */ -- 1.5.6

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[U-Boot] ftp area ftp://ftp.denx.de/pub/u-boot/
by Dusek, Richard (Richard)** CTR ** 22 Dec '08

22 Dec '08

Could you tell me why has the name been changed from the u-boot-1.3.4.tar.bz2 type name to u-boot-2008.10.tar.bz2. The build uses the root directory to create the version number, in version_autogenerated.h, and now it is reported as "U-boot 2008.10" instead of the old "U-Boot 1.3.4" Where is this documented. What does it mean. I searched through the CHANGELOG and the readme file and didn't find any mention of this. Thank you. + Rick Dusek 1 Robbins Rd. Westford Ma 01886 Phone: 978-952-1155

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[U-Boot] jffs2_1pass and jffs2_nand_1pass
by Derek Ou 22 Dec '08

22 Dec '08

Hi, all, I am having problem loading jffs2 from NAND with the latest code. After some research, I am getting confused regarding the two files jffs2_1pass.c and jffs2_nand_1pass.c. Some post suggested jffs2_nand_1pass.c to replace jffs2_1pass.c for jffs2_NAND. The git history 08ab4e1780fa63c88dd5a5ab52f4ff4ed1ee1878 seems to be moving away from using the file jffs2_nand_1pass.c. Is this commit incomplete or I should not use the file jffs2_nand_1pass.c at all? Also, I am trying to load jffs2 from NAND with latest code on my at91sam9263ek-based board. I run into the "### ERROR ### Please RESET the board ###" error. Is this a memory space issue? Any suggestion on how to debug? Many thanks. Derek

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[U-Boot] Ask a question about compiler with u-boot?
by peter meng 22 Dec '08

22 Dec '08

Hi, I met a problem that can not use 'bl' instruction invoke the function that implemented it in another file(use assemble or C language) with s3c2412 . But if i put all function in one file , everything is ok .So i want to know what happens here . Hope get your help about this problem ? Thanks advanced . Best Regards. Peter Meng

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[U-Boot] ARM926EJ-S: defining TEXT_BASE
by Roman Mashak 21 Dec '08

21 Dec '08

Hello I have a trouble defining a valid TEXT_BASE value. On my chip, after reset 0x0 and before remap points at NOR flash, RAM is mapped to 0x1000_0000. Therefore, U-Boot image should be linked to 0x0000_0000 address to properly start off the flash, i.e. TEXT_BASE defined in $(uboot)/board/my_board/config.mk should be 0x00000000, right? But uboot usually copies itself to RAM, which is at 0x1000_0000 in my case -- it won't work as I understand, as my image is linked to 0x0000_0000. Then if we do remap first (making RAM at 0x0000_0000), then copy image to RAM, then there will no be a room for 'malloc' area (which uboot allocates at lower addresses), as we specified TEXT_BASE=0x0, and this is the address U-Boot copies itself in memory at. How should I do then? My guess is that ARM's startup code should be position independent, but I have not found any compiler or linker options doing this (like -fpic or -pie etc.). Perhaps I misunderstand something in a work of U-Boot... Thanks. -- Roman Mashak

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[U-Boot] hello
by tessey geb 21 Dec '08

21 Dec '08

hello My name is miss Tessey I saw your profile at www.denx.de and became interested in you, I would also like to know you more, and I want you to send mail to my email address so I can give you my picture for you to know Who l am.Here my e-mail address (tessey300(a)yahoo.com) think that we can move from here.I am waiting for the mail to my email address above.miss Tessey. (Remember the distance or color does not matter but love matters a lot in life) Please rpely me with my email address Here, thanks to have a good day, kiss (tessey300(a)yahoo.com)

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[U-Boot] How to initial the new memory within u-boot ?
by peter meng 20 Dec '08

20 Dec '08

Hi, ALL I'm newbie with u-boot . I use s3c2412 with a Mobile SDR SDRAM (K4M56163PI chip) and copy the process of initial code(memory controler) that other people already used for s3c2412 in u-boot . I can not access the memory after initial it(memory controler) . For testing ,I only wirte a value into memory then read it from same place , but found the return value is always zero . Therefore i think the process of initial is incorrectly . 1. Does anybody has used this memory chip before ? 2. What's configure option i must consider ? 3. Where can find the setup guide of memory chip with u-boot ? Thanks Advanced . Best Regards. Peter Meng

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[U-Boot] TSEC in loop
by Alemao 19 Dec '08

19 Dec '08

Hi all, I have a MPC8343 board and Im doing some hardware validation, trying to use TSEC1 in RGMII 10 Mbps mode. TSEC1 is connected to a FPGA and while wating for the final logic, Im testing a logic that puts TSEC1 in loop, RXD0 -> TXD0, RXD1 -> TXD1, GTX_CLK -> RX_CLK and so on. The following pins are unconnected in my hardware: TSEC1_COL TSEC1_CRS TSEC1_RX_ER TSEC1_TX_ER My registers configuration: RCWH[TSEC1M] = 00 (RGMII) MACCFG2[IF] = 01 (MII) ECNTRL[RPM] = 1 (Reduced) ECNTRL[R100] = 0 (10 Mbps) --------------------------- MACCFG2 = 0x00007105 ECNTRL = 0x00001010 The problem is that when I send a ping, its sends an arp request so I should receive an arp request cause its in loop, but i got the follwing error (TSEC1 is called TSEC0 in u-boot): => ping 192.168.1.1 Speed: 10, full duplex Using TSEC0 device sending ARP for b0100ae3 ARP broadcast 1 Got error 14 ARP broadcast 2 Got error 14 ping failed Error 14 means: - Rx non-octet aligned frame - Rx CRC error And if a change MACCFG2[IF] to 10 (GMII), i got no packets in rx buffer. Is there any other configuration in u-boot that I have to do? Is there a problem using a loop in FPGA? Or a real PHY do some more things to the signal when we put it in loop? PS: FPGA doesnt reply to any mdio commands, so u-boot thinks its a generic phy. Cheers, -- Alemao

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