November 2008 - U-Boot

[U-Boot] new board SDRAM conf
by 조기성 04 Nov '08

04 Nov '08

Hi!, I’m using ppc440Ep and using u-boot1.3.3 I’m using u-boot1.1.3 with Yosemite configuration. When I boot with Yosemite conf , it stops SDRAM:256 , it’ shows cpu, pci conf My New Board configuration is only different SDRAM Size and Flash Size. Where can I modify my Yosemite configuration. Init.S and Yosemite.h Best Regards, J ###### Yosemite Cofiguration ##################### FLASH (CS0) 64MEGA Boot Flash SDRAM bank 0- 128MB bank 1- 128MB !!!###### My Board ##################### FLASH (CS0) 8MEGA Boot Flash SDRAM bank 0- 128MB bank 1- NONE

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[U-Boot] [PATCH] drivers/qe/uec_phy.c: Added PHY-less (fixed PHY) driver.
by Richard Retanubun 04 Nov '08

04 Nov '08

Copied over the fixed PHY driver as used in pp4xx/4xx_enet.c. This adds support for PHY-less MAC connections to the UEC. Signed-off-by: Richard Retanubun <RichardRetanubun(a)RuggedCom.com> --- drivers/qe/uec_phy.c | 79 ++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 79 insertions(+), 0 deletions(-) diff --git a/drivers/qe/uec_phy.c b/drivers/qe/uec_phy.c index 2243d3b..829f082 100644 --- a/drivers/qe/uec_phy.c +++ b/drivers/qe/uec_phy.c @@ -44,6 +44,54 @@ #define ugphy_vdbg(ugeth, fmt, args...) do { } while (0) #endif /* UEC_VERBOSE_DEBUG */ +/*--------------------------------------------------------------------+ + * Fixed PHY (PHY-less) support for Ethernet Ports. + * + * Copied from cpu/ppc4xx/4xx_enet.c + *--------------------------------------------------------------------*/ + +/* + * Some boards do not have a PHY for each ethernet port. These ports + * are known as Fixed PHY (or PHY-less) ports. For such ports, set + * the appropriate CONFIG_PHY_ADDR equal to CONFIG_FIXED_PHY and + * then define CONFIG_SYS_FIXED_PHY_PORTS to define what the speed and + * duplex should be for these ports in the board configuration + * file. + * + * For Example: + * #define CONFIG_FIXED_PHY 0xFFFFFFFF + * + * #define CONFIG_PHY_ADDR CONFIG_FIXED_PHY + * #define CONFIG_PHY1_ADDR 1 + * #define CONFIG_PHY2_ADDR CONFIG_FIXED_PHY + * #define CONFIG_PHY3_ADDR 3 + * + * #define CONFIG_SYS_FIXED_PHY_PORT(devnum,speed,duplex) \ + * {devnum, speed, duplex}, + * + * #define CONFIG_SYS_FIXED_PHY_PORTS \ + * CONFIG_SYS_FIXED_PHY_PORT(0,SPEED_100,DUPLEX_FULL) \ + * CONFIG_SYS_FIXED_PHY_PORT(2,SPEED_100,DUPLEX_HALF) + */ + +#ifndef CONFIG_FIXED_PHY +#define CONFIG_FIXED_PHY 0xFFFFFFFF /* Fixed PHY (PHY-less) */ +#endif + +#ifndef CONFIG_SYS_FIXED_PHY_PORTS +#define CONFIG_SYS_FIXED_PHY_PORTS /* default is an empty array */ +#endif + +struct fixed_phy_port { + unsigned int devnum; /* ethernet port */ + unsigned int speed; /* specified speed 10,100 or 1000 */ + unsigned int duplex; /* specified duplex FULL or HALF */ +}; + +static const struct fixed_phy_port fixed_phy_port[] = { + CONFIG_SYS_FIXED_PHY_PORTS /* defined in board configuration file */ +}; + static void config_genmii_advert (struct uec_mii_info *mii_info); static void genmii_setup_forced (struct uec_mii_info *mii_info); static void genmii_restart_aneg (struct uec_mii_info *mii_info); @@ -533,6 +581,28 @@ static void dm9161_close (struct uec_mii_info *mii_info) { } +static int fixed_phy_aneg (struct uec_mii_info *mii_info) +{ + mii_info->autoneg = 0; /* Turn off auto negotiation for fixed phy */ + return 0; +} + +static int fixed_phy_read_status (struct uec_mii_info *mii_info) +{ + int i = 0; + + for (i = 0; i < ARRAY_SIZE(fixed_phy_port); i++) { + if (mii_info->mii_id == fixed_phy_port[i].devnum) { + mii_info->speed = fixed_phy_port[i].speed; + mii_info->duplex = fixed_phy_port[i].duplex; + mii_info->link = 1; /* Link is always UP */ + mii_info->pause = 0; + break; + } + } + return 0; +} + static struct phy_info phy_info_dm9161 = { .phy_id = 0x0181b880, .phy_id_mask = 0x0ffffff0, @@ -577,6 +647,14 @@ static struct phy_info phy_info_bcm5481 = { .init = bcm_init, }; +static struct phy_info phy_info_fixedphy = { + .phy_id = CONFIG_FIXED_PHY, + .phy_id_mask = CONFIG_FIXED_PHY, + .name = "Fixed PHY", + .config_aneg = fixed_phy_aneg, + .read_status = fixed_phy_read_status, +}; + static struct phy_info phy_info_genmii = { .phy_id = 0x00000000, .phy_id_mask = 0x00000000, @@ -591,6 +669,7 @@ static struct phy_info *phy_info[] = { &phy_info_dm9161a, &phy_info_marvell, &phy_info_bcm5481, + &phy_info_fixedphy, &phy_info_genmii, NULL }; -- 1.5.5.GIT

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[U-Boot] [PATCH v2 5/9] ColdFire: Add mii driver in drivers/net
by Tsi-Chung Liew 04 Nov '08

04 Nov '08

From: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> All CF platforms' mii.c are consolidated into one Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- drivers/net/Makefile | 4 +- drivers/net/mcffec.c | 18 +--- drivers/net/mcfmii.c | 321 ++++++++++++++++++++++++++++++++++++++++++++++++++ 3 files changed, 326 insertions(+), 17 deletions(-) create mode 100644 drivers/net/mcfmii.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 439c354..7e53136 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -35,13 +35,13 @@ COBJS-$(CONFIG_DRIVER_DM9000) += dm9000x.o COBJS-$(CONFIG_E1000) += e1000.o COBJS-$(CONFIG_EEPRO100) += eepro100.o COBJS-$(CONFIG_ENC28J60) += enc28j60.o -COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o +COBJS-$(CONFIG_FSLDMAFEC) += fsl_mcdmafec.o mcfmii.o COBJS-$(CONFIG_GRETH) += greth.o COBJS-$(CONFIG_INCA_IP_SWITCH) += inca-ip_sw.o COBJS-$(CONFIG_DRIVER_KS8695ETH) += ks8695eth.o COBJS-$(CONFIG_DRIVER_LAN91C96) += lan91c96.o COBJS-$(CONFIG_MACB) += macb.o -COBJS-$(CONFIG_MCFFEC) += mcffec.o +COBJS-$(CONFIG_MCFFEC) += mcffec.o mcfmii.o COBJS-$(CONFIG_MPC5xxx_FEC) += mpc5xxx_fec.o COBJS-$(CONFIG_MPC512x_FEC) += mpc512x_fec.o COBJS-$(CONFIG_NATSEMI) += natsemi.o diff --git a/drivers/net/mcffec.c b/drivers/net/mcffec.c index c00474e..18240a8 100644 --- a/drivers/net/mcffec.c +++ b/drivers/net/mcffec.c @@ -27,14 +27,14 @@ #include <common.h> #include <malloc.h> -#include <asm/fec.h> -#include <asm/immap.h> - #include <command.h> #include <net.h> #include <netdev.h> #include <miiphy.h> +#include <asm/fec.h> +#include <asm/immap.h> + #undef ET_DEBUG #undef MII_DEBUG @@ -101,18 +101,6 @@ int fec_init(struct eth_device *dev, bd_t * bd); void fec_halt(struct eth_device *dev); void fec_reset(struct eth_device *dev); -extern int fecpin_setclear(struct eth_device *dev, int setclear); - -#ifdef CONFIG_SYS_DISCOVER_PHY -extern void __mii_init(void); -extern uint mii_send(uint mii_cmd); -extern int mii_discover_phy(struct eth_device *dev); -extern int mcffec_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short *value); -extern int mcffec_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value); -#endif - void setFecDuplexSpeed(volatile fec_t * fecp, bd_t * bd, int dup_spd) { if ((dup_spd >> 16) == FULL) { diff --git a/drivers/net/mcfmii.c b/drivers/net/mcfmii.c new file mode 100644 index 0000000..2b733c6 --- /dev/null +++ b/drivers/net/mcfmii.c @@ -0,0 +1,321 @@ +/* + * Copyright (C) 2004-2008 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <config.h> +#include <net.h> +#include <netdev.h> + +#ifdef CONFIG_MCF547x_8x +#include <asm/fsl_mcdmafec.h> +#else +#include <asm/fec.h> +#endif +#include <asm/immap.h> + +DECLARE_GLOBAL_DATA_PTR; + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#undef MII_DEBUG +#undef ET_DEBUG + +/*extern int fecpin_setclear(struct eth_device *dev, int setclear);*/ + +#if defined(CONFIG_SYS_DISCOVER_PHY) || defined(CONFIG_CMD_MII) +#include <miiphy.h> + +/* Make MII read/write commands for the FEC. */ +#define mk_mii_read(ADDR, REG) (0x60020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18)) +#define mk_mii_write(ADDR, REG, VAL) (0x50020000 | ((ADDR << 23) | \ + (REG & 0x1f) << 18) | (VAL & 0xffff)) + +#ifndef CONFIG_SYS_UNSPEC_PHYID +# define CONFIG_SYS_UNSPEC_PHYID 0 +#endif +#ifndef CONFIG_SYS_UNSPEC_STRID +# define CONFIG_SYS_UNSPEC_STRID 0 +#endif + +#ifdef CONFIG_MCF547x_8x +typedef struct fec_info_dma FEC_INFO_T; +#define FEC_T fecdma_t +#else +typedef struct fec_info_s FEC_INFO_T; +#define FEC_T fec_t +#endif + +typedef struct phy_info_struct { + u32 phyid; + char *strid; +} phy_info_t; + +phy_info_t phyinfo[] = { + {0x0022561B, "AMD79C784VC"}, /* AMD 79C784VC */ + {0x00406322, "BCM5222"}, /* Broadcom 5222 */ + {0x02a80150, "Intel82555"}, /* Intel 82555 */ + {0x0016f870, "LSI80225"}, /* LSI 80225 */ + {0x0016f880, "LSI80225/B"}, /* LSI 80225/B */ + {0x78100000, "LXT970"}, /* LXT970 */ + {0x001378e0, "LXT971"}, /* LXT971 and 972 */ + {0x00221619, "KS8721BL"}, /* Micrel KS8721BL/SL */ + {0x00221512, "KSZ8041NL"}, /* Micrel KSZ8041NL */ + {0x20005CE1, "N83640"}, /* National 83640 */ + {0x20005C90, "N83848"}, /* National 83848 */ + {0x20005CA2, "N83849"}, /* National 83849 */ + {0x01814400, "QS6612"}, /* QS6612 */ +#if defined(CONFIG_SYS_UNSPEC_PHYID) && defined(CONFIG_SYS_UNSPEC_STRID) + {CONFIG_SYS_UNSPEC_PHYID, CONFIG_SYS_UNSPEC_STRID}, +#endif + {0, 0} +}; + +/* + * mii_init -- Initialize the MII for MII command without ethernet + * This function is a subset of eth_init + */ +void mii_reset(FEC_INFO_T *info) +{ + volatile FEC_T *fecp = (FEC_T *) (info->miibase); + int i; + + fecp->ecr = FEC_ECR_RESET; + + for (i = 0; (fecp->ecr & FEC_ECR_RESET) && (i < FEC_RESET_DELAY); ++i) { + udelay(1); + } + if (i == FEC_RESET_DELAY) + printf("FEC_RESET_DELAY timeout\n"); +} + +/* send command to phy using mii, wait for result */ +uint mii_send(uint mii_cmd) +{ + FEC_INFO_T *info; + volatile FEC_T *ep; + struct eth_device *dev; + uint mii_reply; + int j = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + ep = (FEC_T *) info->miibase; + + ep->mmfr = mii_cmd; /* command to phy */ + + /* wait for mii complete */ + while (!(ep->eir & FEC_EIR_MII) && (j < MCFFEC_TOUT_LOOP)) { + udelay(1); + j++; + } + if (j >= MCFFEC_TOUT_LOOP) { + printf("MII not complete\n"); + return -1; + } + + mii_reply = ep->mmfr; /* result from phy */ + ep->eir = FEC_EIR_MII; /* clear MII complete */ +#ifdef ET_DEBUG + printf("%s[%d] %s: sent=0x%8.8x, reply=0x%8.8x\n", + __FILE__, __LINE__, __FUNCTION__, mii_cmd, mii_reply); +#endif + + return (mii_reply & 0xffff); /* data read from phy */ +} +#endif /* CONFIG_SYS_DISCOVER_PHY || (CONFIG_MII) */ + +#if defined(CONFIG_SYS_DISCOVER_PHY) +int mii_discover_phy(struct eth_device *dev) +{ +#define MAX_PHY_PASSES 11 + FEC_INFO_T *info = dev->priv; + int phyaddr, pass; + uint phyno, phytype; + int i, found = 0; + + if (info->phyname_init) + return info->phy_addr; + + phyaddr = -1; /* didn't find a PHY yet */ + for (pass = 1; pass <= MAX_PHY_PASSES && phyaddr < 0; ++pass) { + if (pass > 1) { + /* PHY may need more time to recover from reset. + * The LXT970 needs 50ms typical, no maximum is + * specified, so wait 10ms before try again. + * With 11 passes this gives it 100ms to wake up. + */ + udelay(10000); /* wait 10ms */ + } + + for (phyno = 0; phyno < 32 && phyaddr < 0; ++phyno) { + + phytype = mii_send(mk_mii_read(phyno, PHY_PHYIDR1)); +#ifdef ET_DEBUG + printf("PHY type 0x%x pass %d type\n", phytype, pass); +#endif + if (phytype != 0xffff) { + phyaddr = phyno; + phytype <<= 16; + phytype |= + mii_send(mk_mii_read(phyno, PHY_PHYIDR2)); + +#ifdef ET_DEBUG + printf("PHY @ 0x%x pass %d\n", phyno, pass); +#endif + + for (i = 0; i < (sizeof(phyinfo) / sizeof(phy_info_t)); i++) { + if (phyinfo[i].phyid == phytype) { +#ifdef ET_DEBUG + printf("phyid %x - %s\n", + phyinfo[i].phyid, + phyinfo[i].strid); +#endif + strcpy(info->phy_name, phyinfo[i].strid); + info->phyname_init = 1; + found = 1; + break; + } + } + + if (!found) { +#ifdef ET_DEBUG + printf("0x%08x\n", phytype); +#endif + strcpy(info->phy_name, "unknown"); + info->phyname_init = 1; + break; + } + } + } + } + + if (phyaddr < 0) + printf("No PHY device found.\n"); + + return phyaddr; +} +#endif /* CONFIG_SYS_DISCOVER_PHY */ + +void mii_init(void) __attribute__((weak,alias("__mii_init"))); + +void __mii_init(void) +{ + FEC_INFO_T *info; + volatile FEC_T *fecp; + struct eth_device *dev; + int miispd = 0, i = 0; + u16 autoneg = 0; + + /* retrieve from register structure */ + dev = eth_get_dev(); + info = dev->priv; + + fecp = (FEC_T *) info->miibase; + + fecpin_setclear(dev, 1); + + mii_reset(info); + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set MII speed */ + miispd = (gd->bus_clk / 1000000) / 5; + fecp->mscr = miispd << 1; + + info->phy_addr = mii_discover_phy(dev); + +#define AUTONEGLINK (PHY_BMSR_AUTN_COMP | PHY_BMSR_LS) + while (i < MCFFEC_TOUT_LOOP) { + autoneg = 0; + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &autoneg); + i++; + + if ((autoneg & AUTONEGLINK) == AUTONEGLINK) + break; + + udelay(500); + } + if (i >= MCFFEC_TOUT_LOOP) { + printf("Auto Negotiation not complete\n"); + } + + /* adapt to the half/full speed settings */ + info->dup_spd = miiphy_duplex(dev->name, info->phy_addr) << 16; + info->dup_spd |= miiphy_speed(dev->name, info->phy_addr); +} + +/* + * Read and write a MII PHY register, routines used by MII Utilities + * + * FIXME: These routines are expected to return 0 on success, but mii_send + * does _not_ return an error code. Maybe 0xFFFF means error, i.e. + * no PHY connected... + * For now always return 0. + * FIXME: These routines only work after calling eth_init() at least once! + * Otherwise they hang in mii_send() !!! Sorry! + */ + +int mcffec_miiphy_read(char *devname, unsigned char addr, unsigned char reg, + unsigned short *value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_read(0x%x) @ 0x%x = ", reg, addr); +#endif + rdreg = mii_send(mk_mii_read(addr, reg)); + + *value = rdreg; + +#ifdef MII_DEBUG + printf("0x%04x\n", *value); +#endif + + return 0; +} + +int mcffec_miiphy_write(char *devname, unsigned char addr, unsigned char reg, + unsigned short value) +{ + short rdreg; /* register working value */ + +#ifdef MII_DEBUG + printf("miiphy_write(0x%x) @ 0x%x = ", reg, addr); +#endif + + rdreg = mii_send(mk_mii_write(addr, reg, value)); + +#ifdef MII_DEBUG + printf("0x%04x\n", value); +#endif + + return 0; +} + +#endif /* CONFIG_CMD_NET, FEC_ENET & NET_MULTI */ -- 1.5.6.4

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[U-Boot] [PATCH] sh: Migo-R: Update BSC value
by Nobuhiro Iwamatsu 04 Nov '08

04 Nov '08

A value of BSC CS4 was wrong, Fixed it. Signed-off-by: Nobuhiro Iwamatsu <iwamatsu.nobuhiro(a)renesas.com> --- board/renesas/MigoR/lowlevel_init.S | 32 ++++++++++++++++---------------- 1 files changed, 16 insertions(+), 16 deletions(-) diff --git a/board/renesas/MigoR/lowlevel_init.S b/board/renesas/MigoR/lowlevel_init.S index e48f7b3..4c1900e 100644 --- a/board/renesas/MigoR/lowlevel_init.S +++ b/board/renesas/MigoR/lowlevel_init.S @@ -1,5 +1,5 @@ /* - * Copyright (C) 2007 + * Copyright (C) 2007-2008 * Nobuhiro Iwamatsu <iwamatsu(a)nigauri.org> * * Copyright (C) 2007 @@ -211,25 +211,25 @@ PFC_PULCR_D: .long 0x6000 PFC_DRVCR_D: .long 0x0464 FRQCR_D: .long 0x07033639 PLLCR_D: .long 0x00005000 -DLLFRQ_D: .long 0x000004F6 ! 20080115 +DLLFRQ_D: .long 0x000004F6 CMNCR_A: .long CMNCR -CMNCR_D: .long 0x0000001B ! 20080115 -CS0BCR_A: .long CS0BCR ! Flash bank 1 +CMNCR_D: .long 0x0000001B +CS0BCR_A: .long CS0BCR CS0BCR_D: .long 0x24920400 -CS4BCR_A: .long CS4BCR ! -CS4BCR_D: .long 0x10003400 ! 20080115 -CS5ABCR_A: .long CS5ABCR ! +CS4BCR_A: .long CS4BCR +CS4BCR_D: .long 0x00003400 +CS5ABCR_A: .long CS5ABCR CS5ABCR_D: .long 0x24920400 -CS5BBCR_A: .long CS5BBCR ! +CS5BBCR_A: .long CS5BBCR CS5BBCR_D: .long 0x24920400 -CS6ABCR_A: .long CS6ABCR ! +CS6ABCR_A: .long CS6ABCR CS6ABCR_D: .long 0x24920400 CS0WCR_A: .long CS0WCR CS0WCR_D: .long 0x00000380 CS4WCR_A: .long CS4WCR -CS4WCR_D: .long 0x00100A81 ! 20080115 +CS4WCR_D: .long 0x00110080 CS5AWCR_A: .long CS5AWCR CS5AWCR_D: .long 0x00000300 CS5BWCR_A: .long CS5BWCR @@ -238,20 +238,20 @@ CS6AWCR_A: .long CS6AWCR CS6AWCR_D: .long 0x00000300 SDCR_A: .long SBSC_SDCR -SDCR_D: .long 0x80160809 ! 20080115 +SDCR_D: .long 0x80160809 SDWCR_A: .long SBSC_SDWCR -SDWCR_D: .long 0x0014450C ! 20080115 +SDWCR_D: .long 0x0014450C SDPCR_A: .long SBSC_SDPCR SDPCR_D: .long 0x00000087 RTCOR_A: .long SBSC_RTCOR RTCNT_A: .long SBSC_RTCNT RTCNT_D: .long 0xA55A0012 -RTCOR_D: .long 0xA55A001C ! 20080115 +RTCOR_D: .long 0xA55A001C RTCSR_A: .long SBSC_RTCSR RFCR_A: .long SBSC_RFCR RFCR_D: .long 0xA55A0221 -RTCSR_D: .long 0xA55A009a ! 20080115 -SDMR3_A: .long 0xFE581180 ! 20080115 +RTCSR_D: .long 0xA55A009a +SDMR3_A: .long 0xFE581180 SR_MASK_D: .long 0xEFFFFF0F @@ -260,5 +260,5 @@ SR_MASK_D: .long 0xEFFFFF0F SBSCR_D: .word 0x0044 PSCR_D: .word 0x0000 RWTCSR_D_1: .word 0xA507 -RWTCSR_D_2: .word 0xA504 ! 20080115 +RWTCSR_D_2: .word 0xA504 RWTCNT_D: .word 0x5A00 -- 1.5.6.5

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[U-Boot] [PATCH 09/13 v5] ARM: OMAP3: Add I2C support
by dirk.behme＠googlemail.com 03 Nov '08

03 Nov '08

Subject: [PATCH 09/13 v5] ARM: OMAP3: Add I2C support From: Dirk Behme <dirk.behme(a)gmail.com> Add I2C support Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- Changes in version v5: - Split functional changes and coding style clean up as proposed by Jean-Christophe PLAGNIOL-VILLARD. Changes in version v2: - Remove SMC911X network init as proposed by Ben Warren. Thanks! drivers/i2c/Makefile | 1 + drivers/i2c/omap24xx_i2c.c | 24 ++++++++++++++++++++++++ 2 files changed, 25 insertions(+) Index: u-boot-main/drivers/i2c/Makefile =================================================================== --- u-boot-main.orig/drivers/i2c/Makefile +++ u-boot-main/drivers/i2c/Makefile @@ -29,6 +29,7 @@ COBJS-$(CONFIG_FSL_I2C) += fsl_i2c.o COBJS-$(CONFIG_I2C_MXC) += mxc_i2c.o COBJS-$(CONFIG_DRIVER_OMAP1510_I2C) += omap1510_i2c.o COBJS-$(CONFIG_DRIVER_OMAP24XX_I2C) += omap24xx_i2c.o +COBJS-$(CONFIG_DRIVER_OMAP34XX_I2C) += omap24xx_i2c.o COBJS-$(CONFIG_SOFT_I2C) += soft_i2c.o COBJS-$(CONFIG_TSI108_I2C) += tsi108_i2c.o Index: u-boot-main/drivers/i2c/omap24xx_i2c.c =================================================================== --- u-boot-main.orig/drivers/i2c/omap24xx_i2c.c +++ u-boot-main/drivers/i2c/omap24xx_i2c.c @@ -25,6 +25,8 @@ #include <asm/arch/i2c.h> #include <asm/io.h> +#define inb(a) __raw_readb(a) +#define outb(a, v) __raw_writeb(a, v) #define inw(a) __raw_readw(a) #define outw(a,v) __raw_writew(a,v) @@ -112,7 +114,11 @@ static int i2c_read_byte (u8 devaddr, u8 status = wait_for_pin (); if (status & I2C_STAT_RRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + *value = inb(I2C_DATA); +#else *value = inw (I2C_DATA); +#endif udelay (20000); } else { i2c_error = 1; @@ -153,8 +159,22 @@ static int i2c_write_byte (u8 devaddr, u status = wait_for_pin (); if (status & I2C_STAT_XRDY) { +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + /* send out 1 byte */ + outb(regoffset, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + status = wait_for_pin(); + if ((status & I2C_STAT_XRDY)) { + /* send out next 1 byte */ + outb(value, I2C_DATA); + outw(I2C_STAT_XRDY, I2C_STAT); + } else { + i2c_error = 1; + } +#else /* send out two bytes */ outw ((value << 8) + regoffset, I2C_DATA); +#endif /* must have enough delay to allow BB bit to go low */ udelay (50000); if (inw (I2C_STAT) & I2C_STAT_NACK) { @@ -191,7 +211,11 @@ static void flush_fifo(void) while(1){ stat = inw(I2C_STAT); if(stat == I2C_STAT_RRDY){ +#if defined(CONFIG_OMAP243X) || defined(CONFIG_OMAP34XX) + inb(I2C_DATA); +#else inw(I2C_DATA); +#endif outw(I2C_STAT_RRDY,I2C_STAT); udelay(1000); }else

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[U-Boot] [PATCH V2] powerpc: change 86xx SMP boot method
by Becky Bruce 03 Nov '08

03 Nov '08

We put the bootpg for the secondary cpus into memory and use BPTR to get to it. This is a step towards converting to the ePAPR boot methodology. Also, the code is written to deal properly with more than 4GB of RAM. Signed-off-by: Becky Bruce <becky.bruce(a)freescale.com> --- cpu/mpc86xx/Makefile | 4 + cpu/mpc86xx/cpu_init.c | 4 + cpu/mpc86xx/fdt.c | 21 +++++ cpu/mpc86xx/mp.c | 68 ++++++++++++++++ cpu/mpc86xx/mp.h | 7 ++ cpu/mpc86xx/release.S | 169 +++++++++++++++++++++++++++++++++++++++++ cpu/mpc86xx/start.S | 77 +------------------ include/configs/MPC8610HPCD.h | 7 ++ include/configs/MPC8641HPCN.h | 7 ++ include/configs/sbc8641d.h | 7 ++ 10 files changed, 298 insertions(+), 73 deletions(-) create mode 100644 cpu/mpc86xx/mp.c create mode 100644 cpu/mpc86xx/mp.h create mode 100644 cpu/mpc86xx/release.S diff --git a/cpu/mpc86xx/Makefile b/cpu/mpc86xx/Makefile index a9767ad..34a9755 100644 --- a/cpu/mpc86xx/Makefile +++ b/cpu/mpc86xx/Makefile @@ -31,6 +31,10 @@ LIB = $(obj)lib$(CPU).a START = start.o SOBJS = cache.o +ifneq ($(CONFIG_NUM_CPUS),1) +COBJS-y += mp.o +SOBJS += release.o +endif COBJS-y += traps.o COBJS-y += cpu.o COBJS-y += cpu_init.o diff --git a/cpu/mpc86xx/cpu_init.c b/cpu/mpc86xx/cpu_init.c index 4ab88f0..06f179c 100644 --- a/cpu/mpc86xx/cpu_init.c +++ b/cpu/mpc86xx/cpu_init.c @@ -31,6 +31,7 @@ #include <mpc86xx.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include "mp.h" DECLARE_GLOBAL_DATA_PTR; @@ -121,6 +122,9 @@ void cpu_init_f(void) */ int cpu_init_r(void) { +#if (CONFIG_NUM_CPUS > 1) + setup_mp(); +#endif return 0; } diff --git a/cpu/mpc86xx/fdt.c b/cpu/mpc86xx/fdt.c index 1fef94f..3adfad9 100644 --- a/cpu/mpc86xx/fdt.c +++ b/cpu/mpc86xx/fdt.c @@ -9,9 +9,17 @@ #include <common.h> #include <libfdt.h> #include <fdt_support.h> +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; void ft_cpu_setup(void *blob, bd_t *bd) { +#if (CONFIG_NUM_CPUS > 1) + int off; + u32 bootpg; +#endif + do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, "timebase-frequency", bd->bi_busfreq / 4, 1); do_fixup_by_prop_u32(blob, "device_type", "cpu", 4, @@ -32,4 +40,17 @@ void ft_cpu_setup(void *blob, bd_t *bd) do_fixup_by_compat_u32(blob, "ns16550", "clock-frequency", CONFIG_SYS_NS16550_CLK, 1); #endif + +#if (CONFIG_NUM_CPUS > 1) + /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ + if (gd->ram_size > 0xfffff000) + bootpg = 0xfff00000; + else + bootpg = gd->ram_size - (1024 * 1024); + + /* Reserve the boot page so OSes dont use it */ + off = fdt_add_mem_rsv(blob, bootpg, (u64)4096); + if (off < 0) + printf("%s: %s\n", __FUNCTION__, fdt_strerror(off)); +#endif } diff --git a/cpu/mpc86xx/mp.c b/cpu/mpc86xx/mp.c new file mode 100644 index 0000000..5014401 --- /dev/null +++ b/cpu/mpc86xx/mp.c @@ -0,0 +1,68 @@ +#include <common.h> +#include <asm/processor.h> +#include <asm/mmu.h> +#include <ioports.h> +#include <lmb.h> +#include <asm/io.h> +#include "mp.h" + +DECLARE_GLOBAL_DATA_PTR; + +#if (CONFIG_NUM_CPUS > 1) +void cpu_mp_lmb_reserve(struct lmb *lmb) +{ + u32 bootpg; + + /* if we have 4G or more of memory, put the boot page at 4Gb-1M */ + if ((u64)gd->ram_size > 0xfffff000) + bootpg = 0xfff00000; + else + bootpg = gd->ram_size - (1024 * 1024); + + /* tell u-boot we stole a page */ + lmb_reserve(lmb, bootpg, 4096); +} + +/* + * Copy the code for other cpus to execute into an + * aligned location accessible via BPTR + */ +void setup_mp(void) +{ + extern ulong __secondary_start_page; + ulong fixup = (ulong)&__secondary_start_page; + u32 bootpg; + u32 bootpg_va; + + /* + * If we have 4G or more of memory, put the boot page at 4Gb-1M. + * Otherwise, put it at the very end of RAM. + */ + if (gd->ram_size > 0xfffff000) + bootpg = 0xfff00000; + else + bootpg = gd->ram_size - (1024 * 1024); + + if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) { + /* We're not covered by the DDR mapping, set up BAT */ + write_bat(DBAT7, CONFIG_SYS_SCRATCH_VA | BATU_BL_128K | + BATU_VS | BATU_VP, + bootpg | BATL_PP_RW | BATL_MEMCOHERENCE); + bootpg_va = CONFIG_SYS_SCRATCH_VA; + } else { + bootpg_va = bootpg; + } + + memcpy((void *)bootpg_va, (void *)fixup, 4096); + flush_cache(bootpg_va, 4096); + + /* remove the temporary BAT mapping */ + if (bootpg >= CONFIG_SYS_MAX_DDR_BAT_SIZE) + write_bat(DBAT7, 0, 0); + + /* If the physical location of bootpg is not at fff00000, set BPTR */ + if (bootpg != 0xfff00000) + out_be32((uint *)(CONFIG_SYS_CCSRBAR + 0x20), 0x80000000 | + (bootpg >> 12)); +} +#endif diff --git a/cpu/mpc86xx/mp.h b/cpu/mpc86xx/mp.h new file mode 100644 index 0000000..886e0c8 --- /dev/null +++ b/cpu/mpc86xx/mp.h @@ -0,0 +1,7 @@ +#ifndef __MPC86XX_MP_H_ +#define __MPC86XX_MP_H_ + +void setup_mp(void); +void cpu_mp_lmb_reserve(struct lmb *lmb); + +#endif diff --git a/cpu/mpc86xx/release.S b/cpu/mpc86xx/release.S new file mode 100644 index 0000000..b524e50 --- /dev/null +++ b/cpu/mpc86xx/release.S @@ -0,0 +1,169 @@ +/* + * Copyright 2004, 2007, 2008 Freescale Semiconductor. + * Srikanth Srinivasan <srikanth.srinivaan(a)freescale.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ +#include <config.h> +#include <mpc86xx.h> +#include <version.h> + +#include <ppc_asm.tmpl> +#include <ppc_defs.h> + +#include <asm/cache.h> +#include <asm/mmu.h> + +/* If this is a multi-cpu system then we need to handle the + * 2nd cpu. The assumption is that the 2nd cpu is being + * held in boot holdoff mode until the 1st cpu unlocks it + * from Linux. We'll do some basic cpu init and then pass + * it to the Linux Reset Vector. + * Sri: Much of this initialization is not required. Linux + * rewrites the bats, and the sprs and also enables the L1 cache. + * + * Core 0 must copy this to a 1M aligned region and set BPTR + * to point to it. + */ +#if (CONFIG_NUM_CPUS > 1) + .align 12 +.globl __secondary_start_page +__secondary_start_page: + .space 0x100 /* space over to reset vector loc */ + mfspr r0, MSSCR0 + andi. r0, r0, 0x0020 + rlwinm r0,r0,27,31,31 + mtspr PIR, r0 + + /* Invalidate BATs */ + li r0, 0 + mtspr IBAT0U, r0 + mtspr IBAT1U, r0 + mtspr IBAT2U, r0 + mtspr IBAT3U, r0 + mtspr IBAT4U, r0 + mtspr IBAT5U, r0 + mtspr IBAT6U, r0 + mtspr IBAT7U, r0 + isync + mtspr DBAT0U, r0 + mtspr DBAT1U, r0 + mtspr DBAT2U, r0 + mtspr DBAT3U, r0 + mtspr DBAT4U, r0 + mtspr DBAT5U, r0 + mtspr DBAT6U, r0 + mtspr DBAT7U, r0 + isync + sync + + /* enable extended addressing */ + mfspr r0, HID0 + lis r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@h + ori r0, r0, (HID0_HIGH_BAT_EN | HID0_XBSEN | HID0_XAEN)@l + mtspr HID0, r0 + sync + isync + +#ifdef CONFIG_SYS_L2 + /* init the L2 cache */ + addis r3, r0, L2_INIT@h + ori r3, r3, L2_INIT@l + sync + mtspr l2cr, r3 +#ifdef CONFIG_ALTIVEC + dssall +#endif + /* invalidate the L2 cache */ + mfspr r3, l2cr + rlwinm. r3, r3, 0, 0, 0 + beq 1f + + mfspr r3, l2cr + rlwinm r3, r3, 0, 1, 31 + +#ifdef CONFIG_ALTIVEC + dssall +#endif + sync + mtspr l2cr, r3 + sync +1: mfspr r3, l2cr + oris r3, r3, L2CR_L2I@h + mtspr l2cr, r3 + +invl2: + mfspr r3, l2cr + andis. r3, r3, L2CR_L2I@h + bne invl2 + sync +#endif + + /* enable and invalidate the data cache */ + mfspr r3, HID0 + li r5, HID0_DCFI|HID0_DLOCK + andc r3, r3, r5 + mtspr HID0, r3 /* no invalidate, unlock */ + ori r3, r3, HID0_DCE + ori r5, r3, HID0_DCFI + mtspr HID0, r5 /* enable + invalidate */ + mtspr HID0, r3 /* enable */ + sync +#ifdef CFG_L2 + sync + lis r3, L2_ENABLE@h + ori r3, r3, L2_ENABLE@l + mtspr l2cr, r3 + isync + sync +#endif + + /* enable and invalidate the instruction cache*/ + mfspr r3, HID0 + li r5, HID0_ICFI|HID0_ILOCK + andc r3, r3, r5 + ori r3, r3, HID0_ICE + ori r5, r3, HID0_ICFI + mtspr HID0, r5 + mtspr HID0, r3 + isync + sync + + /* TBEN in HID0 */ + mfspr r4, HID0 + oris r4, r4, 0x0400 + mtspr HID0, r4 + sync + isync + + /* MCP|SYNCBE|ABE in HID1 */ + mfspr r4, HID1 + oris r4, r4, 0x8000 + ori r4, r4, 0x0C00 + mtspr HID1, r4 + sync + isync + + lis r3, CONFIG_LINUX_RESET_VEC@h + ori r3, r3, CONFIG_LINUX_RESET_VEC@l + mtlr r3 + blr + + /* Never Returns, Running in Linux Now */ +#endif diff --git a/cpu/mpc86xx/start.S b/cpu/mpc86xx/start.S index b1a23b4..48f8c5a 100644 --- a/cpu/mpc86xx/start.S +++ b/cpu/mpc86xx/start.S @@ -179,20 +179,10 @@ _end_of_vectors: boot_cold: boot_warm: - - /* if this is a multi-core system we need to check which cpu - * this is, if it is not cpu 0 send the cpu to the linux reset - * vector */ -#if (CONFIG_NUM_CPUS > 1) - mfspr r0, MSSCR0 - andi. r0, r0, 0x0020 - rlwinm r0,r0,27,31,31 - mtspr PIR, r0 - beq 1f - - bl secondary_cpu_setup -#endif - + /* + * NOTE: Only Cpu 0 will ever come here. Other cores go to an + * address specified by the BPTR + */ 1: #ifdef CONFIG_SYS_RAMBOOT /* disable everything */ @@ -978,63 +968,4 @@ unlock_ram_in_cache: #endif #endif -/* If this is a multi-cpu system then we need to handle the - * 2nd cpu. The assumption is that the 2nd cpu is being - * held in boot holdoff mode until the 1st cpu unlocks it - * from Linux. We'll do some basic cpu init and then pass - * it to the Linux Reset Vector. - * Sri: Much of this initialization is not required. Linux - * rewrites the bats, and the sprs and also enables the L1 cache. - */ -#if (CONFIG_NUM_CPUS > 1) -.globl secondary_cpu_setup -secondary_cpu_setup: - /* Do only core setup on all cores except cpu0 */ - bl invalidate_bats - sync - bl enable_ext_addr -#ifdef CONFIG_SYS_L2 - /* init the L2 cache */ - addis r3, r0, L2_INIT@h - ori r3, r3, L2_INIT@l - sync - mtspr l2cr, r3 -#ifdef CONFIG_ALTIVEC - dssall -#endif - /* invalidate the L2 cache */ - bl l2cache_invalidate - sync -#endif - - /* enable and invalidate the data cache */ - bl dcache_enable - sync - - /* enable and invalidate the instruction cache*/ - bl icache_enable - sync - - /* TBEN in HID0 */ - mfspr r4, HID0 - oris r4, r4, 0x0400 - mtspr HID0, r4 - sync - isync - - /* MCP|SYNCBE|ABE in HID1 */ - mfspr r4, HID1 - oris r4, r4, 0x8000 - ori r4, r4, 0x0C00 - mtspr HID1, r4 - sync - isync - - lis r3, CONFIG_LINUX_RESET_VEC@h - ori r3, r3, CONFIG_LINUX_RESET_VEC@l - mtlr r3 - blr - - /* Never Returns, Running in Linux Now */ -#endif diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index 6f04127..4486763 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -36,6 +36,12 @@ #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xc0000000 + #define CONFIG_PCI 1 /* Enable PCI/PCIE*/ #define CONFIG_PCI1 1 /* PCI controler 1 */ #define CONFIG_PCIE1 1 /* PCIe 1 connected to ULI bridge */ @@ -92,6 +98,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index ad5627f..0dd2156 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -46,6 +46,12 @@ #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 /* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe0000000 + +/* * set this to enable Rapid IO. PCI and RIO are mutually exclusive */ /*#define CONFIG_RIO 1*/ @@ -109,6 +115,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory*/ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL diff --git a/include/configs/sbc8641d.h b/include/configs/sbc8641d.h index 09a9901..e8216ea 100644 --- a/include/configs/sbc8641d.h +++ b/include/configs/sbc8641d.h @@ -49,6 +49,12 @@ #define CONFIG_SYS_RESET_ADDRESS 0xfff00100 +/* + * virtual address to be used for temporary mappings. There + * should be 128k free at this VA. + */ +#define CONFIG_SYS_SCRATCH_VA 0xe8000000 + #define CONFIG_PCI 1 /* Enable PCIE */ #define CONFIG_PCI1 1 /* PCIE controler 1 (slot 1) */ #define CONFIG_PCI2 1 /* PCIE controler 2 (slot 2) */ @@ -108,6 +114,7 @@ #define CONFIG_SYS_DDR_SDRAM_BASE2 0x10000000 /* DDR bank 2 */ #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #define CONFIG_SYS_SDRAM_BASE2 CONFIG_SYS_DDR_SDRAM_BASE2 +#define CONFIG_SYS_MAX_DDR_BAT_SIZE 0x80000000 /* BAT mapping size */ #define CONFIG_VERY_BIG_RAM #define MPC86xx_DDR_SDRAM_CLK_CNTL -- 1.5.5.1

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[U-Boot] [PATCH 2/4]v2: Add vxworks.h to handle CONFIG_SYS_VXWORKS parameters
by Niklaus Giger 03 Nov '08

03 Nov '08

Signed-off-by: Niklaus Giger <niklaus.giger(a)member.fsf.org> --- include/vxworks.h | 53 +++++++++++++++++++++++++++++++++++++++++++++++++++++ 1 files changed, 53 insertions(+), 0 deletions(-) create mode 100644 include/vxworks.h diff --git a/include/vxworks.h b/include/vxworks.h new file mode 100644 index 0000000..548e8e8 --- /dev/null +++ b/include/vxworks.h @@ -0,0 +1,53 @@ +/* + * (C) Copyright 2008 + * Niklaus Giger, niklaus.giger(a)member.fsf.org + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _VXWORKS_H_ +#define _VXWORKS_H_ + +int do_bootvx(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]); + +/* + * Use bootaddr to find the location in memory that VxWorks + * will look for the bootline string. The default value for + * PowerPC is LOCAL_MEM_LOCAL_ADRS + BOOT_LINE_OFFSET which + * defaults to 0x4200 + */ +#ifndef CONFIG_SYS_VXWORKS_BOOT_ADDR +#define CONFIG_SYS_VXWORKS_BOOT_ADDR 0x4200 +#endif + +#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE +#if defined(CONFIG_4xx) +#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)" +#elif defined(CONFIG_IOP480) +#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)" +#else +#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)" +#endif +#endif + +#ifndef CONFIG_SYS_VXWORKS_SERVERNAME +#define CONFIG_SYS_VXWORKS_SERVERNAME srv +#endif + +#endif -- 1.6.0.2

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[U-Boot] [PATCH 03/13 v5] ARM: OMAP3: Add ARM Cortex A8 common directory
by dirk.behme＠googlemail.com 03 Nov '08

03 Nov '08

From: Dirk Behme <dirk.behme(a)gmail.com> Add ARM Cortex A8 common directory Signed-off-by: Dirk Behme <dirk.behme(a)gmail.com> --- cpu/arm_cortexa8/Makefile | 47 ++++ cpu/arm_cortexa8/config.mk | 36 +++ cpu/arm_cortexa8/cpu.c | 238 ++++++++++++++++++++ cpu/arm_cortexa8/start.S | 516 +++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 837 insertions(+) Index: u-boot-main/cpu/arm_cortexa8/cpu.c =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/cpu.c @@ -0,0 +1,238 @@ +/* + * (C) Copyright 2008 Texas Insturments + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * (C) Copyright 2002 + * Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * CPU specific code + */ + +#include <common.h> +#include <command.h> +#include <asm/arch/sys_proto.h> + +#ifdef CONFIG_USE_IRQ +DECLARE_GLOBAL_DATA_PTR; +#endif + +#ifndef CONFIG_L2_OFF +void l2cache_disable(void); +#endif + +static void cache_flush(void); + +/* read co-processor 15, register #1 (control register) */ +static unsigned long read_p15_c1(void) +{ + unsigned long value; + + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 0\ + @ read control reg\n":"=r"(value) + ::"memory"); + return value; +} + +/* write to co-processor 15, register #1 (control register) */ +static void write_p15_c1(unsigned long value) +{ + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 0\ + @ write it back\n"::"r"(value) + : "memory"); + + read_p15_c1(); +} + +static void cp_delay(void) +{ + volatile int i; + + /* Many OMAP regs need at least 2 nops */ + for (i = 0; i < 100; i++) ; +} + +/* See also ARM Ref. Man. */ +#define C1_MMU (1<<0) /* mmu off/on */ +#define C1_ALIGN (1<<1) /* alignment faults off/on */ +#define C1_DC (1<<2) /* dcache off/on */ +#define C1_WB (1<<3) /* merging write buffer on/off */ +#define C1_BIG_ENDIAN (1<<7) /* big endian off/on */ +#define C1_SYS_PROT (1<<8) /* system protection */ +#define C1_ROM_PROT (1<<9) /* ROM protection */ +#define C1_IC (1<<12) /* icache off/on */ +#define C1_HIGH_VECTORS (1<<13) /* location of vectors: low/high addresses */ +#define RESERVED_1 (0xf << 3) /* must be 111b for R/W */ + +int cpu_init(void) +{ + /* + * setup up stacks if necessary + */ +#ifdef CONFIG_USE_IRQ + IRQ_STACK_START = + _armboot_start - CONFIG_SYS_MALLOC_LEN - CONFIG_SYS_GBL_DATA_SIZE - 4; + FIQ_STACK_START = IRQ_STACK_START - CONFIG_STACKSIZE_IRQ; +#endif + return 0; +} + +int cleanup_before_linux(void) +{ + unsigned int i; + + /* + * this function is called just before we call linux + * it prepares the processor for linux + * + * we turn off caches etc ... + */ + disable_interrupts(); + + /* turn off I/D-cache */ + icache_disable(); + dcache_disable(); + + /* invalidate I-cache */ + cache_flush(); + +#ifndef CONFIG_L2_OFF + /* turn off L2 cache */ + l2cache_disable(); + /* invalidate L2 cache also */ + v7_flush_dcache_all(get_device_type()); +#endif + i = 0; + /* mem barrier to sync up things */ + asm("mcr p15, 0, %0, c7, c10, 4": :"r"(i)); + +#ifndef CONFIG_L2_OFF + l2cache_enable(); +#endif + + return 0; +} + +int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) +{ + disable_interrupts(); + reset_cpu(0); + + /* NOTREACHED */ + return 0; +} + +void icache_enable(void) +{ + ulong reg; + + reg = read_p15_c1(); /* get control reg. */ + cp_delay(); + write_p15_c1(reg | C1_IC); +} + +void icache_disable(void) +{ + ulong reg; + + reg = read_p15_c1(); + cp_delay(); + write_p15_c1(reg & ~C1_IC); +} + +void dcache_disable (void) +{ + ulong reg; + + reg = read_p15_c1 (); + cp_delay (); + write_p15_c1 (reg & ~C1_DC); +} + +void l2cache_enable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() == CPU_3430_ES2) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("orr %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* GP Device ROM code API usage here */ + /* r12 = AUXCR Write function and r0 value */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("orr r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } + +} + +void l2cache_disable() +{ + unsigned long i; + volatile unsigned int j; + + /* ES2 onwards we can disable/enable L2 ourselves */ + if (get_cpu_rev() == CPU_3430_ES2) { + __asm__ __volatile__("mrc p15, 0, %0, c1, c0, 1":"=r"(i)); + __asm__ __volatile__("bic %0, %0, #0x2":"=r"(i)); + __asm__ __volatile__("mcr p15, 0, %0, c1, c0, 1":"=r"(i)); + } else { + /* Save r0, r12 and restore them after usage */ + __asm__ __volatile__("mov %0, r12":"=r"(j)); + __asm__ __volatile__("mov %0, r0":"=r"(i)); + + /* GP Device ROM code API usage here */ + /* r12 = AUXCR Write function and r0 value */ + __asm__ __volatile__("mov r12, #0x3"); + __asm__ __volatile__("mrc p15, 0, r0, c1, c0, 1"); + __asm__ __volatile__("bic r0, r0, #0x2"); + /* SMI instruction to call ROM Code API */ + __asm__ __volatile__(".word 0xE1600070"); + __asm__ __volatile__("mov r0, %0":"=r"(i)); + __asm__ __volatile__("mov r12, %0":"=r"(j)); + } +} + +int icache_status(void) +{ + return (read_p15_c1() & C1_IC) != 0; +} + +static void cache_flush(void) +{ + asm ("mcr p15, 0, %0, c7, c5, 0": :"r" (0)); +} + Index: u-boot-main/cpu/arm_cortexa8/Makefile =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/Makefile @@ -0,0 +1,47 @@ +# +# (C) Copyright 2000-2003 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(CPU).a + +START := start.o +COBJS := cpu.o + +SRCS := $(START:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +START := $(addprefix $(obj),$(START)) + +all: $(obj).depend $(START) $(LIB) + +$(LIB): $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### \ No newline at end of file Index: u-boot-main/cpu/arm_cortexa8/config.mk =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/config.mk @@ -0,0 +1,36 @@ +# +# (C) Copyright 2002 +# Gary Jennejohn, DENX Software Engineering, <gj(a)denx.de> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# +PLATFORM_RELFLAGS += -fno-strict-aliasing -fno-common -ffixed-r8 \ + -msoft-float + +# Make ARMv5 to allow more compilers to work, even though its v7a. +PLATFORM_CPPFLAGS += -march=armv5 +# ========================================================================= +# +# Supply options according to compiler version +# +# ========================================================================= +PLATFORM_CPPFLAGS +=$(call cc-option) +PLATFORM_CPPFLAGS +=$(call cc-option,-mno-thumb-interwork,) +PLATFORM_RELFLAGS +=$(call cc-option,-mshort-load-bytes,\ + $(call cc-option,-malignment-traps,)) \ No newline at end of file Index: u-boot-main/cpu/arm_cortexa8/start.S =================================================================== --- /dev/null +++ u-boot-main/cpu/arm_cortexa8/start.S @@ -0,0 +1,516 @@ +/* + * armboot - Startup Code for OMAP3530/ARM Cortex CPU-core + * + * Copyright (c) 2004 Texas Instruments <r-woodruff2(a)ti.com> + * + * Copyright (c) 2001 Marius Gröger <mag(a)sysgo.de> + * Copyright (c) 2002 Alex Züpke <azu(a)sysgo.de> + * Copyright (c) 2002 Gary Jennejohn <gj(a)denx.de> + * Copyright (c) 2003 Richard Woodruff <r-woodruff2(a)ti.com> + * Copyright (c) 2003 Kshitij <kshitij(a)ti.com> + * Copyright (c) 2006-2008 Syed Mohammed Khasim <x0khasim(a)ti.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <config.h> +#include <version.h> + +.globl _start +_start: b reset + ldr pc, _undefined_instruction + ldr pc, _software_interrupt + ldr pc, _prefetch_abort + ldr pc, _data_abort + ldr pc, _not_used + ldr pc, _irq + ldr pc, _fiq + +_undefined_instruction: .word undefined_instruction +_software_interrupt: .word software_interrupt +_prefetch_abort: .word prefetch_abort +_data_abort: .word data_abort +_not_used: .word not_used +_irq: .word irq +_fiq: .word fiq +_pad: .word 0x12345678 /* now 16*4=64 */ +.global _end_vect +_end_vect: + + .balignl 16,0xdeadbeef +/************************************************************************* + * + * Startup Code (reset vector) + * + * do important init only if we don't start from memory! + * setup Memory and board specific bits prior to relocation. + * relocate armboot to ram + * setup stack + * + *************************************************************************/ + +_TEXT_BASE: + .word TEXT_BASE + +.globl _armboot_start +_armboot_start: + .word _start + +/* + * These are defined in the board-specific linker script. + */ +.globl _bss_start +_bss_start: + .word __bss_start + +.globl _bss_end +_bss_end: + .word _end + +#ifdef CONFIG_USE_IRQ +/* IRQ stack memory (calculated at run-time) */ +.globl IRQ_STACK_START +IRQ_STACK_START: + .word 0x0badc0de + +/* IRQ stack memory (calculated at run-time) */ +.globl FIQ_STACK_START +FIQ_STACK_START: + .word 0x0badc0de +#endif + +/* + * the actual reset code + */ + +reset: + /* + * set the cpu to SVC32 mode + */ + mrs r0, cpsr + bic r0, r0, #0x1f + orr r0, r0, #0xd3 + msr cpsr,r0 + +#if (CONFIG_OMAP34XX) + /* Copy vectors to mask ROM indirect addr */ + adr r0, _start @ r0 <- current position of code + add r0, r0, #4 @ skip reset vector + mov r2, #64 @ r2 <- size to copy + add r2, r0, r2 @ r2 <- source end address + mov r1, #SRAM_OFFSET0 @ build vect addr + mov r3, #SRAM_OFFSET1 + add r1, r1, r3 + mov r3, #SRAM_OFFSET2 + add r1, r1, r3 +next: + ldmia r0!, {r3 - r10} @ copy from source address [r0] + stmia r1!, {r3 - r10} @ copy to target address [r1] + cmp r0, r2 @ until source end address [r2] + bne next @ loop until equal */ +#if !defined(CONFIG_SYS_NAND_BOOT) && !defined(CONFIG_SYS_ONENAND_BOOT) + /* No need to copy/exec the clock code - DPLL adjust already done + * in NAND/oneNAND Boot. + */ + bl cpy_clk_code @ put dpll adjust code behind vectors +#endif /* NAND Boot */ +#endif + /* the mask ROM code should have PLL and others stable */ +#ifndef CONFIG_SKIP_LOWLEVEL_INIT + bl cpu_init_crit +#endif + +#ifndef CONFIG_SKIP_RELOCATE_UBOOT +relocate: @ relocate U-Boot to RAM + adr r0, _start @ r0 <- current position of code + ldr r1, _TEXT_BASE @ test if we run from flash or RAM + cmp r0, r1 @ don't reloc during debug + beq stack_setup + + ldr r2, _armboot_start + ldr r3, _bss_start + sub r2, r3, r2 @ r2 <- size of armboot + add r2, r0, r2 @ r2 <- source end address + +copy_loop: @ copy 32 bytes at a time + ldmia r0!, {r3 - r10} @ copy from source address [r0] + stmia r1!, {r3 - r10} @ copy to target address [r1] + cmp r0, r2 @ until source end addreee [r2] + ble copy_loop +#endif /* CONFIG_SKIP_RELOCATE_UBOOT */ + + /* Set up the stack */ +stack_setup: + ldr r0, _TEXT_BASE @ upper 128 KiB: relocated uboot + sub r0, r0, #CONFIG_SYS_MALLOC_LEN @ malloc area + sub r0, r0, #CONFIG_SYS_GBL_DATA_SIZE @ bdinfo +#ifdef CONFIG_USE_IRQ + sub r0, r0, #(CONFIG_STACKSIZE_IRQ + CONFIG_STACKSIZE_FIQ) +#endif + sub sp, r0, #12 @ leave 3 words for abort-stack + and sp, sp, #~7 @ 8 byte alinged for (ldr/str)d + + /* Clear BSS (if any). Is below tx (watch load addr - need space) */ +clear_bss: + ldr r0, _bss_start @ find start of bss segment + ldr r1, _bss_end @ stop here + mov r2, #0x00000000 @ clear value +clbss_l: + str r2, [r0] @ clear BSS location + cmp r0, r1 @ are we at the end yet + add r0, r0, #4 @ increment clear index pointer + bne clbss_l @ keep clearing till at end + + ldr pc, _start_armboot @ jump to C code + +_start_armboot: .word start_armboot + + +/************************************************************************* + * + * CPU_init_critical registers + * + * setup important registers + * setup memory timing + * + *************************************************************************/ +cpu_init_crit: + /* + * Invalidate L1 I/D + */ + mov r0, #0 @ set up for MCR + mcr p15, 0, r0, c8, c7, 0 @ invalidate TLBs + mcr p15, 0, r0, c7, c5, 0 @ invalidate icache + + /* + * disable MMU stuff and caches + */ + mrc p15, 0, r0, c1, c0, 0 + bic r0, r0, #0x00002000 @ clear bits 13 (--V-) + bic r0, r0, #0x00000007 @ clear bits 2:0 (-CAM) + orr r0, r0, #0x00000002 @ set bit 1 (--A-) Align + orr r0, r0, #0x00000800 @ set bit 12 (Z---) BTB + mcr p15, 0, r0, c1, c0, 0 + + /* + * Jump to board specific initialization... + * The Mask ROM will have already initialized + * basic memory. Go here to bump up clock rate and handle + * wake up conditions. + */ + mov ip, lr @ persevere link reg across call + bl lowlevel_init @ go setup pll,mux,memory + mov lr, ip @ restore link + mov pc, lr @ back to my caller +/* + ************************************************************************* + * + * Interrupt handling + * + ************************************************************************* + */ +@ +@ IRQ stack frame. +@ +#define S_FRAME_SIZE 72 + +#define S_OLD_R0 68 +#define S_PSR 64 +#define S_PC 60 +#define S_LR 56 +#define S_SP 52 + +#define S_IP 48 +#define S_FP 44 +#define S_R10 40 +#define S_R9 36 +#define S_R8 32 +#define S_R7 28 +#define S_R6 24 +#define S_R5 20 +#define S_R4 16 +#define S_R3 12 +#define S_R2 8 +#define S_R1 4 +#define S_R0 0 + +#define MODE_SVC 0x13 +#define I_BIT 0x80 + +/* + * use bad_save_user_regs for abort/prefetch/undef/swi ... + * use irq_save_user_regs / irq_restore_user_regs for IRQ/FIQ handling + */ + + .macro bad_save_user_regs + sub sp, sp, #S_FRAME_SIZE @ carve out a frame on current + @ user stack + stmia sp, {r0 - r12} @ Save user registers (now in + @ svc mode) r0-r12 + + ldr r2, _armboot_start + sub r2, r2, #(CONFIG_SYS_MALLOC_LEN) + sub r2, r2, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ set base 2 words into abort + @ stack + ldmia r2, {r2 - r3} @ get values for "aborted" pc + @ and cpsr (into parm regs) + add r0, sp, #S_FRAME_SIZE @ grab pointer to old stack + + add r5, sp, #S_SP + mov r1, lr + stmia r5, {r0 - r3} @ save sp_SVC, lr_SVC, pc, cpsr + mov r0, sp @ save current stack into r0 + @ (param register) + .endm + + .macro irq_save_user_regs + sub sp, sp, #S_FRAME_SIZE + stmia sp, {r0 - r12} @ Calling r0-r12 + add r8, sp, #S_PC @ !! R8 NEEDS to be saved !! + @ a reserved stack spot would + @ be good. + stmdb r8, {sp, lr}^ @ Calling SP, LR + str lr, [r8, #0] @ Save calling PC + mrs r6, spsr + str r6, [r8, #4] @ Save CPSR + str r0, [r8, #8] @ Save OLD_R0 + mov r0, sp + .endm + + .macro irq_restore_user_regs + ldmia sp, {r0 - lr}^ @ Calling r0 - lr + mov r0, r0 + ldr lr, [sp, #S_PC] @ Get PC + add sp, sp, #S_FRAME_SIZE + subs pc, lr, #4 @ return & move spsr_svc into + @ cpsr + .endm + + .macro get_bad_stack + ldr r13, _armboot_start @ setup our mode stack (enter + @ in banked mode) + sub r13, r13, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool + sub r13, r13, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move to reserved a couple + @ spots for abort stack + + str lr, [r13] @ save caller lr in position 0 + @ of saved stack + mrs lr, spsr @ get the spsr + str lr, [r13, #4] @ save spsr in position 1 of + @ saved stack + + mov r13, #MODE_SVC @ prepare SVC-Mode + @ msr spsr_c, r13 + msr spsr, r13 @ switch modes, make sure + @ moves will execute + mov lr, pc @ capture return pc + movs pc, lr @ jump to next instruction & + @ switch modes. + .endm + + .macro get_bad_stack_swi + sub r13, r13, #4 @ space on current stack for + @ scratch reg. + str r0, [r13] @ save R0's value. + ldr r0, _armboot_start @ get data regions start + sub r0, r0, #(CONFIG_SYS_MALLOC_LEN) @ move past malloc pool + sub r0, r0, #(CONFIG_SYS_GBL_DATA_SIZE + 8) @ move past gbl and a couple + @ spots for abort stack + str lr, [r0] @ save caller lr in position 0 + @ of saved stack + mrs r0, spsr @ get the spsr + str lr, [r0, #4] @ save spsr in position 1 of + @ saved stack + ldr r0, [r13] @ restore r0 + add r13, r13, #4 @ pop stack entry + .endm + + .macro get_irq_stack @ setup IRQ stack + ldr sp, IRQ_STACK_START + .endm + + .macro get_fiq_stack @ setup FIQ stack + ldr sp, FIQ_STACK_START + .endm + +/* + * exception handlers + */ + .align 5 +undefined_instruction: + get_bad_stack + bad_save_user_regs + bl do_undefined_instruction + + .align 5 +software_interrupt: + get_bad_stack_swi + bad_save_user_regs + bl do_software_interrupt + + .align 5 +prefetch_abort: + get_bad_stack + bad_save_user_regs + bl do_prefetch_abort + + .align 5 +data_abort: + get_bad_stack + bad_save_user_regs + bl do_data_abort + + .align 5 +not_used: + get_bad_stack + bad_save_user_regs + bl do_not_used + +#ifdef CONFIG_USE_IRQ + + .align 5 +irq: + get_irq_stack + irq_save_user_regs + bl do_irq + irq_restore_user_regs + + .align 5 +fiq: + get_fiq_stack + /* someone ought to write a more effiction fiq_save_user_regs */ + irq_save_user_regs + bl do_fiq + irq_restore_user_regs + +#else + + .align 5 +irq: + get_bad_stack + bad_save_user_regs + bl do_irq + + .align 5 +fiq: + get_bad_stack + bad_save_user_regs + bl do_fiq + +#endif + +/* + * v7_flush_dcache_all() + * + * Flush the whole D-cache. + * + * Corrupted registers: r0-r5, r7, r9-r11 + * + * - mm - mm_struct describing address space + */ + .align 5 +.global v7_flush_dcache_all +v7_flush_dcache_all: + stmfd r13!, {r0 - r5, r7, r9 - r12, r14} + + mov r7, r0 @ take a backup of device type + cmp r0, #0x3 @ check if the device type is + @ GP + moveq r12, #0x1 @ set up to invalide L2 +smi: .word 0x01600070 @ Call SMI monitor (smieq) + cmp r7, #0x3 @ compare again in case its + @ lost + beq finished_inval @ if GP device, inval done + @ above + + mrc p15, 1, r0, c0, c0, 1 @ read clidr + ands r3, r0, #0x7000000 @ extract loc from clidr + mov r3, r3, lsr #23 @ left align loc bit field + beq finished_inval @ if loc is 0, then no need to + @ clean + mov r10, #0 @ start clean at cache level 0 +inval_loop1: + add r2, r10, r10, lsr #1 @ work out 3x current cache + @ level + mov r1, r0, lsr r2 @ extract cache type bits from + @ clidr + and r1, r1, #7 @ mask of the bits for current + @ cache only + cmp r1, #2 @ see what cache we have at + @ this level + blt skip_inval @ skip if no cache, or just + @ i-cache + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mov r2, #0 @ operand for mcr SBZ + mcr p15, 0, r2, c7, c5, 4 @ flush prefetch buffer to + @ sych the new cssr&csidr, + @ with armv7 this is 'isb', + @ but we compile with armv5 + mrc p15, 1, r1, c0, c0, 0 @ read the new csidr + and r2, r1, #7 @ extract the length of the + @ cache lines + add r2, r2, #4 @ add 4 (line length offset) + ldr r4, =0x3ff + ands r4, r4, r1, lsr #3 @ find maximum number on the + @ way size + clz r5, r4 @ find bit position of way + @ size increment + ldr r7, =0x7fff + ands r7, r7, r1, lsr #13 @ extract max number of the + @ index size +inval_loop2: + mov r9, r4 @ create working copy of max + @ way size +inval_loop3: + orr r11, r10, r9, lsl r5 @ factor way and cache number + @ into r11 + orr r11, r11, r7, lsl r2 @ factor index number into r11 + mcr p15, 0, r11, c7, c6, 2 @ invalidate by set/way + subs r9, r9, #1 @ decrement the way + bge inval_loop3 + subs r7, r7, #1 @ decrement the index + bge inval_loop2 +skip_inval: + add r10, r10, #2 @ increment cache number + cmp r3, r10 + bgt inval_loop1 +finished_inval: + mov r10, #0 @ swith back to cache level 0 + mcr p15, 2, r10, c0, c0, 0 @ select current cache level + @ in cssr + mcr p15, 0, r10, c7, c5, 4 @ flush prefetch buffer, + @ with armv7 this is 'isb', + @ but we compile with armv5 + + ldmfd r13!, {r0 - r5, r7, r9 - r12, pc} + + + .align 5 +.global reset_cpu +reset_cpu: + ldr r1, rstctl @ get addr for global reset + @ reg + mov r3, #0x2 @ full reset pll + mpu + str r3, [r1] @ force reset + mov r0, r0 +_loop_forever: + b _loop_forever +rstctl: + .word PRM_RSTCTRL

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[U-Boot] [PATCH 00/13 v5] ARM: OMAP3: Add support for some of TIs ARM-Cortex A8 OMAP3 boards
by dirk.behme＠googlemail.com 03 Nov '08

03 Nov '08

Subject: [PATCH 00/13 v5] ARM: OMAP3: Add support for some of TIs ARM-Cortex A8 OMAP3 boards This patch series adds U-Boot v1 support for some of TI's ARM-Cortex A8 based OMAP3 boards. These are BeagleBoard [1][2], EVM [3] and Overo [4]. The patch series is based on U-Boot tar ball [5] for BeagleBoard and EVM done by several TI employees. To be able to easily add new boards, most of the code is common for all boards. After the header files (patches 1-2) and the common code for ARM Cortex A8 (patch 3) and OMAP3 SoC (patches 4-6), support and drivers for NAND, MMC and I2C is added (patches 7-9). Patches 10-12 introduce the individual board support for Beagle, EVM and Overo, and last patch 13 the config files for these boards. As discussed earlier on this list, we compile for armv5 to be compatible with existing toolchains. This patch adds ~300k of new code. Thanks to Steve Sakoman <sakoman(a)gmail.com> Pillai, Manikandan <mani.pillai(a)ti.com> Syed Mohammed, Khasim <khasim(a)ti.com> Nishanth Menon <nm(a)ti.com> and all others who helped with this. Dirk Changes in version v5: - Additional space changes as proposed by Jean-Christophe PLAGNIOL-VILLARD - Additional NAND driver clean up as proposed by Scott Wood - Add README.omap3 - Reorganization of PinMux and add EVM pin mux as proposed by Steve Sakoman - Start (NAND) to use readx/writex base + offset scheme as proposed by Scott Wood - Rebase to u-boot master, commit 3ec53148eb68ddfb0c3311fb4c06cd2bd0ef3eeb, "Merge branch 'master' of git://git.denx.de/u-boot-nand-flash" Changes in version v4: - Update u-boot-arm.git next base, commit 1c38b6cd7ca20b68766815299385b7e46611ca46, "add tool to check patch and file for CFG_ presence" - Fix/update NAND driver with review comments from Scott Wood and fixes from Nishanth Menon Changes in version v3: - Replace space by tabs in headers as proposed by Jean-Christophe PLAGNIOL-VILLARD - Fix/update NAND driver and seperate it into an own patch as proposed by Scott Wood - Add detection and support for 128MB/256MB RAM by Mans Rullgard Changes in version v2: - Move MMC driver to drivers/mmc/ as suggested by Haavard Skinnemoen. - Move common ARM Cortex A8 code to cpu/arm_cortexa8/ and OMAP3 SoC specific common code to cpu/arm_cortexa8/omap3 as proposed by Wolfgang. - Update Overo pin mux to add and pull down X_GATE, by Steve Sakoman. - Remove SMC911X network init as proposed by Ben Warren. - Rebase against u-boot-arm.git next, commit 4995fed33099bb9813504869056bab72446fe8f9, "add tool to check patch and filr for CFG_ present" (CFG vs. CONFIG changes) This v5 patch series makes all previous (v1, v2, v3 & v4) OMAP3 patches obsolete. [1] http://beagleboard.org/ [2] http://elinux.org/BeagleBoard [3] http://focus.ti.com/docs/toolsw/folders/print/tmdxevm3503.html [4] http://www.gumstix.net/Overo/ [5] http://beagleboard.googlecode.com/files/u-boot_beagle_revb.tar.gz

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[U-Boot] [PATCH] bootvx: Cleanup & improvements
by Niklaus Giger 03 Nov '08

03 Nov '08

The following improvements are made: - document bootvx in README - fix size too small by one in sprintf - changed old (pre 2004) device name ibmEmac to emac - boot device may be overriden in board config - servername may be defined in board config - additional parameters may be defined in board config - fixed some line wrappings - changed netstal-common.h to use the new settings --- README | 17 ++++++++ common/cmd_elf.c | 80 ++++++++++++++++++-------------------- include/configs/netstal-common.h | 29 +++++++------- 3 files changed, 69 insertions(+), 57 deletions(-) diff --git a/README b/README index ebee20f..99d2a3d 100644 --- a/README +++ b/README @@ -379,6 +379,23 @@ The following options need to be configured: This define fills in the correct boot CPU in the boot param header, the default value is zero if undefined. +- vxWorks boot parameters: + + bootvx constructs a valid bootline using the following + environments variables: bootfile, ipaddr, serverip, hostname. + It loads the vxWorks image pointed bootfile. + + CONFIG_SYS_VXWORKS_BOOT_DEVICE - The vxworks device name + CONFIG_SYS_VXWORKS_MAC_PTR - Ethernet 6 byte MA -address + CONFIG_SYS_VXWORKS_SERVERNAME - Name of the server + + CONFIG_SYS_VXWORKS_ADD_PARAMS + + Add it at the end of the bootline. E.g "u=username pw=secret" + + Note: If a "bootargs" environment is defined, it will overwride + the defaults discussed just above. + - Serial Ports: CONFIG_PL010_SERIAL diff --git a/common/cmd_elf.c b/common/cmd_elf.c index 3ebb6d9..d537478 100644 --- a/common/cmd_elf.c +++ b/common/cmd_elf.c @@ -102,10 +102,8 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) unsigned long bootaddr; /* Address to put the bootline */ char *bootline; /* Text of the bootline */ char *tmp; /* Temporary char pointer */ + char build_buf[128]; /* Buffer for building the bootline */ -#if defined(CONFIG_4xx) || defined(CONFIG_IOP480) - char build_buf[80]; /* Buffer for building the bootline */ -#endif /* -------------------------------------------------- */ /* @@ -124,7 +122,8 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) if ((argc == 2) && (strcmp (argv[1], "tftp") == 0)) { if (NetLoop (TFTP) <= 0) return 1; - printf ("Automatic boot of VxWorks image at address 0x%08lx ... \n", addr); + printf ("Automatic boot of VxWorks image at address 0x%08lx ... \n", + addr); } #endif @@ -163,54 +162,53 @@ int do_bootvx (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) */ if ((bootline = getenv ("bootargs")) != NULL) { - memcpy ((void *) bootaddr, bootline, MAX(strlen(bootline), 255)); - flush_cache (bootaddr, MAX(strlen(bootline), 255)); + memcpy ((void *) bootaddr, bootline, + MAX (strlen (bootline), 255)); + flush_cache (bootaddr, MAX (strlen (bootline), 255)); } else { + +#ifndef CONFIG_SYS_VXWORKS_BOOT_DEVICE #if defined(CONFIG_4xx) - sprintf (build_buf, "ibmEmac(0,0)"); +#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "emac(0,0)" +#elif defined(CONFIG_IOP480) +#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "dc(0,0)" +#else +#define CONFIG_SYS_VXWORKS_BOOT_DEVICE "eth(0,0)" +#endif +#endif - if ((tmp = getenv ("hostname")) != NULL) { - sprintf (&build_buf[strlen (build_buf - 1)], - "host:%s ", tmp); +#ifndef CONFIG_SYS_VXWORKS_SERVERNAME +#define CONFIG_SYS_VXWORKS_SERVERNAME srv +#endif + + sprintf (build_buf, CONFIG_SYS_VXWORKS_BOOT_DEVICE); + if ((tmp = getenv ("bootfile")) != NULL) { + sprintf (&build_buf[strlen (build_buf)], + "%s:%s ", CONFIG_SYS_VXWORKS_SERVERNAME, tmp); } else { - sprintf (&build_buf[strlen (build_buf - 1)], - ": "); + sprintf (&build_buf[strlen (build_buf)], + "%s:file ", CONFIG_SYS_VXWORKS_SERVERNAME); } if ((tmp = getenv ("ipaddr")) != NULL) { - sprintf (&build_buf[strlen (build_buf - 1)], - "e=%s ", tmp); + sprintf (&build_buf[strlen (build_buf)], "e=%s ", tmp); } - memcpy ((void *)bootaddr, build_buf, MAX(strlen(build_buf), 255)); - flush_cache (bootaddr, MAX(strlen(build_buf), 255)); -#elif defined(CONFIG_IOP480) - sprintf (build_buf, "dc(0,0)"); - if ((tmp = getenv ("hostname")) != NULL) { - sprintf (&build_buf[strlen (build_buf - 1)], - "host:%s ", tmp); - } else { - sprintf (&build_buf[strlen (build_buf - 1)], - ": "); + if ((tmp = getenv ("serverip")) != NULL) { + sprintf (&build_buf[strlen (build_buf)], "h=%s ", tmp); } - if ((tmp = getenv ("ipaddr")) != NULL) { - sprintf (&build_buf[strlen (build_buf - 1)], - "e=%s ", tmp); + if ((tmp = getenv ("hostname")) != NULL) { + sprintf (&build_buf[strlen (build_buf)], "tn=%s ", tmp); } - memcpy ((void *) bootaddr, build_buf, MAX(strlen(build_buf), 255)); - flush_cache (bootaddr, MAX(strlen(build_buf), 255)); -#else - - /* - * I'm not sure what the device should be for other - * PPC flavors, the hostname and ipaddr should be ok - * to just copy - */ - - puts ("No bootargs defined\n"); - return 1; +#ifdef CONFIG_SYS_VXWORKS_ADD_PARAMS + sprintf (&build_buf[strlen (build_buf)], + CONFIG_SYS_VXWORKS_ADD_PARAMS); #endif + + memcpy ((void *) bootaddr, build_buf, + MAX (strlen (build_buf), 255)); + flush_cache (bootaddr, MAX (strlen (build_buf), 255)); } /* @@ -255,8 +253,7 @@ int valid_elf_image (unsigned long addr) } if (ehdr->e_type != ET_EXEC) { - printf ("## Not a 32-bit elf image at address 0x%08lx\n", - addr); + printf ("## Not a 32-bit elf image at address 0x%08lx\n", addr); return 0; } @@ -271,7 +268,6 @@ int valid_elf_image (unsigned long addr) return 1; } - /* ====================================================================== * A very simple elf loader, assumes the image is valid, returns the * entry point address. diff --git a/include/configs/netstal-common.h b/include/configs/netstal-common.h index 1fa4b00..7f2b015 100644 --- a/include/configs/netstal-common.h +++ b/include/configs/netstal-common.h @@ -201,8 +201,9 @@ #define CONFIG_ETHADDR 00:60:13:00:00:00 /* Netstal Machines AG MAC */ #define CONFIG_OVERWRITE_ETHADDR_ONCE -#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 - +#define CONFIG_SYS_TFTP_LOADADDR 0x01000000 +#define CONFIG_SYS_VXWORKS_ADD_PARAMS "u=dpu pw=netstal8752" +#define CONFIG_SYS_VXWORKS_SERVERNAME "c" /* * General common environment variables shared by all boards produced by Netstal Maschinen */ @@ -222,19 +223,17 @@ "fdt_addr_r=800000\0" \ "hostname=" xstr(CONFIG_HOSTNAME) "\0" \ "bootfile=" xstr(CONFIG_HOSTNAME) "/uImage\0" \ - "load=tftp 200000 " xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ - "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ - "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ - "cp.b ${fileaddr} " xstr(CONFIG_SYS_MONITOR_BASE) " ${filesize};" \ - "setenv filesize\0" \ - "upd=run load update\0" \ - "vx_rom=" xstr(CONFIG_HOSTNAME) "/" \ - xstr(CONFIG_HOSTNAME) "_vx_rom\0" \ - "vx=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " ${vx_rom};run vxargs;" \ - "bootvx\0" \ - "vxargs=setenv bootargs emac(0,0)c:${vx_rom} e=${ipaddr}" \ - " h=${serverip} u=dpu pw=netstal8752 " \ - "tn=" xstr(CONFIG_HOSTNAME) " f=0x3008\0" \ + "uload=tftp " xstr(CONFIG_SYS_TFTP_LOADADDR) " " \ + xstr(CONFIG_HOSTNAME) "/u-boot.bin\0" \ + "vx_rom=" xstr(CONFIG_HOSTNAME) "/" \ + xstr(CONFIG_HOSTNAME) "_vx_rom\0" \ + "update=protect off " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;"\ + "era " xstr(CONFIG_SYS_MONITOR_BASE) " FFFFFFFF;" \ + "cp.b ${fileaddr} "xstr(CONFIG_SYS_MONITOR_BASE) \ + " ${filesize}; setenv filesize\0" \ + "upd=run uload update\0" \ + "vx=setenv bootfile ${vx_rom}; tftp " \ + xstr(CONFIG_SYS_TFTP_LOADADDR) "; bootvx\0" \ CONFIG_NETSTAL_DEF_ENV_ROOTPATH /* -- 1.5.4.3

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