January 2008 - U-Boot

[U-Boot-Users] [PATCH] Add attribute POST_PREREL to ECC memory POST
by Larry Johnson 07 Feb '08

07 Feb '08

Signed-off-by: Larry Johnson <lrj(a)acm.org> --- post/tests.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/post/tests.c b/post/tests.c index 0c49e32..698f85c 100644 --- a/post/tests.c +++ b/post/tests.c @@ -241,8 +241,8 @@ struct post_test post_list[] = { "ECC test", "ecc", - "This test checks ECC facility of memory.", - POST_ROM | POST_ALWAYS, + "This test checks the ECC facility of memory.", + POST_ROM | POST_ALWAYS | POST_PREREL, &ecc_post_test, NULL, NULL, -- 1.5.2.5

3 4

[U-Boot-Users] [PATCH] MPC85xx KGDB support
by Chen Gong 05 Feb '08

05 Feb '08

--- cpu/mpc85xx/Makefile | 4 +- drivers/serial.c | 28 +++++++++++++++++++ include/configs/MPC8548CDS.h | 3 +- lib_ppc/kgdb.c | 62 +++++++++++++++++++++++++++++++++--------- 4 files changed, 81 insertions(+), 16 deletions(-) diff --git a/cpu/mpc85xx/Makefile b/cpu/mpc85xx/Makefile index 32091fa..f5cb148 100644 --- a/cpu/mpc85xx/Makefile +++ b/cpu/mpc85xx/Makefile @@ -28,7 +28,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(CPU).a -START = start.o resetvec.o +START = start.o resetvec.o kgdb.o COBJS = traps.o cpu.o cpu_init.o speed.o interrupts.o \ pci.o serial_scc.o commproc.o ether_fcc.o spd_sdram.o qe_io.o @@ -39,7 +39,7 @@ START := $(addprefix $(obj),$(START)) all: $(obj).depend $(START) $(LIB) $(LIB): $(OBJS) - $(AR) $(ARFLAGS) $@ $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) $(obj)kgdb.o ######################################################################### diff --git a/drivers/serial.c b/drivers/serial.c index 76425d8..42585d7 100644 --- a/drivers/serial.c +++ b/drivers/serial.c @@ -307,6 +307,34 @@ serial_setbrg(void) } #endif +#if defined(CONFIG_CMD_KGDB) +void kgdb_serial_init (void) +{ + /* here presume you have been initialzed appropriate COM# */ + _serial_puts("[on serial] ",CONFIG_KGDB_SER_INDEX); +} + +void putDebugChar (int c) +{ + _serial_putc(c, CONFIG_KGDB_SER_INDEX); +} + +void putDebugStr (const char *str) +{ + _serial_puts(str, CONFIG_KGDB_SER_INDEX); +} + +int getDebugChar (void) +{ + return _serial_getc(CONFIG_KGDB_SER_INDEX); +} + +void kgdb_interruptible (int yes) +{ + return; +} +#endif + #if defined(CONFIG_SERIAL_MULTI) DECLARE_ESERIAL_FUNCTIONS(1); diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index 6083715..396feeb 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -482,6 +482,7 @@ extern unsigned long get_clock_freq(void); #define CONFIG_CMD_PING #define CONFIG_CMD_I2C #define CONFIG_CMD_MII +#define CONFIG_CMD_KGDB #if defined(CONFIG_PCI) #define CONFIG_CMD_PCI @@ -529,7 +530,7 @@ extern unsigned long get_clock_freq(void); #define BOOTFLAG_WARM 0x02 /* Software reboot */ #if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ #define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif diff --git a/lib_ppc/kgdb.c b/lib_ppc/kgdb.c index 78c2f0c..7acdebc 100644 --- a/lib_ppc/kgdb.c +++ b/lib_ppc/kgdb.c @@ -60,20 +60,46 @@ static struct hard_trap_info unsigned int tt; /* Trap type code for powerpc */ unsigned char signo; /* Signal that we map this trap into */ } hard_trap_info[] = { - { 0x200, SIGSEGV }, /* machine check */ - { 0x300, SIGSEGV }, /* address error (store) */ - { 0x400, SIGBUS }, /* instruction bus error */ - { 0x500, SIGINT }, /* interrupt */ - { 0x600, SIGBUS }, /* alingment */ - { 0x700, SIGTRAP }, /* breakpoint trap */ - { 0x800, SIGFPE }, /* fpu unavail */ - { 0x900, SIGALRM }, /* decrementer */ - { 0xa00, SIGILL }, /* reserved */ - { 0xb00, SIGILL }, /* reserved */ - { 0xc00, SIGCHLD }, /* syscall */ - { 0xd00, SIGTRAP }, /* single-step/watch */ - { 0xe00, SIGFPE }, /* fp assist */ +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + { 0x100, SIGINT }, /* critical input interrupt */ + { 0x200, SIGSEGV }, /* machine check */ + { 0x300, SIGSEGV }, /* data storage */ + { 0x400, SIGBUS }, /* instruction storage */ + { 0x500, SIGINT }, /* interrupt */ + { 0x600, SIGBUS }, /* alignment */ + { 0x700, SIGILL }, /* program */ + { 0x800, SIGILL }, /* reserved */ + { 0x900, SIGILL }, /* reserved */ + { 0xa00, SIGILL }, /* reserved */ + { 0xb00, SIGILL }, /* reserved */ + { 0xc00, SIGCHLD }, /* syscall */ + { 0xd00, SIGILL }, /* reserved */ + { 0xe00, SIGILL }, /* reserved */ + { 0xf00, SIGILL }, /* reserved */ + /* + * 0x1000 PIT + * 0x1010 FIT + * 0x1020 watchdog + * 0x1100 data TLB miss + * 0x1200 instruction TLB miss + */ + { 0x2002, SIGTRAP}, /* debug */ +#else + { 0x200, SIGSEGV }, /* machine check */ + { 0x300, SIGSEGV }, /* address error (store) */ + { 0x400, SIGBUS }, /* instruction bus error */ + { 0x500, SIGINT }, /* interrupt */ + { 0x600, SIGBUS }, /* alingment */ + { 0x700, SIGTRAP }, /* breakpoint trap */ + { 0x800, SIGFPE }, /* fpu unavail */ + { 0x900, SIGALRM }, /* decrementer */ + { 0xa00, SIGILL }, /* reserved */ + { 0xb00, SIGILL }, /* reserved */ + { 0xc00, SIGCHLD }, /* syscall */ + { 0xd00, SIGTRAP }, /* single-step/watch */ + { 0xe00, SIGFPE }, /* fp assist */ { 0, 0} /* Must be last */ +#endif }; static int @@ -100,7 +126,12 @@ kgdb_enter(struct pt_regs *regs, kgdb_data *kdp) /* Skip over breakpoint trap insn */ regs->nip += 4; } +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) & ~DBCR_IC); + regs->msr &= ~MSR_DE; +#else regs->msr &= ~MSR_SE; +#endif /* reply to host that an exception has occurred */ kdp->sigval = computeSignal(regs->trap); @@ -130,7 +161,12 @@ kgdb_exit(struct pt_regs *regs, kgdb_data *kdp) break; case KGDBEXIT_SINGLE: +#if defined(CONFIG_40x) || defined(CONFIG_BOOKE) + mtspr(SPRN_DBCR0, mfspr(SPRN_DBCR0) | DBCR_IC); + regs->msr |= MSR_DE; +#else regs->msr |= MSR_SE; +#endif #if 0 set_msr(msr | MSR_SE); #endif -- 1.5.2

4 3

[U-Boot-Users] [PATCH] ColdFire: Fix missing code flash size for M5485EVB
by Tsi-Chung Liew 05 Feb '08

05 Feb '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: James Mahan <kmahan(a)freescale.com> Signed-off-by: TsiChung Liew <Tsi-Chung.Liew(a)freescale.com> --- Makefile | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/Makefile b/Makefile index 0f6cc59..30fda62 100644 --- a/Makefile +++ b/Makefile @@ -1912,7 +1912,7 @@ M5485HFE_config : unconfig M5485EFE_config) BOOT=2;CODE=0;VID=1;USB=1;RAM=64;RAM1=0;; \ M5485FFE_config) BOOT=2;CODE=32;VID=1;USB=1;RAM=64;RAM1=64;; \ M5485GFE_config) BOOT=4;CODE=0;VID=0;USB=0;RAM=64;RAM1=0;; \ - M5485HFE_config) BOOT=2;CODE=;VID=1;USB=0;RAM=64;RAM1=0;; \ + M5485HFE_config) BOOT=2;CODE=16;VID=1;USB=0;RAM=64;RAM1=0;; \ esac; \ >include/config.h ; \ echo "#define CFG_BUSCLK 100000000" > $(obj)include/config.h ; \ -- 1.5.2

3 3

[U-Boot-Users] [PATCH] 85xx: Add the concept of CFG_CCSRBAR_PHYS
by Kumar Gala 05 Feb '08

05 Feb '08

When we go to 36-bit physical addresses we need to keep the concept of the physical CCSRBAR address seperate from the virtual one. For the majority of boards CFG_CCSBAR_PHYS == CFG_CCSRBAR Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- This is in the mpc85xx branch of my git tree. - k board/atum8548/tlb.c | 2 +- board/freescale/mpc8540ads/tlb.c | 2 +- board/freescale/mpc8541cds/tlb.c | 2 +- board/freescale/mpc8544ds/tlb.c | 2 +- board/freescale/mpc8548cds/tlb.c | 2 +- board/freescale/mpc8555cds/tlb.c | 2 +- board/freescale/mpc8560ads/tlb.c | 2 +- board/freescale/mpc8568mds/tlb.c | 2 +- board/mpc8540eval/tlb.c | 2 +- board/pm854/tlb.c | 2 +- board/pm856/tlb.c | 2 +- board/sbc8548/tlb.c | 2 +- board/sbc8560/tlb.c | 2 +- board/stxgp3/tlb.c | 2 +- board/stxssa/tlb.c | 2 +- board/tqm85xx/tlb.c | 2 +- cpu/mpc85xx/cpu_init.c | 6 +++--- include/configs/ATUM8548.h | 1 + include/configs/MPC8540ADS.h | 1 + include/configs/MPC8540EVAL.h | 1 + include/configs/MPC8541CDS.h | 1 + include/configs/MPC8544DS.h | 1 + include/configs/MPC8548CDS.h | 1 + include/configs/MPC8555CDS.h | 1 + include/configs/MPC8560ADS.h | 1 + include/configs/MPC8568MDS.h | 1 + include/configs/PM854.h | 1 + include/configs/PM856.h | 1 + include/configs/SBC8540.h | 1 + include/configs/TQM85xx.h | 1 + include/configs/sbc8548.h | 1 + include/configs/sbc8560.h | 1 + include/configs/stxgp3.h | 1 + include/configs/stxssa.h | 1 + 34 files changed, 36 insertions(+), 19 deletions(-) diff --git a/board/atum8548/tlb.c b/board/atum8548/tlb.c index bb6ce76..1ef4de4 100644 --- a/board/atum8548/tlb.c +++ b/board/atum8548/tlb.c @@ -82,7 +82,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), }; diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index 3eaff01..4fe2862 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8541cds/tlb.c b/board/freescale/mpc8541cds/tlb.c index 92f759b..c5434a0 100644 --- a/board/freescale/mpc8541cds/tlb.c +++ b/board/freescale/mpc8541cds/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8544ds/tlb.c b/board/freescale/mpc8544ds/tlb.c index 34cfb38..61fc609 100644 --- a/board/freescale/mpc8544ds/tlb.c +++ b/board/freescale/mpc8544ds/tlb.c @@ -75,7 +75,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe100_0000 255M PCI IO range */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8548cds/tlb.c b/board/freescale/mpc8548cds/tlb.c index b21f71b..ab99af7 100644 --- a/board/freescale/mpc8548cds/tlb.c +++ b/board/freescale/mpc8548cds/tlb.c @@ -80,7 +80,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe210_0000 1M PCI2 IO * 0xe300_0000 1M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8555cds/tlb.c b/board/freescale/mpc8555cds/tlb.c index 92f759b..c5434a0 100644 --- a/board/freescale/mpc8555cds/tlb.c +++ b/board/freescale/mpc8555cds/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index 3eaff01..4fe2862 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/freescale/mpc8568mds/tlb.c b/board/freescale/mpc8568mds/tlb.c index 225fc94..a866c52 100644 --- a/board/freescale/mpc8568mds/tlb.c +++ b/board/freescale/mpc8568mds/tlb.c @@ -74,7 +74,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 8M PCI1 IO * 0xe280_0000 8M PCIe IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 3, BOOKE_PAGESZ_64M, 1), diff --git a/board/mpc8540eval/tlb.c b/board/mpc8540eval/tlb.c index f041236..1003bf6 100644 --- a/board/mpc8540eval/tlb.c +++ b/board/mpc8540eval/tlb.c @@ -27,7 +27,7 @@ #include <asm/mmu.h> struct fsl_e_tlb_entry tlb_table[] = { - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index 5d87537..a7f3813 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index 5d87537..a7f3813 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 8d6625e..6314005 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -81,7 +81,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe0000000 1M CCSRBAR * 0xe2000000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 4, BOOKE_PAGESZ_64M, 1), diff --git a/board/sbc8560/tlb.c b/board/sbc8560/tlb.c index 155ff64..d073399 100644 --- a/board/sbc8560/tlb.c +++ b/board/sbc8560/tlb.c @@ -28,7 +28,7 @@ struct fsl_e_tlb_entry tlb_table[] = { /* TLB for CCSRBAR (IMMR) */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 1, BOOKE_PAGESZ_1M, 1), diff --git a/board/stxgp3/tlb.c b/board/stxgp3/tlb.c index 529f230..d410416 100644 --- a/board/stxgp3/tlb.c +++ b/board/stxgp3/tlb.c @@ -87,7 +87,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/stxssa/tlb.c b/board/stxssa/tlb.c index 46b1440..86cbd11 100644 --- a/board/stxssa/tlb.c +++ b/board/stxssa/tlb.c @@ -88,7 +88,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe200_0000 16M PCI1 IO * 0xe300_0000 16M PCI2 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 5, BOOKE_PAGESZ_64M, 1), diff --git a/board/tqm85xx/tlb.c b/board/tqm85xx/tlb.c index a178cfe..ad26cae 100644 --- a/board/tqm85xx/tlb.c +++ b/board/tqm85xx/tlb.c @@ -91,7 +91,7 @@ struct fsl_e_tlb_entry tlb_table[] = { * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ - SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR, + SET_TLB_ENTRY(1, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), diff --git a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c index c0ff1d5..5f02e0e 100644 --- a/cpu/mpc85xx/cpu_init.c +++ b/cpu/mpc85xx/cpu_init.c @@ -127,12 +127,12 @@ void config_8560_ioports (volatile ccsr_cpm_t * cpm) /* We run cpu_init_early_f in AS = 1 */ void cpu_init_early_f(void) { - set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR, + set_tlb(0, CFG_CCSRBAR, CFG_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 1, 0, BOOKE_PAGESZ_4K, 0); /* set up CCSR if we want it moved */ -#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) +#if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR_PHYS) { u32 temp; @@ -141,7 +141,7 @@ void cpu_init_early_f(void) 1, 1, BOOKE_PAGESZ_4K, 0); temp = in_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT); - out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR >> 12); + out_be32((volatile u32 *)CFG_CCSRBAR_DEFAULT, CFG_CCSRBAR_PHYS >> 12); temp = in_be32((volatile u32 *)CFG_CCSRBAR); } diff --git a/include/configs/ATUM8548.h b/include/configs/ATUM8548.h index c14376e..0d644da 100644 --- a/include/configs/ATUM8548.h +++ b/include/configs/ATUM8548.h @@ -96,6 +96,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define PCI_SPEED 33333000 /* CPLD currenlty does not have PCI setup info */ diff --git a/include/configs/MPC8540ADS.h b/include/configs/MPC8540ADS.h index 5ea7b25..85934d7 100644 --- a/include/configs/MPC8540ADS.h +++ b/include/configs/MPC8540ADS.h @@ -100,6 +100,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index bf64f27..04276a4 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -83,6 +83,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/MPC8541CDS.h b/include/configs/MPC8541CDS.h index 7334088..f1a86e6 100644 --- a/include/configs/MPC8541CDS.h +++ b/include/configs/MPC8541CDS.h @@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/MPC8544DS.h b/include/configs/MPC8544DS.h index a894209..c83d9e2 100644 --- a/include/configs/MPC8544DS.h +++ b/include/configs/MPC8544DS.h @@ -98,6 +98,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index a3db9f4..2d44df4 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -96,6 +96,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/MPC8555CDS.h b/include/configs/MPC8555CDS.h index 93877ae..fa0f7b3 100644 --- a/include/configs/MPC8555CDS.h +++ b/include/configs/MPC8555CDS.h @@ -82,6 +82,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/MPC8560ADS.h b/include/configs/MPC8560ADS.h index 08884b3..e30302c 100644 --- a/include/configs/MPC8560ADS.h +++ b/include/configs/MPC8560ADS.h @@ -95,6 +95,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index a12d193..7bb20e5 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -90,6 +90,7 @@ extern unsigned long get_clock_freq(void); */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 819bee7..bd058fc 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -92,6 +92,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/PM856.h b/include/configs/PM856.h index 8902f42..38a26dc 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -94,6 +94,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 2bbfe9a..946b3c2 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -99,6 +99,7 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index dd0654b..1239bd3 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -89,6 +89,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xFF700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xE0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ /* diff --git a/include/configs/sbc8548.h b/include/configs/sbc8548.h index 0a7a904..a8fe689 100644 --- a/include/configs/sbc8548.h +++ b/include/configs/sbc8548.h @@ -87,6 +87,7 @@ */ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_PCI1_ADDR (CFG_CCSRBAR+0x8000) diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index f9ede5f..81a1e07 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -93,6 +93,7 @@ #else #define CFG_CCSRBAR 0xff700000 /* default CCSRBAR */ #endif +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ #define CFG_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index 047e1cf..fc5d0cc 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -114,6 +114,7 @@ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xfdf00000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index e09dd71..15f690a 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -127,6 +127,7 @@ #define CFG_CCSRBAR_DEFAULT 0xff700000 /* CCSRBAR Default */ #endif #define CFG_CCSRBAR 0xe0000000 /* relocated CCSRBAR */ +#define CFG_CCSRBAR_PHYS CFG_CCSRBAR /* physical addr of CCSRBAR */ #define CFG_IMMR CFG_CCSRBAR /* PQII uses CFG_IMMR */ -- 1.5.3.8

2 1

[U-Boot-Users] [PATCH] ARM926: Display Ethernet info in do_bdinfo only if CONFIG_CMD_NET is defined
by Hebbar 05 Feb '08

05 Feb '08

Hi, This Patch adds if define to bdinfo command to display ethernet information only if CONFIG_CMD_NET is defined for arm modules. --- u-boot-1.3.1/common/cmd_bdinfo.c 2007-12-06 01:21:19.000000000 -0800 +++ uboot/common/cmd_bdinfo.c 2007-12-18 19:46:41.625000000 -0800 @@ -314,6 +314,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int fl print_num("-> size", bd->bi_dram[i].size); } +#if defined(CONFIG_CMD_NET) puts ("ethaddr ="); for (i=0; i<6; ++i) { printf ("%c%02X", i ? ':' : ' ', bd->bi_enetaddr[i]); @@ -321,6 +322,7 @@ int do_bdinfo ( cmd_tbl_t *cmdtp, int fl puts ( "\n" "ip_addr = "); print_IPaddr (bd->bi_ip_addr); +#endif printf ("\n" "baudrate = %d bps\n", bd->bi_baudrate); Signed-off-by: Hebbar I welcome comments, complaints, suggestions and advices. Regards Gururaja -- View this message in context: http://www.nabble.com/-PATCH--ARM926%3A-Display-Ethernet-info-in-do_bdinfo-… Sent from the Uboot - Users mailing list archive at Nabble.com.

6 9

[U-Boot-Users] [PATCH] TFTP: add host ip addr support
by Jean-Christophe PLAGNIOL-VILLARD 05 Feb '08

05 Feb '08

allow to use a different server as set in serverip Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> diff --git a/common/cmd_net.c b/common/cmd_net.c index 21682c0..b86ca86 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -51,7 +51,7 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( tftpboot, 3, 1, do_tftpb, "tftpboot- boot image via network using TFTP protocol\n", - "[loadAddress] [bootfilename]\n" + "[loadAddress] [[hostIPaddr:]bootfilename]\n" ); int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/net/tftp.c b/net/tftp.c index 8b95bcf..9d87e2c 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -34,7 +34,7 @@ #define TFTP_ERROR 5 #define TFTP_OACK 6 - +static IPaddr_t TftpServerIP; static int TftpServerPort; /* The UDP port at their end */ static int TftpOurPort; /* The UDP port at our end */ static int TftpTimeoutCount; @@ -55,7 +55,7 @@ static int TftpState; #define DEFAULT_NAME_LEN (8 + 4 + 1) static char default_filename[DEFAULT_NAME_LEN]; -static char *tftp_filename; +static char tftp_filename[2048]; #ifdef CFG_DIRECT_FLASH_TFTP extern flash_info_t flash_info[]; @@ -231,7 +231,7 @@ TftpSend (void) break; } - NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len); + NetSendUDPPacket(NetServerEther, TftpServerIP, TftpServerPort, TftpOurPort, len); } @@ -453,30 +453,38 @@ TftpStart (void) char *ep; /* Environment pointer */ #endif + TftpServerIP = NetServerIP; if (BootFile[0] == '\0') { sprintf(default_filename, "%02lX%02lX%02lX%02lX.img", NetOurIP & 0xFF, (NetOurIP >> 8) & 0xFF, (NetOurIP >> 16) & 0xFF, (NetOurIP >> 24) & 0xFF ); - tftp_filename = default_filename; + strcpy (tftp_filename, default_filename); printf ("*** Warning: no boot file name; using '%s'\n", tftp_filename); } else { - tftp_filename = BootFile; + char *p=BootFile; + p = strchr (p, ':'); + if (p != NULL) { + TftpServerIP = string_to_ip (BootFile); + ++p; + strcpy (tftp_filename, p); + } else + strcpy (tftp_filename, BootFile); } #if defined(CONFIG_NET_MULTI) printf ("Using %s device\n", eth_get_name()); #endif - puts ("TFTP from server "); print_IPaddr (NetServerIP); + puts ("TFTP from server "); print_IPaddr (TftpServerIP); puts ("; our IP address is "); print_IPaddr (NetOurIP); /* Check if we need to send across this subnet */ if (NetOurGatewayIP && NetOurSubnetMask) { IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; - IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + IPaddr_t ServerNet = TftpServerIP & NetOurSubnetMask; if (OurNet != ServerNet) { puts ("; sending through gateway "); -- 1.5.3.7

5 26

[U-Boot-Users] [PATCH] ARM: S3C24x0 SoC NAND controller support
by Harald Welte 05 Feb '08

05 Feb '08

This patch adds NAND support to the S3C24x0 SoC code in u-boot Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/cpu/arm920t/s3c24x0/Makefile =================================================================== --- u-boot.orig/cpu/arm920t/s3c24x0/Makefile +++ u-boot/cpu/arm920t/s3c24x0/Makefile @@ -26,7 +26,7 @@ LIB = $(obj)lib$(SOC).a COBJS = i2c.o interrupts.o serial.o speed.o \ - usb.o usb_ohci.o + usb.o usb_ohci.o nand.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(SOBJS) $(COBJS)) Index: u-boot/cpu/arm920t/s3c24x0/nand.c =================================================================== --- /dev/null +++ u-boot/cpu/arm920t/s3c24x0/nand.c @@ -0,0 +1,179 @@ +/* + * (C) Copyright 2006 OpenMoko, Inc. + * Author: Harald Welte <laforge(a)openmoko.org> + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +#if 0 +#define DEBUGN printf +#else +#define DEBUGN(x, args ...) {} +#endif + +#if defined(CONFIG_CMD_NAND) +#if !defined(CFG_NAND_LEGACY) + +#include <nand.h> +#include <s3c2410.h> + +#define __REGb(x) (*(volatile unsigned char *)(x)) +#define __REGi(x) (*(volatile unsigned int *)(x)) + +#define NF_BASE 0x4e000000 +#define NFCONF __REGi(NF_BASE + 0x0) +#define NFCMD __REGb(NF_BASE + 0x4) +#define NFADDR __REGb(NF_BASE + 0x8) +#define NFDATA __REGb(NF_BASE + 0xc) +#define NFSTAT __REGb(NF_BASE + 0x10) +#define NFECC0 __REGb(NF_BASE + 0x14) +#define NFECC1 __REGb(NF_BASE + 0x15) +#define NFECC2 __REGb(NF_BASE + 0x16) + +#define S3C2410_NFCONF_EN (1<<15) +#define S3C2410_NFCONF_512BYTE (1<<14) +#define S3C2410_NFCONF_4STEP (1<<13) +#define S3C2410_NFCONF_INITECC (1<<12) +#define S3C2410_NFCONF_nFCE (1<<11) +#define S3C2410_NFCONF_TACLS(x) ((x)<<8) +#define S3C2410_NFCONF_TWRPH0(x) ((x)<<4) +#define S3C2410_NFCONF_TWRPH1(x) ((x)<<0) + +static void s3c2410_hwcontrol(struct mtd_info *mtd, int cmd) +{ + struct nand_chip *chip = mtd->priv; + + DEBUGN("hwcontrol(): 0x%02x: ", cmd); + + switch (cmd) { + case NAND_CTL_SETNCE: + NFCONF &= ~S3C2410_NFCONF_nFCE; + DEBUGN("NFCONF=0x%08x\n", NFCONF); + break; + case NAND_CTL_CLRNCE: + NFCONF |= S3C2410_NFCONF_nFCE; + DEBUGN("NFCONF=0x%08x\n", NFCONF); + break; + case NAND_CTL_SETALE: + chip->IO_ADDR_W = NF_BASE + 0x8; + DEBUGN("SETALE\n"); + break; + case NAND_CTL_SETCLE: + chip->IO_ADDR_W = NF_BASE + 0x4; + DEBUGN("SETCLE\n"); + break; + default: + chip->IO_ADDR_W = NF_BASE + 0xc; + break; + } + return; +} + +static int s3c2410_dev_ready(struct mtd_info *mtd) +{ + DEBUGN("dev_ready\n"); + return (NFSTAT & 0x01); +} + +#ifdef CONFIG_S3C2410_NAND_HWECC +void s3c2410_nand_enable_hwecc(struct mtd_info *mtd, int mode) +{ + DEBUGN("s3c2410_nand_enable_hwecc(%p, %d)\n", mtd ,mode); + NFCONF |= S3C2410_NFCONF_INITECC; +} + +static int s3c2410_nand_calculate_ecc(struct mtd_info *mtd, const u_char *dat, + u_char *ecc_code) +{ + ecc_code[0] = NFECC0; + ecc_code[1] = NFECC1; + ecc_code[2] = NFECC2; + DEBUGN("s3c2410_nand_calculate_hwecc(%p,): 0x%02x 0x%02x 0x%02x\n", + mtd , ecc_code[0], ecc_code[1], ecc_code[2]); + + return 0; +} + +static int s3c2410_nand_correct_data(struct mtd_info *mtd, u_char *dat, + u_char *read_ecc, u_char *calc_ecc) +{ + if (read_ecc[0] == calc_ecc[0] && + read_ecc[1] == calc_ecc[1] && + read_ecc[2] == calc_ecc[2]) + return 0; + + printf("s3c2410_nand_correct_data: not implemented\n"); + return -1; +} +#endif + +int board_nand_init(struct nand_chip *nand) +{ + u_int32_t cfg; + u_int8_t tacls, twrph0, twrph1; + S3C24X0_CLOCK_POWER * const clk_power = S3C24X0_GetBase_CLOCK_POWER(); + + DEBUGN("board_nand_init()\n"); + + clk_power->CLKCON |= (1 << 4); + + /* initialize hardware */ + twrph0 = 3; twrph1 = 0; tacls = 0; + + cfg = S3C2410_NFCONF_EN; + cfg |= S3C2410_NFCONF_TACLS(tacls - 1); + cfg |= S3C2410_NFCONF_TWRPH0(twrph0 - 1); + cfg |= S3C2410_NFCONF_TWRPH1(twrph1 - 1); + + NFCONF = cfg; + + /* initialize nand_chip data structure */ + nand->IO_ADDR_R = nand->IO_ADDR_W = 0x4e00000c; + + /* read_buf and write_buf are default */ + /* read_byte and write_byte are default */ + + /* hwcontrol always must be implemented */ + nand->hwcontrol = s3c2410_hwcontrol; + + nand->dev_ready = s3c2410_dev_ready; + +#ifdef CONFIG_S3C2410_NAND_HWECC + nand->enable_hwecc = s3c2410_nand_enable_hwecc; + nand->calculate_ecc = s3c2410_nand_calculate_ecc; + nand->correct_data = s3c2410_nand_correct_data; + nand->eccmode = NAND_ECC_HW3_512; +#else + nand->eccmode = NAND_ECC_SOFT; +#endif + +#ifdef CONFIG_S3C2410_NAND_BBT + nand->options = NAND_USE_FLASH_BBT; +#else + nand->options = 0; +#endif + + DEBUGN("end of nand_init\n"); + + return 0; +} + +#else + #error "U-Boot legacy NAND support not available for S3C2410" +#endif +#endif -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

2 2

[U-Boot-Users] [PATCH] OMAP5912: fix FIFO handling in UART driver
by Wolfgang Denk 05 Feb '08

05 Feb '08

According to the OMAP5912 Serial Interfaces Reference Guide (see http://focus.ti.com/lit/ug/spru760c/spru760c.pdf, page 150), the FIFO_EN enable bit in the FIFO Control Register (FCR) can only be changed when the baud clock is not running, i. e. when both DLL and DLH are set to 0. Thus make sure that DLL and DLH are 0 when writing the FCR. Signed-off-by: Wolfgang Denk <wd(a)denx.de> --- drivers/serial/ns16550.c | 16 ++++++++++++---- 1 files changed, 12 insertions(+), 4 deletions(-) Unfortunately I can test this only on a limited number of boards with other NS16550 compatible UARTs (like TQM85xx, TQM83xx); the patch seems to cause no problems there. Comments welcome... diff --git a/drivers/serial/ns16550.c b/drivers/serial/ns16550.c index 2429464..6b3f60e 100644 --- a/drivers/serial/ns16550.c +++ b/drivers/serial/ns16550.c @@ -21,11 +21,15 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) com_port->mdr1 = 0x7; /* mode select reset TL16C750*/ #endif com_port->lcr = LCR_BKSE | LCRVAL; - com_port->dll = baud_divisor & 0xff; - com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->dll = 0; + com_port->dlm = 0; com_port->lcr = LCRVAL; com_port->mcr = MCRVAL; com_port->fcr = FCRVAL; + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = baud_divisor & 0xff; + com_port->dlm = (baud_divisor >> 8) & 0xff; + com_port->lcr = LCRVAL; #if defined(CONFIG_OMAP) #if defined(CONFIG_APTIX) com_port->mdr1 = 3; /* /13 mode so Aptix 6MHz can hit 115200 */ @@ -38,12 +42,16 @@ void NS16550_init (NS16550_t com_port, int baud_divisor) void NS16550_reinit (NS16550_t com_port, int baud_divisor) { com_port->ier = 0x00; + com_port->lcr = LCR_BKSE | LCRVAL; + com_port->dll = 0; + com_port->dlm = 0; + com_port->lcr = LCRVAL; + com_port->mcr = MCRVAL; + com_port->fcr = FCRVAL; com_port->lcr = LCR_BKSE; com_port->dll = baud_divisor & 0xff; com_port->dlm = (baud_divisor >> 8) & 0xff; com_port->lcr = LCRVAL; - com_port->mcr = MCRVAL; - com_port->fcr = FCRVAL; } void NS16550_putc (NS16550_t com_port, char c) -- 1.5.2.2 Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de ...when fits of creativity run strong, more than one programmer or writer has been known to abandon the desktop for the more spacious floor. - Fred Brooks, Jr.

2 3

[U-Boot-Users] [PATCH] ARM: s3c24xx: Multiple serial port support
by Harald Welte 04 Feb '08

04 Feb '08

This patch adds support for CONFIG_SERIAL_MULTI on s3c24x0 CPU's Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/common/serial.c =================================================================== --- u-boot.orig/common/serial.c +++ u-boot/common/serial.c @@ -59,6 +59,16 @@ #else return &serial0_device; #endif +#elif defined(CONFIG_S3C2410) +#if defined(CONFIG_SERIAL1) + return &s3c24xx_serial0_device; +#elif defined(CONFIG_SERIAL2) + return &s3c24xx_serial1_device; +#elif defined(CONFIG_SERIAL3) + return &s3c24xx_serial2_device; +#else +#error "CONFIG_SERIAL? missing." +#endif #else #error No default console #endif @@ -119,6 +129,11 @@ #if defined (CONFIG_STUART) serial_register(&serial_stuart_device); #endif +#if defined(CONFIG_S3C2410) + serial_register(&s3c24xx_serial0_device); + serial_register(&s3c24xx_serial1_device); + serial_register(&s3c24xx_serial2_device); +#endif serial_assign (default_serial_console ()->name); } Index: u-boot/cpu/arm920t/s3c24x0/serial.c =================================================================== --- u-boot.orig/cpu/arm920t/s3c24x0/serial.c +++ u-boot/cpu/arm920t/s3c24x0/serial.c @@ -48,18 +48,74 @@ #error "Bad: you didn't configure serial ..." #endif -void serial_setbrg (void) +#if defined(CONFIG_SERIAL_MULTI) +#include <serial.h> + +/* Multi serial device functions */ +#define DECLARE_S3C_SERIAL_FUNCTIONS(port) \ + int s3serial##port##_init (void) {\ + return serial_init_dev(port);}\ + void s3serial##port##_setbrg (void) {\ + serial_setbrg_dev(port);}\ + int s3serial##port##_getc (void) {\ + return serial_getc_dev(port);}\ + int s3serial##port##_tstc (void) {\ + return serial_tstc_dev(port);}\ + void s3serial##port##_putc (const char c) {\ + serial_putc_dev(port, c);}\ + void s3serial##port##_puts (const char *s) {\ + serial_puts_dev(port, s);} + +#define INIT_S3C_SERIAL_STRUCTURE(port,name,bus) {\ + name,\ + bus,\ + s3serial##port##_init,\ + s3serial##port##_setbrg,\ + s3serial##port##_getc,\ + s3serial##port##_tstc,\ + s3serial##port##_putc,\ + s3serial##port##_puts, } + +#endif /* CONFIG_SERIAL_MULTI */ + +void _serial_setbrg(const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); - int i; + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); unsigned int reg = 0; + int i; /* value is calculated so : (int)(PCLK/16./baudrate) -1 */ reg = get_PCLK() / (16 * gd->baudrate) - 1; + uart->UBRDIV = reg; + for (i = 0; i < 100; i++); +} +#if defined(CONFIG_SERIAL_MULTI) +static inline void +serial_setbrg_dev(unsigned int dev_index) +{ + _serial_setbrg(dev_index); +} +#else +void serial_setbrg(void) +{ + _serial_setbrg(UART_NR); +} +#endif + + +/* Initialise the serial port. The settings are always 8 data bits, no parity, + * 1 stop bit, no start bits. + */ +static int serial_init_dev(const int dev_index) +{ + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); + int i; + /* FIFO enable, Tx/Rx FIFO clear */ uart->UFCON = 0x07; uart->UMCON = 0x0; + /* Normal,No parity,1 stop,8 bit */ uart->ULCON = 0x3; /* @@ -67,40 +123,57 @@ * normal,interrupt or polling */ uart->UCON = 0x245; - uart->UBRDIV = reg; #ifdef CONFIG_HWFLOW uart->UMCON = 0x1; /* RTS up */ #endif - for (i = 0; i < 100; i++); + + /* FIXME: This is sooooooooooooooooooo ugly */ +#if defined(CONFIG_ARCH_GTA02_v1) || defined(CONFIG_ARCH_GTA02_v2) + /* we need auto hw flow control on the gsm and gps port */ + if (dev_index == 0 || dev_index == 1) + uart->UMCON = 0x10; +#endif + _serial_setbrg(dev_index); + + return (0); } -/* - * Initialise the serial port with the given baudrate. The settings - * are always 8 data bits, no parity, 1 stop bit, no start bits. - * +#if !defined(CONFIG_SERIAL_MULTI) +/* Initialise the serial port. The settings are always 8 data bits, no parity, + * 1 stop bit, no start bits. */ int serial_init (void) { - serial_setbrg (); - - return (0); + return serial_init_dev(UART_NR); } +#endif /* * Read a single byte from the serial port. Returns 1 on success, 0 * otherwise. When the function is succesfull, the character read is * written into its argument c. */ -int serial_getc (void) +int _serial_getc (const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); /* wait for character to arrive */ while (!(uart->UTRSTAT & 0x1)); return uart->URXH & 0xff; } +#if defined(CONFIG_SERIAL_MULTI) +static inline int serial_getc_dev(unsigned int dev_index) +{ + return _serial_getc(dev_index); +} +#else +int serial_getc (void) +{ + return _serial_getc(UART_NR); +} +#endif #ifdef CONFIG_HWFLOW static int hwflow = 0; /* turned off by default */ @@ -138,9 +211,9 @@ /* * Output a single byte to the serial port. */ -void serial_putc (const char c) +void _serial_putc (const char c, const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); #ifdef CONFIG_MODEM_SUPPORT if (be_quiet) return; @@ -161,23 +234,72 @@ if (c == '\n') serial_putc ('\r'); } +#if defined(CONFIG_SERIAL_MULTI) +static inline void serial_putc_dev(unsigned int dev_index, const char c) +{ + _serial_putc(c, dev_index); +} +#else +void serial_putc(const char c) +{ + _serial_putc(c, UART_NR); +} +#endif + /* * Test whether a character is in the RX buffer */ -int serial_tstc (void) +int _serial_tstc(const int dev_index) { - S3C24X0_UART * const uart = S3C24X0_GetBase_UART(UART_NR); + S3C24X0_UART * const uart = S3C24X0_GetBase_UART(dev_index); return uart->UTRSTAT & 0x1; } +#if defined(CONFIG_SERIAL_MULTI) +static inline int +serial_tstc_dev(unsigned int dev_index) +{ + return _serial_tstc(dev_index); +} +#else +int serial_tstc(void) +{ + return _serial_tstc(UART_NR); +} +#endif -void -serial_puts (const char *s) +void _serial_puts(const char *s, const int dev_index) { while (*s) { - serial_putc (*s++); + _serial_putc (*s++, dev_index); } } +#if defined(CONFIG_SERIAL_MULTI) +static inline void +serial_puts_dev(int dev_index, const char *s) +{ + _serial_puts(s, dev_index); +} +#else +void +serial_puts (const char *s) +{ + _serial_puts(s, UART_NR); +} +#endif + +#if defined(CONFIG_SERIAL_MULTI) +DECLARE_S3C_SERIAL_FUNCTIONS(0); +struct serial_device s3c24xx_serial0_device = + INIT_S3C_SERIAL_STRUCTURE(0, "s3ser0", "S3UART1"); +DECLARE_S3C_SERIAL_FUNCTIONS(1); +struct serial_device s3c24xx_serial1_device = + INIT_S3C_SERIAL_STRUCTURE(1, "s3ser1", "S3UART2"); +DECLARE_S3C_SERIAL_FUNCTIONS(2); +struct serial_device s3c24xx_serial2_device = + INIT_S3C_SERIAL_STRUCTURE(2, "s3ser2", "S3UART3"); + +#endif /* CONFIG_SERIAL_MULTI */ #endif /* defined(CONFIG_S3C2400) || defined (CONFIG_S3C2410) || defined (CONFIG_TRAB) */ Index: u-boot/include/serial.h =================================================================== --- u-boot.orig/include/serial.h +++ u-boot/include/serial.h @@ -35,6 +35,11 @@ #endif +#if defined(CONFIG_S3C2410) +extern struct serial_device s3c24xx_serial0_device; +extern struct serial_device s3c24xx_serial1_device; +extern struct serial_device s3c24xx_serial2_device; +#endif extern struct serial_device serial_ffuart_device; extern struct serial_device serial_btuart_device; -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

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[U-Boot-Users] [PATCH] ARM: arm920t: Allow use of 'gd' pointer from IRQ
by Harald Welte 04 Feb '08

04 Feb '08

This patch allows us to use the 'gd' pointer (and thus environment and everything else associated with it) from interrupt context on arm920t. Signed-off-by: Harald Welte <laforge(a)openmoko.org> Index: u-boot/cpu/arm920t/start.S =================================================================== --- u-boot.orig/cpu/arm920t/start.S +++ u-boot/cpu/arm920t/start.S @@ -415,12 +415,12 @@ .macro irq_save_user_regs sub sp, sp, #S_FRAME_SIZE stmia sp, {r0 - r12} @ Calling r0-r12 - add r8, sp, #S_PC - stmdb r8, {sp, lr}^ @ Calling SP, LR - str lr, [r8, #0] @ Save calling PC + add r7, sp, #S_PC + stmdb r7, {sp, lr}^ @ Calling SP, LR + str lr, [r7, #0] @ Save calling PC mrs r6, spsr - str r6, [r8, #4] @ Save CPSR - str r0, [r8, #8] @ Save OLD_R0 + str r6, [r7, #4] @ Save CPSR + str r0, [r7, #8] @ Save OLD_R0 mov r0, sp .endm -- - Harald Welte <laforge(a)openmoko.org> http://openmoko.org/ ============================================================================ Software for the world's first truly open Free Software mobile phone

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