January 2008 - U-Boot

[U-Boot-Users] resend#2 [PATCH 6/8] ColdFire: Add MCF547x_8x FEC driver
by Tsi-Chung Liew 12 Feb '08

12 Feb '08

Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- drivers/net/Makefile | 1 + drivers/net/fsl_mcdmafec.c | 582 ++++++++++++++++++++++++++++++++++++++++++++ net/eth.c | 4 + 3 files changed, 587 insertions(+), 0 deletions(-) create mode 100644 drivers/net/fsl_mcdmafec.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 41e1bde..b9723fa 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -33,6 +33,7 @@ COBJS-y += dm9000x.o COBJS-y += e1000.o COBJS-y += eepro100.o COBJS-y += enc28j60.o +COBJS-y += fsl_mcdmafec.o COBJS-y += inca-ip_sw.o COBJS-y += ks8695eth.o COBJS-y += lan91c96.o diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c new file mode 100644 index 0000000..5f6b730 --- /dev/null +++ b/drivers/net/fsl_mcdmafec.c @@ -0,0 +1,582 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <command.h> +#include <config.h> +#include <net.h> +#include <miiphy.h> + +#ifdef CONFIG_FSLDMAFEC +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1536 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) +#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) + +/* RxBD bits definitions */ +#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ + BD_ENET_RX_OV | BD_ENET_RX_TR) + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#include <asm/immap.h> +#include <asm/fsl_mcdmafec.h> + +#include "MCD_dma.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct fec_info_dma fec_info[] = { +#ifdef CFG_FEC0_IOBASE + { + 0, /* index */ + CFG_FEC0_IOBASE, /* io base */ + CFG_FEC0_PINMUX, /* gpio pin muxing */ + CFG_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_dma *)-1, /* next */ + FEC0_RX_TASK, /* rxTask */ + FEC0_TX_TASK, /* txTask */ + FEC0_RX_PRIORITY, /* rxPri */ + FEC0_TX_PRIORITY, /* txPri */ + FEC0_RX_INIT, /* rxInit */ + FEC0_TX_INIT, /* txInit */ + 0, /* usedTbdIndex */ + 0, /* cleanTbdNum */ + }, +#endif +#ifdef CFG_FEC1_IOBASE + { + 1, /* index */ + CFG_FEC1_IOBASE, /* io base */ + CFG_FEC1_PINMUX, /* gpio pin muxing */ + CFG_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_dma *)-1, /* next */ + FEC1_RX_TASK, /* rxTask */ + FEC1_TX_TASK, /* txTask */ + FEC1_RX_PRIORITY, /* rxPri */ + FEC1_TX_PRIORITY, /* txPri */ + FEC1_RX_INIT, /* rxInit */ + FEC1_TX_INIT, /* txInit */ + 0, /* usedTbdIndex */ + 0, /* cleanTbdNum */ + } +#endif +}; + +int fec_send(struct eth_device *dev, volatile void *packet, int length); +int fec_recv(struct eth_device *dev); +int fec_init(struct eth_device *dev, bd_t * bd); +void fec_halt(struct eth_device *dev); +extern int fecpin_setclear(struct eth_device *dev, int setclear); + +#ifdef CFG_DISCOVER_PHY +extern void mii_init(void); +extern uint mii_send(uint mii_cmd); +extern int mii_discover_phy(struct eth_device *dev); +extern int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +#endif + +#ifdef ET_DEBUG +void dbgFecRegs(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); + printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); + printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); + printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); + printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); + printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); + printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); + printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); + printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); + printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); + printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); + printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); + printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); + printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); + printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); + printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); + printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); + printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); +} +#endif + +void setFecDuplexSpeed(volatile fecdma_t * fecp, bd_t * bd, int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +int fec_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct fec_info_dma *info = dev->priv; + cbd_t *pTbd, *pUsedTbd; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + + /* process all the consumed TBDs */ + while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) { + pUsedTbd = &info->txbd[info->usedTbdIdx]; + if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { +#ifdef ET_DEBUG + printf("Cannot clean TBD %d, in use\n", + info->cleanTbdNum); +#endif + return 0; + } + + /* clean this buffer descriptor */ + if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1)) + pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; + else + pUsedTbd->cbd_sc = 0; + + /* update some indeces for a correct handling of the TBD ring */ + info->cleanTbdNum++; + info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER; + } + + /* Check for valid length of data. */ + if ((length > 1500) || (length <= 0)) { + return -1; + } + + /* Check the number of vacant TxBDs. */ + if (info->cleanTbdNum < 1) { + printf("No available TxBDs ...\n"); + return -1; + } + + /* Get the first TxBD to send the mac header */ + pTbd = &info->txbd[info->txIdx]; + pTbd->cbd_datlen = length; + pTbd->cbd_bufaddr = (u32) packet; + pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; + info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER; + + /* Enable DMA transmit task */ + MCD_continDma(info->txTask); + + info->cleanTbdNum -= 1; + + /* wait until frame is sent . */ + while (pTbd->cbd_sc & BD_ENET_TX_READY) { + udelay(10); + } + + return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); +} + +int fec_recv(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + + cbd_t *pRbd = &info->rxbd[info->rxIdx]; + u32 ievent; + int frame_length, len = 0; + + /* Check if any critical events have happened */ + ievent = fecp->eir; + if (ievent != 0) { + fecp->eir = ievent; + + if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { + printf("fec_recv: error\n"); + fec_halt(dev); + fec_init(dev, NULL); + return 0; + } + + if (ievent & FEC_EIR_HBERR) { + /* Heartbeat error */ + fecp->tcr |= FEC_TCR_GTS; + } + + if (ievent & FEC_EIR_GRA) { + /* Graceful stop complete */ + if (fecp->tcr & FEC_TCR_GTS) { + printf("fec_recv: tcr_gts\n"); + fec_halt(dev); + fecp->tcr &= ~FEC_TCR_GTS; + fec_init(dev, NULL); + } + } + } + + if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) { + if ((pRbd->cbd_sc & BD_ENET_RX_LAST) + && !(pRbd->cbd_sc & BD_ENET_RX_ERR) + && ((pRbd->cbd_datlen - 4) > 14)) { + + /* Get buffer address and size */ + frame_length = pRbd->cbd_datlen - 4; + + /* Fill the buffer and pass it to upper layers */ + NetReceive((volatile uchar *)pRbd->cbd_bufaddr, + frame_length); + len = frame_length; + } + + /* Reset buffer descriptor as empty */ + if ((info->rxIdx) == (PKTBUFSRX - 1)) + pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + else + pRbd->cbd_sc = BD_ENET_RX_EMPTY; + + pRbd->cbd_datlen = PKTSIZE_ALIGN; + + /* Now, we have an empty RxBD, restart the DMA receive task */ + MCD_continDma(info->rxTask); + + /* Increment BD count */ + info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; + } + + return len; +} + +void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) +{ + u8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + u32 crc = 0xffffffff; /* initial value */ + + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* Set individual hash table register */ + if (crc >= 32) { + fecp->ialr = (1 << (crc - 32)); + fecp->iaur = 0; + } else { + fecp->ialr = 0; + fecp->iaur = (1 << crc); + } + + /* Set physical address */ + fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; +} + +int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + int i; + +#ifdef ET_DEBUG + printf("fec_init: iobase 0x%08x ...\n", info->iobase); +#endif + + fecpin_setclear(dev, 1); + + fec_halt(dev); + +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CFG_DISCOVER_PHY) + + mii_init(); + + setFecDuplexSpeed(fecp, bd, info->dup_spd); +#else +#ifndef CFG_DISCOVER_PHY + setFecDuplexSpeed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CFG_FEC0_IOBASE) { + fec_set_hwaddr(fecp, bd->bi_enetaddr); + } else { + fec_set_hwaddr(fecp, bd->bi_enet1addr); + } + + /* Set Opcode/Pause Duration Register */ + fecp->opd = 0x00010020; + + /* Setup Buffers and Buffer Desriptors */ + info->rxIdx = 0; + info->txIdx = 0; + + /* Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: Empty, Wrap */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; + info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: Last, Tx CRC */ + for (i = 0; i < CFG_TX_ETH_BUFFER; i++) { + info->txbd[i].cbd_sc = 0; + info->txbd[i].cbd_datlen = 0; + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + + info->usedTbdIdx = 0; + info->cleanTbdNum = CFG_TX_ETH_BUFFER; + + /* Set Rx FIFO alarm and granularity value */ + fecp->rfcr = 0x0c000000; + fecp->rfar = 0x0000030c; + + /* Set Tx FIFO granularity value */ + fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; + fecp->tfar = 0x00000080; + + fecp->tfwr = 0x2; + fecp->ctcwr = 0x03000000; + + /* Enable DMA receive task */ + MCD_startDma(info->rxTask, /* Dma channel */ + (s8 *) info->rxbd, /*Source Address */ + 0, /* Source increment */ + (s8 *) (&fecp->rfdr), /* dest */ + 4, /* dest increment */ + 0, /* DMA size */ + 4, /* xfer size */ + info->rxInit, /* initiator */ + info->rxPri, /* priority */ + (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + ); + + /* Enable DMA tx task with no ready buffer descriptors */ + MCD_startDma(info->txTask, /* Dma channel */ + (s8 *) info->txbd, /*Source Address */ + 0, /* Source increment */ + (s8 *) (&fecp->tfdr), /* dest */ + 4, /* dest incr */ + 0, /* DMA size */ + 4, /* xfer size */ + info->txInit, /* initiator */ + info->txPri, /* priority */ + (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + ); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + return 1; +} + +void fec_halt(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + int counter = 0xffff; + + /* issue graceful stop command to the FEC transmitter if necessary */ + fecp->tcr |= FEC_TCR_GTS; + + /* wait for graceful stop to register */ + while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; + + /* Disable DMA tasks */ + MCD_killDma(info->txTask); + MCD_killDma(info->rxTask);; + + /* Disable the Ethernet Controller */ + fecp->ecr &= ~FEC_ECR_ETHER_EN; + + /* Clear FIFO status registers */ + fecp->rfsr &= FIFO_ERRSTAT; + fecp->tfsr &= FIFO_ERRSTAT; + + fecp->frst = 0x01000000; + + /* Issue a reset command to the FEC chip */ + fecp->ecr |= FEC_ECR_RESET; + + /* wait at least 20 clock cycles */ + udelay(10000); + +#ifdef ET_DEBUG + printf("Ethernet task stopped\n"); +#endif +} + +int mcdmafec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; + + for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + + dev = + (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ + fec_info[i].rxbd = + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + fec_info[i].txbd = + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *)memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); + +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *)memalign(CFG_CACHELINE_SIZE, 32); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + + if (i > 0) + fec_info[i - 1].next = &fec_info[i]; + } + fec_info[i - 1].next = &fec_info[0]; + + /* default speed */ + bis->bi_ethspeed = 10; + + return 1; +} + +#endif /* CONFIG_CMD_NET && CONFIG_NET_MULTI */ +#endif /* CONFIG_FSLDMAFEC */ diff --git a/net/eth.c b/net/eth.c index 5d9e9c1..bcd7d42 100644 --- a/net/eth.c +++ b/net/eth.c @@ -61,6 +61,7 @@ extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); extern int mcffec_initialize(bd_t*); +extern int mcdmafec_initialize(bd_t*); #ifdef CONFIG_API extern void (*push_packet)(volatile void *, int); @@ -272,6 +273,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MCFFEC) mcffec_initialize(bis); #endif +#if defined(CONFIG_FSLDMAFEC) + mcdmafec_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); -- 1.5.2

4 9

[U-Boot-Users] Please pull u-boot-83xx.git
by Kim Phillips 12 Feb '08

12 Feb '08

Wolfgang D., We're up to three versions of patches from different people to fix non-powerpc build breakage (due to the new SPI driver), so I decided to make this easy for you :) I've chosen and applied Ben Warren's version of the fix (which declares the new CONFIG_MPC8XXX_SPI define), along with some seemingly harmless TQM834x flash size fixes. Please pull: The following changes since commit 98b742489c09780be6a832eeaa4e5eff824792bb: Wolfgang Denk (1): inka4x0: remove dead code are available in the git repository at: git://www.denx.de/git/u-boot-mpc83xx.git Ben Warren (1): Fix conditional compilation of mpx8xxx_spi driver Jens Gehrlein (2): TQM834x: support for Spansion N-type Flashes (sector size = 256 KiB at 2x16 Bit). TQM834x: enable DHCP drivers/spi/mpc8xxx_spi.c | 4 ++-- include/configs/MPC8349EMDS.h | 1 + include/configs/TQM834x.h | 7 ++++--- 3 files changed, 7 insertions(+), 5 deletions(-) Danke schoen, Kim

4 3

[U-Boot-Users] Pull request: u-boot-freebsd
by Rafal Jaworowski 12 Feb '08

12 Feb '08

Dear Wolfgang, The following are two fixes which are needed in this release. Without these the build breaks when CONFIG_API is enabled. kind regards, Rafal The following changes since commit 98b742489c09780be6a832eeaa4e5eff824792bb: Wolfgang Denk (1): inka4x0: remove dead code are available in the git repository at: git://denx.de/git/u-boot-freebsd.git master Rafal Jaworowski (2): API: Convert conditional building to the new scheme. API: Provide dummy halt() in the glue layer. Makefile | 9 ++------- api/Makefile | 5 ++--- api_examples/Makefile | 20 +++++++++++++------- api_examples/libgenwrap.c | 7 ++++++- 4 files changed, 23 insertions(+), 18 deletions(-)

2 3

[U-Boot-Users] [PATCH v2] Remove #undef DEBUG from MPC83xx board header files
by Timur Tabi 12 Feb '08

12 Feb '08

Remove the "#undef DEBUG" line from all Freescale 83xx board header files. The inclusion of this line makes it impossible to enable debug code in other source files, because "#define DEBUG" typically needs to be defined before any header files are included. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- Added MPC8360ERDK.h. include/configs/MPC8323ERDB.h | 2 -- include/configs/MPC832XEMDS.h | 2 -- include/configs/MPC8349EMDS.h | 2 -- include/configs/MPC8360EMDS.h | 2 -- include/configs/MPC8360ERDK.h | 2 -- include/configs/MPC837XEMDS.h | 2 -- 6 files changed, 0 insertions(+), 12 deletions(-) diff --git a/include/configs/MPC8323ERDB.h b/include/configs/MPC8323ERDB.h index 4ea8709..0e33fce 100644 --- a/include/configs/MPC8323ERDB.h +++ b/include/configs/MPC8323ERDB.h @@ -9,8 +9,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG - /* * High Level Configuration Options */ diff --git a/include/configs/MPC832XEMDS.h b/include/configs/MPC832XEMDS.h index 25ac58c..8cf0a5b 100644 --- a/include/configs/MPC832XEMDS.h +++ b/include/configs/MPC832XEMDS.h @@ -20,8 +20,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 437a9a5..2c6534c 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -29,8 +29,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8360EMDS.h b/include/configs/MPC8360EMDS.h index fdacb90..310d03f 100644 --- a/include/configs/MPC8360EMDS.h +++ b/include/configs/MPC8360EMDS.h @@ -22,8 +22,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG - /* * High Level Configuration Options */ diff --git a/include/configs/MPC8360ERDK.h b/include/configs/MPC8360ERDK.h index 0f6f8f1..72d36c1 100644 --- a/include/configs/MPC8360ERDK.h +++ b/include/configs/MPC8360ERDK.h @@ -17,8 +17,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG - /* * High Level Configuration Options */ diff --git a/include/configs/MPC837XEMDS.h b/include/configs/MPC837XEMDS.h index 2b84e9c..61de084 100644 --- a/include/configs/MPC837XEMDS.h +++ b/include/configs/MPC837XEMDS.h @@ -21,8 +21,6 @@ #ifndef __CONFIG_H #define __CONFIG_H -#undef DEBUG - /* * High Level Configuration Options */ -- 1.5.2.4

4 5

[U-Boot-Users] [PATCH] 86xx: Fix compilation warning in sys_eprom.c
by Jon Loeliger 07 Feb '08

07 Feb '08

sys_eeprom.c:82:9: warning: unknown escape sequence '\/' Signed-off-by: Jon Loeliger <jdl(a)freescale.com> --- Wolfgang, Could you please apply this bugfix directly? Thanks, jdl board/freescale/common/sys_eeprom.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/board/freescale/common/sys_eeprom.c b/board/freescale/common/sys_eeprom.c index 44c0978..c8e17d0 100644 --- a/board/freescale/common/sys_eeprom.c +++ b/board/freescale/common/sys_eeprom.c @@ -79,7 +79,7 @@ int mac_show(void) /* Show Build Date, * BCD date values, as YYMMDDhhmmss. */ - printf("Date 20%02x\/%02x\/%02x %02x:%02x:%02x\n", + printf("Date 20%02x/%02x/%02x %02x:%02x:%02x\n", mac_data.date[0], mac_data.date[1], mac_data.date[2], -- 1.5.4.rc0

2 1

[U-Boot-Users] [PATCH v2] QE IO: Add initial data to pin configuration + read/write functions
by David Saada 07 Feb '08

07 Feb '08

On the MPC83xx & MPC85xx architectures that have QE, add initial data to the pin configuration table (qe_iop_conf_tab). QE initialization tables in all relevant boards were also replaced. In addition, add IO pin read & write functions. Signed-off-by: David Saada <david.saada(a)ecitele.com> diff -purN a/include/ioports.h b/include/ioports.h --- a/include/ioports.h 2008-01-02 13:39:04.000000000 +0200 +++ b/include/ioports.h 2008-01-06 10:20:40.342453000 +0200 @@ -60,6 +60,7 @@ typedef struct { int dir; int open_drain; int assign; + int data; } qe_iop_conf_t; #define QE_IOP_TAB_END (-1) diff -purN a/cpu/mpc85xx/cpu_init.c b/cpu/mpc85xx/cpu_init.c --- a/cpu/mpc85xx/cpu_init.c 2008-01-02 13:39:04.000000000 +0200 +++ b/cpu/mpc85xx/cpu_init.c 2008-01-06 10:27:18.963593000 +0200 @@ -37,14 +37,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, - int open_drain, int assign); + int open_drain, int assign, int data); extern void qe_init(uint qe_base); extern void qe_reset(void); static void config_qe_ioports(void) { u8 port, pin; - int dir, open_drain, assign; + int dir, open_drain, assign, data; int i; for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { @@ -53,7 +53,8 @@ static void config_qe_ioports(void) dir = qe_iop_conf_tab[i].dir; open_drain = qe_iop_conf_tab[i].open_drain; assign = qe_iop_conf_tab[i].assign; - qe_config_iopin(port, pin, dir, open_drain, assign); + data = qe_iop_conf_tab[i].data; + qe_config_iopin(port, pin, dir, open_drain, assign, data); } } #endif diff -purN a/cpu/mpc85xx/qe_io.c b/cpu/mpc85xx/qe_io.c --- a/cpu/mpc85xx/qe_io.c 2008-01-02 13:39:04.000000000 +0200 +++ b/cpu/mpc85xx/qe_io.c 2008-01-06 10:54:24.201604000 +0200 @@ -27,7 +27,7 @@ #if defined(CONFIG_QE) #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign, int data) { u32 pin_2bit_mask; u32 pin_2bit_dir; @@ -38,6 +38,16 @@ void qe_config_iopin(u8 port, u8 pin, in volatile par_io_t *par_io = (volatile par_io_t *) &(gur->qe_par_io); + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the data */ + tmp_val = in_be32(&par_io[port].cpdat); + if (data) + out_be32(&par_io[port].cpdat, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpdat, ~pin_1bit_mask & tmp_val); + /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); @@ -55,9 +65,6 @@ void qe_config_iopin(u8 port, u8 pin, in out_be32(&par_io[port].cpdir1, pin_2bit_dir | tmp_val); } - /* Calculate pin location for 1bit mask */ - pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); - /* Setup the open drain */ tmp_val = in_be32(&par_io[port].cpodr); if (open_drain) @@ -82,4 +89,39 @@ void qe_config_iopin(u8 port, u8 pin, in } } +void qe_read_iopin(u8 port, u8 pin, int *data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile par_io_t *par_io = (volatile par_io_t *) + &(gur->qe_par_io); + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Read the data */ + tmp_val = in_be32(&par_io[port].cpdat); + *data = (tmp_val >> (NUM_OF_PINS - (pin+1))) & 0x1; +} + +void qe_write_iopin(u8 port, u8 pin, int data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + volatile ccsr_gur_t *gur = (void *)(CFG_MPC85xx_GUTS_ADDR); + volatile par_io_t *par_io = (volatile par_io_t *) + &(gur->qe_par_io); + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Write the data */ + tmp_val = in_be32(&par_io[port].cpdat); + if (data) + out_be32(&par_io[port].cpdat, pin_1bit_mask | tmp_val); + else + out_be32(&par_io[port].cpdat, ~pin_1bit_mask & tmp_val); +} + #endif /* CONFIG_QE */ diff -purN a/cpu/mpc83xx/cpu_init.c b/cpu/mpc83xx/cpu_init.c --- a/cpu/mpc83xx/cpu_init.c 2008-01-16 23:06:52.000000000 +0200 +++ b/cpu/mpc83xx/cpu_init.c 2008-01-17 15:32:37.791769000 +0200 @@ -29,14 +29,14 @@ DECLARE_GLOBAL_DATA_PTR; #ifdef CONFIG_QE extern qe_iop_conf_t qe_iop_conf_tab[]; extern void qe_config_iopin(u8 port, u8 pin, int dir, - int open_drain, int assign); + int open_drain, int assign, int data); extern void qe_init(uint qe_base); extern void qe_reset(void); static void config_qe_ioports(void) { u8 port, pin; - int dir, open_drain, assign; + int dir, open_drain, assign, data; int i; for (i = 0; qe_iop_conf_tab[i].assign != QE_IOP_TAB_END; i++) { @@ -45,7 +45,8 @@ static void config_qe_ioports(void) dir = qe_iop_conf_tab[i].dir; open_drain = qe_iop_conf_tab[i].open_drain; assign = qe_iop_conf_tab[i].assign; - qe_config_iopin(port, pin, dir, open_drain, assign); + data = qe_iop_conf_tab[i].data; + qe_config_iopin(port, pin, dir, open_drain, assign, data); } } #endif diff -purN a/cpu/mpc83xx/qe_io.c b/cpu/mpc83xx/qe_io.c --- a/cpu/mpc83xx/qe_io.c 2008-01-02 13:39:04.000000000 +0200 +++ b/cpu/mpc83xx/qe_io.c 2008-01-06 10:59:54.410427000 +0200 @@ -27,7 +27,7 @@ #if defined(CONFIG_QE) #define NUM_OF_PINS 32 -void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign) +void qe_config_iopin(u8 port, u8 pin, int dir, int open_drain, int assign, int data) { u32 pin_2bit_mask; u32 pin_2bit_dir; @@ -37,6 +37,17 @@ void qe_config_iopin(u8 port, u8 pin, in volatile immap_t *im = (volatile immap_t *)CFG_IMMR; volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the data */ + tmp_val = in_be32(&par_io->ioport[port].pdat); + if (data) { + out_be32(&par_io->ioport[port].pdat, pin_1bit_mask | tmp_val); + } else { + out_be32(&par_io->ioport[port].pdat, ~pin_1bit_mask & tmp_val); + } + /* Caculate pin location and 2bit mask and dir */ pin_2bit_mask = (u32)(0x3 << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); pin_2bit_dir = (u32)(dir << (NUM_OF_PINS-(pin%(NUM_OF_PINS/2)+1)*2)); @@ -54,9 +65,6 @@ void qe_config_iopin(u8 port, u8 pin, in out_be32(&par_io->ioport[port].dir1, pin_2bit_dir | tmp_val); } - /* Calculate pin location for 1bit mask */ - pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); - /* Setup the open drain */ tmp_val = in_be32(&par_io->ioport[port].podr); if (open_drain) { @@ -82,4 +90,38 @@ void qe_config_iopin(u8 port, u8 pin, in } } +void qe_read_iopin(u8 port, u8 pin, int *data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Read the data */ + tmp_val = in_be32(&par_io->ioport[port].pdat); + *data = (tmp_val >> (NUM_OF_PINS - (pin+1))) & 0x1; +} + +void qe_write_iopin(u8 port, u8 pin, int data) +{ + u32 pin_1bit_mask; + u32 tmp_val; + volatile immap_t *im = (volatile immap_t *)CFG_IMMR; + volatile qepio83xx_t *par_io = (volatile qepio83xx_t *)&im->qepio; + + /* Calculate pin location for 1bit mask */ + pin_1bit_mask = (u32)(1 << (NUM_OF_PINS - (pin+1))); + + /* Setup the data */ + tmp_val = in_be32(&par_io->ioport[port].pdat); + if (data) { + out_be32(&par_io->ioport[port].pdat, pin_1bit_mask | tmp_val); + } else { + out_be32(&par_io->ioport[port].pdat, ~pin_1bit_mask & tmp_val); + } +} + #endif /* CONFIG_QE */ diff -purN a/board/freescale/mpc8360emds/mpc8360emds.c b/board/freescale/mpc8360emds/mpc8360emds.c --- a/board/freescale/mpc8360emds/mpc8360emds.c 2008-01-16 23:06:51.000000000 +0200 +++ b/board/freescale/mpc8360emds/mpc8360emds.c 2008-01-17 16:03:27.428958000 +0200 @@ -34,63 +34,63 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {1, 6, 1, 0, 3}, /* TxD4 */ - {1, 7, 1, 0, 1}, /* TxD5 */ - {1, 9, 1, 0, 2}, /* TxD6 */ - {1, 10, 1, 0, 2}, /* TxD7 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 13, 2, 0, 1}, /* RxD4 */ - {1, 1, 2, 0, 2}, /* RxD5 */ - {1, 0, 2, 0, 2}, /* RxD6 */ - {1, 4, 2, 0, 2}, /* RxD7 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 16, 2, 0, 1}, /* RX_ER */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + {0, 3, 1, 0, 1, 0}, /* TxD0 */ + {0, 4, 1, 0, 1, 0}, /* TxD1 */ + {0, 5, 1, 0, 1, 0}, /* TxD2 */ + {0, 6, 1, 0, 1, 0}, /* TxD3 */ + {1, 6, 1, 0, 3, 0}, /* TxD4 */ + {1, 7, 1, 0, 1, 0}, /* TxD5 */ + {1, 9, 1, 0, 2, 0}, /* TxD6 */ + {1, 10, 1, 0, 2, 0}, /* TxD7 */ + {0, 9, 2, 0, 1, 0}, /* RxD0 */ + {0, 10, 2, 0, 1, 0}, /* RxD1 */ + {0, 11, 2, 0, 1, 0}, /* RxD2 */ + {0, 12, 2, 0, 1, 0}, /* RxD3 */ + {0, 13, 2, 0, 1, 0}, /* RxD4 */ + {1, 1, 2, 0, 2, 0}, /* RxD5 */ + {1, 0, 2, 0, 2, 0}, /* RxD6 */ + {1, 4, 2, 0, 2, 0}, /* RxD7 */ + {0, 7, 1, 0, 1, 0}, /* TX_EN */ + {0, 8, 1, 0, 1, 0}, /* TX_ER */ + {0, 15, 2, 0, 1, 0}, /* RX_DV */ + {0, 16, 2, 0, 1, 0}, /* RX_ER */ + {0, 0, 2, 0, 1, 0}, /* RX_CLK */ + {2, 9, 1, 0, 3, 0}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1, 0}, /* GTX125 - CLK9 */ /* GETH2 */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {1, 2, 1, 0, 1}, /* TxD4 */ - {1, 3, 1, 0, 2}, /* TxD5 */ - {1, 5, 1, 0, 3}, /* TxD6 */ - {1, 8, 1, 0, 3}, /* TxD7 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 27, 2, 0, 1}, /* RxD4 */ - {1, 12, 2, 0, 2}, /* RxD5 */ - {1, 13, 2, 0, 3}, /* RxD6 */ - {1, 11, 2, 0, 2}, /* RxD7 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 30, 2, 0, 1}, /* RX_ER */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK = CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ - - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ - - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ + {0, 17, 1, 0, 1, 0}, /* TxD0 */ + {0, 18, 1, 0, 1, 0}, /* TxD1 */ + {0, 19, 1, 0, 1, 0}, /* TxD2 */ + {0, 20, 1, 0, 1, 0}, /* TxD3 */ + {1, 2, 1, 0, 1, 0}, /* TxD4 */ + {1, 3, 1, 0, 2, 0}, /* TxD5 */ + {1, 5, 1, 0, 3, 0}, /* TxD6 */ + {1, 8, 1, 0, 3, 0}, /* TxD7 */ + {0, 23, 2, 0, 1, 0}, /* RxD0 */ + {0, 24, 2, 0, 1, 0}, /* RxD1 */ + {0, 25, 2, 0, 1, 0}, /* RxD2 */ + {0, 26, 2, 0, 1, 0}, /* RxD3 */ + {0, 27, 2, 0, 1, 0}, /* RxD4 */ + {1, 12, 2, 0, 2, 0}, /* RxD5 */ + {1, 13, 2, 0, 3, 0}, /* RxD6 */ + {1, 11, 2, 0, 2, 0}, /* RxD7 */ + {0, 21, 1, 0, 1, 0}, /* TX_EN */ + {0, 22, 1, 0, 1, 0}, /* TX_ER */ + {0, 29, 2, 0, 1, 0}, /* RX_DV */ + {0, 30, 2, 0, 1, 0}, /* RX_ER */ + {0, 31, 2, 0, 1, 0}, /* RX_CLK */ + {2, 2, 1, 0, 2, 0}, /* GTX_CLK = CLK10 */ + {2, 3, 2, 0, 1, 0}, /* GTX125 - CLK4 */ + + {0, 1, 3, 0, 2, 0}, /* MDIO */ + {0, 2, 1, 0, 1, 0}, /* MDC */ + + {5, 0, 1, 0, 2, 0}, /* UART2_SOUT */ + {5, 1, 2, 0, 3, 0}, /* UART2_CTS */ + {5, 2, 1, 0, 1, 0}, /* UART2_RTS */ + {5, 3, 2, 0, 2, 0}, /* UART2_SIN */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, 0}, /* END of table */ }; int board_early_init_f(void) diff -purN a/board/freescale/mpc8360erdk/mpc8360erdk.c b/board/freescale/mpc8360erdk/mpc8360erdk.c --- a/board/freescale/mpc8360erdk/mpc8360erdk.c 2008-01-16 23:06:52.000000000 +0200 +++ b/board/freescale/mpc8360erdk/mpc8360erdk.c 2008-01-17 16:07:14.451836000 +0200 @@ -27,168 +27,168 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* MDIO */ - {0, 1, 3, 0, 2}, /* MDIO */ - {0, 2, 1, 0, 1}, /* MDC */ + {0, 1, 3, 0, 2, 0}, /* MDIO */ + {0, 2, 1, 0, 1, 0}, /* MDC */ /* UCC1 - UEC (Gigabit) */ - {0, 3, 1, 0, 1}, /* TxD0 */ - {0, 4, 1, 0, 1}, /* TxD1 */ - {0, 5, 1, 0, 1}, /* TxD2 */ - {0, 6, 1, 0, 1}, /* TxD3 */ - {0, 9, 2, 0, 1}, /* RxD0 */ - {0, 10, 2, 0, 1}, /* RxD1 */ - {0, 11, 2, 0, 1}, /* RxD2 */ - {0, 12, 2, 0, 1}, /* RxD3 */ - {0, 7, 1, 0, 1}, /* TX_EN */ - {0, 8, 1, 0, 1}, /* TX_ER */ - {0, 15, 2, 0, 1}, /* RX_DV */ - {0, 0, 2, 0, 1}, /* RX_CLK */ - {2, 9, 1, 0, 3}, /* GTX_CLK - CLK10 */ - {2, 8, 2, 0, 1}, /* GTX125 - CLK9 */ + {0, 3, 1, 0, 1, 0}, /* TxD0 */ + {0, 4, 1, 0, 1, 0}, /* TxD1 */ + {0, 5, 1, 0, 1, 0}, /* TxD2 */ + {0, 6, 1, 0, 1, 0}, /* TxD3 */ + {0, 9, 2, 0, 1, 0}, /* RxD0 */ + {0, 10, 2, 0, 1, 0}, /* RxD1 */ + {0, 11, 2, 0, 1, 0}, /* RxD2 */ + {0, 12, 2, 0, 1, 0}, /* RxD3 */ + {0, 7, 1, 0, 1, 0}, /* TX_EN */ + {0, 8, 1, 0, 1, 0}, /* TX_ER */ + {0, 15, 2, 0, 1, 0}, /* RX_DV */ + {0, 0, 2, 0, 1, 0}, /* RX_CLK */ + {2, 9, 1, 0, 3, 0}, /* GTX_CLK - CLK10 */ + {2, 8, 2, 0, 1, 0}, /* GTX125 - CLK9 */ /* UCC2 - UEC (Gigabit) */ - {0, 17, 1, 0, 1}, /* TxD0 */ - {0, 18, 1, 0, 1}, /* TxD1 */ - {0, 19, 1, 0, 1}, /* TxD2 */ - {0, 20, 1, 0, 1}, /* TxD3 */ - {0, 23, 2, 0, 1}, /* RxD0 */ - {0, 24, 2, 0, 1}, /* RxD1 */ - {0, 25, 2, 0, 1}, /* RxD2 */ - {0, 26, 2, 0, 1}, /* RxD3 */ - {0, 21, 1, 0, 1}, /* TX_EN */ - {0, 22, 1, 0, 1}, /* TX_ER */ - {0, 29, 2, 0, 1}, /* RX_DV */ - {0, 31, 2, 0, 1}, /* RX_CLK */ - {2, 2, 1, 0, 2}, /* GTX_CLK - CLK10 */ - {2, 3, 2, 0, 1}, /* GTX125 - CLK4 */ + {0, 17, 1, 0, 1, 0}, /* TxD0 */ + {0, 18, 1, 0, 1, 0}, /* TxD1 */ + {0, 19, 1, 0, 1, 0}, /* TxD2 */ + {0, 20, 1, 0, 1, 0}, /* TxD3 */ + {0, 23, 2, 0, 1, 0}, /* RxD0 */ + {0, 24, 2, 0, 1, 0}, /* RxD1 */ + {0, 25, 2, 0, 1, 0}, /* RxD2 */ + {0, 26, 2, 0, 1, 0}, /* RxD3 */ + {0, 21, 1, 0, 1, 0}, /* TX_EN */ + {0, 22, 1, 0, 1, 0}, /* TX_ER */ + {0, 29, 2, 0, 1, 0}, /* RX_DV */ + {0, 31, 2, 0, 1, 0}, /* RX_CLK */ + {2, 2, 1, 0, 2, 0}, /* GTX_CLK - CLK10 */ + {2, 3, 2, 0, 1, 0}, /* GTX125 - CLK4 */ /* UCC7 - UEC */ - {4, 0, 1, 0, 1}, /* TxD0 */ - {4, 1, 1, 0, 1}, /* TxD1 */ - {4, 2, 1, 0, 1}, /* TxD2 */ - {4, 3, 1, 0, 1}, /* TxD3 */ - {4, 6, 2, 0, 1}, /* RxD0 */ - {4, 7, 2, 0, 1}, /* RxD1 */ - {4, 8, 2, 0, 1}, /* RxD2 */ - {4, 9, 2, 0, 1}, /* RxD3 */ - {4, 4, 1, 0, 1}, /* TX_EN */ - {4, 5, 1, 0, 1}, /* TX_ER */ - {4, 12, 2, 0, 1}, /* RX_DV */ - {4, 13, 2, 0, 1}, /* RX_ER */ - {4, 10, 2, 0, 1}, /* COL */ - {4, 11, 2, 0, 1}, /* CRS */ - {2, 18, 2, 0, 1}, /* TX_CLK - CLK19 */ - {2, 19, 2, 0, 1}, /* RX_CLK - CLK20 */ + {4, 0, 1, 0, 1, 0}, /* TxD0 */ + {4, 1, 1, 0, 1, 0}, /* TxD1 */ + {4, 2, 1, 0, 1, 0}, /* TxD2 */ + {4, 3, 1, 0, 1, 0}, /* TxD3 */ + {4, 6, 2, 0, 1, 0}, /* RxD0 */ + {4, 7, 2, 0, 1, 0}, /* RxD1 */ + {4, 8, 2, 0, 1, 0}, /* RxD2 */ + {4, 9, 2, 0, 1, 0}, /* RxD3 */ + {4, 4, 1, 0, 1, 0}, /* TX_EN */ + {4, 5, 1, 0, 1, 0}, /* TX_ER */ + {4, 12, 2, 0, 1, 0}, /* RX_DV */ + {4, 13, 2, 0, 1, 0}, /* RX_ER */ + {4, 10, 2, 0, 1, 0}, /* COL */ + {4, 11, 2, 0, 1, 0}, /* CRS */ + {2, 18, 2, 0, 1, 0}, /* TX_CLK - CLK19 */ + {2, 19, 2, 0, 1, 0}, /* RX_CLK - CLK20 */ /* UCC4 - UEC */ - {1, 14, 1, 0, 1}, /* TxD0 */ - {1, 15, 1, 0, 1}, /* TxD1 */ - {1, 16, 1, 0, 1}, /* TxD2 */ - {1, 17, 1, 0, 1}, /* TxD3 */ - {1, 20, 2, 0, 1}, /* RxD0 */ - {1, 21, 2, 0, 1}, /* RxD1 */ - {1, 22, 2, 0, 1}, /* RxD2 */ - {1, 23, 2, 0, 1}, /* RxD3 */ - {1, 18, 1, 0, 1}, /* TX_EN */ - {1, 19, 1, 0, 2}, /* TX_ER */ - {1, 26, 2, 0, 1}, /* RX_DV */ - {1, 27, 2, 0, 1}, /* RX_ER */ - {1, 24, 2, 0, 1}, /* COL */ - {1, 25, 2, 0, 1}, /* CRS */ - {2, 6, 2, 0, 1}, /* TX_CLK - CLK7 */ - {2, 7, 2, 0, 1}, /* RX_CLK - CLK8 */ + {1, 14, 1, 0, 1, 0}, /* TxD0 */ + {1, 15, 1, 0, 1, 0}, /* TxD1 */ + {1, 16, 1, 0, 1, 0}, /* TxD2 */ + {1, 17, 1, 0, 1, 0}, /* TxD3 */ + {1, 20, 2, 0, 1, 0}, /* RxD0 */ + {1, 21, 2, 0, 1, 0}, /* RxD1 */ + {1, 22, 2, 0, 1, 0}, /* RxD2 */ + {1, 23, 2, 0, 1, 0}, /* RxD3 */ + {1, 18, 1, 0, 1, 0}, /* TX_EN */ + {1, 19, 1, 0, 2, 0}, /* TX_ER */ + {1, 26, 2, 0, 1, 0}, /* RX_DV */ + {1, 27, 2, 0, 1, 0}, /* RX_ER */ + {1, 24, 2, 0, 1, 0}, /* COL */ + {1, 25, 2, 0, 1, 0}, /* CRS */ + {2, 6, 2, 0, 1, 0}, /* TX_CLK - CLK7 */ + {2, 7, 2, 0, 1, 0}, /* RX_CLK - CLK8 */ /* PCI1 */ - {5, 4, 2, 0, 3}, /* PCI_M66EN */ - {5, 5, 1, 0, 3}, /* PCI_INTA */ - {5, 6, 1, 0, 3}, /* PCI_RSTO */ - {5, 7, 3, 0, 3}, /* PCI_C_BE0 */ - {5, 8, 3, 0, 3}, /* PCI_C_BE1 */ - {5, 9, 3, 0, 3}, /* PCI_C_BE2 */ - {5, 10, 3, 0, 3}, /* PCI_C_BE3 */ - {5, 11, 3, 0, 3}, /* PCI_PAR */ - {5, 12, 3, 0, 3}, /* PCI_FRAME */ - {5, 13, 3, 0, 3}, /* PCI_TRDY */ - {5, 14, 3, 0, 3}, /* PCI_IRDY */ - {5, 15, 3, 0, 3}, /* PCI_STOP */ - {5, 16, 3, 0, 3}, /* PCI_DEVSEL */ - {5, 17, 0, 0, 0}, /* PCI_IDSEL */ - {5, 18, 3, 0, 3}, /* PCI_SERR */ - {5, 19, 3, 0, 3}, /* PCI_PERR */ - {5, 20, 3, 0, 3}, /* PCI_REQ0 */ - {5, 21, 2, 0, 3}, /* PCI_REQ1 */ - {5, 22, 2, 0, 3}, /* PCI_GNT2 */ - {5, 23, 3, 0, 3}, /* PCI_GNT0 */ - {5, 24, 1, 0, 3}, /* PCI_GNT1 */ - {5, 25, 1, 0, 3}, /* PCI_GNT2 */ - {5, 26, 0, 0, 0}, /* PCI_CLK0 */ - {5, 27, 0, 0, 0}, /* PCI_CLK1 */ - {5, 28, 0, 0, 0}, /* PCI_CLK2 */ - {5, 29, 0, 0, 3}, /* PCI_SYNC_OUT */ - {6, 0, 3, 0, 3}, /* PCI_AD0 */ - {6, 1, 3, 0, 3}, /* PCI_AD1 */ - {6, 2, 3, 0, 3}, /* PCI_AD2 */ - {6, 3, 3, 0, 3}, /* PCI_AD3 */ - {6, 4, 3, 0, 3}, /* PCI_AD4 */ - {6, 5, 3, 0, 3}, /* PCI_AD5 */ - {6, 6, 3, 0, 3}, /* PCI_AD6 */ - {6, 7, 3, 0, 3}, /* PCI_AD7 */ - {6, 8, 3, 0, 3}, /* PCI_AD8 */ - {6, 9, 3, 0, 3}, /* PCI_AD9 */ - {6, 10, 3, 0, 3}, /* PCI_AD10 */ - {6, 11, 3, 0, 3}, /* PCI_AD11 */ - {6, 12, 3, 0, 3}, /* PCI_AD12 */ - {6, 13, 3, 0, 3}, /* PCI_AD13 */ - {6, 14, 3, 0, 3}, /* PCI_AD14 */ - {6, 15, 3, 0, 3}, /* PCI_AD15 */ - {6, 16, 3, 0, 3}, /* PCI_AD16 */ - {6, 17, 3, 0, 3}, /* PCI_AD17 */ - {6, 18, 3, 0, 3}, /* PCI_AD18 */ - {6, 19, 3, 0, 3}, /* PCI_AD19 */ - {6, 20, 3, 0, 3}, /* PCI_AD20 */ - {6, 21, 3, 0, 3}, /* PCI_AD21 */ - {6, 22, 3, 0, 3}, /* PCI_AD22 */ - {6, 23, 3, 0, 3}, /* PCI_AD23 */ - {6, 24, 3, 0, 3}, /* PCI_AD24 */ - {6, 25, 3, 0, 3}, /* PCI_AD25 */ - {6, 26, 3, 0, 3}, /* PCI_AD26 */ - {6, 27, 3, 0, 3}, /* PCI_AD27 */ - {6, 28, 3, 0, 3}, /* PCI_AD28 */ - {6, 29, 3, 0, 3}, /* PCI_AD29 */ - {6, 30, 3, 0, 3}, /* PCI_AD30 */ - {6, 31, 3, 0, 3}, /* PCI_AD31 */ + {5, 4, 2, 0, 3, 0}, /* PCI_M66EN */ + {5, 5, 1, 0, 3, 0}, /* PCI_INTA */ + {5, 6, 1, 0, 3, 0}, /* PCI_RSTO */ + {5, 7, 3, 0, 3, 0}, /* PCI_C_BE0 */ + {5, 8, 3, 0, 3, 0}, /* PCI_C_BE1 */ + {5, 9, 3, 0, 3, 0}, /* PCI_C_BE2 */ + {5, 10, 3, 0, 3, 0}, /* PCI_C_BE3 */ + {5, 11, 3, 0, 3, 0}, /* PCI_PAR */ + {5, 12, 3, 0, 3, 0}, /* PCI_FRAME */ + {5, 13, 3, 0, 3, 0}, /* PCI_TRDY */ + {5, 14, 3, 0, 3, 0}, /* PCI_IRDY */ + {5, 15, 3, 0, 3, 0}, /* PCI_STOP */ + {5, 16, 3, 0, 3, 0}, /* PCI_DEVSEL */ + {5, 17, 0, 0, 0, 0}, /* PCI_IDSEL */ + {5, 18, 3, 0, 3, 0}, /* PCI_SERR */ + {5, 19, 3, 0, 3, 0}, /* PCI_PERR */ + {5, 20, 3, 0, 3, 0}, /* PCI_REQ0 */ + {5, 21, 2, 0, 3, 0}, /* PCI_REQ1 */ + {5, 22, 2, 0, 3, 0}, /* PCI_GNT2 */ + {5, 23, 3, 0, 3, 0}, /* PCI_GNT0 */ + {5, 24, 1, 0, 3, 0}, /* PCI_GNT1 */ + {5, 25, 1, 0, 3, 0}, /* PCI_GNT2 */ + {5, 26, 0, 0, 0, 0}, /* PCI_CLK0 */ + {5, 27, 0, 0, 0, 0}, /* PCI_CLK1 */ + {5, 28, 0, 0, 0, 0}, /* PCI_CLK2 */ + {5, 29, 0, 0, 3, 0}, /* PCI_SYNC_OUT */ + {6, 0, 3, 0, 3, 0}, /* PCI_AD0 */ + {6, 1, 3, 0, 3, 0}, /* PCI_AD1 */ + {6, 2, 3, 0, 3, 0}, /* PCI_AD2 */ + {6, 3, 3, 0, 3, 0}, /* PCI_AD3 */ + {6, 4, 3, 0, 3, 0}, /* PCI_AD4 */ + {6, 5, 3, 0, 3, 0}, /* PCI_AD5 */ + {6, 6, 3, 0, 3, 0}, /* PCI_AD6 */ + {6, 7, 3, 0, 3, 0}, /* PCI_AD7 */ + {6, 8, 3, 0, 3, 0}, /* PCI_AD8 */ + {6, 9, 3, 0, 3, 0}, /* PCI_AD9 */ + {6, 10, 3, 0, 3, 0}, /* PCI_AD10 */ + {6, 11, 3, 0, 3, 0}, /* PCI_AD11 */ + {6, 12, 3, 0, 3, 0}, /* PCI_AD12 */ + {6, 13, 3, 0, 3, 0}, /* PCI_AD13 */ + {6, 14, 3, 0, 3, 0}, /* PCI_AD14 */ + {6, 15, 3, 0, 3, 0}, /* PCI_AD15 */ + {6, 16, 3, 0, 3, 0}, /* PCI_AD16 */ + {6, 17, 3, 0, 3, 0}, /* PCI_AD17 */ + {6, 18, 3, 0, 3, 0}, /* PCI_AD18 */ + {6, 19, 3, 0, 3, 0}, /* PCI_AD19 */ + {6, 20, 3, 0, 3, 0}, /* PCI_AD20 */ + {6, 21, 3, 0, 3, 0}, /* PCI_AD21 */ + {6, 22, 3, 0, 3, 0}, /* PCI_AD22 */ + {6, 23, 3, 0, 3, 0}, /* PCI_AD23 */ + {6, 24, 3, 0, 3, 0}, /* PCI_AD24 */ + {6, 25, 3, 0, 3, 0}, /* PCI_AD25 */ + {6, 26, 3, 0, 3, 0}, /* PCI_AD26 */ + {6, 27, 3, 0, 3, 0}, /* PCI_AD27 */ + {6, 28, 3, 0, 3, 0}, /* PCI_AD28 */ + {6, 29, 3, 0, 3, 0}, /* PCI_AD29 */ + {6, 30, 3, 0, 3, 0}, /* PCI_AD30 */ + {6, 31, 3, 0, 3, 0}, /* PCI_AD31 */ /* NAND */ - {4, 18, 2, 0, 0}, /* NAND_RYnBY */ + {4, 18, 2, 0, 0, 0}, /* NAND_RYnBY */ /* DUART - UART2 */ - {5, 0, 1, 0, 2}, /* UART2_SOUT */ - {5, 2, 1, 0, 1}, /* UART2_RTS */ - {5, 3, 2, 0, 2}, /* UART2_SIN */ - {5, 1, 2, 0, 3}, /* UART2_CTS */ + {5, 0, 1, 0, 2, 0}, /* UART2_SOUT */ + {5, 2, 1, 0, 1, 0}, /* UART2_RTS */ + {5, 3, 2, 0, 2, 0}, /* UART2_SIN */ + {5, 1, 2, 0, 3, 0}, /* UART2_CTS */ /* UCC5 - UART3 */ - {3, 0, 1, 0, 1}, /* UART3_TX */ - {3, 4, 1, 0, 1}, /* UART3_RTS */ - {3, 6, 2, 0, 1}, /* UART3_RX */ - {3, 12, 2, 0, 0}, /* UART3_CTS */ - {3, 13, 2, 0, 0}, /* UCC5_CD */ + {3, 0, 1, 0, 1, 0}, /* UART3_TX */ + {3, 4, 1, 0, 1, 0}, /* UART3_RTS */ + {3, 6, 2, 0, 1, 0}, /* UART3_RX */ + {3, 12, 2, 0, 0, 0}, /* UART3_CTS */ + {3, 13, 2, 0, 0, 0}, /* UCC5_CD */ /* UCC6 - UART4 */ - {3, 14, 1, 0, 1}, /* UART4_TX */ - {3, 18, 1, 0, 1}, /* UART4_RTS */ - {3, 20, 2, 0, 1}, /* UART4_RX */ - {3, 26, 2, 0, 0}, /* UART4_CTS */ - {3, 27, 2, 0, 0}, /* UCC6_CD */ + {3, 14, 1, 0, 1, 0}, /* UART4_TX */ + {3, 18, 1, 0, 1, 0}, /* UART4_RTS */ + {3, 20, 2, 0, 1, 0}, /* UART4_RX */ + {3, 26, 2, 0, 0, 0}, /* UART4_CTS */ + {3, 27, 2, 0, 0, 0}, /* UCC6_CD */ /* Fujitsu MB86277 (MINT) graphics controller */ - {0, 30, 1, 0, 0}, /* nSRESET_GRAPHICS */ - {1, 5, 1, 0, 0}, /* nXRST_GRAPHICS */ - {1, 7, 1, 0, 0}, /* LVDS_BKLT_CTR */ - {2, 16, 1, 0, 0}, /* LVDS_BKLT_EN */ + {0, 30, 1, 0, 0, 0}, /* nSRESET_GRAPHICS */ + {1, 5, 1, 0, 0, 0}, /* nXRST_GRAPHICS */ + {1, 7, 1, 0, 0, 0}, /* LVDS_BKLT_CTR */ + {2, 16, 1, 0, 0, 0}, /* LVDS_BKLT_EN */ /* END of table */ - {0, 0, 0, 0, QE_IOP_TAB_END}, + {0, 0, 0, 0, QE_IOP_TAB_END, 0}, }; int board_early_init_f(void) diff -purN a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c --- a/board/freescale/mpc8568mds/mpc8568mds.c 2008-01-16 23:06:52.000000000 +0200 +++ b/board/freescale/mpc8568mds/mpc8568mds.c 2008-01-17 16:03:46.708593000 +0200 @@ -37,64 +37,64 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* GETH1 */ - {4, 10, 1, 0, 2}, /* TxD0 */ - {4, 9, 1, 0, 2}, /* TxD1 */ - {4, 8, 1, 0, 2}, /* TxD2 */ - {4, 7, 1, 0, 2}, /* TxD3 */ - {4, 23, 1, 0, 2}, /* TxD4 */ - {4, 22, 1, 0, 2}, /* TxD5 */ - {4, 21, 1, 0, 2}, /* TxD6 */ - {4, 20, 1, 0, 2}, /* TxD7 */ - {4, 15, 2, 0, 2}, /* RxD0 */ - {4, 14, 2, 0, 2}, /* RxD1 */ - {4, 13, 2, 0, 2}, /* RxD2 */ - {4, 12, 2, 0, 2}, /* RxD3 */ - {4, 29, 2, 0, 2}, /* RxD4 */ - {4, 28, 2, 0, 2}, /* RxD5 */ - {4, 27, 2, 0, 2}, /* RxD6 */ - {4, 26, 2, 0, 2}, /* RxD7 */ - {4, 11, 1, 0, 2}, /* TX_EN */ - {4, 24, 1, 0, 2}, /* TX_ER */ - {4, 16, 2, 0, 2}, /* RX_DV */ - {4, 30, 2, 0, 2}, /* RX_ER */ - {4, 17, 2, 0, 2}, /* RX_CLK */ - {4, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ + {4, 10, 1, 0, 2, 0}, /* TxD0 */ + {4, 9, 1, 0, 2, 0}, /* TxD1 */ + {4, 8, 1, 0, 2, 0}, /* TxD2 */ + {4, 7, 1, 0, 2, 0}, /* TxD3 */ + {4, 23, 1, 0, 2, 0}, /* TxD4 */ + {4, 22, 1, 0, 2, 0}, /* TxD5 */ + {4, 21, 1, 0, 2, 0}, /* TxD6 */ + {4, 20, 1, 0, 2, 0}, /* TxD7 */ + {4, 15, 2, 0, 2, 0}, /* RxD0 */ + {4, 14, 2, 0, 2, 0}, /* RxD1 */ + {4, 13, 2, 0, 2, 0}, /* RxD2 */ + {4, 12, 2, 0, 2, 0}, /* RxD3 */ + {4, 29, 2, 0, 2, 0}, /* RxD4 */ + {4, 28, 2, 0, 2, 0}, /* RxD5 */ + {4, 27, 2, 0, 2, 0}, /* RxD6 */ + {4, 26, 2, 0, 2, 0}, /* RxD7 */ + {4, 11, 1, 0, 2, 0}, /* TX_EN */ + {4, 24, 1, 0, 2, 0}, /* TX_ER */ + {4, 16, 2, 0, 2, 0}, /* RX_DV */ + {4, 30, 2, 0, 2, 0}, /* RX_ER */ + {4, 17, 2, 0, 2, 0}, /* RX_CLK */ + {4, 19, 1, 0, 2, 0}, /* GTX_CLK */ + {1, 31, 2, 0, 3, 0}, /* GTX125 */ /* GETH2 */ - {5, 10, 1, 0, 2}, /* TxD0 */ - {5, 9, 1, 0, 2}, /* TxD1 */ - {5, 8, 1, 0, 2}, /* TxD2 */ - {5, 7, 1, 0, 2}, /* TxD3 */ - {5, 23, 1, 0, 2}, /* TxD4 */ - {5, 22, 1, 0, 2}, /* TxD5 */ - {5, 21, 1, 0, 2}, /* TxD6 */ - {5, 20, 1, 0, 2}, /* TxD7 */ - {5, 15, 2, 0, 2}, /* RxD0 */ - {5, 14, 2, 0, 2}, /* RxD1 */ - {5, 13, 2, 0, 2}, /* RxD2 */ - {5, 12, 2, 0, 2}, /* RxD3 */ - {5, 29, 2, 0, 2}, /* RxD4 */ - {5, 28, 2, 0, 2}, /* RxD5 */ - {5, 27, 2, 0, 3}, /* RxD6 */ - {5, 26, 2, 0, 2}, /* RxD7 */ - {5, 11, 1, 0, 2}, /* TX_EN */ - {5, 24, 1, 0, 2}, /* TX_ER */ - {5, 16, 2, 0, 2}, /* RX_DV */ - {5, 30, 2, 0, 2}, /* RX_ER */ - {5, 17, 2, 0, 2}, /* RX_CLK */ - {5, 19, 1, 0, 2}, /* GTX_CLK */ - {1, 31, 2, 0, 3}, /* GTX125 */ - {4, 6, 3, 0, 2}, /* MDIO */ - {4, 5, 1, 0, 2}, /* MDC */ + {5, 10, 1, 0, 2, 0}, /* TxD0 */ + {5, 9, 1, 0, 2, 0}, /* TxD1 */ + {5, 8, 1, 0, 2, 0}, /* TxD2 */ + {5, 7, 1, 0, 2, 0}, /* TxD3 */ + {5, 23, 1, 0, 2, 0}, /* TxD4 */ + {5, 22, 1, 0, 2, 0}, /* TxD5 */ + {5, 21, 1, 0, 2, 0}, /* TxD6 */ + {5, 20, 1, 0, 2, 0}, /* TxD7 */ + {5, 15, 2, 0, 2, 0}, /* RxD0 */ + {5, 14, 2, 0, 2, 0}, /* RxD1 */ + {5, 13, 2, 0, 2, 0}, /* RxD2 */ + {5, 12, 2, 0, 2, 0}, /* RxD3 */ + {5, 29, 2, 0, 2, 0}, /* RxD4 */ + {5, 28, 2, 0, 2, 0}, /* RxD5 */ + {5, 27, 2, 0, 3, 0}, /* RxD6 */ + {5, 26, 2, 0, 2, 0}, /* RxD7 */ + {5, 11, 1, 0, 2, 0}, /* TX_EN */ + {5, 24, 1, 0, 2, 0}, /* TX_ER */ + {5, 16, 2, 0, 2, 0}, /* RX_DV */ + {5, 30, 2, 0, 2, 0}, /* RX_ER */ + {5, 17, 2, 0, 2, 0}, /* RX_CLK */ + {5, 19, 1, 0, 2, 0}, /* GTX_CLK */ + {1, 31, 2, 0, 3, 0}, /* GTX125 */ + {4, 6, 3, 0, 2, 0}, /* MDIO */ + {4, 5, 1, 0, 2, 0}, /* MDC */ /* UART1 */ - {2, 0, 1, 0, 2}, /* UART_SOUT1 */ - {2, 1, 1, 0, 2}, /* UART_RTS1 */ - {2, 2, 2, 0, 2}, /* UART_CTS1 */ - {2, 3, 2, 0, 2}, /* UART_SIN1 */ + {2, 0, 1, 0, 2, 0}, /* UART_SOUT1 */ + {2, 1, 1, 0, 2, 0}, /* UART_RTS1 */ + {2, 2, 2, 0, 2, 0}, /* UART_CTS1 */ + {2, 3, 2, 0, 2, 0}, /* UART_SIN1 */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, 0}, /* END of table */ }; diff -purN a/board/freescale/mpc8323erdb/mpc8323erdb.c b/board/freescale/mpc8323erdb/mpc8323erdb.c --- a/board/freescale/mpc8323erdb/mpc8323erdb.c 2008-01-16 23:06:52.000000000 +0200 +++ b/board/freescale/mpc8323erdb/mpc8323erdb.c 2008-01-17 16:09:44.661841000 +0200 @@ -28,47 +28,47 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* UCC3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ + {1, 0, 1, 0, 1, 0}, /* TxD0 */ + {1, 1, 1, 0, 1, 0}, /* TxD1 */ + {1, 2, 1, 0, 1, 0}, /* TxD2 */ + {1, 3, 1, 0, 1, 0}, /* TxD3 */ + {1, 9, 1, 0, 1, 0}, /* TxER */ + {1, 12, 1, 0, 1, 0}, /* TxEN */ + {3, 24, 2, 0, 1, 0}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1, 0}, /* RxD0 */ + {1, 5, 2, 0, 1, 0}, /* RxD1 */ + {1, 6, 2, 0, 1, 0}, /* RxD2 */ + {1, 7, 2, 0, 1, 0}, /* RxD3 */ + {1, 8, 2, 0, 1, 0}, /* RxER */ + {1, 10, 2, 0, 1, 0}, /* RxDV */ + {0, 13, 2, 0, 1, 0}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1, 0}, /* COL */ + {1, 13, 2, 0, 1, 0}, /* CRS */ /* UCC2 */ - {0, 18, 1, 0, 1}, /* TxD0 */ - {0, 19, 1, 0, 1}, /* TxD1 */ - {0, 20, 1, 0, 1}, /* TxD2 */ - {0, 21, 1, 0, 1}, /* TxD3 */ - {0, 27, 1, 0, 1}, /* TxER */ - {0, 30, 1, 0, 1}, /* TxEN */ - {3, 23, 2, 0, 1}, /* TxCLK->CLK3 */ - - {0, 22, 2, 0, 1}, /* RxD0 */ - {0, 23, 2, 0, 1}, /* RxD1 */ - {0, 24, 2, 0, 1}, /* RxD2 */ - {0, 25, 2, 0, 1}, /* RxD3 */ - {0, 26, 1, 0, 1}, /* RxER */ - {0, 28, 2, 0, 1}, /* Rx_DV */ - {3, 21, 2, 0, 1}, /* RxCLK->CLK16 */ - {0, 29, 2, 0, 1}, /* COL */ - {0, 31, 2, 0, 1}, /* CRS */ + {0, 18, 1, 0, 1, 0}, /* TxD0 */ + {0, 19, 1, 0, 1, 0}, /* TxD1 */ + {0, 20, 1, 0, 1, 0}, /* TxD2 */ + {0, 21, 1, 0, 1, 0}, /* TxD3 */ + {0, 27, 1, 0, 1, 0}, /* TxER */ + {0, 30, 1, 0, 1, 0}, /* TxEN */ + {3, 23, 2, 0, 1, 0}, /* TxCLK->CLK3 */ + + {0, 22, 2, 0, 1, 0}, /* RxD0 */ + {0, 23, 2, 0, 1, 0}, /* RxD1 */ + {0, 24, 2, 0, 1, 0}, /* RxD2 */ + {0, 25, 2, 0, 1, 0}, /* RxD3 */ + {0, 26, 1, 0, 1, 0}, /* RxER */ + {0, 28, 2, 0, 1, 0}, /* Rx_DV */ + {3, 21, 2, 0, 1, 0}, /* RxCLK->CLK16 */ + {0, 29, 2, 0, 1, 0}, /* COL */ + {0, 31, 2, 0, 1, 0}, /* CRS */ - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ + {3, 4, 3, 0, 2, 0}, /* MDIO */ + {3, 5, 1, 0, 2, 0}, /* MDC */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, 0}, /* END of table */ }; int board_early_init_f(void) diff -purN a/board/freescale/mpc832xemds/mpc832xemds.c b/board/freescale/mpc832xemds/mpc832xemds.c --- a/board/freescale/mpc832xemds/mpc832xemds.c 2008-01-16 23:06:52.000000000 +0200 +++ b/board/freescale/mpc832xemds/mpc832xemds.c 2008-01-17 16:10:52.724934000 +0200 @@ -36,47 +36,47 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { /* ETH3 */ - {1, 0, 1, 0, 1}, /* TxD0 */ - {1, 1, 1, 0, 1}, /* TxD1 */ - {1, 2, 1, 0, 1}, /* TxD2 */ - {1, 3, 1, 0, 1}, /* TxD3 */ - {1, 9, 1, 0, 1}, /* TxER */ - {1, 12, 1, 0, 1}, /* TxEN */ - {3, 24, 2, 0, 1}, /* TxCLK->CLK10 */ - - {1, 4, 2, 0, 1}, /* RxD0 */ - {1, 5, 2, 0, 1}, /* RxD1 */ - {1, 6, 2, 0, 1}, /* RxD2 */ - {1, 7, 2, 0, 1}, /* RxD3 */ - {1, 8, 2, 0, 1}, /* RxER */ - {1, 10, 2, 0, 1}, /* RxDV */ - {0, 13, 2, 0, 1}, /* RxCLK->CLK9 */ - {1, 11, 2, 0, 1}, /* COL */ - {1, 13, 2, 0, 1}, /* CRS */ + {1, 0, 1, 0, 1, 0}, /* TxD0 */ + {1, 1, 1, 0, 1, 0}, /* TxD1 */ + {1, 2, 1, 0, 1, 0}, /* TxD2 */ + {1, 3, 1, 0, 1, 0}, /* TxD3 */ + {1, 9, 1, 0, 1, 0}, /* TxER */ + {1, 12, 1, 0, 1, 0}, /* TxEN */ + {3, 24, 2, 0, 1, 0}, /* TxCLK->CLK10 */ + + {1, 4, 2, 0, 1, 0}, /* RxD0 */ + {1, 5, 2, 0, 1, 0}, /* RxD1 */ + {1, 6, 2, 0, 1, 0}, /* RxD2 */ + {1, 7, 2, 0, 1, 0}, /* RxD3 */ + {1, 8, 2, 0, 1, 0}, /* RxER */ + {1, 10, 2, 0, 1, 0}, /* RxDV */ + {0, 13, 2, 0, 1, 0}, /* RxCLK->CLK9 */ + {1, 11, 2, 0, 1, 0}, /* COL */ + {1, 13, 2, 0, 1, 0}, /* CRS */ /* ETH4 */ - {1, 18, 1, 0, 1}, /* TxD0 */ - {1, 19, 1, 0, 1}, /* TxD1 */ - {1, 20, 1, 0, 1}, /* TxD2 */ - {1, 21, 1, 0, 1}, /* TxD3 */ - {1, 27, 1, 0, 1}, /* TxER */ - {1, 30, 1, 0, 1}, /* TxEN */ - {3, 6, 2, 0, 1}, /* TxCLK->CLK8 */ - - {1, 22, 2, 0, 1}, /* RxD0 */ - {1, 23, 2, 0, 1}, /* RxD1 */ - {1, 24, 2, 0, 1}, /* RxD2 */ - {1, 25, 2, 0, 1}, /* RxD3 */ - {1, 26, 1, 0, 1}, /* RxER */ - {1, 28, 2, 0, 1}, /* Rx_DV */ - {3, 31, 2, 0, 1}, /* RxCLK->CLK7 */ - {1, 29, 2, 0, 1}, /* COL */ - {1, 31, 2, 0, 1}, /* CRS */ + {1, 18, 1, 0, 1, 0}, /* TxD0 */ + {1, 19, 1, 0, 1, 0}, /* TxD1 */ + {1, 20, 1, 0, 1, 0}, /* TxD2 */ + {1, 21, 1, 0, 1, 0}, /* TxD3 */ + {1, 27, 1, 0, 1, 0}, /* TxER */ + {1, 30, 1, 0, 1, 0}, /* TxEN */ + {3, 6, 2, 0, 1, 0}, /* TxCLK->CLK8 */ + + {1, 22, 2, 0, 1, 0}, /* RxD0 */ + {1, 23, 2, 0, 1, 0}, /* RxD1 */ + {1, 24, 2, 0, 1, 0}, /* RxD2 */ + {1, 25, 2, 0, 1, 0}, /* RxD3 */ + {1, 26, 1, 0, 1, 0}, /* RxER */ + {1, 28, 2, 0, 1, 0}, /* Rx_DV */ + {3, 31, 2, 0, 1, 0}, /* RxCLK->CLK7 */ + {1, 29, 2, 0, 1, 0}, /* COL */ + {1, 31, 2, 0, 1, 0}, /* CRS */ - {3, 4, 3, 0, 2}, /* MDIO */ - {3, 5, 1, 0, 2}, /* MDC */ + {3, 4, 3, 0, 2, 0}, /* MDIO */ + {3, 5, 1, 0, 2, 0}, /* MDC */ - {0, 0, 0, 0, QE_IOP_TAB_END}, /* END of table */ + {0, 0, 0, 0, QE_IOP_TAB_END, 0}, /* END of table */ }; int board_early_init_f(void)

3 16

[U-Boot-Users] Fix interrupt sub mask on S3C2410, Fix clock calculation for S3C2410 cpu.
by Peter Pearse 07 Feb '08

07 Feb '08

Martin Your patches (slightly amended as per Wolfgangs comments) are available for test from git://linux-arm.org/u-boot-armdev.git#S3C2410 Please confirm that the code runs on whatever S3C boards you have available. Sorry for the delay, I hope to get this merged in the next window Regards Peter -- IMPORTANT NOTICE: The contents of this email and any attachments are confidential and may also be privileged. If you are not the intended recipient, please notify the sender immediately and do not disclose the contents to any other person, use it for any purpose, or store or copy the information in any medium. Thank you.

3 3

[U-Boot-Users] [PATCHv2] [ads5121] DDR2 init/timing update.
by Grzegorz Bernacki 07 Feb '08

07 Feb '08

>From Chris Alger's CW bluestone config file. Signed-off-by: John Rigby <jrigby(a)freescale.com> Signed-off-by: Grzegorz Bernacki <gjb(a)semihalf.com> --- This patch was created by John Rigby. I tested it and rebased against current top of the tree. This is cleaned up version of previous patch, some defines were updated and unused defines were removed. board/ads5121/ads5121.c | 34 +++++++++++++++++++++------------- include/configs/ads5121.h | 15 ++++++--------- 2 files changed, 27 insertions(+), 22 deletions(-) diff --git a/board/ads5121/ads5121.c b/board/ads5121/ads5121.c index 1582c22..462f41d 100644 --- a/board/ads5121/ads5121.c +++ b/board/ads5121/ads5121.c @@ -126,24 +126,24 @@ long int fixed_sdram (void) im->mddrc.prioman_config2 = CFG_MDDRCGRP_PM_CFG2; im->mddrc.hiprio_config = CFG_MDDRCGRP_HIPRIO_CFG; im->mddrc.lut_table0_main_upper = CFG_MDDRCGRP_LUT0_MU; - im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; - im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; - im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; - im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; im->mddrc.lut_table0_main_lower = CFG_MDDRCGRP_LUT0_ML; + im->mddrc.lut_table1_main_upper = CFG_MDDRCGRP_LUT1_MU; im->mddrc.lut_table1_main_lower = CFG_MDDRCGRP_LUT1_ML; + im->mddrc.lut_table2_main_upper = CFG_MDDRCGRP_LUT2_MU; im->mddrc.lut_table2_main_lower = CFG_MDDRCGRP_LUT2_ML; + im->mddrc.lut_table3_main_upper = CFG_MDDRCGRP_LUT3_MU; im->mddrc.lut_table3_main_lower = CFG_MDDRCGRP_LUT3_ML; + im->mddrc.lut_table4_main_upper = CFG_MDDRCGRP_LUT4_MU; im->mddrc.lut_table4_main_lower = CFG_MDDRCGRP_LUT4_ML; im->mddrc.lut_table0_alternate_upper = CFG_MDDRCGRP_LUT0_AU; - im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; - im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; - im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; - im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; im->mddrc.lut_table0_alternate_lower = CFG_MDDRCGRP_LUT0_AL; + im->mddrc.lut_table1_alternate_upper = CFG_MDDRCGRP_LUT1_AU; im->mddrc.lut_table1_alternate_lower = CFG_MDDRCGRP_LUT1_AL; + im->mddrc.lut_table2_alternate_upper = CFG_MDDRCGRP_LUT2_AU; im->mddrc.lut_table2_alternate_lower = CFG_MDDRCGRP_LUT2_AL; + im->mddrc.lut_table3_alternate_upper = CFG_MDDRCGRP_LUT3_AU; im->mddrc.lut_table3_alternate_lower = CFG_MDDRCGRP_LUT3_AL; + im->mddrc.lut_table4_alternate_upper = CFG_MDDRCGRP_LUT4_AU; im->mddrc.lut_table4_alternate_lower = CFG_MDDRCGRP_LUT4_AL; /* Initialize MDDRC */ @@ -157,18 +157,26 @@ long int fixed_sdram (void) im->mddrc.ddr_command = CFG_MICRON_NOP; im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_RFSH; + im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_RFSH; + im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; + im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_EM2; + im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; im->mddrc.ddr_command = CFG_MICRON_EM2; im->mddrc.ddr_command = CFG_MICRON_EM3; im->mddrc.ddr_command = CFG_MICRON_EN_DLL; - im->mddrc.ddr_command = CFG_MICRON_RST_DLL; + im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; im->mddrc.ddr_command = CFG_MICRON_RFSH; im->mddrc.ddr_command = CFG_MICRON_INIT_DEV_OP; im->mddrc.ddr_command = CFG_MICRON_OCD_DEFAULT; - im->mddrc.ddr_command = CFG_MICRON_OCD_EXIT; - - for (i = 0; i < 10; i++) - im->mddrc.ddr_command = CFG_MICRON_NOP; + im->mddrc.ddr_command = CFG_MICRON_PCHG_ALL; + im->mddrc.ddr_command = CFG_MICRON_NOP; /* Start MDDRC */ im->mddrc.ddr_time_config0 = CFG_MDDRC_TIME_CFG0_RUN; diff --git a/include/configs/ads5121.h b/include/configs/ads5121.h index ce458ae..79e6306 100644 --- a/include/configs/ads5121.h +++ b/include/configs/ads5121.h @@ -109,25 +109,22 @@ * [04:00] DRAM tRPA */ -#define CFG_MDDRC_SYS_CFG 0xF8604200 -#define CFG_MDDRC_SYS_CFG_RUN 0xE8604200 -#define CFG_MDDRC_SYS_CFG_EN 0x30000000 -#define CFG_MDDRC_TIME_CFG0 0x0000281E -#define CFG_MDDRC_TIME_CFG0_RUN 0x01F4281E +#define CFG_MDDRC_SYS_CFG 0xF8604A00 +#define CFG_MDDRC_SYS_CFG_RUN 0xE8604A00 +#define CFG_MDDRC_SYS_CFG_EN 0xF0000000 +#define CFG_MDDRC_TIME_CFG0 0x00003D2E +#define CFG_MDDRC_TIME_CFG0_RUN 0x06183D2E #define CFG_MDDRC_TIME_CFG1 0x54EC1168 #define CFG_MDDRC_TIME_CFG2 0x35210864 #define CFG_MICRON_NOP 0x01380000 #define CFG_MICRON_PCHG_ALL 0x01100400 -#define CFG_MICRON_MR 0x01000022 #define CFG_MICRON_EM2 0x01020000 #define CFG_MICRON_EM3 0x01030000 #define CFG_MICRON_EN_DLL 0x01010000 -#define CFG_MICRON_RST_DLL 0x01000932 #define CFG_MICRON_RFSH 0x01080000 -#define CFG_MICRON_INIT_DEV_OP 0x01000832 +#define CFG_MICRON_INIT_DEV_OP 0x01000432 #define CFG_MICRON_OCD_DEFAULT 0x01010780 -#define CFG_MICRON_OCD_EXIT 0x01010400 /* DDR Priority Manager Configuration */ #define CFG_MDDRCGRP_PM_CFG1 0x000777AA -- 1.5.2.2

2 1

[U-Boot-Users] [PATCH] [ADS5121] Change IPS freq to 66MHz
by John Rigby 07 Feb '08

07 Feb '08

Recommended frequency is 66MHz Change divider from 4 to 3. Signed-off-by: John Rigby <jrigby(a)freescale.com> --- include/mpc512x.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/include/mpc512x.h b/include/mpc512x.h index d1c6fb2..b51cf78 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -185,7 +185,7 @@ /* SCFR1 System Clock Frequency Register 1 */ -#define SCFR1_IPS_DIV 0x4 +#define SCFR1_IPS_DIV 0x3 #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 -- 1.5.4.rc4.23.gcab31

3 4

[U-Boot-Users] [PATCHv2] [ads5121] Set ips dividor to 1/3 of csb clock.
by Grzegorz Bernacki 07 Feb '08

07 Feb '08

Previous setting cause ips clock to be out of spec. This bug was found by John Rigby from Freescale. Signed-off-by: Grzegorz Bernacki <gjb(a)semihalf.com> diff --git a/include/mpc512x.h b/include/mpc512x.h index a06b5c6..b51cf78 100644 --- a/include/mpc512x.h +++ b/include/mpc512x.h @@ -185,7 +185,7 @@ /* SCFR1 System Clock Frequency Register 1 */ -#define SCFR1_IPS_DIV 0x2 +#define SCFR1_IPS_DIV 0x3 #define SCFR1_IPS_DIV_MASK 0x03800000 #define SCFR1_IPS_DIV_SHIFT 23 -- 1.5.2.2

2 1