January 2008 - U-Boot

[U-Boot-Users] [PATCH 4/5]: add AcTux-3 board support
by Michael Schwingen 14 Jan '08

14 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/include/configs/actux3.h b/include/configs/actux3.h new file mode 100644 index 0000000..9492f95 --- /dev/null +++ b/include/configs/actux3.h @@ -0,0 +1,216 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_ACTUX3 1 /* on an AcTux-3 Board */ + +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + + + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTCOMMAND "run boot_flash" +//#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + + + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0xbd113442 + +/* + * SDRAM settings + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CFG_DRAM_BASE 0x00000000 + + +// 16MB SDRAM +# define CFG_SDR_CONFIG 0x3A +# define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x01000000 + + +/* + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 140 /* max number of sectors on one chip */ +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * environment organization + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 /* size of one complete sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000; loady ${loadaddr}; run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000; tftp ${loadaddr} u-boot.bin; run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff; protect off 50006000 5003ffff; erase 50000000 50003fff; erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000; cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff; erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};era ${rootaddr} +${filesize}; cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};era ${kerneladdr} +${filesize}; cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth; bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth; tftpboot ${loadaddr} ${kernelfile}; bootm\0" \ + + +/* + * Ethernet + */ +#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 /* use separate flash sector with ucode images */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0x10 /* NPE0 PHY address */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MII_ETHSWITCH 1 /* ethernet switch connected to MII port */ + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS /* NFS support */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 + +#endif /* __CONFIG_H */ diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c new file mode 100644 index 0000000..bc3a128 --- /dev/null +++ b/board/actux3/actux3.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> + +#include <miiphy.h> + +#include "actux3_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ +int board_post_init (void) +{ + return (0); +} + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX3; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_ENABLE(CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DSR); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DCD); + GPIO_OUTPUT_ENABLE(CFG_GPIO_LED5_GN); + GPIO_OUTPUT_ENABLE(CFG_GPIO_LED6_RT); + GPIO_OUTPUT_ENABLE(CFG_GPIO_LED6_GN); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); + GPIO_OUTPUT_SET (CFG_GPIO_DCD); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN); + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT); + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN); + + /* + * Setup GPIO's for Interrupt inputs + */ + GPIO_OUTPUT_DISABLE(CFG_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE(CFG_GPIO_ETHINT); + + /* + * Setup GPIO's for 33MHz clock output + */ + GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + *IXP425_EXP_CS1 = 0x94d10013; // CS1: IPAC-X + *IXP425_EXP_CS5 = 0x9d520003; // CS5: Debug port + *IXP425_EXP_CS6 = 0x81860001; // CS6: HwRel + *IXP425_EXP_CS7 = 0x80900003; // CS7: LED + + udelay (533); + GPIO_OUTPUT_SET(CFG_GPIO_IORST); + GPIO_OUTPUT_SET(CFG_GPIO_ETHRST); + + ACTUX3_LED1_RT(1); + ACTUX3_LED1_GN(0); + ACTUX3_LED2_RT(0); + ACTUX3_LED2_GN(0); + ACTUX3_LED3_RT(0); + ACTUX3_LED3_GN(0); + ACTUX3_LED4_GN(0); + ACTUX3_LED5_RT(0); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard(void) +{ + char revision; + char *s = getenv("serial#"); + + puts("Board: AcTux-3 rev."); + putc(ACTUX3_BOARDREL + 'A' - 1); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev(void) +{ + return ACTUX3_BOARDREL; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +void reset_phy(void) +{ + int i; + + /* initialize the PHY */ + miiphy_reset("NPE0", CONFIG_PHY_ADDR); + + /* all LED outputs = Link/Act */ + miiphy_write("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); + + /* set all ethernet switch ports to forwarding state */ + for (i=1; i <=5; i++) + miiphy_write("NPE0", CONFIG_PHY_ADDR+8+i, 0x04, 0x03); + +} diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h new file mode 100644 index 0000000..00e0bad --- /dev/null +++ b/board/actux3/actux3_hw.h @@ -0,0 +1,67 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX3_HW_H +#define _ACTUX3_HW_H + +// 0 = LED off,1 = ON +#define ACTUX3_LED1_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 0)) = (a) +#define ACTUX3_LED1_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 1)) = (a) +#define ACTUX3_LED2_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 2)) = (a) +#define ACTUX3_LED2_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 3)) = (a) +#define ACTUX3_LED3_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 4)) = (a) +#define ACTUX3_LED3_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 5)) = (a) +#define ACTUX3_LED4_GN(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 6)) = ((a)^1) +#define ACTUX3_LED5_RT(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 7)) = (a) + +#define ACTUX3_DBG_PORT ((volatile u8 *)(IXP425_EXP_BUS_CS5_BASE_PHYS)) +#define ACTUX3_BOARDREL ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) +#define ACTUX3_OPTION ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) + + +/* + * GPIO settings + */ +#define CFG_GPIO_DBGINT 0 +#define CFG_GPIO_ETHINT 1 +#define CFG_GPIO_ETHRST 2 // Out +#define CFG_GPIO_LED5_GN 3 // Out +#define CFG_GPIO_LED6_RT 4 // Out +#define CFG_GPIO_LED6_GN 5 // Out +#define CFG_GPIO_DSR 6 // Out +#define CFG_GPIO_DCD 7 // Out +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 // Out +#define CFG_GPIO_PCI_CLK 14 // Out +#define CFG_GPIO_EXTBUS_CLK 15 // Out + + + + +#endif + diff --git a/board/actux3/config.mk b/board/actux3/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux3/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds new file mode 100644 index 0000000..25eb7bf --- /dev/null +++ b/board/actux3/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + /* WARNING - the following is hand-optimized to fit within + the sector before the environment sector. If it throws an + error during compilation remove an object here to get it + linked after the configuration sector. */ + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_arm/board.o (.text) + common/dlmalloc.o (.text) + drivers/mtd/cfi_flash.o (.text) + cpu/ixp/cpu.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +}

2 3

[U-Boot-Users] [PATCH 3/5]: add AcTux-2 board support
by Michael Schwingen 14 Jan '08

14 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/include/configs/actux2.h b/include/configs/actux2.h new file mode 100644 index 0000000..873b2f9 --- /dev/null +++ b/include/configs/actux2.h @@ -0,0 +1,215 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_ACTUX2 1 /* on an AcTux-3 Board */ + +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +//#define CONFIG_CMD_PCI +//#define CONFIG_PCI + +#define CONFIG_BOOTCOMMAND "run boot_flash" +//#define CONFIG_BOOTARGS "console=ttyS0,115200" +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0xbd113042 + +/* + * SDRAM settings + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CFG_DRAM_BASE 0x00000000 + + +// 16MB SDRAM +# define CFG_SDR_CONFIG 0x3A +# define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x01000000 + + +/* + * FLASH organization + */ +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 140 /* max number of sectors on one chip */ +#define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * environment organization + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 /* size of one complete sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000; loady ${loadaddr}; run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000; tftp ${loadaddr} u-boot.bin; run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff; protect off 50006000 5003ffff; erase 50000000 50003fff; erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000; cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff; erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};era ${rootaddr} +${filesize}; cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};era ${kerneladdr} +${filesize}; cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth; bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth; tftpboot ${loadaddr} ${kernelfile}; bootm\0" \ + + +/* + * Ethernet + */ +#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 /* use separate flash sector with ucode images */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0x00 /* NPE0 PHY address */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_RESET_PHY_R 1 +#define CONFIG_MII_ETHSWITCH 1 /* ethernet switch connected to MII port */ + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS /* NFS support */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 + + +#endif /* __CONFIG_H */ diff --git a/board/actux2/Makefile b/board/actux2/Makefile new file mode 100644 index 0000000..1ff9785 --- /dev/null +++ b/board/actux2/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c new file mode 100644 index 0000000..ef6473a --- /dev/null +++ b/board/actux2/actux2.c @@ -0,0 +1,141 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> + +#include <miiphy.h> + +#include "actux2_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ +int board_post_init (void) +{ + return (0); +} + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_ENABLE(CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DSR); + GPIO_OUTPUT_ENABLE(CFG_GPIO_DCD); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); + GPIO_OUTPUT_SET (CFG_GPIO_DCD); + + /* + * Setup GPIO's for Interrupt inputs + */ + GPIO_OUTPUT_DISABLE(CFG_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE(CFG_GPIO_ETHINT); + + /* + * Setup GPIO's for 33MHz clock output + */ + GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + *IXP425_EXP_CS1 = 0x94d10013; // CS1: IPAC-X + *IXP425_EXP_CS5 = 0x9d520003; // CS5: Debug port + *IXP425_EXP_CS6 = 0x81860001; // CS6: HwRel + *IXP425_EXP_CS7 = 0x80900003; // CS7: LED + + udelay (533); + GPIO_OUTPUT_SET(CFG_GPIO_IORST); + GPIO_OUTPUT_SET(CFG_GPIO_ETHRST); + + ACTUX2_LED1(1); + ACTUX2_LED2(0); + ACTUX2_LED3(0); + ACTUX2_LED4(0); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard(void) +{ + char revision; + char *s = getenv("serial#"); + + puts("Board: AcTux-2 rev."); + putc(ACTUX2_BOARDREL + 'A' - 1); + putc('\n'); + + return (0); +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev(void) +{ + return ACTUX2_BOARDREL; +} + +void reset_phy(void) +{ + int i; + + /* init ethernet switch to native IP175C mode */ + miiphy_write("NPE0", 29, 31, 0x175C); +} diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h new file mode 100644 index 0000000..9bece5b --- /dev/null +++ b/board/actux2/actux2_hw.h @@ -0,0 +1,62 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX2_HW_H +#define _ACTUX2_HW_H + +// 0 = LED off,1 = green, 2 = red, 3 = orange +#define ACTUX2_LED1(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 0)) = (a ? 2 : 0) +#define ACTUX2_LED2(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 1)) = (a ? 2 : 0) +#define ACTUX2_LED3(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 2)) = (a ? 0 : 2) +#define ACTUX2_LED4(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 3)) = (a ? 0 : 2) + +#define ACTUX2_DBG_PORT ((volatile u8 *)(IXP425_EXP_BUS_CS5_BASE_PHYS + 0x10)) +#define ACTUX2_BOARDREL ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) +#define ACTUX2_OPTION ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) + + +/* + * GPIO settings + */ +#define CFG_GPIO_DBGINT 0 +#define CFG_GPIO_ETHINT 1 +#define CFG_GPIO_ETHRST 2 // Out +#define CFG_GPIO_LED5_GN 3 // Out +#define CFG_GPIO_UNUSED4 4 +#define CFG_GPIO_UNUSED5 5 +#define CFG_GPIO_DSR 6 // Out +#define CFG_GPIO_DCD 7 // Out +#define CFG_GPIO_IPAC_INT 8 +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 // Out +#define CFG_GPIO_PCI_CLK 14 // Out +#define CFG_GPIO_EXTBUS_CLK 15 // Out + + +#endif + diff --git a/board/actux2/config.mk b/board/actux2/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux2/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds new file mode 100644 index 0000000..25eb7bf --- /dev/null +++ b/board/actux2/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + /* WARNING - the following is hand-optimized to fit within + the sector before the environment sector. If it throws an + error during compilation remove an object here to get it + linked after the configuration sector. */ + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_arm/board.o (.text) + common/dlmalloc.o (.text) + drivers/mtd/cfi_flash.o (.text) + cpu/ixp/cpu.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +}

1 2

[U-Boot-Users] [PATCH 2/5]: add AcTux-1 board support
by Michael Schwingen 14 Jan '08

14 Jan '08

This patch adds the AcTux-1 specific files. cu Michael Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/include/configs/actux1.h b/include/configs/actux1.h new file mode 100644 index 0000000..1ecf31e --- /dev/null +++ b/include/configs/actux1.h @@ -0,0 +1,241 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_ACTUX1_32MB 0 /* 1: development board with 32MB DRAM */ +#define CONFIG_ACTUX1_FLASH2X2 1 /* 1: 2*2MB FLASH */ +#define CONFIG_ACTUX1_FLASH1X8 0 /* 1: 1*8MB FLASH */ + + +#define CONFIG_ACTUX1_SINGLE_ETH_LED 1 + +/* + * High Level Configuration Options + * (easy to change) + */ +#define CONFIG_IXP425 1 /* This is an IXP425 CPU */ +#define CONFIG_ACTUX1 1 /* on an AcTux-1 Board */ + +#define CONFIG_DISPLAY_CPUINFO 1 /* display cpu info (and speed) */ +#define CONFIG_DISPLAY_BOARDINFO 1 /* display board info */ + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + + + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +#define CFG_GBL_DATA_SIZE 128 /* size in bytes reserved for initial data */ + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +//#define CONFIG_CMD_PCI +//#define CONFIG_PCI + +#define CONFIG_BOOTCOMMAND "run boot_flash" +//#define CONFIG_BOOTARGS "root=/dev/mtdblock2 rootfstype=cramfs console=ttyS0,115200 mtdparts=IXP4XX-Flash.0:256k(uboot),2048k(linux),-(root)" +#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#endif + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x00800000 /* 4 ... 8 MB in DRAM */ + +#undef CFG_CLKS_IN_HZ /* everything, incl board info, in Hz */ + +#define CFG_LOAD_ADDR 0x00010000 /* default load address */ + +#define CFG_HZ 3333333 /* spec says 66.666 MHz, but it appears to be 33 */ + /* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* + * Expansion bus settings + */ +#define CFG_EXP_CS0 0xbd113842 + +/* + * SDRAM settings + */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 /* SDRAM Bank #1 */ +#define CFG_DRAM_BASE 0x00000000 + + +#if CONFIG_ACTUX1_32MB // 32MB SDRAM +# define CFG_SDR_CONFIG 0x18 +# define PHYS_SDRAM_1_SIZE 0x02000000 /* 32 MB */ +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x02000000 +#else // 16MB SDRAM +# define CFG_SDR_CONFIG 0x3A +# define PHYS_SDRAM_1_SIZE 0x01000000 /* 16 MB */ +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x01000000 +#endif + + + +/* + * FLASH organization + */ +#if CONFIG_ACTUX1_FLASH2X2 +# define CFG_MAX_FLASH_BANKS 2 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 40 /* max number of sectors on one chip */ +# define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +# define PHYS_FLASH_2 0x50200000 /* Flash Bank #2 */ +# define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } +#endif +#if CONFIG_ACTUX1_FLASH1X8 +# define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +# define CFG_MAX_FLASH_SECT 140 /* max number of sectors on one chip */ +# define PHYS_FLASH_1 0x50000000 /* Flash Bank #1 */ +# define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } +#endif + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ + +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT /* no byte writes on IXP4xx */ +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ + +/* + * environment organization + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 /* size of one complete sector */ +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000; loady ${loadaddr}; run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000; tftp ${loadaddr} u-boot.bin; run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff; protect off 50006000 5003ffff; erase 50000000 50003fff; erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000; cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff; erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};era ${rootaddr} +${filesize}; cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};era ${kerneladdr} +${filesize}; cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3 rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth; bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth; tftpboot ${loadaddr} ${kernelfile}; bootm\0" \ + +/* + * Ethernet + */ +#define CONFIG_IXP4XX_NPE 1 /* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 /* use separate flash sector with ucode images */ +#define CONFIG_NET_MULTI 1 +#define CONFIG_PHY_ADDR 0 /* NPE0 PHY address */ +//#define CONFIG_HAS_ETH1 +//#define CONFIG_PHY1_ADDR 1 /* NPE1 PHY address */ +#define CONFIG_MII 1 /* MII PHY management */ +#define CFG_RX_ETH_BUFFER 16 /* Number of ethernet rx buffers & descriptors */ +#define CONFIG_RESET_PHY_R 1 + + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS /* NFS support */ + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 32 + + +#endif /* __CONFIG_H */ diff --git a/board/actux1/Makefile b/board/actux1/Makefile new file mode 100644 index 0000000..a7e8322 --- /dev/null +++ b/board/actux1/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux1.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c new file mode 100644 index 0000000..9fd5f1c --- /dev/null +++ b/board/actux1/actux1.c @@ -0,0 +1,169 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> + +#include <miiphy.h> + +#include "actux1_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +/* + * Miscelaneous platform dependent initialisations + */ +int board_post_init (void) +{ + return (0); +} + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE(CFG_GPIO_IORST); + + /* + * Setup GPIO's for PCI INTA + */ + GPIO_OUTPUT_DISABLE(CFG_GPIO_PCI1_INTA); + GPIO_INT_ACT_LOW_SET(CFG_GPIO_PCI1_INTA); + + /* + * Setup GPIO's for 33MHz clock output + */ + GPIO_OUTPUT_ENABLE(CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE(CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + *IXP425_EXP_CS5 = 0x9d520003; // CS5: Debug port + *IXP425_EXP_CS6 = 0x81860001; // CS6: HwRel + *IXP425_EXP_CS7 = 0x80900003; // CS7: LED + + udelay (533); + GPIO_OUTPUT_SET(CFG_GPIO_IORST); + + ACTUX1_LED1(2); + ACTUX1_LED2(2); + ACTUX1_LED3(0); + ACTUX1_LED4(0); + ACTUX1_LED5(0); + ACTUX1_LED6(0); + ACTUX1_LED7(0); + + ACTUX1_HS(ACTUX1_HS_DCD); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard(void) +{ + char revision; + char *s = getenv("serial#"); + + puts("Board: AcTux-1 rev."); + putc(ACTUX1_BOARDREL + 'A' - 1); + + if (s != NULL) { + puts(", serial# "); + puts(s); + } + putc('\n'); + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev(void) +{ + return ACTUX1_BOARDREL; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) +extern struct pci_controller hose; +extern void pci_ixp_init(struct pci_controller * hose); + +void pci_init_board(void) +{ + extern void pci_ixp_init (struct pci_controller *hose); + + pci_ixp_init(&hose); +} +#endif + +void reset_phy(void) +{ + u16 id1, id2; + + /* initialize the PHY */ + miiphy_reset("NPE0", CONFIG_PHY_ADDR); + + miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2); + + id2 &= 0xFFF0; /* mask out revision bits */ + + if (id1 == 0x13 && id2 == 0x78e0) { /* LXT971/LXT972 */ + /* set LED outputs: LED1(green) = Link/ACT, LED2 (unused) = LINK, LED3(red) = Coll */ + miiphy_write("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); + } + else if (id1 == 0x143 && id2 == 0xbc30) { /* BCM5241 */ + /* default values are OK */ + } + else + printf("unknown ethernet PHY ID: %x %x\n", id1, id2); +} + diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h new file mode 100644 index 0000000..34cef2f --- /dev/null +++ b/board/actux1/actux1_hw.h @@ -0,0 +1,64 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX1_HW_H +#define _ACTUX1_HW_H + +// 0 = LED off,1 = green, 2 = red, 3 = orange +#define ACTUX1_LED1(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 0)) = (a) +#define ACTUX1_LED2(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 1)) = (a) +#define ACTUX1_LED3(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 2)) = (a) +#define ACTUX1_LED4(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 3)) = ((a)^3) +#define ACTUX1_LED5(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 4)) = ((a)^3) +#define ACTUX1_LED6(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 5)) = ((a)^3) +#define ACTUX1_LED7(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 6)) = ((a)^3) +#define ACTUX1_HS(a) (*(volatile u8 *)(IXP425_EXP_BUS_CS7_BASE_PHYS + 7)) = (a) +#define ACTUX1_HS_DCD 0x01 +#define ACTUX1_HS_DSR 0x02 + +#define ACTUX1_DBG_PORT ((volatile u8 *)(IXP425_EXP_BUS_CS5_BASE_PHYS + 0x10)) +#define ACTUX1_BOARDREL ((*(volatile u8 *)IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) + + +/* + * GPIO settings + */ +#define CFG_GPIO_PCI1_INTA 2 +#define CFG_GPIO_PCI2_INTA 3 +#define CFG_GPIO_I2C_SDA 4 +#define CFG_GPIO_I2C_SCL 5 +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 // Out +#define CFG_GPIO_PCI_CLK 14 // Out +#define CFG_GPIO_EXTBUS_CLK 15 // Out + + + + +#endif + diff --git a/board/actux1/config.mk b/board/actux1/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux1/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds new file mode 100644 index 0000000..4dbdb2c --- /dev/null +++ b/board/actux1/u-boot.lds @@ -0,0 +1,70 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH(arm) +ENTRY(_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN(4); + .text : + { + cpu/ixp/start.o (.text) + /* WARNING - the following is hand-optimized to fit within + the sector before the environment sector. If it throws an + error during compilation remove an object here to get it + linked after the configuration sector. */ + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_arm/board.o (.text) + common/dlmalloc.o (.text) + drivers/mtd/cfi_flash.o (.text) + cpu/ixp/cpu.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + *(.text) + } + + . = ALIGN(4); + .rodata : { *(.rodata) } + + . = ALIGN(4); + .data : { *(.data) } + + . = ALIGN(4); + .got : { *(.got) } + + . = .; + __u_boot_cmd_start = .; + .u_boot_cmd : { *(.u_boot_cmd) } + __u_boot_cmd_end = .; + + . = ALIGN(4); + __bss_start = .; + .bss (NOLOAD) : { *(.bss) } + _end = .; +}

2 3

[U-Boot-Users] build breakage for make -jN
by Kumar Gala 14 Jan '08

14 Jan '08

It looks like the following commit has broken the build a bit: ae6d1056d2c2e4d1266413c0ae8a6d5529ecde4b - Fix Makefile dependencies issues; allow silent build make distclean ; make MPC8544DS_config ; make -j4 I get: board/freescale/mpc8544ds/libmpc8544ds.a(mpc8544ds.o): In function `ft_board_setup': /local/home/galak/git/master/u-boot/board/freescale/mpc8544ds/ mpc8544ds.c:514: undefined reference to `ft_cpu_setup' /local/home/galak/git/master/u-boot/board/freescale/mpc8544ds/ mpc8544ds.c:516: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/board/freescale/mpc8544ds/ mpc8544ds.c:520: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/board/freescale/mpc8544ds/ mpc8544ds.c:527: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/board/freescale/mpc8544ds/ mpc8544ds.c:534: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/board/freescale/mpc8544ds/ mpc8544ds.c:541: undefined reference to `fdt_getprop' common/libcommon.a(cmd_bootm.o): In function `do_bootm_linux': /local/home/galak/git/master/u-boot/common/cmd_bootm.c:748: undefined reference to `fdt_check_header' /local/home/galak/git/master/u-boot/common/cmd_bootm.c:799: undefined reference to `fdt_check_header' /local/home/galak/git/master/u-boot/common/cmd_bootm.c:849: undefined reference to `fdt_check_header' /local/home/galak/git/master/u-boot/common/cmd_bootm.c:965: undefined reference to `fdt_open_into' common/libcommon.a(cmd_fdt.o): In function `fdt_valid': /local/home/galak/git/master/u-boot/common/cmd_fdt.c:339: undefined reference to `fdt_check_header' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:344: undefined reference to `fdt_strerror' common/libcommon.a(cmd_fdt.o): In function `do_fdt': /local/home/galak/git/master/u-boot/common/cmd_fdt.c:87: undefined reference to `fdt_open_into' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:89: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:137: undefined reference to `fdt_open_into' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:139: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:165: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:174: undefined reference to `fdt_add_subnode' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:176: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:210: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:220: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:222: undefined reference to `fdt_strerror' common/libcommon.a(cmd_fdt.o): In function `fdt_print': /local/home/galak/git/master/u-boot/common/cmd_fdt.c:573: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:587: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:609: undefined reference to `fdt_next_tag' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:612: undefined reference to `fdt_get_name' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:636: undefined reference to `fdt_offset_ptr' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:638: undefined reference to `fdt_string' common/libcommon.a(cmd_fdt.o): In function `do_fdt': /local/home/galak/git/master/u-boot/common/cmd_fdt.c:271: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:276: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:285: undefined reference to `fdt_delprop' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:287: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:292: undefined reference to `fdt_del_node' /local/home/galak/git/master/u-boot/common/cmd_fdt.c:294: undefined reference to `fdt_strerror' common/libcommon.a(cmd_fdt.o): In function `fdt_print': /local/home/galak/git/master/u-boot/common/cmd_fdt.c:643: undefined reference to `fdt_strerror' common/libcommon.a(fdt_support.o): In function `fdt_fixup_memory': /local/home/galak/git/master/u-boot/common/fdt_support.c:500: undefined reference to `fdt_check_header' /local/home/galak/git/master/u-boot/common/fdt_support.c:502: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:507: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/fdt_support.c:509: undefined reference to `fdt_add_subnode' /local/home/galak/git/master/u-boot/common/fdt_support.c:511: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:515: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:518: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:523: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:543: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:563: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:565: undefined reference to `fdt_strerror' common/libcommon.a(fdt_support.o): In function `do_fixup_by_compat': /local/home/galak/git/master/u-boot/common/fdt_support.c:481: undefined reference to `fdt_get_property' /local/home/galak/git/master/u-boot/common/fdt_support.c:482: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:483: undefined reference to `fdt_node_offset_by_compatible' common/libcommon.a(fdt_support.o): In function `fdt_find_and_setprop': /local/home/galak/git/master/u-boot/common/fdt_support.c:63: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/fdt_support.c:68: undefined reference to `fdt_get_property' /local/home/galak/git/master/u-boot/common/fdt_support.c:71: undefined reference to `fdt_setprop' common/libcommon.a(fdt_support.o): In function `do_fixup_by_path': /local/home/galak/git/master/u-boot/common/fdt_support.c:428: undefined reference to `fdt_strerror' common/libcommon.a(fdt_support.o): In function `fdt_fixup_ethernet': /local/home/galak/git/master/u-boot/common/fdt_support.c:580: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/fdt_support.c:583: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:592: undefined reference to `fdt_getprop' common/libcommon.a(fdt_support.o): In function `do_fixup_by_prop': /local/home/galak/git/master/u-boot/common/fdt_support.c:454: undefined reference to `fdt_get_property' /local/home/galak/git/master/u-boot/common/fdt_support.c:455: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:456: undefined reference to `fdt_node_offset_by_prop_value' common/libcommon.a(fdt_support.o): In function `fdt_chosen': /local/home/galak/git/master/u-boot/common/fdt_support.c:119: undefined reference to `fdt_check_header' /local/home/galak/git/master/u-boot/common/fdt_support.c:137: undefined reference to `fdt_del_mem_rsv' /local/home/galak/git/master/u-boot/common/fdt_support.c:127: undefined reference to `fdt_num_mem_rsv' /local/home/galak/git/master/u-boot/common/fdt_support.c:135: undefined reference to `fdt_get_mem_rsv' /local/home/galak/git/master/u-boot/common/fdt_support.c:142: undefined reference to `fdt_add_mem_rsv' /local/home/galak/git/master/u-boot/common/fdt_support.c:144: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:152: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/fdt_support.c:161: undefined reference to `fdt_add_subnode' /local/home/galak/git/master/u-boot/common/fdt_support.c:163: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:176: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:178: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:181: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:186: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:189: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:192: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:196: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:199: undefined reference to `fdt_strerror' /local/home/galak/git/master/u-boot/common/fdt_support.c:205: undefined reference to `fdt_getprop' common/libcommon.a(fdt_support.o): In function `fdt_fixup_stdout': /local/home/galak/git/master/u-boot/common/fdt_support.c:85: undefined reference to `fdt_path_offset' /local/home/galak/git/master/u-boot/common/fdt_support.c:88: undefined reference to `fdt_getprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:94: undefined reference to `fdt_setprop' /local/home/galak/git/master/u-boot/common/fdt_support.c:104: undefined reference to `fdt_strerror' make: *** [u-boot] Error 1 - k

2 4

[U-Boot-Users] [PATCH 2/2] ppc4xx: Complete DU440 board support
by Matthias Fuchs 13 Jan '08

13 Jan '08

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- MAINTAINERS | 1 + MAKEALL | 1 + Makefile | 3 + include/configs/DU440.h | 438 +++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 443 insertions(+), 0 deletions(-) create mode 100644 include/configs/DU440.h diff --git a/MAINTAINERS b/MAINTAINERS index 2ef2f5c..1996688 100644 --- a/MAINTAINERS +++ b/MAINTAINERS @@ -150,6 +150,7 @@ Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> DASA_SIM IOP480 (PPC401) DP405 PPC405EP DU405 PPC405GP + DU440 PPC440EPx G2000 PPC405EP HH405 PPC405EP HUB405 PPC405EP diff --git a/MAKEALL b/MAKEALL index ebc5a22..0777dac 100755 --- a/MAKEALL +++ b/MAKEALL @@ -175,6 +175,7 @@ LIST_4xx=" \ DASA_SIM \ DP405 \ DU405 \ + DU440 \ ebony \ ERIC \ EXBITGEN \ diff --git a/Makefile b/Makefile index 1983ca0..7de2286 100644 --- a/Makefile +++ b/Makefile @@ -1191,6 +1191,9 @@ DP405_config: unconfig DU405_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx du405 esd +DU440_config: unconfig + @$(MKCONFIG) $(@:_config=) ppc ppc4xx du440 esd + ebony_config: unconfig @$(MKCONFIG) $(@:_config=) ppc ppc4xx ebony amcc diff --git a/include/configs/DU440.h b/include/configs/DU440.h new file mode 100644 index 0000000..30ac437 --- /dev/null +++ b/include/configs/DU440.h @@ -0,0 +1,438 @@ +/* + * (C) Copyright 2008 + * Matthias Fuchs, esd gmbh, matthias.fuchs(a)esd-electronics.com + * + * based on the Sequoia board configuration by + * Stefan Roese, Jacqueline Pira-Ferriol and Alain Saurel + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/************************************************************************ + * DU440.h - configuration for esd DU440 board (PowerPC440EPx) + ***********************************************************************/ +#ifndef __CONFIG_H +#define __CONFIG_H + +/*----------------------------------------------------------------------- + * High Level Configuration Options + *----------------------------------------------------------------------*/ +#define CONFIG_DU440 1 /* Board is esd DU440 */ +#define CONFIG_440EPX 1 /* Specific PPC440EPx */ +#define CONFIG_4xx 1 /* ... PPC4xx family */ +#define CONFIG_SYS_CLK_FREQ 33333400 /* external freq to pll */ + +#define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ +#define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ +#define CONFIG_LAST_STAGE_INIT 1 /* last_stage_init */ + +/*----------------------------------------------------------------------- + * Base addresses -- Note these are effective addresses where the + * actual resources get mapped (not physical addresses) + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (384 * 1024) /* Reserve 384 kB for Monitor */ +#define CFG_MALLOC_LEN (8 << 20) /* Reserve 8 MB for malloc() */ + +#define CFG_BOOT_BASE_ADDR 0xf0000000 +#define CFG_SDRAM_BASE 0x00000000 /* _must_ be 0 */ +#define CFG_FLASH_BASE 0xfc000000 /* start of FLASH */ +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_NAND0_ADDR 0xd0000000 /* NAND Flash */ +#define CFG_NAND1_ADDR 0xd0100000 /* NAND Flash */ +#define CFG_OCM_BASE 0xe0010000 /* ocm */ +#define CFG_PCI_BASE 0xe0000000 /* Internal PCI regs */ +#define CFG_PCI_MEMBASE 0x80000000 /* mapped pci memory */ +#define CFG_PCI_MEMBASE1 CFG_PCI_MEMBASE + 0x10000000 +#define CFG_PCI_MEMBASE2 CFG_PCI_MEMBASE1 + 0x10000000 +#define CFG_PCI_MEMBASE3 CFG_PCI_MEMBASE2 + 0x10000000 +#define CFG_PCI_IOBASE 0xe8000000 + + +/* Don't change either of these */ +#define CFG_PERIPHERAL_BASE 0xef600000 /* internal peripherals */ + +#define CFG_USB2D0_BASE 0xe0000100 +#define CFG_USB_DEVICE 0xe0000000 +#define CFG_USB_HOST 0xe0000400 + +/*----------------------------------------------------------------------- + * Initial RAM & stack pointer + *----------------------------------------------------------------------*/ +/* 440EPx/440GRx have 16KB of internal SRAM, so no need for D-Cache */ +#define CFG_INIT_RAM_OCM 1 /* OCM as init ram */ +#define CFG_INIT_RAM_ADDR CFG_OCM_BASE /* OCM */ + +#define CFG_INIT_RAM_END (4 << 10) +#define CFG_GBL_DATA_SIZE 256 /* num bytes initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Serial Port + *----------------------------------------------------------------------*/ +/* TODO: external clock oscillator will be removed */ +#define CFG_EXT_SERIAL_CLOCK 11059200 /* ext. 11.059MHz clk */ +#define CONFIG_BAUDRATE 115200 +#define CONFIG_SERIAL_MULTI 1 +#undef CONFIG_UART1_CONSOLE + +#define CFG_BAUDRATE_TABLE \ + {300, 600, 1200, 2400, 4800, 9600, 19200, 38400, 57600, 115200} + +/*----------------------------------------------------------------------- + * Video Port + *----------------------------------------------------------------------*/ +#define CONFIG_VIDEO +#define CONFIG_VIDEO_SMI_LYNXEM +#define CONFIG_CFB_CONSOLE +#define CONFIG_VIDEO_LOGO +#define CONFIG_VGA_AS_SINGLE_DEVICE +#define CONFIG_SPLASH_SCREEN +#define CONFIG_SPLASH_SCREEN_ALIGN +#define CONFIG_VIDEO_BMP_GZIP /* gzip compressed bmp images */ +#define CFG_VIDEO_LOGO_MAX_SIZE (4 << 20) /* for decompressed img */ +#define CFG_DEFAULT_VIDEO_MODE 0x31a /* 1280x1024,16bpp */ +#define CFG_CONSOLE_IS_IN_ENV +#define CFG_ISA_IO CFG_PCI_IOBASE + +/*----------------------------------------------------------------------- + * Environment + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_EEPROM 1 /* use FLASH for environment vars */ + +/*----------------------------------------------------------------------- + * FLASH related + *----------------------------------------------------------------------*/ +#define CFG_FLASH_CFI /* The flash is CFI compatible */ +#define CFG_FLASH_CFI_DRIVER /* Use common CFI driver */ + +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } + +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 512 /* max number of sectors on one chip */ + +#define CFG_FLASH_ERASE_TOUT 120000 /* Timeout for Flash Erase (in ms) */ +#define CFG_FLASH_WRITE_TOUT 500 /* Timeout for Flash Write (in ms) */ + +#define CFG_FLASH_USE_BUFFER_WRITE 1 /* use buffered writes (20x faster) */ +/* CFI_FLASH_PROTECTION make flash_protect hang sometimes -> disabled */ +#define CFG_FLASH_PROTECTION 1 /* use hardware flash protection */ + +#define CFG_FLASH_EMPTY_INFO /* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_QUIET_TEST 1 /* don't warn upon unknown flash */ + +#ifdef CFG_ENV_IS_IN_FLASH +#define CFG_ENV_SECT_SIZE 0x20000 /* size of one complete sector */ +#define CFG_ENV_ADDR ((-CFG_MONITOR_LEN)-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE 0x2000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_ADDR_REDUND (CFG_ENV_ADDR-CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) +#endif + +#ifdef CFG_ENV_IS_IN_EEPROM +#define CFG_ENV_OFFSET 0 /* environment starts at the beginning of the EEPROM */ +#define CFG_ENV_SIZE 0x1000 /* 4096 bytes may be used for env vars*/ +#endif + +/*----------------------------------------------------------------------- + * DDR SDRAM + *----------------------------------------------------------------------*/ +#define CFG_MBYTES_SDRAM (1024) /* 512 MiB TODO: remove */ +#define CONFIG_DDR_DATA_EYE /* use DDR2 optimization */ +#define CONFIG_SPD_EEPROM /* Use SPD EEPROM for setup */ +#if 0 +#define CONFIG_ZERO_SDRAM /* Zero SDRAM after setup */ +#endif +#define CONFIG_DDR_ECC /* Use ECC when available */ +#define SPD_EEPROM_ADDRESS {0x50} +#define CONFIG_PROG_SDRAM_TLB + +/*----------------------------------------------------------------------- + * I2C + *----------------------------------------------------------------------*/ +#define CONFIG_HARD_I2C 1 /* I2C with hardware support */ +#undef CONFIG_SOFT_I2C /* I2C bit-banged */ +#define CFG_I2C_SPEED 100000 /* I2C speed and slave address */ +#define CFG_I2C_SLAVE 0x7F +#define CONFIG_I2C_CMD_TREE 1 +#define CONFIG_I2C_MULTI_BUS 1 + +#define CFG_SPD_BUS_NUM 0 +#define IIC1_MCP3021_ADDR 0x4d +#define IIC1_USB2507_ADDR 0x2c +#ifdef CONFIG_I2C_MULTI_BUS +#define CFG_I2C_NOPROBES {{1, IIC1_USB2507_ADDR}} +#endif +#define CFG_I2C_MULTI_EEPROMS +#define CFG_I2C_EEPROM_ADDR 0x54 +#define CFG_I2C_EEPROM_ADDR_LEN 2 +#define CFG_EEPROM_PAGE_WRITE_ENABLE +#define CFG_EEPROM_PAGE_WRITE_BITS 5 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 +#define CFG_I2C_EEPROM_ADDR_OVERFLOW 0x01 + +#define CFG_EEPROM_WREN 1 +#define CFG_I2C_BOOT_EEPROM_ADDR 0x52 + +/* + * standard dtt sensor configuration - bottom bit will determine local or + * remote sensor of the TMP401 + */ +#define CONFIG_DTT_SENSORS { 0, 1 } + +/* + * The PMC440 uses a TI TMP401 temperature sensor. This part + * is basically compatible to the ADM1021 that is supported + * by U-Boot. + * + * - i2c addr 0x4c + * - conversion rate 0x02 = 0.25 conversions/second + * - ALERT ouput disabled + * - local temp sensor enabled, min set to 0 deg, max set to 70 deg + * - remote temp sensor enabled, min set to 0 deg, max set to 70 deg + */ +#define CONFIG_DTT_ADM1021 +#define CFG_DTT_ADM1021 { { 0x4c, 0x02, 0, 1, 70, 0, 1, 70, 0} } + +/*----------------------------------------------------------------------- + * RTC stuff + *----------------------------------------------------------------------- + */ +#define CONFIG_RTC_DS1338 +#define CFG_I2C_RTC_ADDR 0x68 + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "ethrotate=no\0" \ + "hostname=du440\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0"\ + "flash_self=run ramargs addip addtty optargs;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${img};run nfsargs addip addtty optargs;" \ + "bootm\0" \ + "rootpath=/tftpboot/du440/target_root_du440\0" \ + "img=/tftpboot/du440/uImage\0" \ + "kernel_addr=FFC00000\0" \ + "ramdisk_addr=FFE00000\0" \ + "initrd_high=30000000\0" \ + "load=tftp 100000 /tftpboot/du440/u-boot.bin\0" \ + "update=protect off FFFA0000 FFFFFFFF;era FFFA0000 FFFFFFFF;" \ + "cp.b 100000 FFFA0000 60000\0" \ + "" +#if 0 +#define CONFIG_BOOTCOMMAND "run flash_self" +#endif + +#define CONFIG_PREBOOT /* enable preboot variable */ + +#define CONFIG_BOOTDELAY 3 /* autoboot after 5 seconds */ + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#define CFG_LOADS_BAUD_CHANGE 1 /* allow baudrate change */ + +#ifndef __ASSEMBLY__ +int du440_phy_addr(int devnum); +#endif + +#define CONFIG_IBM_EMAC4_V4 1 +#define CONFIG_MII 1 /* MII PHY management */ +#define CONFIG_PHY_ADDR du440_phy_addr(0) /* PHY address, See schematics */ + +#define CONFIG_PHY_RESET 1 /* reset phy upon startup */ +#define CONFIG_PHY_GIGE 1 /* Include GbE speed/duplex detection */ + +#define CONFIG_HAS_ETH0 +#define CFG_RX_ETH_BUFFER 128 /* Number of ethernet rx buffers & descriptors */ + +#define CONFIG_NET_MULTI 1 +#define CONFIG_HAS_ETH1 1 /* add support for "eth1addr" */ +#define CONFIG_PHY1_ADDR du440_phy_addr(1) + +/* USB */ +#define CONFIG_USB_OHCI_NEW +#define CONFIG_USB_STORAGE +#define CFG_OHCI_BE_CONTROLLER + +#define CFG_USB_OHCI_CPU_INIT 1 +#define CFG_USB_OHCI_REGS_BASE CFG_USB_HOST +#define CFG_USB_OHCI_SLOT_NAME "du440" +#define CFG_USB_OHCI_MAX_ROOT_PORTS 15 + +/* Comment this out to enable USB 1.1 device */ +#define USB_2_0_DEVICE + +/* Partitions */ +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION +#define CONFIG_ISO_PARTITION + +#include <config_cmd_default.h> + +#define CONFIG_CMD_BSP +#define CONFIG_CMD_DATE +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_DTT +#define CONFIG_CMD_DIAG +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_ELF +#define CONFIG_CMD_FAT +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IRQ +#define CONFIG_CMD_MII +#define CONFIG_CMD_NAND +#define CONFIG_CMD_NET +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PCI +#define CONFIG_CMD_PING +#define CONFIG_CMD_USB +#define CONFIG_CMD_REGINFO +#define CONFIG_CMD_SDRAM + +#define CONFIG_SUPPORT_VFAT + +/*----------------------------------------------------------------------- + * Miscellaneous configurable options + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x00400000 /* memtest works on */ +#define CFG_MEMTEST_END 0x3f000000 /* 4 ... < 1GB DRAM */ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ +#define CFG_EXTBDINFO 1 /* To use extended board_into (bd_t) */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CONFIG_LOOPW 1 /* enable loopw command */ +#define CONFIG_MX_CYCLIC 1 /* enable mdc/mwc commands */ +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ +#define CONFIG_VERSION_VARIABLE 1 /* include version env variable */ + +#define CONFIG_AUTOBOOT_KEYED 1 +#define CONFIG_AUTOBOOT_PROMPT "Press SPACE to abort autoboot in %d seconds\n" +#define CONFIG_AUTOBOOT_DELAY_STR "d" +#define CONFIG_AUTOBOOT_STOP_STR " " + +/*----------------------------------------------------------------------- + * PCI stuff + *----------------------------------------------------------------------*/ +/* General PCI */ +#define CONFIG_PCI /* include pci support */ +#define CONFIG_PCI_PNP /* do (not) pci plug-and-play */ +#define CONFIG_PCI_SCAN_SHOW /* show pci devices on startup */ +#define CFG_PCI_TARGBASE 0x80000000 /* PCIaddr mapped to CFG_PCI_MEMBASE*/ + +/* Board-specific PCI */ +#define CFG_PCI_PRE_INIT /* enable board pci_pre_init() */ +#define CFG_PCI_TARGET_INIT +#define CFG_PCI_MASTER_INIT + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * External Bus Controller (EBC) Setup + *----------------------------------------------------------------------*/ +#define CFG_FLASH CFG_FLASH_BASE + +#define CFG_CPLD_BASE 0xC0000000 +#define CFG_CPLD_RANGE 0x00000010 +#define CFG_DUMEM_BASE 0xC0100000 +#define CFG_DUMEM_RANGE 0x00100000 +#define CFG_DUIO_BASE 0xC0200000 +#define CFG_DUIO_RANGE 0x00010000 + +/* + * On Sequoia CS0 and CS3 are switched when configuring for NAND booting + */ +#define CFG_NAND0_CS 2 /* NAND chip connected to CSx */ +#define CFG_NAND1_CS 3 /* NAND chip connected to CSx */ +/* Memory Bank 0 (NOR-FLASH) initialization */ +#define CFG_EBC_PB0AP 0x04017200 /* mf test-only - disabled ready# */ +/* 0x03017200 = 90ns */ /* mf test-only - use 0x04017200 for 120ns */ +#define CFG_EBC_PB0CR (CFG_FLASH_BASE | 0xda000) + +/* Memory Bank 1 (CPLD, 16 bytes needed, but 1MB is minimum) */ +#define CFG_EBC_PB1AP 0x018003c0 +#define CFG_EBC_PB1CR (CFG_CPLD_BASE | 0x18000) + +/* Memory Bank 2 (NAND-FLASH) initialization */ +#define CFG_EBC_PB2AP 0x018003c0 +#define CFG_EBC_PB2CR (CFG_NAND0_ADDR | 0x1c000) + +/* Memory Bank 3 (NAND-FLASH) initialization */ +#define CFG_EBC_PB3AP 0x018003c0 +#define CFG_EBC_PB3CR (CFG_NAND1_ADDR | 0x1c000) + +/* Memory Bank 4 (DUMEM, 1MB) initialization */ +#define CFG_EBC_PB4AP 0x018053c0 +#define CFG_EBC_PB4CR (CFG_DUMEM_BASE | 0x18000) + +/* Memory Bank 5 (DUIO, 64KB needed, but 1MB is minimum) */ +#define CFG_EBC_PB5AP 0x018053c0 +#define CFG_EBC_PB5CR (CFG_DUIO_BASE | 0x18000) + +/*----------------------------------------------------------------------- + * NAND FLASH + *----------------------------------------------------------------------*/ +#define CFG_MAX_NAND_DEVICE 2 +#define NAND_MAX_CHIPS CFG_MAX_NAND_DEVICE +#define CFG_NAND_SELECT_DEVICE 1 /* nand driver supports mutipl. chips */ +#define CFG_NAND_BASE_LIST {CFG_NAND0_ADDR + CFG_NAND0_CS, CFG_NAND1_ADDR + CFG_NAND1_CS} + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +#if (CONFIG_COMMANDS & CFG_CMD_KGDB) +#define CONFIG_KGDB_BAUDRATE 230400 /* speed to run kgdb serial port */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ +#endif + +#if 0 +#define CONFIG_SHOW_ACTIVITY 1 +#endif + +#endif /* __CONFIG_H */ -- 1.5.3

1 0

[U-Boot-Users] [PATCH] cmd_nand : fix compiler warning.
by Jean-Christophe PLAGNIOL-VILLARD 13 Jan '08

13 Jan '08

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> diff --git a/common/cmd_nand.c b/common/cmd_nand.c index b248a2c..8d6c959 100644 --- a/common/cmd_nand.c +++ b/common/cmd_nand.c @@ -350,10 +350,10 @@ int do_nand(cmd_tbl_t * cmdtp, int flag, int argc, char *argv[]) } else if (s != NULL && !strcmp(s, ".oob")) { /* read out-of-band data */ if (read) - ret = nand->read_oob(nand, off, size, &size, + ret = nand->read_oob(nand, off, size, (size_t *) &size, (u_char *) addr); else - ret = nand->write_oob(nand, off, size, &size, + ret = nand->write_oob(nand, off, size, (size_t *) &size, (u_char *) addr); } else { if (read) -- 1.5.3.7

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[U-Boot-Users] [PATCH 2/2] Implement hard SPI driver on MPC8349EMDS
by Ben Warren 13 Jan '08

13 Jan '08

This patch implements the fsl_spi driver on the MPC8349EMDS evaluation board. This board has an ST M25P40 4Mbit EEPROM on its SPI bus Signed-off-by: Ben Warren <biggerbadderben(a)gmail.com> --- board/freescale/mpc8349emds/mpc8349emds.c | 29 +++++++++++++++++++++++++++++ include/configs/MPC8349EMDS.h | 10 ++++++++++ 2 files changed, 39 insertions(+), 0 deletions(-) diff --git a/board/freescale/mpc8349emds/mpc8349emds.c b/board/freescale/mpc8349emds/mpc8349emds.c index 3d72eb7..3fb2a45 100644 --- a/board/freescale/mpc8349emds/mpc8349emds.c +++ b/board/freescale/mpc8349emds/mpc8349emds.c @@ -27,6 +27,7 @@ #include <mpc83xx.h> #include <asm/mpc8349_pci.h> #include <i2c.h> +#include <spi.h> #include <spd.h> #include <miiphy.h> #if defined(CONFIG_SPD_EEPROM) @@ -251,6 +252,34 @@ void sdram_init(void) } #endif +/* + * The following are used to control the SPI chip selects for the SPI command. + */ +#ifdef CONFIG_HARD_SPI + +#define SPI_CS_MASK 0x80000000 + +void spi_eeprom_chipsel(int cs) +{ + volatile gpio83xx_t *iopd = &((immap_t *)CFG_IMMR)->gpio[0]; + + if(cs) + iopd->dat &= ~SPI_CS_MASK; + else + iopd->dat |= SPI_CS_MASK; +} + +/* + * The SPI command uses this table of functions for controlling the SPI + * chip selects. + */ +spi_chipsel_type spi_chipsel[] = { + spi_eeprom_chipsel, +}; +int spi_chipsel_cnt = sizeof(spi_chipsel) / sizeof(spi_chipsel[0]); + +#endif /* CONFIG_HARD_SPI */ + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/MPC8349EMDS.h b/include/configs/MPC8349EMDS.h index 437a9a5..584c59d 100644 --- a/include/configs/MPC8349EMDS.h +++ b/include/configs/MPC8349EMDS.h @@ -355,6 +355,16 @@ #define CFG_I2C_OFFSET 0x3000 #define CFG_I2C2_OFFSET 0x3100 +/* SPI */ +#define CONFIG_HARD_SPI /* SPI with hardware support*/ +#undef CONFIG_SOFT_SPI /* SPI bit-banged */ +#define CONFIG_FSL_SPI + +/* GPIOs. Used as SPI chip selects */ +#define CFG_GPIO1_PRELIM +#define CFG_GPIO1_DIR 0xC0000000 /* SPI CS on 0, LED on 1 */ +#define CFG_GPIO1_DAT 0xC0000000 /* Both are active LOW */ + /* TSEC */ #define CFG_TSEC1_OFFSET 0x24000 #define CFG_TSEC1 (CFG_IMMR+CFG_TSEC1_OFFSET) -- 1.5.2.5

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[U-Boot-Users] Misc minor fixes
by Wolfgang Denk 13 Jan '08

13 Jan '08

Hi, I tried to clean up a few (usually minor) compile problems in the current tree; you may want to update your repos, and/or review the following commits: commit 2b2f43ed6a30ece77f76191c845ac95267daa31a MPC8360ERDK: fix incorrect initialization of CFG_I2C_NOPROBES commit 08e99e1dd01a3e0e3dc3a7138eb827c997e2b74d MPC8xx FEC driver: fix compiler warning. commit ae6d1056d2c2e4d1266413c0ae8a6d5529ecde4b - get rid of "version" target whichdidn't really work - make autoconf.mk depend on version_autogenerated.h to make sure to rebuild files as needed - add XECHO macro to allow for silent build using "make -s" commit e343ab83d5135b558aa58db9be8fc7faa68d77ed ADS5121e: fix compile warning commit f2b6f4610627fe3d607620e25082916a01538875 MUNICes: fix board Makefile for remote build directory Best regards, Wolfgang Denk -- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Why don't you have a Linux partition installed so you can be working in a programmer-friendly environment instead of a keep-gates'-bank- account-happy one? :-) -- Tom Christiansen

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[U-Boot-Users] [PATCH 1/3] Add the RapidIO framework for U-Boot
by Zhang Wei 13 Jan '08

13 Jan '08

The patch adds the RapidIO framework into U-Boot. The board configuration can be added into individual rio_init_board() function. Some functions about RapidIO can be added later. The support for Freescale PowerPC RapidIO controller is also added. Signed-off-by: Zhang Wei <wei.zhang(a)freescale.com> --- Makefile | 1 + drivers/rio/Makefile | 35 ++++++++++++++++++++++++++ drivers/rio/fsl_rio.c | 64 ++++++++++++++++++++++++++++++++++++++++++++++++ drivers/rio/rio.c | 65 +++++++++++++++++++++++++++++++++++++++++++++++++ include/common.h | 3 ++ include/rio.h | 46 ++++++++++++++++++++++++++++++++++ include/rio_ids.h | 9 +++++++ lib_ppc/board.c | 5 ++++ 8 files changed, 228 insertions(+), 0 deletions(-) create mode 100644 drivers/rio/Makefile create mode 100644 drivers/rio/fsl_rio.c create mode 100644 drivers/rio/rio.c create mode 100644 include/rio.h create mode 100644 include/rio_ids.h diff --git a/Makefile b/Makefile index 1983ca0..1f3f26a 100644 --- a/Makefile +++ b/Makefile @@ -228,6 +228,7 @@ endif ifeq ($(CPU),mpc85xx) LIBS += drivers/qe/qe.a endif +LIBS += drivers/rio/librio.a LIBS += drivers/rtc/librtc.a LIBS += drivers/serial/libserial.a LIBS += drivers/usb/libusb.a diff --git a/drivers/rio/Makefile b/drivers/rio/Makefile new file mode 100644 index 0000000..4b940c2 --- /dev/null +++ b/drivers/rio/Makefile @@ -0,0 +1,35 @@ +# +# Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved. +# +# Author: Zhang Wei, wei.zhang(a)freescale.com, Jan 2008 +# +# This is free software; you can redistribute it and/or modify +# it under the terms of the GNU General Public License as published by +# the Free Software Foundation; either version 2 of the License, or +# (at your option) any later version. +# + +include $(TOPDIR)/config.mk + +LIB := $(obj)librio.a + +COBJS-y += rio.o +COBJS-y += fsl_rio.o + +COBJS := $(COBJS-y) +SRCS := $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) + +all: $(LIB) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/drivers/rio/fsl_rio.c b/drivers/rio/fsl_rio.c new file mode 100644 index 0000000..c8bfa92 --- /dev/null +++ b/drivers/rio/fsl_rio.c @@ -0,0 +1,64 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved. + * + * Author: Zhang Wei, wei.zhang(a)freescale.com, Jan 2008 + * + * Description: + * Freescale PowerPC RapidIO controller initialization file. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <common.h> + +#ifdef CONFIG_RAPIDIO +#include <command.h> +#include <malloc.h> +#include <rio.h> +#include <rio_ids.h> + +#include <asm/processor.h> +#include <asm/io.h> +#include <asm/immap_86xx.h> +#include <asm/io.h> + +void fsl_rio_init(void *base, int busno) +{ + struct rio_dev *dev; + volatile ccsr_rio_t *rio = base; + struct rio_controller *hose; + + dev = malloc(sizeof(struct rio_dev)); + memset(dev, 0, sizeof(struct rio_dev)); + + dev->vendor = in_be32(&rio->didcar) & 0xffff; + dev->device = (in_be32(&rio->didcar) >> 16) & 0xffff; + + hose = malloc(sizeof(struct rio_controller)); + memset(hose, 0, sizeof(struct rio_controller)); + + INIT_LIST_HEAD(&hose->dev_list); + hose->busno = busno; + hose->base = base; + hose->self = dev; + list_add_tail(&hose->node, &rio_hose_list); + + printf("RIO%d (%04x:%04x) on 0x%08x\n", hose->busno, dev->vendor, + dev->device, base); +} + +void fsl_rio_quirk(struct rio_controller *hose, struct rio_dev *rdev) +{ +#ifdef FSL_RIO_IP_V2 + volatile ccsr_rio_t *rio = hose->base; + /* Set the controller to accept all packets + * without checking the target ID + */ + out_be32(&rio->ptaacr, 1); +#endif +} +#endif diff --git a/drivers/rio/rio.c b/drivers/rio/rio.c new file mode 100644 index 0000000..9391384 --- /dev/null +++ b/drivers/rio/rio.c @@ -0,0 +1,65 @@ +/* + * Copyright (C) 2007-2008 Freescale Semiconductor, Inc. All rights reserved. + * + * Author: Zhang Wei, wei.zhang(a)freescale.com, Jun 2007 + * + * Description: + * RapidIO initialization file. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#include <common.h> + +#ifdef CONFIG_RAPIDIO + +#include <command.h> +#include <linux/list.h> +#include <rio.h> +#include <rio_ids.h> +#include <asm/processor.h> +#include <asm/io.h> + +struct list_head rio_hose_list; + +struct rio_quirk rio_post_quirk[] = { + {RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548E, fsl_rio_quirk}, + {RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8548, fsl_rio_quirk}, + {RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568E, fsl_rio_quirk}, + {RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8568, fsl_rio_quirk}, + {RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641, fsl_rio_quirk}, + {RIO_VENDOR_ID_FREESCALE, RIO_DEVICE_ID_MPC8641D, fsl_rio_quirk}, + {}, +}; + +void rio_hose_post(void) +{ + struct rio_controller *hose; + struct rio_quirk *post_quirk; + + list_for_each_entry(hose, &rio_hose_list, node) + for (post_quirk = rio_post_quirk; + post_quirk->vendor || post_quirk->device; post_quirk++) + if ((post_quirk->vendor == hose->self->vendor) + && (post_quirk->device == hose->self->device) + && post_quirk->quirk) { + post_quirk->quirk(hose, hose->self); + break; + } +} + +void rio_init(void) +{ + INIT_LIST_HEAD(&rio_hose_list); + + /* Call board specific rio_init() */ + rio_init_board(); + + rio_hose_post(); +} + +#endif /* CONFIG_RAPIDIO */ diff --git a/include/common.h b/include/common.h index 9ef9344..84ff943 100644 --- a/include/common.h +++ b/include/common.h @@ -275,6 +275,9 @@ void pciinfo (int, int); #endif #endif +void rio_init (void); +void rio_init_board(void); + int misc_init_f (void); int misc_init_r (void); diff --git a/include/rio.h b/include/rio.h new file mode 100644 index 0000000..379c56c --- /dev/null +++ b/include/rio.h @@ -0,0 +1,46 @@ +/* + * Copyright (C) 2008 Freescale Semiconductor, Inc. All rights reserved. + * + * This is free software; you can redistribute it and/or modify + * it under the terms of the GNU General Public License as published by + * the Free Software Foundation; either version 2 of the License, or + * (at your option) any later version. + * + */ + +#ifndef __INCLUDE_RIO_H_ +#define __INCLUDE_RIO_H_ + +#include <linux/list.h> + +struct rio_dev { + struct list_head node; + u16 vendor; /* Vendor ID */ + u16 device; /* Device ID */ + + u32 devno; /* Device number */ + u32 hostno; /* Host number in the bus */ +}; + +struct rio_controller { + struct list_head node; + struct list_head dev_list; + + int busno; + + struct rio_dev *self; /* Controler RIO device */ + void *base; /* Register base */ +}; + +struct rio_quirk { + u16 vendor; + u16 device; + void (*quirk)(struct rio_controller *hose, struct rio_dev *dev); +}; + +void fsl_rio_init(void *base, int busno); +void fsl_rio_quirk(struct rio_controller *hose, struct rio_dev *rdev); + +extern struct list_head rio_hose_list; + +#endif /* __INCLUDE_RIO_H_ */ diff --git a/include/rio_ids.h b/include/rio_ids.h new file mode 100644 index 0000000..b6a4ab8 --- /dev/null +++ b/include/rio_ids.h @@ -0,0 +1,9 @@ + +#define RIO_VENDOR_ID_FREESCALE 0x0002 + +#define RIO_DEVICE_ID_MPC8548E 0x0012 +#define RIO_DEVICE_ID_MPC8548 0x0013 +#define RIO_DEVICE_ID_MPC8568E 0x0020 +#define RIO_DEVICE_ID_MPC8568 0x0021 +#define RIO_DEVICE_ID_MPC8641 0x7010 +#define RIO_DEVICE_ID_MPC8641D 0x7011 diff --git a/lib_ppc/board.c b/lib_ppc/board.c index 0719745..75746ff 100644 --- a/lib_ppc/board.c +++ b/lib_ppc/board.c @@ -921,6 +921,11 @@ void board_init_r (gd_t *id, ulong dest_addr) pci_init (); #endif +#if defined(CONFIG_RAPIDIO) + /* Do RapidIO configuration */ + rio_init (); +#endif + /** leave this here (after malloc(), environment and PCI are working) **/ /* Initialize devices */ devices_init (); -- 1.5.2

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Re: [U-Boot-Users] [PATCH] Not use absolute MBAR in MPC5200 Bestcomm firmware
by Oliver Weber 12 Jan '08

12 Jan '08

I hope now everything is ok with the format. Best Regards Oliver Weber Signed-off-by: Oliver Weber <almoeli(a)gmx.de> diff --git a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S index 1d83fe2..a07c776 100644 --- a/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S +++ b/cpu/mpc5xxx/firmware_sc_task_bestcomm.impl.S @@ -23,7 +23,7 @@ scEthernetRecv_Entry: /* Task 0 */ .long 0x00000000 .long 0x00000000 .long scEthernetRecv_CSave - taskTable /* Task 0 context save space */ -.long 0xf0000000 +.long CFG_MBAR .globl scEthernetXmit_Entry scEthernetXmit_Entry: /* Task 1 */ .long scEthernetXmit_TDT - taskTable /* Task 1 Descriptor Table */ @@ -33,7 +33,7 @@ scEthernetXmit_Entry: /* Task 1 */ .long 0x00000000 .long 0x00000000 .long scEthernetXmit_CSave - taskTable /* Task 1 context save space */ -.long 0xf0000000 +.long CFG_MBAR .globl scEthernetRecv_TDT @@ -151,7 +151,7 @@ scEthernetRecv_VarTab: /* Task 0 Variabl .long 0x00000000 /* var[6] */ .long 0x00000000 /* var[7] */ .long 0x00000000 /* var[8] */ -.long 0xf0008800 /* var[9] */ +.long (CFG_MBAR + 0x8800) /* var[9] */ .long 0x00000008 /* var[10] */ .long 0x0000000c /* var[11] */ .long 0x80000000 /* var[12] */ @@ -190,7 +190,7 @@ scEthernetXmit_VarTab: /* Task 1 Variabl .long 0x00000000 /* var[8] */ .long 0x00000000 /* var[9] */ .long 0x00000000 /* var[10] */ -.long 0xf0008800 /* var[11] */ +.long (CFG_MBAR + 0x8800) /* var[11] */ .long 0x00000000 /* var[12] */ .long 0x80000000 /* var[13] */ .long 0x10000000 /* var[14] */ -- Der GMX SmartSurfer hilft bis zu 70% Ihrer Onlinekosten zu sparen! Ideal für Modem und ISDN: http://www.gmx.net/de/go/smartsurfer

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