January 2008 - U-Boot

[U-Boot-Users] [PATCH] Add support for the TK885D baseboard from TELE-DATA
by Guennadi Liakhovetski 12 Jan '08

12 Jan '08

The TK885D board uses a TQM885D module from TQ, this port adds an own configuration file and adds a last_stage_init() method to configure the two PHYs, depending on the phy_auto_nego environment variable. Signed-off-by: Guennadi Liakhovetski <lg(a)denx.de> --- MAKEALL | 1 + Makefile | 1 + board/tqm8xx/tqm8xx.c | 47 +++++ include/configs/TK885D.h | 513 ++++++++++++++++++++++++++++++++++++++++++++++ 4 files changed, 562 insertions(+), 0 deletions(-) create mode 100644 include/configs/TK885D.h diff --git a/MAKEALL b/MAKEALL index ebc5a22..e770a66 100755 --- a/MAKEALL +++ b/MAKEALL @@ -135,6 +135,7 @@ LIST_8xx=" \ SPD823TS \ svm_sc8xx \ SXNI855T \ + TK885D \ TOP860 \ TQM823L \ TQM823L_LCD \ diff --git a/Makefile b/Makefile index 1983ca0..457a064 100644 --- a/Makefile +++ b/Makefile @@ -1062,6 +1062,7 @@ TQM860M_config \ TQM862M_config \ TQM866M_config \ TQM885D_config \ +TK885D_config \ virtlab2_config: unconfig @mkdir -p $(obj)include @ >$(obj)include/config.h diff --git a/board/tqm8xx/tqm8xx.c b/board/tqm8xx/tqm8xx.c index fcd941e..18bf2a8 100644 --- a/board/tqm8xx/tqm8xx.c +++ b/board/tqm8xx/tqm8xx.c @@ -504,4 +504,51 @@ int misc_init_r (void) } #endif /* CONFIG_NSCU */ +/* ---------------------------------------------------------------------------- */ +/* TK885D specific initializaion */ +/* ---------------------------------------------------------------------------- */ +#ifdef CONFIG_TK885D +#include <miiphy.h> +int last_stage_init(void) +{ + const unsigned char phy[] = {CONFIG_FEC1_PHY, CONFIG_FEC2_PHY}; + unsigned short reg; + int ret, i = 100; + char *s; + + mii_init(); + /* Without this delay 0xff is read from the UART buffer later in + * abortboot() and autoboot is aborted */ + udelay(10000); + while (tstc() && i--) + (void)getc(); + + /* Check if auto-negotiation is prohibited */ + s = getenv("phy_auto_nego"); + + if (!s || !strcmp(s, "on")) + /* Nothing to do - autonegotiation by default */ + return 0; + + for (i = 0; i < 2; i++) { + ret = miiphy_read("FEC ETHERNET", phy[i], PHY_BMCR, &reg); + if (ret) { + printf("Cannot read BMCR on PHY %d\n", phy[i]); + return 0; + } + /* Auto-negotiation off, hard set full duplex, 100Mbps */ + ret = miiphy_write("FEC ETHERNET", phy[i], + PHY_BMCR, (reg | PHY_BMCR_100MB | + PHY_BMCR_DPLX) & ~PHY_BMCR_AUTON); + if (ret) { + printf("Cannot write BMCR on PHY %d\n", phy[i]); + return 0; + } + } + + return 0; +} + +#endif + /* ------------------------------------------------------------------------- */ diff --git a/include/configs/TK885D.h b/include/configs/TK885D.h new file mode 100644 index 0000000..761a352 --- /dev/null +++ b/include/configs/TK885D.h @@ -0,0 +1,513 @@ +/* + * (C) Copyright 2000-2005 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2006 + * Martin Krause, TQ-Systems GmBH, martin.krause(a)tqs.de + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +/* + * board/config.h - configuration options, board specific + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* + * High Level Configuration Options + * (easy to change) + */ + +#define CONFIG_MPC885 1 /* This is a MPC885 CPU */ +#define CONFIG_TQM885D 1 /* ...on a TQM88D module */ +#define CONFIG_TK885D 1 /* ...in a TK885D base board */ + +#define CONFIG_8xx_OSCLK 10000000 /* 10 MHz - PLL input clock */ +#define CFG_8xx_CPUCLK_MIN 15000000 /* 15 MHz - CPU minimum clock */ +#define CFG_8xx_CPUCLK_MAX 133000000 /* 133 MHz - CPU maximum clock */ +#define CONFIG_8xx_CPUCLK_DEFAULT 66000000 /* 66 MHz - CPU default clock */ + /* (it will be used if there is no */ + /* 'cpuclk' variable with valid value) */ + +#define CONFIG_8xx_CONS_SMC1 1 /* Console is on SMC1 */ + +#define CONFIG_BAUDRATE 115200 /* console baudrate = 115kbps */ + +#define CONFIG_BOOTCOUNT_LIMIT + +#define CONFIG_BOOTDELAY 5 /* autoboot after 5 seconds */ + +#define CONFIG_BOARD_TYPES 1 /* support board types */ + +#define CONFIG_PREBOOT "echo;" \ + "echo Type \"run flash_nfs\" to mount root filesystem over NFS;" \ + "echo" + +#undef CONFIG_BOOTARGS + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "netdev=eth0\0" \ + "nfsargs=setenv bootargs root=/dev/nfs rw " \ + "nfsroot=${serverip}:${rootpath}\0" \ + "ramargs=setenv bootargs root=/dev/ram rw\0" \ + "addip=setenv bootargs ${bootargs} " \ + "ip=${ipaddr}:${serverip}:${gatewayip}:${netmask}" \ + ":${hostname}:${netdev}:off panic=1\0" \ + "flash_nfs=run nfsargs addip;" \ + "bootm ${kernel_addr}\0" \ + "flash_self=run ramargs addip;" \ + "bootm ${kernel_addr} ${ramdisk_addr}\0" \ + "net_nfs=tftp 200000 ${bootfile};run nfsargs addip;bootm\0" \ + "rootpath=/opt/eldk/ppc_8xx\0" \ + "bootfile=/tftpboot/TQM885D/uImage\0" \ + "kernel_addr=40080000\0" \ + "ramdisk_addr=40180000\0" \ + "load=tftp 200000 ${u-boot}\0" \ + "update=protect off 40000000 +${filesize};" \ + "erase 40000000 +${filesize};" \ + "cp.b 200000 40000000 ${filesize};" \ + "protect on 40000000 +${filesize}\0" \ + "" +#define CONFIG_BOOTCOMMAND "run flash_self" + +#define CONFIG_LOADS_ECHO 1 /* echo on for serial download */ +#undef CFG_LOADS_BAUD_CHANGE /* don't allow baudrate change */ + +#undef CONFIG_WATCHDOG /* watchdog disabled */ + +#define CONFIG_STATUS_LED 1 /* Status LED enabled */ + +#undef CONFIG_CAN_DRIVER /* CAN Driver support disabled */ + +/* enable I2C and select the hardware/software driver */ +#undef CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_SOFT_I2C 1 /* I2C bit-banged */ + +#define CFG_I2C_SPEED 93000 /* 93 kHz is supposed to work */ +#define CFG_I2C_SLAVE 0xFE + +#ifdef CONFIG_SOFT_I2C +/* + * Software (bit-bang) I2C driver configuration + */ +#define PB_SCL 0x00000020 /* PB 26 */ +#define PB_SDA 0x00000010 /* PB 27 */ + +#define I2C_INIT (immr->im_cpm.cp_pbdir |= PB_SCL) +#define I2C_ACTIVE (immr->im_cpm.cp_pbdir |= PB_SDA) +#define I2C_TRISTATE (immr->im_cpm.cp_pbdir &= ~PB_SDA) +#define I2C_READ ((immr->im_cpm.cp_pbdat & PB_SDA) != 0) +#define I2C_SDA(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SDA; \ + else immr->im_cpm.cp_pbdat &= ~PB_SDA +#define I2C_SCL(bit) if(bit) immr->im_cpm.cp_pbdat |= PB_SCL; \ + else immr->im_cpm.cp_pbdat &= ~PB_SCL +#define I2C_DELAY udelay(2) /* 1/4 I2C clock duration */ +#endif /* CONFIG_SOFT_I2C */ + +#define CFG_I2C_EEPROM_ADDR 0x50 /* EEPROM AT24C?? */ +#define CFG_I2C_EEPROM_ADDR_LEN 2 /* two byte address */ +#define CFG_EEPROM_PAGE_WRITE_BITS 4 +#define CFG_EEPROM_PAGE_WRITE_DELAY_MS 10 /* and takes up to 10 msec */ + +# define CONFIG_RTC_DS1337 1 +# define CFG_I2C_RTC_ADDR 0x68 + +/* + * BOOTP options + */ +#define CONFIG_BOOTP_SUBNETMASK +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_BOOTFILESIZE + + +#define CONFIG_MAC_PARTITION +#define CONFIG_DOS_PARTITION + +#undef CONFIG_RTC_MPC8xx /* MPC885 does not support RTC */ + +#define CONFIG_TIMESTAMP /* but print image timestmps */ + + +/* + * Command line configuration. + */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ASKENV +#define CONFIG_CMD_DATE +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_EEPROM +#define CONFIG_CMD_I2C +#define CONFIG_CMD_IDE +#define CONFIG_CMD_MII +#define CONFIG_CMD_NFS +#define CONFIG_CMD_PING + + +/* + * Miscellaneous configurable options + */ +#define CFG_LONGHELP /* undef to save memory */ +#define CFG_PROMPT "=> " /* Monitor Command Prompt */ + +#define CONFIG_CMDLINE_EDITING 1 /* add command line history */ +#define CFG_HUSH_PARSER 1 /* Use the HUSH parser */ +#ifdef CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " +#endif + +#if defined(CONFIG_CMD_KGDB) +#define CFG_CBSIZE 1024 /* Console I/O Buffer Size */ +#else +#define CFG_CBSIZE 256 /* Console I/O Buffer Size */ +#endif +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print Buffer Size */ +#define CFG_MAXARGS 16 /* max number of command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot Argument Buffer Size */ + +#define CFG_MEMTEST_START 0x0100000 /* memtest works on */ +#define CFG_MEMTEST_END 0x0300000 /* 1 ... 3 MB in DRAM */ +#define CFG_ALT_MEMTEST /* alternate, more extensive + memory test.*/ + +#define CFG_LOAD_ADDR 0x100000 /* default load address */ + +#define CFG_HZ 1000 /* decrementer freq: 1 ms ticks */ + +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 } + +/* + * Enable loopw command. + */ +#define CONFIG_LOOPW + +/* + * Low Level Configuration Settings + * (address mappings, register initial values, etc.) + * You should know what you are doing if you make changes here. + */ +/*----------------------------------------------------------------------- + * Internal Memory Mapped Register + */ +#define CFG_IMMR 0xFFF00000 + +/*----------------------------------------------------------------------- + * Definitions for initial stack pointer and data area (in DPRAM) + */ +#define CFG_INIT_RAM_ADDR CFG_IMMR +#define CFG_INIT_RAM_END 0x2F00 /* End of used area in DPRAM */ +#define CFG_GBL_DATA_SIZE 64 /* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET + +/*----------------------------------------------------------------------- + * Start addresses for the final memory configuration + * (Set up by the startup code) + * Please note that CFG_SDRAM_BASE _must_ start at 0 + */ +#define CFG_SDRAM_BASE 0x00000000 +#define CFG_FLASH_BASE 0x40000000 +#define CFG_MONITOR_LEN (256 << 10) /* Reserve 256 kB for Monitor */ +#define CFG_MONITOR_BASE CFG_FLASH_BASE +#define CFG_MALLOC_LEN (256 << 10) /* Reserve 128 kB for malloc() */ + +/* + * For booting Linux, the board info and command line data + * have to be in the first 8 MB of memory, since this is + * the maximum mapped by the Linux kernel during initialization. + */ +#define CFG_BOOTMAPSZ (8 << 20) /* Initial Memory map for Linux */ + +/*----------------------------------------------------------------------- + * FLASH organization + */ + +/* use CFI flash driver */ +#define CFG_FLASH_CFI 1 /* Flash is CFI conformant */ +#define CFG_FLASH_CFI_DRIVER 1 /* Use the common driver */ +#define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } +#define CFG_FLASH_EMPTY_INFO +#define CFG_FLASH_USE_BUFFER_WRITE 1 +#define CFG_MAX_FLASH_BANKS 1 /* max number of memory banks */ +#define CFG_MAX_FLASH_SECT 256 /* max number of sectors on one chip */ + +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_OFFSET 0x40000 /* Offset of Environment Sector */ +#define CFG_ENV_SIZE 0x08000 /* Total Size of Environment */ +#define CFG_ENV_SECT_SIZE 0x20000 /* Total Size of Environment Sector */ + +/* Address and size of Redundant Environment Sector */ +#define CFG_ENV_OFFSET_REDUND (CFG_ENV_OFFSET+CFG_ENV_SECT_SIZE) +#define CFG_ENV_SIZE_REDUND (CFG_ENV_SIZE) + +/*----------------------------------------------------------------------- + * Hardware Information Block + */ +#define CFG_HWINFO_OFFSET 0x0003FFC0 /* offset of HW Info block */ +#define CFG_HWINFO_SIZE 0x00000040 /* size of HW Info block */ +#define CFG_HWINFO_MAGIC 0x54514D38 /* 'TQM8' */ + +/*----------------------------------------------------------------------- + * Cache Configuration + */ +#define CFG_CACHELINE_SIZE 16 /* For all MPC8xx CPUs */ +#if defined(CONFIG_CMD_KGDB) +#define CFG_CACHELINE_SHIFT 4 /* log base 2 of the above value */ +#endif + +/*----------------------------------------------------------------------- + * SYPCR - System Protection Control 11-9 + * SYPCR can only be written once after reset! + *----------------------------------------------------------------------- + * Software & Bus Monitor Timer max, Bus Monitor enable, SW Watchdog freeze + */ +#if defined(CONFIG_WATCHDOG) +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | \ + SYPCR_SWE | SYPCR_SWRI| SYPCR_SWP) +#else +#define CFG_SYPCR (SYPCR_SWTC | SYPCR_BMT | SYPCR_BME | SYPCR_SWF | SYPCR_SWP) +#endif + +/*----------------------------------------------------------------------- + * SIUMCR - SIU Module Configuration 11-6 + *----------------------------------------------------------------------- + * PCMCIA config., multi-function pin tri-state + */ +#ifndef CONFIG_CAN_DRIVER +#define CFG_SIUMCR (SIUMCR_DBGC00 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#else /* we must activate GPL5 in the SIUMCR for CAN */ +#define CFG_SIUMCR (SIUMCR_DBGC11 | SIUMCR_DBPC00 | SIUMCR_MLRC01) +#endif /* CONFIG_CAN_DRIVER */ + +/*----------------------------------------------------------------------- + * TBSCR - Time Base Status and Control 11-26 + *----------------------------------------------------------------------- + * Clear Reference Interrupt Status, Timebase freezing enabled + */ +#define CFG_TBSCR (TBSCR_REFA | TBSCR_REFB | TBSCR_TBF) + +/*----------------------------------------------------------------------- + * PISCR - Periodic Interrupt Status and Control 11-31 + *----------------------------------------------------------------------- + * Clear Periodic Interrupt Status, Interrupt Timer freezing enabled + */ +#define CFG_PISCR (PISCR_PS | PISCR_PITF) + +/*----------------------------------------------------------------------- + * SCCR - System Clock and reset Control Register 15-27 + *----------------------------------------------------------------------- + * Set clock output, timebase and RTC source and divider, + * power management and some other internal clocks + */ +#define SCCR_MASK SCCR_EBDF11 +#define CFG_SCCR (SCCR_COM00 | SCCR_DFSYNC00 | SCCR_DFBRG00 | \ + SCCR_DFNL000 | SCCR_DFNH000 | SCCR_DFLCD000 | \ + SCCR_DFALCD00) + +/*----------------------------------------------------------------------- + * PCMCIA stuff + *----------------------------------------------------------------------- + * + */ +#define CFG_PCMCIA_MEM_ADDR (0xE0000000) +#define CFG_PCMCIA_MEM_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_DMA_ADDR (0xE4000000) +#define CFG_PCMCIA_DMA_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_ATTRB_ADDR (0xE8000000) +#define CFG_PCMCIA_ATTRB_SIZE ( 64 << 20 ) +#define CFG_PCMCIA_IO_ADDR (0xEC000000) +#define CFG_PCMCIA_IO_SIZE ( 64 << 20 ) + +/*----------------------------------------------------------------------- + * IDE/ATA stuff (Supports IDE harddisk on PCMCIA Adapter) + *----------------------------------------------------------------------- + */ + +#define CONFIG_IDE_8xx_PCCARD 1 /* Use IDE with PC Card Adapter */ + +#undef CONFIG_IDE_8xx_DIRECT /* Direct IDE not supported */ +#undef CONFIG_IDE_LED /* LED for ide not supported */ +#undef CONFIG_IDE_RESET /* reset for ide not supported */ + +#define CFG_IDE_MAXBUS 1 /* max. 1 IDE bus */ +#define CFG_IDE_MAXDEVICE 1 /* max. 1 drive per IDE bus */ + +#define CFG_ATA_IDE0_OFFSET 0x0000 + +#define CFG_ATA_BASE_ADDR CFG_PCMCIA_MEM_ADDR + +/* Offset for data I/O */ +#define CFG_ATA_DATA_OFFSET (CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for normal register accesses */ +#define CFG_ATA_REG_OFFSET (2 * CFG_PCMCIA_MEM_SIZE + 0x320) + +/* Offset for alternate registers */ +#define CFG_ATA_ALT_OFFSET 0x0100 + +/*----------------------------------------------------------------------- + * + *----------------------------------------------------------------------- + * + */ +#define CFG_DER 0 + +/* + * Init Memory Controller: + * + * BR0/1 and OR0/1 (FLASH) + */ + +#define FLASH_BASE0_PRELIM 0x40000000 /* FLASH bank #0 */ +#define FLASH_BASE1_PRELIM 0x60000000 /* FLASH bank #0 */ + +/* used to re-map FLASH both when starting from SRAM or FLASH: + * restrict access enough to keep SRAM working (if any) + * but not too much to meddle with FLASH accesses + */ +#define CFG_REMAP_OR_AM 0x80000000 /* OR addr mask */ +#define CFG_PRELIM_OR_AM 0xE0000000 /* OR addr mask */ + +/* + * FLASH timing: Default value of OR0 after reset + */ +#define CFG_OR_TIMING_FLASH (OR_CSNT_SAM | OR_ACS_MSK | OR_BI | \ + OR_SCY_6_CLK | OR_TRLX) + +#define CFG_OR0_REMAP (CFG_REMAP_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_OR0_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_FLASH) +#define CFG_BR0_PRELIM ((FLASH_BASE0_PRELIM & BR_BA_MSK) | BR_V ) + +#define CFG_OR1_REMAP CFG_OR0_REMAP +#define CFG_OR1_PRELIM CFG_OR0_PRELIM +#define CFG_BR1_PRELIM ((FLASH_BASE1_PRELIM & BR_BA_MSK) | BR_V ) + +/* + * BR2/3 and OR2/3 (SDRAM) + * + */ +#define SDRAM_BASE2_PRELIM 0x00000000 /* SDRAM bank #0 */ +#define SDRAM_BASE3_PRELIM 0x20000000 /* SDRAM bank #1 */ +#define SDRAM_MAX_SIZE (256 << 20) /* max 256 MB per bank */ + +/* SDRAM timing: Multiplexed addresses, GPL5 output to GPL5_A (don't care) */ +#define CFG_OR_TIMING_SDRAM 0x00000A00 + +#define CFG_OR2_PRELIM (CFG_PRELIM_OR_AM | CFG_OR_TIMING_SDRAM ) +#define CFG_BR2_PRELIM ((SDRAM_BASE2_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) + +#ifndef CONFIG_CAN_DRIVER +#define CFG_OR3_PRELIM CFG_OR2_PRELIM +#define CFG_BR3_PRELIM ((SDRAM_BASE3_PRELIM & BR_BA_MSK) | BR_MS_UPMA | BR_V ) +#else /* CAN uses CS3#, so we can have only one SDRAM bank anyway */ +#define CFG_CAN_BASE 0xC0000000 /* CAN mapped at 0xC0000000 */ +#define CFG_CAN_OR_AM 0xFFFF8000 /* 32 kB address mask */ +#define CFG_OR3_CAN (CFG_CAN_OR_AM | OR_G5LA | OR_BI) +#define CFG_BR3_CAN ((CFG_CAN_BASE & BR_BA_MSK) | \ + BR_PS_8 | BR_MS_UPMB | BR_V ) +#endif /* CONFIG_CAN_DRIVER */ + +/* + * 4096 Rows from SDRAM example configuration + * 1000 factor s -> ms + * 64 PTP (pre-divider from MPTPR) from SDRAM example configuration + * 4 Number of refresh cycles per period + * 64 Refresh cycle in ms per number of rows + */ +#define CFG_PTA_PER_CLK ((4096 * 64 * 1000) / (4 * 64)) + +/* + * Periodic timer (MAMR[PTx]) for 4 * 7.8 us refresh (= 31.2 us per quad) + * + * CPUclock(MHz) * 31.2 + * CFG_MAMR_PTA = ----------------------------------- with DFBRG = 0 + * 2^(2*SCCR[DFBRG]) * MPTPR_PTP_DIV16 + * + * CPU clock = 15 MHz: CFG_MAMR_PTA = 29 -> 4 * 7.73 us + * CPU clock = 50 MHz: CFG_MAMR_PTA = 97 -> 4 * 7.76 us + * CPU clock = 66 MHz: CFG_MAMR_PTA = 128 -> 4 * 7.75 us + * CPU clock = 133 MHz: CFG_MAMR_PTA = 255 -> 4 * 7.67 us + * + * Value 97 is for 4 * 7.8 us at 50 MHz. So the refresh cycle requirement will + * be met also in the default configuration, i.e. if environment variable + * 'cpuclk' is not set. + */ +#define CFG_MAMR_PTA 128 + +/* + * Memory Periodic Timer Prescaler Register (MPTPR) values. + */ +/* 4 * 7.8 us refresh (= 31.2 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_4K MPTPR_PTP_DIV16 +/* 4 * 3.9 us refresh (= 15.6 us per quad) at 50 MHz and PTA = 97 */ +#define CFG_MPTPR_2BK_8K MPTPR_PTP_DIV8 + +/* + * MAMR settings for SDRAM + */ + +/* 8 column SDRAM */ +#define CFG_MAMR_8COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_0 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A11 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 9 column SDRAM */ +#define CFG_MAMR_9COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_1 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A10 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) +/* 10 column SDRAM */ +#define CFG_MAMR_10COL ((CFG_MAMR_PTA << MAMR_PTA_SHIFT) | MAMR_PTAE | \ + MAMR_AMA_TYPE_2 | MAMR_DSA_1_CYCL | MAMR_G0CLA_A9 | \ + MAMR_RLFA_1X | MAMR_WLFA_1X | MAMR_TLFA_4X) + +/* + * Internal Definitions + * + * Boot Flags + */ +#define BOOTFLAG_COLD 0x01 /* Normal Power-On: Boot from FLASH */ +#define BOOTFLAG_WARM 0x02 /* Software reboot */ + +/* + * Network configuration + */ +#define CONFIG_FEC_ENET /* enable ethernet on FEC */ +#define CONFIG_ETHER_ON_FEC1 /* ... for FEC1 */ +#define CONFIG_ETHER_ON_FEC2 /* ... for FEC2 */ + +#define CONFIG_LAST_STAGE_INIT 1 /* Have to configure PHYs for Linux */ + +/* CFG_DISCOVER_PHY only works with FEC if only one interface is enabled */ +#if (!defined(CONFIG_ETHER_ON_FEC1) || !defined(CONFIG_ETHER_ON_FEC2)) +#define CFG_DISCOVER_PHY +#endif + +#ifndef CFG_DISCOVER_PHY +/* PHY addresses - hard wired in hardware */ +#define CONFIG_FEC1_PHY 1 +#define CONFIG_FEC2_PHY 2 +#endif + +#define CONFIG_NET_RETRY_COUNT 3 +#define CONFIG_ETHPRIME "FEC ETHERNET" + +#endif /* __CONFIG_H */ -- 1.5.2.2

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[U-Boot-Users] Pull request: u-boot-video
by Rodolfo Giometti 12 Jan '08

12 Jan '08

The following changes since commit 20c450ef61ef2eb1c96f9b59ba0eb8d849bba058: Anatolij Gustschin (1): Fix video console newline and carriage return handling are available in the git repository at: git://www.denx.de/git/u-boot-video.git master Anatolij Gustschin (1): Add Fujitsu CoralP/Lime video driver drivers/video/Makefile | 1 + drivers/video/cfb_console.c | 42 +++++ drivers/video/mb862xx.c | 414 +++++++++++++++++++++++++++++++++++++++++++ include/mb862xx.h | 44 +++++ 4 files changed, 501 insertions(+), 0 deletions(-) create mode 100644 drivers/video/mb862xx.c create mode 100644 include/mb862xx.h

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[U-Boot-Users] Please pull u-boot-mpc83xx.git
by Kim Phillips 12 Jan '08

12 Jan '08

Wolfgang D., please pull: The following changes since commit 422b1a01602b6e2fbf8444a1192c7ba31461fd4c: Ben Warren (1): Fix Ethernet init() return codes are available in the git repository at: git://www.denx.de/git/u-boot-mpc83xx.git Anton Vorontsov (2): mpc83xx: add "fsl, qe" compatible fixups mpc83xx: add support for the MPC8360E-RDK Dave Liu (7): mpc83xx: Remove cache config from config.h mpc83xx: Fix the typo in global data struct mpc83xx: Fix the typo in mpc83xx.h mpc83xx: Fix the wrong definition of MPC8315E mpc83xx: Reduce the latency of DDR mpc83xx: Make the code more readable mpc83xx: Fix the bug of 266MHz data rate DDR Kim Phillips (1): mpc83xx: add missing CONFIG_HAS_ETH0 defines MAINTAINERS | 4 + MAKEALL | 2 + Makefile | 11 + board/freescale/mpc8360erdk/Makefile | 50 +++ board/freescale/mpc8360erdk/config.mk | 28 ++ board/freescale/mpc8360erdk/mpc8360erdk.c | 340 ++++++++++++++++++ cpu/mpc83xx/fdt.c | 6 + cpu/mpc83xx/spd_sdram.c | 6 +- include/asm-ppc/global_data.h | 2 +- include/configs/MPC8313ERDB.h | 5 - include/configs/MPC8323ERDB.h | 10 +- include/configs/MPC832XEMDS.h | 10 +- include/configs/MPC8349EMDS.h | 7 - include/configs/MPC8349ITX.h | 9 - include/configs/MPC8360EMDS.h | 10 +- include/configs/MPC8360ERDK.h | 538 +++++++++++++++++++++++++++++ include/configs/MPC837XEMDS.h | 38 +- include/configs/TQM834x.h | 9 - include/configs/sbc8349.h | 7 - include/mpc83xx.h | 56 ++-- 20 files changed, 1036 insertions(+), 112 deletions(-) create mode 100644 board/freescale/mpc8360erdk/Makefile create mode 100644 board/freescale/mpc8360erdk/config.mk create mode 100644 board/freescale/mpc8360erdk/mpc8360erdk.c create mode 100644 include/configs/MPC8360ERDK.h Thanks, Kim

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[U-Boot-Users] Please Pull u-boot-mpc86xx repository
by Jon Loeliger 12 Jan '08

12 Jan '08

The following changes since commit 6007f3251c0967adc13f2ed8be1b924ddc30124d: Wolfgang Denk (1): Coding Style cleanup, update CHANGELOG are available in the git repository at: git://www.denx.de/git/u-boot-mpc86xx.git master Becky Bruce (1): 86xx: Support 2GB DIMMs Jon Loeliger (3): 8610: Fix lingering compile warnings. Convert MPC8610HPCD to use libfdt. 86xx: Remove cache config from configs.h board/freescale/mpc8610hpcd/mpc8610hpcd.c | 78 ++++++++++++++++------------- cpu/mpc86xx/spd_sdram.c | 11 ++++- include/configs/MPC8610HPCD.h | 38 +++++--------- 3 files changed, 68 insertions(+), 59 deletions(-) This should cover these items from your recent patch list: 12818 01/04 Jon Loeliger [PATCH] Convert MPC8610HPCD to use libfdt. 12820 01/04 Timur Tabi [PATCH] 8610: Fix lingering compile warnings. Thanks, jdl

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[U-Boot-Users] U-Boot Ethernet Troubles
by Kyle McDowell 12 Jan '08

12 Jan '08

In the process of porting uboot to an MPC8280 board I've run into a problem with Ethernet. Ping and tftpboot failed and after examining the connection with Wireshark I noticed the initial ARP request is malformed. Observed malformed ARP request: 0000 ff ff ff ff ff ff 00 80 ff ff ff ff ff ff 00 80 ........ ........ 0010 ff ff ff ff ff ff 00 80 ff ff ff ff ff ff 00 80 ........ ........ 0020 00 00 00 00 00 00 0a 01 00 00 00 00 00 00 00 00 ........ ........ 0030 0a 01 00 00 00 00 00 00 0a 01 00 00 ........ .... The destination is correct along with the first 2 bytes of the source MAC address, but the request and the info portions are corrupted. The pattern looks vary suspicious. I just don't have a clue what in my configuration would cause this type of error. Example correct ARP request: 0000 ff ff ff ff ff ff 00 c0 CO RR EC T0 08 06 00 01 ........ ........ 0010 08 00 06 04 00 01 00 c0 CO RR EC T0 0a 01 01 01 ........ ........ 0020 ff ff ff ff ff ff 0a 01 01 0a 00 00 00 00 00 00 ........ ........ 0030 00 00 00 00 00 00 00 00 00 00 00 00 ........ .... In porting uboot to other boards in the past I've witnessed memory initialization errors causing issues during Ethernet transactions, but I'm fairly confident in my DRAM initialization for this board. The board has a long track record of working with other boot loaders and operating systems so a hardware failure is unlikely. Here is an excerpt from the configs header: /* * Select ethernet configuration * * If either CONFIG_ETHER_ON_SCC or CONFIG_ETHER_ON_FCC is selected, * then CONFIG_ETHER_INDEX must be set to the channel number (1-4 for * SCC, 1-3 for FCC) * * If CONFIG_ETHER_NONE is defined, then either the ethernet routines * must be defined elsewhere (as for the console), or CFG_CMD_NET must * be removed from CONFIG_COMMANDS to remove support for networking. */ #undef CONFIG_ETHER_ON_SCC /* Ethernet is not on SCC */ #define CONFIG_ETHER_ON_FCC /* Ethernet is on FCC */ #undef CONFIG_ETHER_NONE /* No external Ethernet */ #ifdef CONFIG_ETHER_ON_FCC #define CONFIG_ETHER_INDEX 1 /* FCC1 is used for Ethernet */ #if (CONFIG_ETHER_INDEX == 1) /* - Tx clock is CLK10 * - Rx clock is CLK12 * - BDs/buffers on 60x bus * - Full duplex */ #define CFG_CMXFCR_MASK (CMXFCR_FC1 | CMXFCR_RF1CS_MSK | CMXFCR_TF1CS_MSK) #define CFG_CMXFCR_VALUE (CMXFCR_RF1CS_CLK12 | CMXFCR_TF1CS_CLK10) #define CFG_CPMFCR_RAMTYPE 0 #define CFG_FCC_PSMR (FCC_PSMR_FDE | FCC_PSMR_LPB) #endif /* CONFIG_ETHER_INDEX */ #define CFG_PHY_ADDR 1 #define CONFIG_MII /* MII PHY management */ #define CONFIG_BITBANGMII /* Bit-banged MDIO interface */ #define CONFIG_RESET_PHY_R 1 /* * GPIO pins used for bit-banged MII communications */ #define MDIO_PORT 1 /* Port A */ #define PHY_RESET_PORT 1 /* Port A */ #define CFG_PHY_RESET 0x00000100 /*PC23 */ #define CFG_MDIO_PIN 0x00000080 /* PC24 */ #define CFG_MDC_PIN 0x00000040 /* PC25 */ #define MDIO_ACTIVE (iop->pdir |= CFG_MDIO_PIN) #define MDIO_TRISTATE (iop->pdir &= ~CFG_MDIO_PIN) #define MDIO_READ ((iop->pdat & CFG_MDIO_PIN) != 0) #define MDIO(bit) if(bit) iop->pdat |= CFG_MDIO_PIN; \ else iop->pdat &= ~CFG_MDIO_PIN #define MDC(bit) if(bit) iop->pdat |= CFG_MDC_PIN; \ else iop->pdat &= ~CFG_MDC_PIN #define MIIDELAY udelay(1) #endif /* CONFIG_ETHER_ON_FCC */ I've never used the DP83843 PHY before but believe I have the reset_phy function correct (the carrier sense and full duplex LEDs are illuminated: void reset_phy(void) { volatile ioport_t *iop = ioport_addr ((immap_t *) CFG_IMMR, PHY_RESET_PORT); iop->pdat |= CFG_PHY_RESET; MIIDELAY; iop->pdat &= ~CFG_PHY_RESET; udelay(1000); #if 0 unsigned short phy_data; bb_miiphy_read(NULL, CFG_PHY_ADDR, PHY_ANAR, &phy_data); bb_miiphy_read(NULL, CFG_PHY_ADDR, PHY_PHYSTS, &phy_data); bb_miiphy_read(NULL, CFG_PHY_ADDR, PHY_BMCR, &phy_data); #endif bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_ANAR, 0x01E0); bb_miiphy_write(NULL, CFG_PHY_ADDR, PHY_BMCR, 0x1200); } Here is what I see at the console: Net: FCC1 ETHERNET Reset Ethernet PHY ### main_loop entered: bootdelay=5 ### main_loop: bootcmd="<UNDEFINED>" => tftpboot 0x100000 image Trying FCC1 ETHERNET Using FCC1 ETHERNET device TFTP from server 10.1.1.12; our IP address is 10.1.1.26 Filename 'StarsA3I2K'. Load address: 0x100000 Loading: sending ARP for 0a01010c ARP broadcast 1 cycles: 60 status: 6c00 T sending ARP for 0a01010c ARP broadcast 1 cycles: 56 status: 6c00 T sending ARP for 0a01010c ARP broadcast 1 cycles: 66 status: 6c00 T sending ARP for 0a01010c ARP broadcast 1 cycles: 60 status: 6c00 Any ideas on potential problems or suggestions on steps for further debugging would be greatly appreciated. Thanks, Kyle McDowell

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[U-Boot-Users] Pull Request: u-boot-nios.git
by Scott McNutt 11 Jan '08

11 Jan '08

Nios2: remove common/cmd_bdinfo.c unused variable. Please pull from the merge branch at: git://www.denx.de/git/u-boot-nios.git merge The following changes since commit: 422b1a01602b6e2fbf8444a1192c7ba31461fd4c common/cmd_bdinfo.c | 2 ++ 1 files changed, 2 insertions(+), 0 deletions(-)

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[U-Boot-Users] [PATCH] TFTP: add host ip addr support
by Jean-Christophe PLAGNIOL-VILLARD 11 Jan '08

11 Jan '08

Signed-off-by: Jean-Christophe PLAGNIOL-VILLARD <plagnioj(a)jcrosoft.com> diff --git a/common/cmd_net.c b/common/cmd_net.c index 21682c0..2fb0e7c 100644 --- a/common/cmd_net.c +++ b/common/cmd_net.c @@ -51,7 +51,7 @@ int do_tftpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) U_BOOT_CMD( tftpboot, 3, 1, do_tftpb, "tftpboot- boot image via network using TFTP protocol\n", - "[loadAddress] [bootfilename]\n" + "[loadAddress] [host ip addr:bootfilename]\n" ); int do_rarpb (cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) diff --git a/net/tftp.c b/net/tftp.c index 8b95bcf..d5d6e65 100644 --- a/net/tftp.c +++ b/net/tftp.c @@ -34,7 +34,7 @@ #define TFTP_ERROR 5 #define TFTP_OACK 6 - +static IPaddr_t TftpServerIP; static int TftpServerPort; /* The UDP port at their end */ static int TftpOurPort; /* The UDP port at our end */ static int TftpTimeoutCount; @@ -231,7 +231,7 @@ TftpSend (void) break; } - NetSendUDPPacket(NetServerEther, NetServerIP, TftpServerPort, TftpOurPort, len); + NetSendUDPPacket(NetServerEther, TftpServerIP, TftpServerPort, TftpOurPort, len); } @@ -464,19 +464,27 @@ TftpStart (void) printf ("*** Warning: no boot file name; using '%s'\n", tftp_filename); } else { - tftp_filename = BootFile; + char *p=BootFile; + p = strchr (p, ':'); + if (p != NULL) { + TftpServerIP = string_to_ip (BootFile); + ++p; + strcpy (tftp_filename, p); + } else { + strcpy (tftp_filename, BootFile); + } } #if defined(CONFIG_NET_MULTI) printf ("Using %s device\n", eth_get_name()); #endif - puts ("TFTP from server "); print_IPaddr (NetServerIP); + puts ("TFTP from server "); print_IPaddr (TftpServerIP); puts ("; our IP address is "); print_IPaddr (NetOurIP); /* Check if we need to send across this subnet */ if (NetOurGatewayIP && NetOurSubnetMask) { IPaddr_t OurNet = NetOurIP & NetOurSubnetMask; - IPaddr_t ServerNet = NetServerIP & NetOurSubnetMask; + IPaddr_t ServerNet = TftpServerIP & NetOurSubnetMask; if (OurNet != ServerNet) { puts ("; sending through gateway "); -- 1.5.3.7

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[U-Boot-Users] [PATCH] Fix compiler warning
by Kumar Gala 11 Jan '08

11 Jan '08

main.c: In function 'readline_into_buffer': main.c:927: warning: unused variable 'p_buf' Signed-off-by: Kumar Gala <galak(a)kernel.crashing.org> --- common/main.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/common/main.c b/common/main.c index ad2a386..1c7d73e 100644 --- a/common/main.c +++ b/common/main.c @@ -924,7 +924,6 @@ int readline (const char *const prompt) int readline_into_buffer (const char *const prompt, char * buffer) { char *p = buffer; - char * p_buf = p; #ifdef CONFIG_CMDLINE_EDITING unsigned int len=MAX_CMDBUF_SIZE; int rc; @@ -940,6 +939,7 @@ int readline_into_buffer (const char *const prompt, char * buffer) rc = cread_line(prompt, p, &len); return rc < 0 ? rc : len; #else + char * p_buf = p; int n = 0; /* buffer index */ int plen = 0; /* prompt length */ int col; /* output column cnt */ -- 1.5.3.7

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[U-Boot-Users] ppc4xx: Problems running POST on PPC405GPr board
by Niklaus Giger 11 Jan '08

11 Jan '08

Hi I am trying to add POST for my PPC405GPr based boards and I am running into a few problems: a) the post/cpu/ppc4xx/uart.c assumed 4 UARTS. I would rather try only as much UARTs as defined by the CPUs. Would a patch like the attached one be considered a good solution for this problem? b) looking at the log I get <4>POST cache FAILED <4>POST i2c PASSED <4>POST cpu PASSED <4>POST ethernet PASSED <4>POST spr The value of PIR special register is incorrect: 0x0000005F <4>The value of IVOR0 special register is incorrect: 0x2000005F <4>The value of IVOR1 special register is incorrect: 0x2000005F <4>The value of IVOR2 special register is incorrect: 0x2000005F <4>The value of IVOR3 special register is incorrect: 0x2000005F <4>The value of IVOR4 special register is incorrect: 0x2000005F <4>The value of IVOR5 special register is incorrect: 0x2000005F <4>The value of IVOR6 special register is incorrect: 0x2000005F <4>The value of IVOR7 special register is incorrect: 0x2000005F <4>The value of IVOR8 special register is incorrect: 0x2000005F <4>The value of IVOR10 special register is incorrect: 0x2000005F <4>The value of IVOR13 special register is incorrect: 0x2000005F <4>The value of IVOR14 special register is incorrect: 0x2000005F <4>The value of IVOR15 special register is incorrect: 0x2000005F <4>The value of DVLIM special register is incorrect: 0x2000005F <4>The value of IVLIM special register is incorrect: 0x2000005F <4>FAILED What would be the correct #if to exclude the IVOR<x> part in post/cpu/ppc4xx/spr.c, as it make no sense to test these non existant registers on a PPC405 processor? Has anybody a suggestion how to fill in a good value for for the PIR (Processor Identification Register)? c) I will investigate the exact cause for the POST cache FAILED. Best regards Niklaus

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[U-Boot-Users] [PATCH] ppc4xx: Update PMC440 config file
by Matthias Fuchs 11 Jan '08

11 Jan '08

Signed-off-by: Matthias Fuchs <matthias.fuchs(a)esd-electronics.com> --- include/configs/PMC440.h | 16 +++------------- 1 files changed, 3 insertions(+), 13 deletions(-) diff --git a/include/configs/PMC440.h b/include/configs/PMC440.h index 87fca3c..67bf4b1 100644 --- a/include/configs/PMC440.h +++ b/include/configs/PMC440.h @@ -41,7 +41,9 @@ #define CONFIG_SYS_CLK_FREQ 33333400 +#if 0 /* temporary disabled because OS/9 does not like dcache on startup */ #define CONFIG_4xx_DCACHE /* enable dcache */ +#endif #define CONFIG_BOARD_EARLY_INIT_F 1 /* Call board_early_init_f */ #define CONFIG_MISC_INIT_R 1 /* Call misc_init_r */ @@ -272,6 +274,7 @@ CFG_BOOTFILE \ CFG_ROOTPATH \ "netdev=eth0\0" \ + "ethrotate=no\0" \ "nfsargs=setenv bootargs root=/dev/nfs rw " \ "nfsroot=${serverip}:${rootpath}\0" \ "ramargs=setenv bootargs root=/dev/ram rw\0" \ @@ -354,10 +357,6 @@ #define CONFIG_CMD_SDRAM /* POST support */ -/* ethernet POST sometimes freezes the CPU. - * So disable it for now until issue is solved - */ -#if 0 #define CONFIG_POST (CFG_POST_MEMORY | \ CFG_POST_CPU | \ CFG_POST_UART | \ @@ -366,15 +365,6 @@ CFG_POST_FPU | \ CFG_POST_ETHER | \ CFG_POST_SPR) -#else -#define CONFIG_POST (CFG_POST_MEMORY | \ - CFG_POST_CPU | \ - CFG_POST_UART | \ - CFG_POST_I2C | \ - CFG_POST_CACHE | \ - CFG_POST_FPU | \ - CFG_POST_SPR) -#endif #define CFG_POST_WORD_ADDR (CFG_GBL_DATA_OFFSET - 0x4) -- 1.5.3

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