January 2008 - U-Boot

[U-Boot-Users] resend #5: [PATCH 2/5]: add AcTux-1 board support
by Michael Schwingen 17 Jan '08

17 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/board/actux1/Makefile b/board/actux1/Makefile new file mode 100644 index 0000000..83611e7 --- /dev/null +++ b/board/actux1/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux1.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux1/actux1.c b/board/actux1/actux1.c new file mode 100644 index 0000000..e9acf02 --- /dev/null +++ b/board/actux1/actux1.c @@ -0,0 +1,161 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> +#include <asm/io.h> +#include <miiphy.h> + +#include "actux1_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX1; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + + /* Setup GPIO's for PCI INTA */ + GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI1_INTA); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI1_INTA); + + /* Setup GPIO's for 33MHz clock output */ + GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + /* CS5: Debug port */ + *IXP425_EXP_CS5 = 0x9d520003; + /* CS6: HwRel */ + *IXP425_EXP_CS6 = 0x81860001; + /* CS7: LEDs */ + *IXP425_EXP_CS7 = 0x80900003; + + udelay (533); + GPIO_OUTPUT_SET (CFG_GPIO_IORST); + + ACTUX1_LED1 (2); + ACTUX1_LED2 (2); + ACTUX1_LED3 (0); + ACTUX1_LED4 (0); + ACTUX1_LED5 (0); + ACTUX1_LED6 (0); + ACTUX1_LED7 (0); + + ACTUX1_HS (ACTUX1_HS_DCD); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard (void) +{ + char revision; + char *s = getenv ("serial#"); + + puts ("Board: AcTux-1 rev."); + putc (ACTUX1_BOARDREL + 'A' - 1); + + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev (void) +{ + return ACTUX1_BOARDREL; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +#if (CONFIG_COMMANDS & CFG_CMD_PCI) || defined(CONFIG_PCI) +extern struct pci_controller hose; +extern void pci_ixp_init (struct pci_controller *hose); + +void pci_init_board (void) +{ + extern void pci_ixp_init (struct pci_controller *hose); + pci_ixp_init (&hose); +} +#endif + +void reset_phy (void) +{ + u16 id1, id2; + + /* initialize the PHY */ + miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + + miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR1, &id1); + miiphy_read ("NPE0", CONFIG_PHY_ADDR, PHY_PHYIDR2, &id2); + + id2 &= 0xFFF0; /* mask out revision bits */ + + if (id1 == 0x13 && id2 == 0x78e0) { + /* + * LXT971/LXT972 PHY: set LED outputs: + * LED1(green) = Link/ACT, + * LED2 (unused) = LINK, + * LED3(red) = Coll + */ + miiphy_write ("NPE0", CONFIG_PHY_ADDR, 20, 0xD432); + } else if (id1 == 0x143 && id2 == 0xbc30) { + /* BCM5241: default values are OK */ + } else + printf ("unknown ethernet PHY ID: %x %x\n", id1, id2); +} diff --git a/board/actux1/actux1_hw.h b/board/actux1/actux1_hw.h new file mode 100644 index 0000000..bb3b7f9 --- /dev/null +++ b/board/actux1/actux1_hw.h @@ -0,0 +1,57 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX1_HW_H +#define _ACTUX1_HW_H + +/* 0 = LED off,1 = green, 2 = red, 3 = orange */ +#define ACTUX1_LED1(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) +#define ACTUX1_LED2(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) +#define ACTUX1_LED3(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) +#define ACTUX1_LED4(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 3) +#define ACTUX1_LED5(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 4) +#define ACTUX1_LED6(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 5) +#define ACTUX1_LED7(a) writeb((a)^3, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) +#define ACTUX1_HS(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) +#define ACTUX1_HS_DCD 0x01 +#define ACTUX1_HS_DSR 0x02 + +#define ACTUX1_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS +#define ACTUX1_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) + +/* GPIO settings */ +#define CFG_GPIO_PCI1_INTA 2 +#define CFG_GPIO_PCI2_INTA 3 +#define CFG_GPIO_I2C_SDA 4 +#define CFG_GPIO_I2C_SCL 5 +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 /* Out */ +#define CFG_GPIO_PCI_CLK 14 /* Out */ +#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ + +#endif diff --git a/board/actux1/config.mk b/board/actux1/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux1/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux1/u-boot.lds b/board/actux1/u-boot.lds new file mode 100644 index 0000000..0de78d3 --- /dev/null +++ b/board/actux1/u-boot.lds @@ -0,0 +1,69 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH (arm) +ENTRY (_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN (4); + .text : { + cpu/ixp/start.o(.text) + lib_generic/string.o(.text) + lib_generic/vsprintf.o(.text) + lib_arm/board.o(.text) + common/dlmalloc.o(.text) + cpu/ixp/cpu.o(.text) + . = env_offset; + common/environment.o(.ppcenv) + * (.text) + } + + . = ALIGN (4); + .rodata : { + *(.rodata) + } + . = ALIGN (4); + .data : { + *(.data) + } + . = ALIGN (4); + .got : { + *(.got) + } + . =.; + __u_boot_cmd_start =.; + .u_boot_cmd : { + *(.u_boot_cmd) + } + __u_boot_cmd_end =.; + + . = ALIGN (4); + __bss_start =.; + .bss (NOLOAD): { + *(.bss) + } + _end =.; +} diff --git a/include/configs/actux1.h b/include/configs/actux1.h new file mode 100644 index 0000000..4c4b1d1 --- /dev/null +++ b/include/configs/actux1.h @@ -0,0 +1,247 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-1 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/* 1: modified board with 32MB DRAM */ +#define CONFIG_ACTUX1_32MB 0 +/* 1: 2*2MB FLASH (standard) */ +#define CONFIG_ACTUX1_FLASH2X2 1 +/* 1: 1*8MB FLASH (upgraded boards) */ +#define CONFIG_ACTUX1_FLASH1X8 0 + +#define CONFIG_IXP425 1 +#define CONFIG_ACTUX1 1 + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ + +/* + * Size of malloc() pool + */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_PCI +#undef CONFIG_PCI + +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_KGDB_BAUDRATE 230400 +/* which serial port to use */ +# define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +/* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +/* max number of command args */ +#define CFG_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x00800000 + +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* spec says 66.666 MHz, but it appears to be 33 */ +#define CFG_HZ 3333333 + +/* default load address */ +#define CFG_LOAD_ADDR 0x00010000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* Expansion bus settings */ +#define CFG_EXP_CS0 0xbd113842 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CFG_DRAM_BASE 0x00000000 + +#if CONFIG_ACTUX1_32MB +# define CFG_SDR_CONFIG 0x18 +# define PHYS_SDRAM_1_SIZE 0x02000000 +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x02000000 +#else /* 16MB SDRAM */ +# define CFG_SDR_CONFIG 0x3A +# define PHYS_SDRAM_1_SIZE 0x01000000 +# define CFG_SDRAM_REFRESH_CNT 0x81a +# define CFG_SDR_MODE_CONFIG 0x1 +# define CFG_DRAM_SIZE 0x01000000 +#endif + +/* FLASH organization */ +#if CONFIG_ACTUX1_FLASH2X2 +# define CFG_MAX_FLASH_BANKS 2 +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT 40 +# define PHYS_FLASH_1 0x50000000 +# define PHYS_FLASH_2 0x50200000 +# define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } +#endif +#if CONFIG_ACTUX1_FLASH1X8 +# define CFG_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +# define CFG_MAX_FLASH_SECT 140 +# define PHYS_FLASH_1 0x50000000 +# define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } +#endif + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) + +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +/* use separate flash sector with ucode images */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0 +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 16 +#define CONFIG_RESET_PHY_R 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 32 + +/* + * environment organization: + * one flash sector, embedded in uboot area (bottom bootblock flash) + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff;" \ + " protect off 50006000 5003ffff;" \ + " erase 50000000 50003fff;" \ + " erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000;" \ + " cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff;" \ + " erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +#endif /* __CONFIG_H */

3 2

[U-Boot-Users] [PATCH] ColdFire: Add MCF547x_8x FEC driver
by Tsi-Chung Liew 17 Jan '08

17 Jan '08

From: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> Signed-off-by: TsiChungLiew <Tsi-Chung.Liew(a)freescale.com> --- drivers/net/Makefile | 1 + drivers/net/fsl_mcdmafec.c | 583 ++++++++++++++++++++++++++++++++++++++++++++ net/eth.c | 4 + 3 files changed, 588 insertions(+), 0 deletions(-) create mode 100644 drivers/net/fsl_mcdmafec.c diff --git a/drivers/net/Makefile b/drivers/net/Makefile index 41e1bde..b9723fa 100644 --- a/drivers/net/Makefile +++ b/drivers/net/Makefile @@ -33,6 +33,7 @@ COBJS-y += dm9000x.o COBJS-y += e1000.o COBJS-y += eepro100.o COBJS-y += enc28j60.o +COBJS-y += fsl_mcdmafec.o COBJS-y += inca-ip_sw.o COBJS-y += ks8695eth.o COBJS-y += lan91c96.o diff --git a/drivers/net/fsl_mcdmafec.c b/drivers/net/fsl_mcdmafec.c new file mode 100644 index 0000000..cd8722b --- /dev/null +++ b/drivers/net/fsl_mcdmafec.c @@ -0,0 +1,583 @@ +/* + * (C) Copyright 2000-2004 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * (C) Copyright 2007 Freescale Semiconductor, Inc. + * TsiChung Liew (Tsi-Chung.Liew(a)freescale.com) + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <malloc.h> +#include <command.h> +#include <config.h> +#include <net.h> +#include <miiphy.h> + +#ifdef CONFIG_FSLDMAFEC +#undef ET_DEBUG +#undef MII_DEBUG + +/* Ethernet Transmit and Receive Buffers */ +#define DBUF_LENGTH 1520 +#define PKT_MAXBUF_SIZE 1518 +#define PKT_MINBUF_SIZE 64 +#define PKT_MAXBLR_SIZE 1536 +#define LAST_PKTBUFSRX PKTBUFSRX - 1 +#define BD_ENET_RX_W_E (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY) +#define BD_ENET_TX_RDY_LST (BD_ENET_TX_READY | BD_ENET_TX_LAST) +#define FIFO_ERRSTAT (FIFO_STAT_RXW | FIFO_STAT_UF | FIFO_STAT_OF) + +/* RxBD bits definitions */ +#define BD_ENET_RX_ERR (BD_ENET_RX_LG | BD_ENET_RX_NO | BD_ENET_RX_CR | \ + BD_ENET_RX_OV | BD_ENET_RX_TR) + +#if defined(CONFIG_CMD_NET) && defined(CONFIG_NET_MULTI) +#include <asm/immap.h> +#include <asm/fsl_mcdmafec.h> + +#include "MCD_dma.h" + +DECLARE_GLOBAL_DATA_PTR; + +struct fec_info_dma fec_info[] = { +#ifdef CFG_FEC0_IOBASE + { + 0, /* index */ + CFG_FEC0_IOBASE, /* io base */ + CFG_FEC0_PINMUX, /* gpio pin muxing */ + CFG_FEC0_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phyname init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_dma *)-1, /* next */ + FEC0_RX_TASK, /* rxTask */ + FEC0_TX_TASK, /* txTask */ + FEC0_RX_PRIORITY, /* rxPri */ + FEC0_TX_PRIORITY, /* txPri */ + FEC0_RX_INIT, /* rxInit */ + FEC0_TX_INIT, /* txInit */ + 0, /* usedTbdIndex */ + 0, /* cleanTbdNum */ + }, +#endif +#ifdef CFG_FEC1_IOBASE + { + 1, /* index */ + CFG_FEC1_IOBASE, /* io base */ + CFG_FEC1_PINMUX, /* gpio pin muxing */ + CFG_FEC1_MIIBASE, /* mii base */ + -1, /* phy_addr */ + 0, /* duplex and speed */ + 0, /* phy name */ + 0, /* phy name init */ + 0, /* RX BD */ + 0, /* TX BD */ + 0, /* rx Index */ + 0, /* tx Index */ + 0, /* tx buffer */ + 0, /* initialized flag */ + (struct fec_info_dma *)-1, /* next */ + FEC1_RX_TASK, /* rxTask */ + FEC1_TX_TASK, /* txTask */ + FEC1_RX_PRIORITY, /* rxPri */ + FEC1_TX_PRIORITY, /* txPri */ + FEC1_RX_INIT, /* rxInit */ + FEC1_TX_INIT, /* txInit */ + 0, /* usedTbdIndex */ + 0, /* cleanTbdNum */ + } +#endif +}; + +static int fec_send(struct eth_device *dev, volatile void *packet, int length); +static int fec_recv(struct eth_device *dev); +static int fec_init(struct eth_device *dev, bd_t * bd); +static void fec_halt(struct eth_device *dev); +extern int fecpin_setclear(struct eth_device *dev, int setclear); + +#ifdef CFG_DISCOVER_PHY +extern void mii_init(void); +extern uint mii_send(uint mii_cmd); +extern int mii_discover_phy(struct eth_device *dev); +extern int mcffec_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short *value); +extern int mcffec_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value); +#endif + +#ifdef ET_DEBUG +void dbg_fec_regs(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + + printf("=====\n"); + printf("ievent %x - %x\n", (int)&fecp->eir, fecp->eir); + printf("imask %x - %x\n", (int)&fecp->eimr, fecp->eimr); + printf("ecntrl %x - %x\n", (int)&fecp->ecr, fecp->ecr); + printf("mii_mframe %x - %x\n", (int)&fecp->mmfr, fecp->mmfr); + printf("mii_speed %x - %x\n", (int)&fecp->mscr, fecp->mscr); + printf("mii_ctrlstat %x - %x\n", (int)&fecp->mibc, fecp->mibc); + printf("r_cntrl %x - %x\n", (int)&fecp->rcr, fecp->rcr); + printf("r hash %x - %x\n", (int)&fecp->rhr, fecp->rhr); + printf("x_cntrl %x - %x\n", (int)&fecp->tcr, fecp->tcr); + printf("padr_l %x - %x\n", (int)&fecp->palr, fecp->palr); + printf("padr_u %x - %x\n", (int)&fecp->paur, fecp->paur); + printf("op_pause %x - %x\n", (int)&fecp->opd, fecp->opd); + printf("iadr_u %x - %x\n", (int)&fecp->iaur, fecp->iaur); + printf("iadr_l %x - %x\n", (int)&fecp->ialr, fecp->ialr); + printf("gadr_u %x - %x\n", (int)&fecp->gaur, fecp->gaur); + printf("gadr_l %x - %x\n", (int)&fecp->galr, fecp->galr); + printf("x_wmrk %x - %x\n", (int)&fecp->tfwr, fecp->tfwr); + printf("r_fdata %x - %x\n", (int)&fecp->rfdr, fecp->rfdr); + printf("r_fstat %x - %x\n", (int)&fecp->rfsr, fecp->rfsr); + printf("r_fctrl %x - %x\n", (int)&fecp->rfcr, fecp->rfcr); + printf("r_flrfp %x - %x\n", (int)&fecp->rlrfp, fecp->rlrfp); + printf("r_flwfp %x - %x\n", (int)&fecp->rlwfp, fecp->rlwfp); + printf("r_frfar %x - %x\n", (int)&fecp->rfar, fecp->rfar); + printf("r_frfrp %x - %x\n", (int)&fecp->rfrp, fecp->rfrp); + printf("r_frfwp %x - %x\n", (int)&fecp->rfwp, fecp->rfwp); + printf("t_fdata %x - %x\n", (int)&fecp->tfdr, fecp->tfdr); + printf("t_fstat %x - %x\n", (int)&fecp->tfsr, fecp->tfsr); + printf("t_fctrl %x - %x\n", (int)&fecp->tfcr, fecp->tfcr); + printf("t_flrfp %x - %x\n", (int)&fecp->tlrfp, fecp->tlrfp); + printf("t_flwfp %x - %x\n", (int)&fecp->tlwfp, fecp->tlwfp); + printf("t_ftfar %x - %x\n", (int)&fecp->tfar, fecp->tfar); + printf("t_ftfrp %x - %x\n", (int)&fecp->tfrp, fecp->tfrp); + printf("t_ftfwp %x - %x\n", (int)&fecp->tfwp, fecp->tfwp); + printf("frst %x - %x\n", (int)&fecp->frst, fecp->frst); + printf("ctcwr %x - %x\n", (int)&fecp->ctcwr, fecp->ctcwr); +} +#endif + +static void set_fec_duplex_speed(volatile fecdma_t * fecp, bd_t * bd, + int dup_spd) +{ + if ((dup_spd >> 16) == FULL) { + /* Set maximum frame length */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | FEC_RCR_MII_MODE | + FEC_RCR_PROM | 0x100; + fecp->tcr = FEC_TCR_FDEN; + } else { + /* Half duplex mode */ + fecp->rcr = FEC_RCR_MAX_FL(PKT_MAXBUF_SIZE) | + FEC_RCR_MII_MODE | FEC_RCR_DRT; + fecp->tcr &= ~FEC_TCR_FDEN; + } + + if ((dup_spd & 0xFFFF) == _100BASET) { +#ifdef MII_DEBUG + printf("100Mbps\n"); +#endif + bd->bi_ethspeed = 100; + } else { +#ifdef MII_DEBUG + printf("10Mbps\n"); +#endif + bd->bi_ethspeed = 10; + } +} + +static int fec_send(struct eth_device *dev, volatile void *packet, int length) +{ + struct fec_info_dma *info = dev->priv; + cbd_t *pTbd, *pUsedTbd; + u16 phyStatus; + + miiphy_read(dev->name, info->phy_addr, PHY_BMSR, &phyStatus); + + /* process all the consumed TBDs */ + while (info->cleanTbdNum < CFG_TX_ETH_BUFFER) { + pUsedTbd = &info->txbd[info->usedTbdIdx]; + if (pUsedTbd->cbd_sc & BD_ENET_TX_READY) { +#ifdef ET_DEBUG + printf("Cannot clean TBD %d, in use\n", + info->cleanTbdNum); +#endif + return 0; + } + + /* clean this buffer descriptor */ + if (info->usedTbdIdx == (CFG_TX_ETH_BUFFER - 1)) + pUsedTbd->cbd_sc = BD_ENET_TX_WRAP; + else + pUsedTbd->cbd_sc = 0; + + /* update some indeces for a correct handling of the TBD ring */ + info->cleanTbdNum++; + info->usedTbdIdx = (info->usedTbdIdx + 1) % CFG_TX_ETH_BUFFER; + } + + /* Check for valid length of data. */ + if ((length > 1500) || (length <= 0)) { + return -1; + } + + /* Check the number of vacant TxBDs. */ + if (info->cleanTbdNum < 1) { + printf("No available TxBDs ...\n"); + return -1; + } + + /* Get the first TxBD to send the mac header */ + pTbd = &info->txbd[info->txIdx]; + pTbd->cbd_datlen = length; + pTbd->cbd_bufaddr = (u32) packet; + pTbd->cbd_sc |= BD_ENET_TX_LAST | BD_ENET_TX_TC | BD_ENET_TX_READY; + info->txIdx = (info->txIdx + 1) % CFG_TX_ETH_BUFFER; + + /* Enable DMA transmit task */ + MCD_continDma(info->txTask); + + info->cleanTbdNum -= 1; + + /* wait until frame is sent . */ + while (pTbd->cbd_sc & BD_ENET_TX_READY) { + udelay(10); + } + + return (int)(info->txbd[info->txIdx].cbd_sc & BD_ENET_TX_STATS); +} + +static int fec_recv(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + + cbd_t *pRbd = &info->rxbd[info->rxIdx]; + u32 ievent; + int frame_length, len = 0; + + /* Check if any critical events have happened */ + ievent = fecp->eir; + if (ievent != 0) { + fecp->eir = ievent; + + if (ievent & (FEC_EIR_BABT | FEC_EIR_TXERR | FEC_EIR_RXERR)) { + printf("fec_recv: error\n"); + fec_halt(dev); + fec_init(dev, NULL); + return 0; + } + + if (ievent & FEC_EIR_HBERR) { + /* Heartbeat error */ + fecp->tcr |= FEC_TCR_GTS; + } + + if (ievent & FEC_EIR_GRA) { + /* Graceful stop complete */ + if (fecp->tcr & FEC_TCR_GTS) { + printf("fec_recv: tcr_gts\n"); + fec_halt(dev); + fecp->tcr &= ~FEC_TCR_GTS; + fec_init(dev, NULL); + } + } + } + + if (!(pRbd->cbd_sc & BD_ENET_RX_EMPTY)) { + if ((pRbd->cbd_sc & BD_ENET_RX_LAST) + && !(pRbd->cbd_sc & BD_ENET_RX_ERR) + && ((pRbd->cbd_datlen - 4) > 14)) { + + /* Get buffer address and size */ + frame_length = pRbd->cbd_datlen - 4; + + /* Fill the buffer and pass it to upper layers */ + NetReceive((volatile uchar *)pRbd->cbd_bufaddr, + frame_length); + len = frame_length; + } + + /* Reset buffer descriptor as empty */ + if ((info->rxIdx) == (PKTBUFSRX - 1)) + pRbd->cbd_sc = (BD_ENET_RX_WRAP | BD_ENET_RX_EMPTY); + else + pRbd->cbd_sc = BD_ENET_RX_EMPTY; + + pRbd->cbd_datlen = PKTSIZE_ALIGN; + + /* Now, we have an empty RxBD, restart the DMA receive task */ + MCD_continDma(info->rxTask); + + /* Increment BD count */ + info->rxIdx = (info->rxIdx + 1) % PKTBUFSRX; + } + + return len; +} + +static void fec_set_hwaddr(volatile fecdma_t * fecp, u8 * mac) +{ + u8 currByte; /* byte for which to compute the CRC */ + int byte; /* loop - counter */ + int bit; /* loop - counter */ + u32 crc = 0xffffffff; /* initial value */ + + for (byte = 0; byte < 6; byte++) { + currByte = mac[byte]; + for (bit = 0; bit < 8; bit++) { + if ((currByte & 0x01) ^ (crc & 0x01)) { + crc >>= 1; + crc = crc ^ 0xedb88320; + } else { + crc >>= 1; + } + currByte >>= 1; + } + } + + crc = crc >> 26; + + /* Set individual hash table register */ + if (crc >= 32) { + fecp->ialr = (1 << (crc - 32)); + fecp->iaur = 0; + } else { + fecp->ialr = 0; + fecp->iaur = (1 << crc); + } + + /* Set physical address */ + fecp->palr = (mac[0] << 24) + (mac[1] << 16) + (mac[2] << 8) + mac[3]; + fecp->paur = (mac[4] << 24) + (mac[5] << 16) + 0x8808; + + /* Clear multicast address hash table */ + fecp->gaur = 0; + fecp->galr = 0; +} + +static int fec_init(struct eth_device *dev, bd_t * bd) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + int i; + +#ifdef ET_DEBUG + printf("fec_init: iobase 0x%08x ...\n", info->iobase); +#endif + + fecpin_setclear(dev, 1); + + fec_halt(dev); + +#if defined(CONFIG_CMD_MII) || defined (CONFIG_MII) || \ + defined (CFG_DISCOVER_PHY) + + mii_init(); + + set_fec_duplex_speed(fecp, bd, info->dup_spd); +#else +#ifndef CFG_DISCOVER_PHY + set_fec_duplex_speed(fecp, bd, (FECDUPLEX << 16) | FECSPEED); +#endif /* ifndef CFG_DISCOVER_PHY */ +#endif /* CONFIG_CMD_MII || CONFIG_MII */ + + /* We use strictly polling mode only */ + fecp->eimr = 0; + + /* Clear any pending interrupt */ + fecp->eir = 0xffffffff; + + /* Set station address */ + if ((u32) fecp == CFG_FEC0_IOBASE) { + fec_set_hwaddr(fecp, bd->bi_enetaddr); + } else { + fec_set_hwaddr(fecp, bd->bi_enet1addr); + } + + /* Set Opcode/Pause Duration Register */ + fecp->opd = 0x00010020; + + /* Setup Buffers and Buffer Desriptors */ + info->rxIdx = 0; + info->txIdx = 0; + + /* Setup Receiver Buffer Descriptors (13.14.24.18) + * Settings: Empty, Wrap */ + for (i = 0; i < PKTBUFSRX; i++) { + info->rxbd[i].cbd_sc = BD_ENET_RX_EMPTY; + info->rxbd[i].cbd_datlen = PKTSIZE_ALIGN; + info->rxbd[i].cbd_bufaddr = (uint) NetRxPackets[i]; + } + info->rxbd[PKTBUFSRX - 1].cbd_sc |= BD_ENET_RX_WRAP; + + /* Setup Ethernet Transmitter Buffer Descriptors (13.14.24.19) + * Settings: Last, Tx CRC */ + for (i = 0; i < CFG_TX_ETH_BUFFER; i++) { + info->txbd[i].cbd_sc = 0; + info->txbd[i].cbd_datlen = 0; + info->txbd[i].cbd_bufaddr = (uint) (&info->txbuf[0]); + } + info->txbd[CFG_TX_ETH_BUFFER - 1].cbd_sc |= BD_ENET_TX_WRAP; + + info->usedTbdIdx = 0; + info->cleanTbdNum = CFG_TX_ETH_BUFFER; + + /* Set Rx FIFO alarm and granularity value */ + fecp->rfcr = 0x0c000000; + fecp->rfar = 0x0000030c; + + /* Set Tx FIFO granularity value */ + fecp->tfcr = FIFO_CTRL_FRAME | FIFO_CTRL_GR(6) | 0x00040000; + fecp->tfar = 0x00000080; + + fecp->tfwr = 0x2; + fecp->ctcwr = 0x03000000; + + /* Enable DMA receive task */ + MCD_startDma(info->rxTask, /* Dma channel */ + (s8 *) info->rxbd, /*Source Address */ + 0, /* Source increment */ + (s8 *) (&fecp->rfdr), /* dest */ + 4, /* dest increment */ + 0, /* DMA size */ + 4, /* xfer size */ + info->rxInit, /* initiator */ + info->rxPri, /* priority */ + (MCD_FECRX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + ); + + /* Enable DMA tx task with no ready buffer descriptors */ + MCD_startDma(info->txTask, /* Dma channel */ + (s8 *) info->txbd, /*Source Address */ + 0, /* Source increment */ + (s8 *) (&fecp->tfdr), /* dest */ + 4, /* dest incr */ + 0, /* DMA size */ + 4, /* xfer size */ + info->txInit, /* initiator */ + info->txPri, /* priority */ + (MCD_FECTX_DMA | MCD_TT_FLAGS_DEF), /* Flags */ + (MCD_NO_CSUM | MCD_NO_BYTE_SWAP) /* Function description */ + ); + + /* Now enable the transmit and receive processing */ + fecp->ecr |= FEC_ECR_ETHER_EN; + + return 1; +} + +static void fec_halt(struct eth_device *dev) +{ + struct fec_info_dma *info = dev->priv; + volatile fecdma_t *fecp = (fecdma_t *) (info->iobase); + int counter = 0xffff; + + /* issue graceful stop command to the FEC transmitter if necessary */ + fecp->tcr |= FEC_TCR_GTS; + + /* wait for graceful stop to register */ + while ((counter--) && (!(fecp->eir & FEC_EIR_GRA))) ; + + /* Disable DMA tasks */ + MCD_killDma(info->txTask); + MCD_killDma(info->rxTask);; + + /* Disable the Ethernet Controller */ + fecp->ecr &= ~FEC_ECR_ETHER_EN; + + /* Clear FIFO status registers */ + fecp->rfsr &= FIFO_ERRSTAT; + fecp->tfsr &= FIFO_ERRSTAT; + + fecp->frst = 0x01000000; + + /* Issue a reset command to the FEC chip */ + fecp->ecr |= FEC_ECR_RESET; + + /* wait at least 20 clock cycles */ + udelay(10000); + +#ifdef ET_DEBUG + printf("Ethernet task stopped\n"); +#endif +} + +int mcdmafec_initialize(bd_t * bis) +{ + struct eth_device *dev; + int i; + + for (i = 0; i < sizeof(fec_info) / sizeof(fec_info[0]); i++) { + + dev = + (struct eth_device *)memalign(CFG_CACHELINE_SIZE, + sizeof *dev); + if (dev == NULL) + hang(); + + memset(dev, 0, sizeof(*dev)); + + sprintf(dev->name, "FEC%d", fec_info[i].index); + + dev->priv = &fec_info[i]; + dev->init = fec_init; + dev->halt = fec_halt; + dev->send = fec_send; + dev->recv = fec_recv; + + /* setup Receive and Transmit buffer descriptor */ + fec_info[i].rxbd = + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (PKTBUFSRX * sizeof(cbd_t))); + fec_info[i].txbd = + (cbd_t *) memalign(CFG_CACHELINE_SIZE, + (CFG_TX_ETH_BUFFER * sizeof(cbd_t))); + fec_info[i].txbuf = + (char *) memalign(CFG_CACHELINE_SIZE, DBUF_LENGTH); + +#ifdef ET_DEBUG + printf("rxbd %x txbd %x\n", + (int)fec_info[i].rxbd, (int)fec_info[i].txbd); +#endif + + fec_info[i].phy_name = (char *) memalign(CFG_CACHELINE_SIZE, 32); + + eth_register(dev); + +#if defined(CONFIG_MII) || defined(CONFIG_CMD_MII) + miiphy_register(dev->name, + mcffec_miiphy_read, mcffec_miiphy_write); +#endif + + if (i > 0) + fec_info[i - 1].next = &fec_info[i]; + } + fec_info[i - 1].next = &fec_info[0]; + + /* default speed */ + bis->bi_ethspeed = 10; + + return 1; +} + +#endif /* CONFIG_CMD_NET && CONFIG_NET_MULTI */ +#endif /* CONFIG_FSLDMAFEC */ diff --git a/net/eth.c b/net/eth.c index 5d9e9c1..bcd7d42 100644 --- a/net/eth.c +++ b/net/eth.c @@ -61,6 +61,7 @@ extern int uec_initialize(int); extern int bfin_EMAC_initialize(bd_t *); extern int atstk1000_eth_initialize(bd_t *); extern int mcffec_initialize(bd_t*); +extern int mcdmafec_initialize(bd_t*); #ifdef CONFIG_API extern void (*push_packet)(volatile void *, int); @@ -272,6 +273,9 @@ int eth_initialize(bd_t *bis) #if defined(CONFIG_MCFFEC) mcffec_initialize(bis); #endif +#if defined(CONFIG_FSLDMAFEC) + mcdmafec_initialize(bis); +#endif if (!eth_devices) { puts ("No ethernet found.\n"); -- 1.5.2

1 0

[U-Boot-Users] resend #5: [PATCH 3/5]: add AcTux-2 board support
by Michael Schwingen 16 Jan '08

16 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/board/actux2/Makefile b/board/actux2/Makefile new file mode 100644 index 0000000..37fd262 --- /dev/null +++ b/board/actux2/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux2.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux2/actux2.c b/board/actux2/actux2.c new file mode 100644 index 0000000..f3a81a8 --- /dev/null +++ b/board/actux2/actux2.c @@ -0,0 +1,134 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> +#include <asm/io.h> + +#include <miiphy.h> + +#include "actux2_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX2; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR); + GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); + GPIO_OUTPUT_SET (CFG_GPIO_DCD); + + /* Setup GPIO's for Interrupt inputs */ + GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT); + + /* Setup GPIO's for 33MHz clock output */ + GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + /* CS1: IPAC-X */ + *IXP425_EXP_CS1 = 0x94d10013; + /* CS5: Debug port */ + *IXP425_EXP_CS5 = 0x9d520003; + /* CS6: HW release register */ + *IXP425_EXP_CS6 = 0x81860001; + /* CS7: LEDs */ + *IXP425_EXP_CS7 = 0x80900003; + + udelay (533); + GPIO_OUTPUT_SET (CFG_GPIO_IORST); + GPIO_OUTPUT_SET (CFG_GPIO_ETHRST); + + ACTUX2_LED1 (1); + ACTUX2_LED2 (0); + ACTUX2_LED3 (0); + ACTUX2_LED4 (0); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard (void) +{ + char revision; + char *s = getenv ("serial#"); + + puts ("Board: AcTux-2 rev."); + putc (ACTUX2_BOARDREL + 'A' - 1); + putc ('\n'); + + return (0); +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev (void) +{ + return ACTUX2_BOARDREL; +} + +void reset_phy (void) +{ + int i; + + /* init IcPlus IP175C ethernet switch to native IP175C mode */ + miiphy_write ("NPE0", 29, 31, 0x175C); +} diff --git a/board/actux2/actux2_hw.h b/board/actux2/actux2_hw.h new file mode 100644 index 0000000..8ffb82a --- /dev/null +++ b/board/actux2/actux2_hw.h @@ -0,0 +1,59 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX2_HW_H +#define _ACTUX2_HW_H + +/* 0 = LED off,1 = green, 2 = red, 3 = orange */ +#define ACTUX2_LED1(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) +#define ACTUX2_LED2(a) writeb((a ? 2 : 0), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) +#define ACTUX2_LED3(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) +#define ACTUX2_LED4(a) writeb((a ? 0 : 2), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) + +#define ACTUX2_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS +#define ACTUX2_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) +#define ACTUX2_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) + +/* + * GPIO settings + */ +#define CFG_GPIO_DBGINT 0 +#define CFG_GPIO_ETHINT 1 +#define CFG_GPIO_ETHRST 2 /* Out */ +#define CFG_GPIO_LED5_GN 3 /* Out */ +#define CFG_GPIO_UNUSED4 4 +#define CFG_GPIO_UNUSED5 5 +#define CFG_GPIO_DSR 6 /* Out */ +#define CFG_GPIO_DCD 7 /* Out */ +#define CFG_GPIO_IPAC_INT 8 +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 /* Out */ +#define CFG_GPIO_PCI_CLK 14 /* Out */ +#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ + +#endif diff --git a/board/actux2/config.mk b/board/actux2/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux2/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux2/u-boot.lds b/board/actux2/u-boot.lds new file mode 100644 index 0000000..90cafce --- /dev/null +++ b/board/actux2/u-boot.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH (arm) +ENTRY (_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN (4); + .text : { + cpu/ixp/start.o(.text) + lib_generic/string.o(.text) + lib_generic/vsprintf.o(.text) + lib_arm/board.o(.text) + common/dlmalloc.o(.text) + cpu/ixp/cpu.o(.text) + + . = env_offset; + common/environment.o (.ppcenv) + + * (.text) + } + + . = ALIGN (4); + .rodata : { + *(.rodata) + } + + . = ALIGN (4); + .data : { + *(.data) + } + + . = ALIGN (4); + .got : { + *(.got) + } + + . =.; + __u_boot_cmd_start =.; + .u_boot_cmd : { + *(.u_boot_cmd) + } + __u_boot_cmd_end =.; + + . = ALIGN (4); + __bss_start =.; + .bss (NOLOAD): { + *(.bss) + } + _end =.; +} diff --git a/include/configs/actux2.h b/include/configs/actux2.h new file mode 100644 index 0000000..873fced --- /dev/null +++ b/include/configs/actux2.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-2 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_IXP425 1 +#define CONFIG_ACTUX2 1 + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 5 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ + +/* Size of malloc() pool */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF +#undef CONFIG_CMD_PCI +#undef CONFIG_PCI + +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_KGDB_BAUDRATE 230400 +/* which serial port to use */ +# define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +/* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +/* max number of command args */ +#define CFG_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x00800000 + +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* spec says 66.666 MHz, but it appears to be 33 */ +#define CFG_HZ 3333333 + +/* default load address */ +#define CFG_LOAD_ADDR 0x00010000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* Expansion bus settings */ +#define CFG_EXP_CS0 0xbd113042 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CFG_DRAM_BASE 0x00000000 + +/* 16MB SDRAM */ +#define CFG_SDR_CONFIG 0x3A +#define PHYS_SDRAM_1_SIZE 0x01000000 +#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDR_MODE_CONFIG 0x1 +#define CFG_DRAM_SIZE 0x01000000 + +/* FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 140 +#define PHYS_FLASH_1 0x50000000 +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) + +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +/* use separate flash sector with ucode images */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0x00 +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 16 +#define CONFIG_RESET_PHY_R 1 +/* ethernet switch connected to MII port */ +#define CONFIG_MII_ETHSWITCH 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 32 + +/* + * environment organization: + * one flash sector, embedded in uboot area (bottom bootblock flash) + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff;" \ + " protect off 50006000 5003ffff;" \ + " erase 50000000 50003fff;" \ + " erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000;" \ + " cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff;" \ + " erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +#endif /* __CONFIG_H */

2 1

[U-Boot-Users] resend #5: [PATCH 4/5]: add AcTux-3 board support
by Michael Schwingen 16 Jan '08

16 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/board/actux3/Makefile b/board/actux3/Makefile new file mode 100644 index 0000000..f6168c3 --- /dev/null +++ b/board/actux3/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux3.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux3/actux3.c b/board/actux3/actux3.c new file mode 100644 index 0000000..647e4e7 --- /dev/null +++ b/board/actux3/actux3.c @@ -0,0 +1,165 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> +#include <asm/io.h> + +#include <miiphy.h> + +#include "actux3_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX3; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_ETHRST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_DSR); + GPIO_OUTPUT_ENABLE (CFG_GPIO_DCD); + GPIO_OUTPUT_ENABLE (CFG_GPIO_LED5_GN); + GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_RT); + GPIO_OUTPUT_ENABLE (CFG_GPIO_LED6_GN); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_CLEAR (CFG_GPIO_ETHRST); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_DSR); + GPIO_OUTPUT_SET (CFG_GPIO_DCD); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED5_GN); + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_RT); + GPIO_OUTPUT_CLEAR (CFG_GPIO_LED6_GN); + + /* + * Setup GPIO's for Interrupt inputs + */ + GPIO_OUTPUT_DISABLE (CFG_GPIO_DBGINT); + GPIO_OUTPUT_DISABLE (CFG_GPIO_ETHINT); + + /* + * Setup GPIO's for 33MHz clock output + */ + GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); + GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + *IXP425_GPIO_GPCLKR = 0x011001FF; + + /* CS1: IPAC-X */ + *IXP425_EXP_CS1 = 0x94d10013; + /* CS5: Debug port */ + *IXP425_EXP_CS5 = 0x9d520003; + /* CS6: Release/Option register */ + *IXP425_EXP_CS6 = 0x81860001; + /* CS7: LEDs */ + *IXP425_EXP_CS7 = 0x80900003; + + udelay (533); + GPIO_OUTPUT_SET (CFG_GPIO_IORST); + GPIO_OUTPUT_SET (CFG_GPIO_ETHRST); + + ACTUX3_LED1_RT (1); + ACTUX3_LED1_GN (0); + ACTUX3_LED2_RT (0); + ACTUX3_LED2_GN (0); + ACTUX3_LED3_RT (0); + ACTUX3_LED3_GN (0); + ACTUX3_LED4_GN (0); + ACTUX3_LED5_RT (0); + + return 0; +} + +/* + * Check Board Identity + */ +int checkboard (void) +{ + char revision; + char *s = getenv ("serial#"); + + puts ("Board: AcTux-3 rev."); + putc (ACTUX3_BOARDREL + 'A' - 1); + + if (s != NULL) { + puts (", serial# "); + puts (s); + } + putc ('\n'); + + return (0); +} + +/************************************************************************* + * get_board_rev() - setup to pass kernel board revision information + * 0 = reserved + * 1 = Rev. A + * 2 = Rev. B + *************************************************************************/ +u32 get_board_rev (void) +{ + return ACTUX3_BOARDREL; +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +void reset_phy (void) +{ + int i; + + /* initialize the PHY */ + miiphy_reset ("NPE0", CONFIG_PHY_ADDR); + + /* all LED outputs = Link/Act */ + miiphy_write ("NPE0", CONFIG_PHY_ADDR, 0x16, 0x0AAA); + + /* + * The Marvell 88E6060 switch comes up with all ports disabled. + * set all ethernet switch ports to forwarding state + */ + for (i = 1; i <= 5; i++) + miiphy_write ("NPE0", CONFIG_PHY_ADDR + 8 + i, 0x04, 0x03); + +} diff --git a/board/actux3/actux3_hw.h b/board/actux3/actux3_hw.h new file mode 100644 index 0000000..9b7cbce --- /dev/null +++ b/board/actux3/actux3_hw.h @@ -0,0 +1,60 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX3_HW_H +#define _ACTUX3_HW_H + +/* 0 = LED off,1 = ON */ +#define ACTUX3_LED1_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 0) +#define ACTUX3_LED1_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 1) +#define ACTUX3_LED2_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 2) +#define ACTUX3_LED2_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 3) +#define ACTUX3_LED3_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 4) +#define ACTUX3_LED3_GN(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 5) +#define ACTUX3_LED4_GN(a) writeb((a)^1, IXP425_EXP_BUS_CS7_BASE_PHYS + 6) +#define ACTUX3_LED5_RT(a) writeb((a), IXP425_EXP_BUS_CS7_BASE_PHYS + 7) + +#define ACTUX3_DBG_PORT IXP425_EXP_BUS_CS5_BASE_PHYS +#define ACTUX3_BOARDREL (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0x0F) +#define ACTUX3_OPTION (readb(IXP425_EXP_BUS_CS6_BASE_PHYS) & 0xF0) + +/* GPIO settings */ +#define CFG_GPIO_DBGINT 0 +#define CFG_GPIO_ETHINT 1 +#define CFG_GPIO_ETHRST 2 /* Out */ +#define CFG_GPIO_LED5_GN 3 /* Out */ +#define CFG_GPIO_LED6_RT 4 /* Out */ +#define CFG_GPIO_LED6_GN 5 /* Out */ +#define CFG_GPIO_DSR 6 /* Out */ +#define CFG_GPIO_DCD 7 /* Out */ +#define CFG_GPIO_DBGJUMPER 9 +#define CFG_GPIO_BUTTON1 10 +#define CFG_GPIO_DBGSENSE 11 +#define CFG_GPIO_DTR 12 +#define CFG_GPIO_IORST 13 /* Out */ +#define CFG_GPIO_PCI_CLK 14 /* Out */ +#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ + +#endif diff --git a/board/actux3/config.mk b/board/actux3/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux3/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux3/u-boot.lds b/board/actux3/u-boot.lds new file mode 100644 index 0000000..b9a9eb9 --- /dev/null +++ b/board/actux3/u-boot.lds @@ -0,0 +1,74 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH (arm) +ENTRY (_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN (4); + .text : { + cpu/ixp/start.o (.text) + lib_generic/string.o (.text) + lib_generic/vsprintf.o (.text) + lib_arm/board.o (.text) + common/dlmalloc.o (.text) + cpu/ixp/cpu.o (.text) + + . = env_offset; + common/environment.o (.ppcenv) + + * (.text) + } + + . = ALIGN (4); + .rodata : { + *(.rodata) + } + + . = ALIGN (4); + .data : { + *(.data) + } + + . = ALIGN (4); + .got : { + *(.got) + } + + . =.; + __u_boot_cmd_start =.; + .u_boot_cmd : { + *(.u_boot_cmd) + } + __u_boot_cmd_end =.; + + . = ALIGN (4); + __bss_start =.; + .bss (NOLOAD): { + *(.bss) + } + _end =.; +} diff --git a/include/configs/actux3.h b/include/configs/actux3.h new file mode 100644 index 0000000..5e468e6 --- /dev/null +++ b/include/configs/actux3.h @@ -0,0 +1,224 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-3 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_IXP425 1 +#define CONFIG_ACTUX3 1 + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CFG_IXP425_CONSOLE IXP425_UART2 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ + +/* Size of malloc() pool */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration. */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 +#define CONFIG_REVISION_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_KGDB_BAUDRATE 230400 +/* which serial port to use */ +# define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +/* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +/* max number of command args */ +#define CFG_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x00800000 + +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* spec says 66.666 MHz, but it appears to be 33 */ +#define CFG_HZ 3333333 + +/* default load address */ +#define CFG_LOAD_ADDR 0x00010000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* Expansion bus settings */ +#define CFG_EXP_CS0 0xbd113442 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CFG_DRAM_BASE 0x00000000 + +/* 16MB SDRAM */ +#define CFG_SDR_CONFIG 0x3A +#define PHYS_SDRAM_1_SIZE 0x01000000 +#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDR_MODE_CONFIG 0x1 +#define CFG_DRAM_SIZE 0x01000000 + +/* FLASH organization */ +#define CFG_MAX_FLASH_BANKS 1 +/* max number of sectors on one chip */ +#define CFG_MAX_FLASH_SECT 140 +#define PHYS_FLASH_1 0x50000000 +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1 } + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (256 << 10) + +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* no byte writes on IXP4xx */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT + +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +/* use separate flash sector with ucode images */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x50040000 + +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0x10 +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 16 +#define CONFIG_RESET_PHY_R 1 +/* ethernet switch connected to MII port */ +#define CONFIG_MII_ETHSWITCH 1 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 32 + +/* + * environment organization: + * one flash sector, embedded in uboot area (bottom bootblock flash) + */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x2000 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x4000) +#define CFG_USE_PPCENV 1 + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:256k(uboot),64k(ucode),1152k(linux),-(root)\0" \ + "kerneladdr=50050000\0" \ + "rootaddr=50170000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 50003fff;" \ + " protect off 50006000 5003ffff;" \ + " erase 50000000 50003fff;" \ + " erase 50006000 5003ffff\0" \ + "writeboot=cp.b 10000 50000000 4000;" \ + " cp.b 16000 50006000 3a000\0" \ + "eraseenv=protect off 50004000 50005fff;" \ + " erase 50004000 50005fff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock3" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +#endif /* __CONFIG_H */

2 1

[U-Boot-Users] resend #5: [PATCH 5/5]: add AcTux-4 board support
by Michael Schwingen 16 Jan '08

16 Jan '08

Signed-off-by: Michael Schwingen <michael(a)schwingen.org> diff --git a/board/actux4/Makefile b/board/actux4/Makefile new file mode 100644 index 0000000..845af93 --- /dev/null +++ b/board/actux4/Makefile @@ -0,0 +1,50 @@ +# +# (C) Copyright 2000-2006 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = $(obj)lib$(BOARD).a + +COBJS := actux4.o + +SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) +OBJS := $(addprefix $(obj),$(COBJS)) +SOBJS := $(addprefix $(obj),$(SOBJS)) + +$(LIB): $(obj).depend $(OBJS) + $(AR) $(ARFLAGS) $@ $(OBJS) + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +# defines $(obj).depend target +include $(SRCTREE)/rules.mk + +sinclude $(obj).depend + +######################################################################### diff --git a/board/actux4/actux4.c b/board/actux4/actux4.c new file mode 100644 index 0000000..84037fa --- /dev/null +++ b/board/actux4/actux4.c @@ -0,0 +1,132 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * (C) Copyright 2006 + * Stefan Roese, DENX Software Engineering, sr(a)denx.de. + * + * (C) Copyright 2002 + * Kyle Harris, Nexus Technologies, Inc. kharris(a)nexus-tech.net + * + * (C) Copyright 2002 + * Sysgo Real-Time Solutions, GmbH <www.elinos.com> + * Marius Groeger <mgroeger(a)sysgo.de> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> +#include <command.h> +#include <malloc.h> +#include <asm/arch/ixp425.h> + +#include <miiphy.h> + +#include "actux4_hw.h" + +DECLARE_GLOBAL_DATA_PTR; + +int board_init (void) +{ + gd->bd->bi_arch_number = MACH_TYPE_ACTUX4; + + /* adress of boot parameters */ + gd->bd->bi_boot_params = 0x00000100; + + GPIO_OUTPUT_CLEAR (CFG_GPIO_nPWRON); + GPIO_OUTPUT_ENABLE (CFG_GPIO_nPWRON); + + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + GPIO_OUTPUT_ENABLE (CFG_GPIO_IORST); + + /* led not populated on board*/ + GPIO_OUTPUT_ENABLE (CFG_GPIO_LED3); + GPIO_OUTPUT_SET (CFG_GPIO_LED3); + + /* middle LED */ + GPIO_OUTPUT_ENABLE (CFG_GPIO_LED2); + GPIO_OUTPUT_SET (CFG_GPIO_LED2); + + /* right LED */ + /* weak pulldown = LED weak on */ + GPIO_OUTPUT_DISABLE (CFG_GPIO_LED1); + GPIO_OUTPUT_SET (CFG_GPIO_LED1); + + /* Setup GPIO's for Interrupt inputs */ + GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTA); + GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTB); + GPIO_OUTPUT_DISABLE (CFG_GPIO_USBINTC); + GPIO_OUTPUT_DISABLE (CFG_GPIO_RTCINT); + GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTA); + GPIO_OUTPUT_DISABLE (CFG_GPIO_PCI_INTB); + + GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTA); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTB); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_USBINTC); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_RTCINT); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTA); + GPIO_INT_ACT_LOW_SET (CFG_GPIO_PCI_INTB); + + /* Setup GPIO's for 33MHz clock output */ + *IXP425_GPIO_GPCLKR = 0x011001FF; + GPIO_OUTPUT_ENABLE (CFG_GPIO_EXTBUS_CLK); + GPIO_OUTPUT_ENABLE (CFG_GPIO_PCI_CLK); + + *IXP425_EXP_CS1 = 0xbd113c42; + + udelay (10000); + GPIO_OUTPUT_SET (CFG_GPIO_IORST); + udelay (10000); + GPIO_OUTPUT_CLEAR (CFG_GPIO_IORST); + udelay (10000); + GPIO_OUTPUT_SET (CFG_GPIO_IORST); + + return 0; +} + +/* Check Board Identity */ +int checkboard (void) +{ + puts ("Board: AcTux-4\n"); + return (0); +} + +int dram_init (void) +{ + gd->bd->bi_dram[0].start = PHYS_SDRAM_1; + gd->bd->bi_dram[0].size = PHYS_SDRAM_1_SIZE; + + return (0); +} + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI SST 39VF020 flash, 8 bit flash / 8 bit bus. + * Flash 1 is an Intel *16 flash using the CFI driver. + */ +ulong board_flash_get_legacy (ulong base, int banknum, flash_info_t * info) +{ + if (banknum == 0) { /* non-CFI boot flash */ + info->portwidth = 1; + info->chipwidth = 1; + info->interface = FLASH_CFI_X8; + return 1; + } else + return 0; +} diff --git a/board/actux4/actux4_hw.h b/board/actux4/actux4_hw.h new file mode 100644 index 0000000..8b3ecf3 --- /dev/null +++ b/board/actux4/actux4_hw.h @@ -0,0 +1,49 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * hardware register definitions for the AcTux-4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef _ACTUX4_HW_H +#define _ACTUX4_HW_H + +/* + * GPIO settings + */ +#define CFG_GPIO_USBINTA 0 +#define CFG_GPIO_USBINTB 1 +#define CFG_GPIO_USBINTC 2 +#define CFG_GPIO_nPWRON 3 /* Out */ +#define CFG_GPIO_I2C_SCL 4 +#define CFG_GPIO_I2C_SDA 5 +#define CFG_GPIO_PCI_INTB 6 +#define CFG_GPIO_BUTTON1 7 +#define CFG_GPIO_LED1 8 /* Out */ +#define CFG_GPIO_RTCINT 9 +#define CFG_GPIO_LED2 10 /* Out */ +#define CFG_GPIO_PCI_INTA 11 +#define CFG_GPIO_IORST 12 /* Out */ +#define CFG_GPIO_LED3 13 /* Out */ +#define CFG_GPIO_PCI_CLK 14 /* Out */ +#define CFG_GPIO_EXTBUS_CLK 15 /* Out */ + +#endif diff --git a/board/actux4/config.mk b/board/actux4/config.mk new file mode 100644 index 0000000..9a634cd --- /dev/null +++ b/board/actux4/config.mk @@ -0,0 +1,4 @@ +TEXT_BASE = 0x00e00000 + +# include NPE ethernet driver +BOARDLIBS = cpu/ixp/npe/libnpe.a diff --git a/board/actux4/u-boot.lds b/board/actux4/u-boot.lds new file mode 100644 index 0000000..c8784a0 --- /dev/null +++ b/board/actux4/u-boot.lds @@ -0,0 +1,65 @@ +/* + * (C) Copyright 2000 + * Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +OUTPUT_FORMAT ("elf32-bigarm", "elf32-bigarm", "elf32-bigarm") +OUTPUT_ARCH (arm) +ENTRY (_start) +SECTIONS +{ + . = 0x00000000; + + . = ALIGN (4); + .text : { + cpu/ixp/start.o(.text) + *(.text) + } + + . = ALIGN (4); + .rodata : { + *(.rodata) + } + + . = ALIGN (4); + .data : { + *(.data) + } + + . = ALIGN (4); + .got : { + *(.got) + } + + . =.; + __u_boot_cmd_start =.; + .u_boot_cmd : { + *(.u_boot_cmd) + } + __u_boot_cmd_end =.; + + . = ALIGN (4); + __bss_start =.; + .bss (NOLOAD): { + *(.bss) + } + _end =.; +} diff --git a/include/configs/actux4.h b/include/configs/actux4.h new file mode 100644 index 0000000..e4dca2a --- /dev/null +++ b/include/configs/actux4.h @@ -0,0 +1,218 @@ +/* + * (C) Copyright 2007 + * Michael Schwingen, michael(a)schwingen.org + * + * Configuration settings for the AcTux-4 board. + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +#define CONFIG_IXP425 1 +#define CONFIG_ACTUX4 1 + +#define CONFIG_DISPLAY_CPUINFO 1 +#define CONFIG_DISPLAY_BOARDINFO 1 + +#define CFG_IXP425_CONSOLE IXP425_UART1 +#define CONFIG_BAUDRATE 115200 +#define CONFIG_BOOTDELAY 3 +#define CONFIG_ZERO_BOOTDELAY_CHECK /* check for keypress on bootdelay==0 */ + +/*************************************************************** + * U-boot generic defines start here. + ***************************************************************/ +#undef CONFIG_USE_IRQ + +/* Size of malloc() pool */ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) +/* size in bytes reserved for initial data */ +#define CFG_GBL_DATA_SIZE 128 + +/* allow to overwrite serial and ethaddr */ +#define CONFIG_ENV_OVERWRITE + +/* Command line configuration */ +#include <config_cmd_default.h> + +#define CONFIG_CMD_ELF + +#define CONFIG_BOOTCOMMAND "run boot_flash" +/* enable passing of ATAGs */ +#define CONFIG_CMDLINE_TAG 1 +#define CONFIG_SETUP_MEMORY_TAGS 1 +#define CONFIG_INITRD_TAG 1 + +#if defined(CONFIG_CMD_KGDB) +# define CONFIG_KGDB_BAUDRATE 230400 +/* which serial port to use */ +# define CONFIG_KGDB_SER_INDEX 1 +#endif + +/* Miscellaneous configurable options */ +#define CFG_LONGHELP +#define CFG_PROMPT "=> " +/* Console I/O Buffer Size */ +#define CFG_CBSIZE 256 +/* Print Buffer Size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) +/* max number of command args */ +#define CFG_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CFG_BARGSIZE CFG_CBSIZE + +#define CFG_MEMTEST_START 0x00400000 +#define CFG_MEMTEST_END 0x00800000 + +/* everything, incl board info, in Hz */ +#undef CFG_CLKS_IN_HZ +/* spec says 66.666 MHz, but it appears to be 33 */ +#define CFG_HZ 3333333 + +/* default load address */ +#define CFG_LOAD_ADDR 0x00010000 + +/* valid baudrates */ +#define CFG_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, \ + 115200, 230400 } +#define CONFIG_SERIAL_RTS_ACTIVE 1 + +/* + * Stack sizes + * The stack sizes are set up in start.S using the settings below + */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#ifdef CONFIG_USE_IRQ +# define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +# define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#endif + +/* Expansion bus settings */ +#define CFG_EXP_CS0 0xbd113003 + +/* SDRAM settings */ +#define CONFIG_NR_DRAM_BANKS 1 +#define PHYS_SDRAM_1 0x00000000 +#define CFG_DRAM_BASE 0x00000000 + +/* 32MB SDRAM */ +#define CFG_SDR_CONFIG 0x18 +#define PHYS_SDRAM_1_SIZE 0x02000000 +#define CFG_SDRAM_REFRESH_CNT 0x81a +#define CFG_SDR_MODE_CONFIG 0x1 +#define CFG_DRAM_SIZE 0x02000000 + +/* FLASH organization */ +#define CFG_MAX_FLASH_BANKS 2 +/* max # of sectors per chip */ +#define CFG_MAX_FLASH_SECT 70 +#define PHYS_FLASH_1 0x50000000 +#define PHYS_FLASH_2 0x51000000 +#define CFG_FLASH_BANKS_LIST { PHYS_FLASH_1, PHYS_FLASH_2 } + +#define CFG_FLASH_BASE PHYS_FLASH_1 +#define CFG_MONITOR_BASE PHYS_FLASH_1 +#define CFG_MONITOR_LEN (252 << 10) + +/* Use common CFI driver */ +#define CFG_FLASH_CFI +#define CFG_FLASH_CFI_DRIVER +/* board provides its own flash_init code */ +#define CONFIG_FLASH_CFI_LEGACY 1 +/* no byte writes on IXP4xx */ +#define CFG_FLASH_CFI_WIDTH FLASH_CFI_16BIT +/* SST 39VF020 etc. support */ +#define CFG_FLASH_LEGACY_256Kx8 1 + +/* print 'E' for empty sector on flinfo */ +#define CFG_FLASH_EMPTY_INFO + +/* Ethernet */ + +/* include IXP4xx NPE support */ +#define CONFIG_IXP4XX_NPE 1 +/* use separate flash sector with ucode images */ +#define CONFIG_IXP4XX_NPE_EXT_UCODE_BASE 0x51000000 + +#define CONFIG_NET_MULTI 1 +/* NPE0 PHY address */ +#define CONFIG_PHY_ADDR 0x1C +/* MII PHY management */ +#define CONFIG_MII 1 +/* Number of ethernet rx buffers & descriptors */ +#define CFG_RX_ETH_BUFFER 16 + +#define CONFIG_CMD_DHCP +#define CONFIG_CMD_NET +#define CONFIG_CMD_MII +#define CONFIG_CMD_PING +#undef CONFIG_CMD_NFS + +/* BOOTP options */ +#define CONFIG_BOOTP_BOOTFILESIZE +#define CONFIG_BOOTP_BOOTPATH +#define CONFIG_BOOTP_GATEWAY +#define CONFIG_BOOTP_HOSTNAME + +/* Cache Configuration */ +#define CFG_CACHELINE_SIZE 32 + +/* environment organization: one complete 4k flash sector */ +#define CFG_ENV_IS_IN_FLASH 1 +#define CFG_ENV_SIZE 0x1000 +#define CFG_ENV_ADDR (PHYS_FLASH_1 + 0x3f000) + +#define CONFIG_EXTRA_ENV_SETTINGS \ + "mtd=IXP4XX-Flash.0:252k(uboot),4k(uboot_env);" \ + "IXP4XX-Flash.1:128k(ucode),1280k(linux),-(root)\0" \ + "kerneladdr=51020000\0" \ + "rootaddr=51160000\0" \ + "loadaddr=10000\0" \ + "updateboot_ser=mw.b 10000 ff 40000;" \ + " loady ${loadaddr};" \ + " run eraseboot writeboot\0" \ + "updateboot_net=mw.b 10000 ff 40000;" \ + " tftp ${loadaddr} u-boot.bin;" \ + " run eraseboot writeboot\0" \ + "eraseboot=protect off 50000000 5003efff;" \ + " erase 50000000 +${filesize}\0" \ + "writeboot=cp.b 10000 50000000 ${filesize}\0" \ + "eraseenv=protect off 5003f000 5003ffff;" \ + " erase 5003f000 5003ffff\0" \ + "updateroot=tftp ${loadaddr} ${rootfile};" \ + " era ${rootaddr} +${filesize};" \ + " cp.b ${loadaddr} ${rootaddr} ${filesize}\0" \ + "updatekern=tftp ${loadaddr} ${kernelfile};" \ + " era ${kerneladdr} +${filesize};" \ + " cp.b ${loadaddr} ${kerneladdr} ${filesize}\0" \ + "flashargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "netargs=setenv bootargs mtdparts=${mtd} root=/dev/mtdblock4" \ + " rootfstype=squashfs,jffs2 init=/etc/preinit\0" \ + "addtty=setenv bootargs ${bootargs} console=ttyS0,${baudrate}\0" \ + "addeth=setenv bootargs ${bootargs} ethaddr=${ethaddr}\0" \ + "boot_flash=run flashargs addtty addeth;" \ + " bootm ${kerneladdr}\0" \ + "boot_net=run netargs addtty addeth;" \ + " tftpboot ${loadaddr} ${kernelfile};" \ + " bootm\0" + +#endif /* __CONFIG_H */

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[U-Boot-Users] resend #5: [PATCH 1/5]: add AcTux board support (common)
by Michael Schwingen 16 Jan '08

16 Jan '08

Hi, here is the next update of the AcTux patch set - I found some comments that still referred to the wrong boards, and added comments to the ethernet switch init code. The patch adds 4 boards, called AcTux-1..AcTux-4. This patch contains the files that contain changes for multiple boards (MAINTAINERS, MAKEALL, Makefile plus the complete update of include/asm-arm/mach-types.h), the board-specific files follow as 4 separate patches. cu Michael Signed-off-by: Michael Schwingen <michael(a)schwingen.org> (patch compressed due to size)

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[U-Boot-Users] [PATCH] 86xx: enable command-line editing
by Timur Tabi 16 Jan '08

16 Jan '08

Enable command-line editing for all MPC86xx boards. Signed-off-by: Timur Tabi <timur(a)freescale.com> --- include/configs/MPC8610HPCD.h | 1 + include/configs/MPC8641HPCN.h | 1 + 2 files changed, 2 insertions(+), 0 deletions(-) diff --git a/include/configs/MPC8610HPCD.h b/include/configs/MPC8610HPCD.h index eb6ccb6..cf2438d 100644 --- a/include/configs/MPC8610HPCD.h +++ b/include/configs/MPC8610HPCD.h @@ -493,6 +493,7 @@ * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ diff --git a/include/configs/MPC8641HPCN.h b/include/configs/MPC8641HPCN.h index 7f485c6..d806dfd 100644 --- a/include/configs/MPC8641HPCN.h +++ b/include/configs/MPC8641HPCN.h @@ -552,6 +552,7 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); * Miscellaneous configurable options */ #define CFG_LONGHELP /* undef to save memory */ +#define CONFIG_CMDLINE_EDITING /* Command-line editing */ #define CFG_LOAD_ADDR 0x2000000 /* default load address */ #define CFG_PROMPT "=> " /* Monitor Command Prompt */ -- 1.5.2.4

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[U-Boot-Users] Pull Request for git://www.denx.de/git/u-boot-mpc86xx.git
by Jon Loeliger 16 Jan '08

16 Jan '08

Wolfgang, Please pull the u-boot-mpc86xx custodian repository! Thanks, jdl The following changes since commit cd9d23053d435c08fc8695017b5cb9003fcda786: Anton Vorontsov (1): nand: FSL UPM NAND driver are available in the git repository at: git://www.denx.de/git/u-boot-mpc86xx.git master James Yang (1): FSL: Generalize PIXIS reset command parsing. Jon Loeliger (1): FSL: Convert board/freescale/common/Makefile to use CONFIG_ Roy Zang (1): Use CONFIG_ULI526X as MPC8610HPCD default Ethernet driver board/freescale/common/Makefile | 15 +-- board/freescale/common/fsl_diu_fb.c | 3 - board/freescale/common/pixis.c | 218 +++++++++++++++++----------------- board/freescale/common/pq-mds-pib.c | 3 - board/freescale/common/sys_eeprom.c | 2 - board/freescale/mpc8610hpcd/Makefile | 12 +- include/configs/MPC8610HPCD.h | 10 +- include/configs/MPC8641HPCN.h | 3 + 8 files changed, 128 insertions(+), 138 deletions(-)

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[U-Boot-Users] Please pull u-boot-mpc83xx.git
by Kim Phillips 16 Jan '08

16 Jan '08

WD, please pull support for two new boards (mpc8315erdb and mpc837xerdb), and some fixes for some bugs that crept in recently: The following changes since commit cd9d23053d435c08fc8695017b5cb9003fcda786: Anton Vorontsov (1): nand: FSL UPM NAND driver are available in the git repository at: git://www.denx.de/git/u-boot-mpc83xx.git Dave Liu (3): mpc83xx: Remove cache config from MPC8360ERDK.h mpc83xx: Add config of eTSEC emergency priority in SPCR mpc83xx: Add the support for MPC8315ERDB board Jerry Van Baren (1): Enable the isdram command on the MPC8360EMDS board Kim Phillips (5): mpc83xx: fix phy-connection-type fixup code mpc83xx: clean up mpc8360emds.c warnings mpc83xx: fix QE ETHPRIMEs to correct 'FSL UEC0' value mpc83xx: add support for more system clock performance controls Add support for the MPC837xERDB Kumar Gala (1): mpc83xx: fix mpc8313/mpc8315/mpc8349itx Makefiles for silent build (with -s) Poonam Aggrwal (1): Changes in uboot DDR configuration for MPC8313eRDB CREDITS | 2 +- MAINTAINERS | 5 + MAKEALL | 2 + Makefile | 6 + board/freescale/mpc8313erdb/Makefile | 2 +- board/freescale/mpc8315erdb/Makefile | 50 +++ board/freescale/mpc8315erdb/config.mk | 1 + board/freescale/mpc8315erdb/mpc8315erdb.c | 132 +++++++ board/freescale/mpc8315erdb/sdram.c | 120 ++++++ board/freescale/mpc8349itx/Makefile | 2 +- board/freescale/mpc8360emds/mpc8360emds.c | 34 +- board/freescale/mpc837xerdb/Makefile | 50 +++ board/freescale/mpc837xerdb/config.mk | 28 ++ board/freescale/mpc837xerdb/mpc837xerdb.c | 150 ++++++++ board/freescale/mpc837xerdb/pci.c | 59 +++ cpu/mpc83xx/cpu_init.c | 78 +++- cpu/mpc83xx/speed.c | 12 +- doc/README.mpc8315erdb | 80 ++++ doc/README.mpc837xerdb | 98 +++++ include/configs/MPC8313ERDB.h | 32 +- include/configs/MPC8315ERDB.h | 547 ++++++++++++++++++++++++++ include/configs/MPC8323ERDB.h | 2 +- include/configs/MPC832XEMDS.h | 2 +- include/configs/MPC8360EMDS.h | 3 +- include/configs/MPC8360ERDK.h | 11 +- include/configs/MPC837XERDB.h | 596 +++++++++++++++++++++++++++++ include/mpc83xx.h | 13 +- 27 files changed, 2040 insertions(+), 77 deletions(-) create mode 100644 board/freescale/mpc8315erdb/Makefile create mode 100644 board/freescale/mpc8315erdb/config.mk create mode 100644 board/freescale/mpc8315erdb/mpc8315erdb.c create mode 100644 board/freescale/mpc8315erdb/sdram.c create mode 100644 board/freescale/mpc837xerdb/Makefile create mode 100644 board/freescale/mpc837xerdb/config.mk create mode 100644 board/freescale/mpc837xerdb/mpc837xerdb.c create mode 100644 board/freescale/mpc837xerdb/pci.c create mode 100644 doc/README.mpc8315erdb create mode 100644 doc/README.mpc837xerdb create mode 100644 include/configs/MPC8315ERDB.h create mode 100644 include/configs/MPC837XERDB.h Thanks, Kim

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[U-Boot-Users] Merge Window
by Darcy Watkins 16 Jan '08

16 Jan '08

Hello, The merge window closes soon after the 17th right? Will there be a release candidate soon after that? When? I have an arch/powerpc (not arch/ppc) 2.6.23 kernel for AMCC 405EP using a cuImage that launches from old style U-Boot (the version shipped with the Taihu and a 1.3.0-rc2 in our own board). I'll be interested in trying out the new U-boot's OF FDT boot scheme (i.e. uImage instead of cuImage) for ppc4xx using this kernel. Regards, Darcy

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