October 2007 - U-Boot

[U-Boot-Users] [PATCH] DHCP Client Fix
by Justin Flammia 29 Oct '07

29 Oct '07

I recently upgraded the firmware on some of my old Linksys WRT54G routers (version 5) from firmware version 1.0.6 to firmware version 1.02.2, both of which are released by Linksys and U-Boot was no longer able to get an IP address using DHCP. However, with the older firmware (version 1.0.6), U-Boot was still able to get an IP through DHCP. Using a hub and a packet sniffer, I was able to locate the problem. The U-Boot code will bind to an IP address offered by the DHCP server prematurely and the DHCP server will not respond with an ACK, rendering the system without an IP address. This is no longer valid when using a Linksys router as DHCP server. I modified the code to operate the way the Linux DHCP client does by not binding to the offered IP until the DHCP client receives the ACK sent by the server, ending the conversation. After making the appropriate changes, DCHP service was restored for all flavors of the Linksys firmware that I have available (v 1.02.2 and v1.0.6 for the version 5 router, v8.00.2 for the version 8 router). It has also been tested on an AirPort Extreme router running DHCP. Attached is the patch with the code changes that were made. Any feed back would be appreciated.

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Re: [U-Boot-Users] [PATCH] DHCP Client Fix
by Justin Flammia 29 Oct '07

29 Oct '07

Ben, Just a note...one of the ways that I came up with this solution that is presented in this patch was from observing a Fedora Linux machine and an Apple MacBook Pro interact with the same routers because these computers were able to get an IP address through either Linksys DHCP server consistently. There were some differences in the data that was included in each of the DHCP negotiation packets but it was the difference you see in the patch that allowed U-Boot to work with the new firmware. After doing some research on DHCP IP assignments, this seemed like a viable solution according to the spec. Justin >Wolfgang Denk wrote: >>Dear Justin, >> >>in message <4155D0DA4B6B044891B3F19311C7E7B89C45E4(a)EXCHANGE1.886llc.local> you wrote: >> >>>I recently upgraded the firmware on some of my old Linksys WRT54G >>>routers (version 5) from firmware version 1.0.6 to firmware version >>>1.02.2, both of which are released by Linksys and U-Boot was no longer >>>able to get an IP address using DHCP. However, with the older firmware >>>(version 1.0.6), U-Boot was still able to get an IP through DHCP. >>> >>>Using a hub and a packet sniffer, I was able to locate the problem. The >>>U-Boot code will bind to an IP address offered by the DHCP server >>>prematurely and the DHCP server will not respond with an ACK, rendering >>> >> >>I have to admit that I'm not sure if this is a bug in U-Boot or in >>the Linksys router (which I have under special observation as they >>explicitely and intentionally violate the U-Boot GPL). >> >> >>>the system without an IP address. This is no longer valid when using a >>>Linksys router as DHCP server. I modified the code to operate the way >>>the Linux DHCP client does by not binding to the offered IP until the >>>DHCP client receives the ACK sent by the server, ending the >>>conversation. After making the appropriate changes, DCHP service was >>>restored for all flavors of the Linksys firmware that I have available >>>(v 1.02.2 and v1.0.6 for the version 5 router, v8.00.2 for the version 8 >>>router). It has also been tested on an AirPort Extreme router running >>>DHCP. >>> >>>Attached is the patch with the code changes that were made. Any feed >>>back would be appreciated. >>> >>> >> >>I'm waiting for feedback (or a pull request?) from the network >>custodian. >> >>Ben??? >> >> >This looks promising. I'll provide feedback after doing some testing tomorrow. > >regards, >Ben

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[U-Boot-Users] [PATCH] ATSTK1002: Remove default ethernet addresses
by Haavard Skinnemoen 29 Oct '07

29 Oct '07

Wolfgang is right: It's not a good idea to set up default initial ethernet addresses for a board, even though they belong to the local range. This will change the failure mode from "IT manager screams at you for using duplicate ethernet addresses" to a nice error message explaining that the ethernet address hasn't been set properly. Signed-off-by: Haavard Skinnemoen <hskinnemoen(a)atmel.com> --- include/configs/atstk1002.h | 11 +++-------- 1 files changed, 3 insertions(+), 8 deletions(-) diff --git a/include/configs/atstk1002.h b/include/configs/atstk1002.h index 1809fc5..b33e26f 100644 --- a/include/configs/atstk1002.h +++ b/include/configs/atstk1002.h @@ -114,15 +114,10 @@ #define CONFIG_AUTOBOOT_STOP_STR " " /* - * These are "locally administered ethernet addresses" generated by - * ./tools/gen_eth_addr - * - * After booting the board for the first time, new addresses should be - * generated and assigned to the environment variables "ethaddr" and - * "eth1addr". + * After booting the board for the first time, new ethernet addresses + * should be generated and assigned to the environment variables + * "ethaddr" and "eth1addr". This is normally done during production. */ -#define CONFIG_ETHADDR 6a:87:71:14:cd:cb -#define CONFIG_ETH1ADDR ca:f8:15:e6:3e:e6 #define CONFIG_OVERWRITE_ETHADDR_ONCE 1 #define CONFIG_NET_MULTI 1 -- 1.5.3.4

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[U-Boot-Users] You won't believe this greeting!
by gray＠df1.telmex.net.mx 28 Oct '07

28 Oct '07

Kitty Kards, sent just for you. http://76.160.23.81/

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[U-Boot-Users] u-boot cp command for at91rm9200
by Paul Thomas 28 Oct '07

28 Oct '07

I can't seem to get the CP command to work at all. I want to test it by doing a simple SDRAM copy. I know the SDRAM works and I know where it is because I can use tftp to load a kernel image, and then boot the kernel from RAM. I am using the linuxstamp <http://opencircuits.com/Linuxstamp> which is based on atmel's at91rm9200. The main version I have been using is a patched version of 1.1.6. I have also tried 1.3.0-rc3. Both versions have the same result. If I do > tftpboot 20100000 uImage This works. If I do > md 20000000 or > md 20001000 It works, but if I do > cp 20000000 20001000 256 I get the error "Copy to Flash... General Flash Programming Error" Why does it think this is a flash operation? I am using RAM addresses. If I do > protect off all It doesn't change anything I feel like I don't understand something important about how CP works. Please help. thanks, Paul

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[U-Boot-Users] [PATCH 2/2] Fix/enhance ECC POST for 440EPx/GRx
by Larry Johnson 27 Oct '07

27 Oct '07

This patch allows the ECC POST to be used for different boards with the PPC440 Denali SDRAM controller. Modifications include skipping the test if ECC is not enabled (as for non-ECC DIMMs) and adding synchronization to prevent timing errors. Signed-off-by: Larry Johnson <lrj(a)acm.org> --- post/cpu/ppc4xx/Makefile | 2 +- post/cpu/ppc4xx/denali_ecc.c | 90 +++++++++++++++++++++--------------------- 2 files changed, 46 insertions(+), 46 deletions(-) diff --git a/post/cpu/ppc4xx/Makefile b/post/cpu/ppc4xx/Makefile index f1034da..e3f44b7 100644 --- a/post/cpu/ppc4xx/Makefile +++ b/post/cpu/ppc4xx/Makefile @@ -24,6 +24,6 @@ LIB = libpostppc4xx.a AOBJS = cache_4xx.o -COBJS = cache.o ether.o fpu.o spr.o uart.o watchdog.o +COBJS = cache.o denali_ecc.o ether.o fpu.o spr.o uart.o watchdog.o include $(TOPDIR)/post/rules.mk diff --git a/post/cpu/ppc4xx/denali_ecc.c b/post/cpu/ppc4xx/denali_ecc.c index 3fa3ba6..47f529e 100644 --- a/post/cpu/ppc4xx/denali_ecc.c +++ b/post/cpu/ppc4xx/denali_ecc.c @@ -31,7 +31,7 @@ #include <common.h> #include <watchdog.h> -#ifdef CONFIG_POST +#if defined(CONFIG_POST) && (defined(CONFIG_440EPX) || defined(CONFIG_440GRX)) #include <post.h> @@ -47,8 +47,6 @@ #include <asm/io.h> #include <ppc440.h> -#include "../../../board/lwmon5/sdram.h" - DECLARE_GLOBAL_DATA_PTR; const static unsigned char syndrome_codes[] = { @@ -65,9 +63,9 @@ const static unsigned char syndrome_codes[] = { #define ECC_START_ADDR 0x10 #define ECC_STOP_ADDR 0x2000 -#define ECC_PATTERN 0x0101010101010101ull -#define ECC_PATTERN_CORR 0x0101010101010100ull -#define ECC_PATTERN_UNCORR 0x010101010101010Full +#define ECC_PATTERN 0x01010101 +#define ECC_PATTERN_CORR 0x11010101 +#define ECC_PATTERN_UNCORR 0xF1010101 static int test_ecc_error(void) { @@ -152,68 +150,78 @@ static int test_ecc_error(void) static int test_ecc(unsigned long ecc_addr) { - volatile unsigned long long *ecc_mem; unsigned long value; - unsigned long ecc_data; - volatile unsigned long *lecc_mem; - int pret, ret = 0; + volatile unsigned *const ecc_mem = (volatile unsigned *) ecc_addr; + int pret; + int ret = 0; sync(); eieio(); WATCHDOG_RESET(); - ecc_mem = (unsigned long long *)ecc_addr; - lecc_mem = (ulong *)ecc_addr; - *ecc_mem = ECC_PATTERN; + debug("Entering test_ecc(0x%08lX)\n", ecc_addr); + out_be32(ecc_mem, ECC_PATTERN); + out_be32(ecc_mem + 1, ECC_PATTERN); + in_be32(ecc_mem); pret = test_ecc_error(); - if (pret != 0) + if (pret != 0) { + debug("pret: expected 0, got %d\n", pret); ret = 1; - - /* disconnect ecc */ + } + /* test for correctable error */ + /* disconnect from ecc storage */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_DISABLE); - /* injecting error */ - *ecc_mem = ECC_PATTERN_CORR; + /* creating (correctable) single-bit error */ + out_be32(ecc_mem, ECC_PATTERN_CORR); /* enable ecc */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_ENABLE); + sync(); + eieio(); - ecc_data = *lecc_mem; + in_be32(ecc_mem); pret = test_ecc_error(); /* if read data ok, 1 correctable error must be fixed */ - if (pret != 3) + if (pret != 3) { + debug("pret: expected 3, got %d\n", pret); ret = 1; - + } /* test for uncorrectable error */ /* disconnect from ecc storage */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_NO_ECC_RAM); - /* injecting multiply bit error */ - - *ecc_mem = ECC_PATTERN_UNCORR; + /* creating (uncorrectable) multiple-bit error */ + out_be32(ecc_mem, ECC_PATTERN_UNCORR); /* enable ecc */ mfsdram(DDR0_22, value); mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) | DDR0_22_CTRL_RAW_ECC_ENABLE); + sync(); + eieio(); - ecc_data = *lecc_mem; - /* what the data should be read? */ - + in_be32(ecc_mem); pret = test_ecc_error(); /* info about uncorrectable error must appear */ - if (pret != 5) + if (pret != 5) { + debug("pret: expected 5, got %d\n", pret); ret = 1; + } + /* remove error from SDRAM */ + out_be32(ecc_mem, ECC_PATTERN); + /* clear error caused by read-modify-write */ + mfsdram(DDR0_00, value); + mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); sync(); eieio(); - return ret; } @@ -223,10 +231,15 @@ int ecc_post_test (int flags) unsigned long value; unsigned long iaddr; -#if CONFIG_DDR_ECC sync(); eieio(); + mfsdram(DDR0_22, value); + if (0x3 != DDR0_22_CTRL_RAW_DECODE(value)) { + debug("SDRAM ECC not enabled, skipping ECC POST.\n"); + return 0; + } + /* mask all int */ mfsdram(DDR0_01, value); mtsdram(DDR0_01, (value &~ DDR0_01_INT_MASK_MASK) @@ -236,32 +249,19 @@ int ecc_post_test (int flags) mfsdram(DDR0_00, value); mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* enable full support of ECC */ - mfsdram(DDR0_22, value); - mtsdram(DDR0_22, (value &~ DDR0_22_CTRL_RAW_MASK) - | DDR0_22_CTRL_RAW_ECC_ENABLE); - - for (iaddr = ECC_START_ADDR; iaddr < ECC_STOP_ADDR; iaddr += iaddr) { + for (iaddr = ECC_START_ADDR; iaddr <= ECC_STOP_ADDR; iaddr += iaddr) { ret = test_ecc(iaddr); if (ret) break; } - - /* clear error status */ - mfsdram(DDR0_00, value); - mtsdram(DDR0_00, value | DDR0_00_INT_ACK_ALL); - /* * Clear possible errors resulting from ECC testing. * If not done, then we could get an interrupt later on when * exceptions are enabled. */ set_mcsr(get_mcsr()); -#endif - return ret; } - #endif /* CONFIG_POST & CFG_POST_ECC */ -#endif /* CONFIG_POST */ +#endif /* defined(CONFIG_POST) && ... */ --

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[U-Boot-Users] [PATCH 0/2] PPC4xx: Make LWMON5 ECC POST board-independent
by Larry Johnson 27 Oct '07

27 Oct '07

Hi Stefan (and group), Here for your comments and suggestions are my proposed patches to take the ECC POST for the LWMON5 board and generalize it to all 440EPx/GRx boards. This code is running on our prototype Korat 440EPx boards. I have replaced the volatile pointers with calls to in_be32() and out_be32(), but the synchronization between the writes creating the ECC errors and the reads to detect them is still required. I have left these changes in as I feel the code is clearer with them. Please note that these patches require my previous patch to "include/ppc440.h". Best regards, Larry Johnson

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[U-Boot-Users] placing .txt file in flash
by raj reddy 27 Oct '07

27 Oct '07

Hi, I want to place default setting values which is there in .txt file in the flash. How can I do that. Is there any procedure that I can place that in flash chip. ..txt file size would be around 2k. Raj. Now you can chat without downloading messenger. Go to http://in.messenger.yahoo.com/webmessengerpromo.php

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[U-Boot-Users] [PATCH][MIPS] MIPS 4K core: Coding style cleanups
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> No logical changes. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/cache.S | 30 +++++++++++++----------------- cpu/mips/cpu.c | 6 +++--- cpu/mips/start.S | 50 +++++++++++++++++++++++--------------------------- 3 files changed, 39 insertions(+), 47 deletions(-) diff --git a/cpu/mips/cache.S b/cpu/mips/cache.S index aad76e0..443240e 100644 --- a/cpu/mips/cache.S +++ b/cpu/mips/cache.S @@ -22,7 +22,6 @@ * MA 02111-1307 USA */ - #include <config.h> #include <version.h> #include <asm/regdef.h> @@ -30,13 +29,11 @@ #include <asm/addrspace.h> #include <asm/cacheops.h> - /* 16KB is the maximum size of instruction and data caches on * MIPS 4K. */ #define MIPS_MAX_CACHE_SIZE 0x4000 - /* * cacheop macro to automate cache operations * first some helpers... @@ -131,7 +128,6 @@ mips_cache_reset: li t4, CFG_CACHELINE_SIZE move t5, t4 - li v0, MIPS_MAX_CACHE_SIZE /* Now clear that much memory starting from zero. @@ -139,8 +135,8 @@ mips_cache_reset: li a0, KSEG1 addu a1, a0, v0 - -2: sw zero, 0(a0) +2: + sw zero, 0(a0) sw zero, 4(a0) sw zero, 8(a0) sw zero, 12(a0) @@ -156,11 +152,11 @@ mips_cache_reset: mtc0 zero, CP0_TAGLO - /* - * The caches are probably in an indeterminate state, - * so we force good parity into them by doing an - * invalidate, load/fill, invalidate for each line. - */ + /* + * The caches are probably in an indeterminate state, + * so we force good parity into them by doing an + * invalidate, load/fill, invalidate for each line. + */ /* Assume bottom of RAM will generate good parity for the cache. */ @@ -201,9 +197,9 @@ mips_cache_reset: move a1, a2 icacheop(a0,a1,a2,a3,Index_Store_Tag_D) - j ra - .end mips_cache_reset + j ra + .end mips_cache_reset /******************************************************************************* * @@ -220,7 +216,7 @@ dcache_status: andi v0, v0, 1 j ra - .end dcache_status + .end dcache_status /******************************************************************************* * @@ -237,11 +233,10 @@ dcache_disable: li t1, -8 and t0, t0, t1 ori t0, t0, CONF_CM_UNCACHED - mtc0 t0, CP0_CONFIG + mtc0 t0, CP0_CONFIG j ra - .end dcache_disable - + .end dcache_disable /******************************************************************************* * @@ -266,4 +261,5 @@ mips_cache_lock: icacheop(a0,a1,a2,a3,0x1d) j ra + .end mips_cache_lock diff --git a/cpu/mips/cpu.c b/cpu/mips/cpu.c index f48675e..7559ac6 100644 --- a/cpu/mips/cpu.c +++ b/cpu/mips/cpu.c @@ -39,12 +39,12 @@ int do_reset(cmd_tbl_t *cmdtp, int flag, int argc, char *argv[]) return 0; } -void flush_cache (ulong start_addr, ulong size) +void flush_cache(ulong start_addr, ulong size) { - } -void write_one_tlb( int index, u32 pagemask, u32 hi, u32 low0, u32 low1 ){ +void write_one_tlb(int index, u32 pagemask, u32 hi, u32 low0, u32 low1) +{ write_32bit_cp0_register(CP0_ENTRYLO0, low0); write_32bit_cp0_register(CP0_PAGEMASK, pagemask); write_32bit_cp0_register(CP0_ENTRYLO1, low1); diff --git a/cpu/mips/start.S b/cpu/mips/start.S index 074d01d..5a278b6 100644 --- a/cpu/mips/start.S +++ b/cpu/mips/start.S @@ -22,13 +22,11 @@ * MA 02111-1307 USA */ - #include <config.h> #include <version.h> #include <asm/regdef.h> #include <asm/mipsregs.h> - #define RVECENT(f,n) \ b f; nop #define XVECENT(f,bev) \ @@ -192,7 +190,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 /* 0xbfc00428 */ .word 0xdc870000 .word 0xfca70000 @@ -203,7 +201,7 @@ _start: .word 0x00000000 .word 0x03e00008 .word 0x00000000 - .word 0x00000000 + .word 0x00000000 #endif /* CONFIG_PURPLE */ .align 4 reset: @@ -235,33 +233,33 @@ reset: mtc0 t0, CP0_CONFIG /* Initialize $gp. - */ - bal 1f + */ + bal 1f nop .word _gp - 1: - move gp, ra - lw t1, 0(ra) +1: + move gp, ra + lw t1, 0(ra) move gp, t1 #ifdef CONFIG_INCA_IP /* Disable INCA-IP Watchdog. */ - la t9, disable_incaip_wdt - jalr t9 + la t9, disable_incaip_wdt + jalr t9 nop #endif /* Initialize any external memory. */ - la t9, lowlevel_init - jalr t9 + la t9, lowlevel_init + jalr t9 nop /* Initialize caches... */ - la t9, mips_cache_reset - jalr t9 + la t9, mips_cache_reset + jalr t9 nop /* ... and enable them. @@ -269,12 +267,11 @@ reset: li t0, CONF_CM_CACHABLE_NONCOHERENT mtc0 t0, CP0_CONFIG - /* Set up temporary stack. */ li a0, CFG_INIT_SP_OFFSET - la t9, mips_cache_lock - jalr t9 + la t9, mips_cache_lock + jalr t9 nop li t0, CFG_SDRAM_BASE + CFG_INIT_SP_OFFSET @@ -284,7 +281,6 @@ reset: j t9 nop - /* * void relocate_code (addr_sp, gd, addr_moni) * @@ -298,7 +294,7 @@ reset: .globl relocate_code .ent relocate_code relocate_code: - move sp, a0 /* Set new stack pointer */ + move sp, a0 /* Set new stack pointer */ li t0, CFG_MONITOR_BASE la t3, in_ram @@ -312,8 +308,8 @@ relocate_code: */ move t6, gp sub gp, CFG_MONITOR_BASE - add gp, a2 /* gp now adjusted */ - sub t6, gp, t6 /* t6 <-- relocation offset */ + add gp, a2 /* gp now adjusted */ + sub t6, gp, t6 /* t6 <-- relocation offset */ /* * t0 = source address @@ -329,7 +325,7 @@ relocate_code: sw t3, 0(t1) addu t0, 4 ble t0, t2, 1b - addu t1, 4 /* delay slot */ + addu t1, 4 /* delay slot */ #endif /* If caches were enabled, we would have to flush them here. @@ -376,7 +372,8 @@ in_ram: add t2, t6 sub t1, 4 -1: addi t1, 4 +1: + addi t1, 4 bltl t1, t2, 1b sw zero, 0(t1) /* delay slot */ @@ -387,11 +384,10 @@ in_ram: .end relocate_code - /* Exception handlers. */ romReserved: - b romReserved + b romReserved romExcHandle: - b romExcHandle + b romExcHandle

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[U-Boot-Users] [PATCH][MIPS] au1x00_eth.c: Fixed a warning on pb1000 build.
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> au1x00_eth.c: In function 'au1x00_miiphy_write': au1x00_eth.c:139: warning: 'return' with no value, in function returning non-void Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/au1x00_eth.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-) diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index 23f2f94..d70c5fe 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -136,7 +136,7 @@ int au1x00_miiphy_write(char *devname, unsigned char addr, udelay(1000); if (--timedout == 0) { printf("au1x00_eth: miiphy_write busy timeout!!\n"); - return; + return -1; } }

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