October 2007 - U-Boot

[U-Boot-Users] [PATCH][MIPS] au1x00_eth.c: Fix au1x00_miiphy_{read, write} build error
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> au1x00_eth.c: In function 'au1x00_enet_initialize': au1x00_eth.c:246: error: 'au1x00_miiphy_read' undeclared (first use in this function) au1x00_eth.c:246: error: (Each undeclared identifier is reported only once au1x00_eth.c:246: error: for each function it appears in.) au1x00_eth.c:246: error: 'au1x00_miiphy_write' undeclared (first use in this function) au1x00_eth.c: In function 'au1x00_miiphy_write': au1x00_eth.c:298: warning: 'return' with no value, in function returning non-void make[1]: *** [au1x00_eth.o] Error 1 Fixed by moving these two functions forward. Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- cpu/mips/au1x00_eth.c | 118 +++++++++++++++++++++++++------------------------ 1 files changed, 59 insertions(+), 59 deletions(-) diff --git a/cpu/mips/au1x00_eth.c b/cpu/mips/au1x00_eth.c index b69741a..23f2f94 100644 --- a/cpu/mips/au1x00_eth.c +++ b/cpu/mips/au1x00_eth.c @@ -90,6 +90,65 @@ mac_fifo_t mac_fifo[NO_OF_FIFOS]; #define MAX_WAIT 1000 +#if defined(CONFIG_CMD_MII) +int au1x00_miiphy_read(char *devname, unsigned char addr, + unsigned char reg, unsigned short * value) +{ + volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); + volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); + u32 mii_control; + unsigned int timedout = 20; + + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_read busy timeout!!\n"); + return -1; + } + } + + mii_control = MAC_SET_MII_SELECT_REG(reg) | + MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; + + *mii_control_reg = mii_control; + + timedout = 20; + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_read busy timeout!!\n"); + return -1; + } + } + *value = *mii_data_reg; + return 0; +} + +int au1x00_miiphy_write(char *devname, unsigned char addr, + unsigned char reg, unsigned short value) +{ + volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); + volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); + u32 mii_control; + unsigned int timedout = 20; + + while (*mii_control_reg & MAC_MII_BUSY) { + udelay(1000); + if (--timedout == 0) { + printf("au1x00_eth: miiphy_write busy timeout!!\n"); + return; + } + } + + mii_control = MAC_SET_MII_SELECT_REG(reg) | + MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; + + *mii_data_reg = value; + *mii_control_reg = mii_control; + return 0; +} +#endif + static int au1x00_send(struct eth_device* dev, volatile void *packet, int length){ volatile mac_fifo_t *fifo_tx = (volatile mac_fifo_t*)(MAC0_TX_DMA_ADDR+MAC_TX_BUFF0_STATUS); @@ -249,63 +308,4 @@ int au1x00_enet_initialize(bd_t *bis){ return 1; } -#if defined(CONFIG_CMD_MII) -int au1x00_miiphy_read(char *devname, unsigned char addr, - unsigned char reg, unsigned short * value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_READ; - - *mii_control_reg = mii_control; - - timedout = 20; - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_read busy timeout!!\n"); - return -1; - } - } - *value = *mii_data_reg; - return 0; -} - -int au1x00_miiphy_write(char *devname, unsigned char addr, - unsigned char reg, unsigned short value) -{ - volatile u32 *mii_control_reg = (volatile u32*)(ETH0_BASE+MAC_MII_CNTRL); - volatile u32 *mii_data_reg = (volatile u32*)(ETH0_BASE+MAC_MII_DATA); - u32 mii_control; - unsigned int timedout = 20; - - while (*mii_control_reg & MAC_MII_BUSY) { - udelay(1000); - if (--timedout == 0) { - printf("au1x00_eth: miiphy_write busy timeout!!\n"); - return; - } - } - - mii_control = MAC_SET_MII_SELECT_REG(reg) | - MAC_SET_MII_SELECT_PHY(addr) | MAC_MII_WRITE; - - *mii_data_reg = value; - *mii_control_reg = mii_control; - return 0; -} -#endif - #endif /* CONFIG_AU1X00 */

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[U-Boot-Users] [PATCH] MAKEALL: Added missing pb1000 board
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- MAKEALL | 1 + 1 files changed, 1 insertions(+), 0 deletions(-) diff --git a/MAKEALL b/MAKEALL index 20e8137..20ef4e1 100755 --- a/MAKEALL +++ b/MAKEALL @@ -554,6 +554,7 @@ LIST_mips5kc_el="" LIST_au1xx0_el=" \ dbau1550_el \ + pb1000 \ " LIST_mips_el=" \

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[U-Boot-Users] [PATCH][MIPS] pb1000: Replace obsolete memsetup.S with lowlevel_init.S
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/pb1x00/Makefile | 2 board/pb1x00/lowlevel_init.S | 392 ++++++++++++++++++++++++++++++++++++++++++ board/pb1x00/memsetup.S | 392 ------------------------------------------ 3 files changed, 393 insertions(+), 393 deletions(-) diff --git a/board/pb1x00/Makefile b/board/pb1x00/Makefile index f7d5841..afe02c2 100644 --- a/board/pb1x00/Makefile +++ b/board/pb1x00/Makefile @@ -26,7 +26,7 @@ include $(TOPDIR)/config.mk LIB = $(obj)lib$(BOARD).a COBJS = $(BOARD).o flash.o -SOBJS = memsetup.o +SOBJS = lowlevel_init.o SRCS := $(SOBJS:.o=.S) $(COBJS:.o=.c) OBJS := $(addprefix $(obj),$(COBJS)) diff --git a/board/pb1x00/lowlevel_init.S b/board/pb1x00/lowlevel_init.S new file mode 100644 index 0000000..e851e2f --- /dev/null +++ b/board/pb1x00/lowlevel_init.S @@ -0,0 +1,392 @@ +/* Memory sub-system initialization code */ + +#include <config.h> +#include <version.h> +#include <asm/regdef.h> +#include <asm/au1x00.h> +#include <asm/mipsregs.h> + +#define AU1500_SYS_ADDR 0xB1900000 +#define sys_endian 0x0038 +#define CP0_Config0 $16 +#define MEM_1MS ((396000000/1000000) * 1000) + + .text + .set noreorder + .set mips32 + + .globl lowlevel_init +lowlevel_init: + /* + * Step 1) Establish CPU endian mode. + * NOTE: A fair amount of code is necessary on the Pb1000 to + * obtain the value of Switch S8.1 which is used to determine + * endian at run-time. + */ + + /* RCE1 */ + li t0, MEM_STCFG1 + li t1, 0x00000083 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x33030A10 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x11803E40 + sw t1, 0(t0) + + /* Set DSTRB bits so switch will read correctly */ + li t1, 0xBE00000C + lw t2, 0(t1) + or t2, t2, 0x00000300 + sw t2, 0(t1) + + /* Check switch setting */ + li t1, 0xBE000014 + lw t2, 0(t1) + and t2, t2, 0x00000100 + bne t2, zero, big_endian + nop + +little_endian: + + /* Change Au1 core to little endian */ + li t0, AU1500_SYS_ADDR + li t1, 1 + sw t1, sys_endian(t0) + mfc0 t2, CP0_CONFIG + mtc0 t2, CP0_CONFIG + nop + nop + + /* Big Endian is default so nothing to do but fall through */ + +big_endian: + + /* + * Step 2) Establish Status Register + * (set BEV, clear ERL, clear EXL, clear IE) + */ + li t1, 0x00400000 + mtc0 t1, CP0_STATUS + + /* + * Step 3) Establish CP0 Config0 + * (set OD, set K0=3) + */ + li t1, 0x00080003 + mtc0 t1, CP0_CONFIG + + /* + * Step 4) Disable Watchpoint facilities + */ + li t1, 0x00000000 + mtc0 t1, CP0_WATCHLO + mtc0 t1, CP0_IWATCHLO + /* + * Step 5) Disable the performance counters + */ + mtc0 zero, CP0_PERFORMANCE + nop + + /* + * Step 6) Establish EJTAG Debug register + */ + mtc0 zero, CP0_DEBUG + nop + + /* + * Step 7) Establish Cause + * (set IV bit) + */ + li t1, 0x00800000 + mtc0 t1, CP0_CAUSE + + /* Establish Wired (and Random) */ + mtc0 zero, CP0_WIRED + nop + + /* First setup pll:s to make serial work ok */ + /* We have a 12 MHz crystal */ + li t0, SYS_CPUPLL + li t1, 0x21 /* 396 MHz */ + sw t1, 0(t0) + sync + nop + nop + + /* wait 1mS for clocks to settle */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + /* Setup AUX PLL */ + li t0, SYS_AUXPLL + li t1, 8 /* 96 MHz */ + sw t1, 0(t0) /* aux pll */ + sync + + /* Static memory controller */ + + /* RCE0 8MB AMD29D323 Flash */ + li t0, MEM_STCFG0 + li t1, 0x00001403 + sw t1, 0(t0) + + li t0, MEM_STTIME0 + li t1, 0xFFFFFFDD + sw t1, 0(t0) + + li t0, MEM_STADDR0 + li t1, 0x11F83FE0 + sw t1, 0(t0) + + /* RCE1 CPLD Board Logic */ + li t0, MEM_STCFG1 + li t1, 0x00000083 + sw t1, 0(t0) + + li t0, MEM_STTIME1 + li t1, 0x33030A10 + sw t1, 0(t0) + + li t0, MEM_STADDR1 + li t1, 0x11803E40 + sw t1, 0(t0) + + /* RCE2 CPLD Board Logic */ + li t0, MEM_STCFG2 + li t1, 0x00000004 + sw t1, 0(t0) + + li t0, MEM_STTIME2 + li t1, 0x08061908 + sw t1, 0(t0) + + li t0, MEM_STADDR2 + li t1, 0x12A03FC0 + sw t1, 0(t0) + + /* RCE3 PCMCIA 250ns */ + li t0, MEM_STCFG3 + li t1, 0x00000002 + sw t1, 0(t0) + + li t0, MEM_STTIME3 + li t1, 0x280E3E07 + sw t1, 0(t0) + + li t0, MEM_STADDR3 + li t1, 0x10000000 + sw t1, 0(t0) + + sync + + /* Set peripherals to a known state */ + li t0, IC0_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC0_CFG0CLR + sw t1, 0(t0) + + li t0, IC0_CFG1CLR + sw t1, 0(t0) + + li t0, IC0_CFG2CLR + sw t1, 0(t0) + + li t0, IC0_SRCSET + sw t1, 0(t0) + + li t0, IC0_ASSIGNSET + sw t1, 0(t0) + + li t0, IC0_WAKECLR + sw t1, 0(t0) + + li t0, IC0_RISINGCLR + sw t1, 0(t0) + + li t0, IC0_FALLINGCLR + sw t1, 0(t0) + + li t0, IC0_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, IC1_CFG0CLR + li t1, 0xFFFFFFFF + sw t1, 0(t0) + + li t0, IC1_CFG0CLR + sw t1, 0(t0) + + li t0, IC1_CFG1CLR + sw t1, 0(t0) + + li t0, IC1_CFG2CLR + sw t1, 0(t0) + + li t0, IC1_SRCSET + sw t1, 0(t0) + + li t0, IC1_ASSIGNSET + sw t1, 0(t0) + + li t0, IC1_WAKECLR + sw t1, 0(t0) + + li t0, IC1_RISINGCLR + sw t1, 0(t0) + + li t0, IC1_FALLINGCLR + sw t1, 0(t0) + + li t0, IC1_TESTBIT + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, SYS_FREQCTRL0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_FREQCTRL1 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_CLKSRC + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_PININPUTEN + li t1, 0x00000000 + sw t1, 0(t0) + sync + + li t0, 0xB1100100 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, 0xB1400100 + li t1, 0x00000000 + sw t1, 0(t0) + + + li t0, SYS_WAKEMSK + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, SYS_WAKESRC + li t1, 0x00000000 + sw t1, 0(t0) + + /* wait 1mS before setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + + /* + * Skip memory setup if we are running from memory + */ + li t0, 0x90000000 + sub t0, ra, t0 + bltz t0, skip_memsetup + nop + + /* + * SDCS0 - Not used, for SMROM + * SDCS1 - 32MB Micron 48LCBM16A2 + * SDCS2 - 32MB Micron 48LCBM16A2 + */ + li t0, MEM_SDMODE0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDMODE1 + li t1, 0x00552229 + sw t1, 0(t0) + + li t0, MEM_SDMODE2 + li t1, 0x00552229 + sw t1, 0(t0) + + li t0, MEM_SDADDR0 + li t1, 0x00000000 + sw t1, 0(t0) + + li t0, MEM_SDADDR1 + li t1, 0x001003F8 + sw t1, 0(t0) + + li t0, MEM_SDADDR2 + li t1, 0x001023F8 + sw t1, 0(t0) + + sync + + li t0, MEM_SDREFCFG + li t1, 0x74000c30 /* Disable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDPRECMD + sw zero, 0(t0) + sync + + li t0, MEM_SDAUTOREF + sw zero, 0(t0) + sync + sw zero, 0(t0) + sync + + li t0, MEM_SDREFCFG + li t1, 0x76000c30 /* Enable */ + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD0 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD1 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + li t0, MEM_SDWRMD2 + li t1, 0x00000023 + sw t1, 0(t0) + sync + + /* wait 1mS after setup */ + li t1, MEM_1MS +1: add t1, -1 + bne t1, zero, 1b + nop + +skip_memsetup: + + li t0, SYS_PINFUNC + li t1, 0/*0x00008080*/ + sw t1, 0(t0) + + /* + li t0, SYS_TRIOUTCLR + li t1, 0x00001FFF + sw t1, 0(t0) + + li t0, SYS_OUTPUTCLR + li t1, 0x00008000 + sw t1, 0(t0) + */ + sync + + j ra + nop diff --git a/board/pb1x00/memsetup.S b/board/pb1x00/memsetup.S deleted file mode 100644 index 44f02b9..0000000 --- a/board/pb1x00/memsetup.S +++ /dev/null @@ -1,392 +0,0 @@ -/* Memory sub-system initialization code */ - -#include <config.h> -#include <version.h> -#include <asm/regdef.h> -#include <asm/au1x00.h> -#include <asm/mipsregs.h> - -#define AU1500_SYS_ADDR 0xB1900000 -#define sys_endian 0x0038 -#define CP0_Config0 $16 -#define MEM_1MS ((396000000/1000000) * 1000) - - .text - .set noreorder - .set mips32 - - .globl memsetup -memsetup: - /* - * Step 1) Establish CPU endian mode. - * NOTE: A fair amount of code is necessary on the Pb1000 to - * obtain the value of Switch S8.1 which is used to determine - * endian at run-time. - */ - - /* RCE1 */ - li t0, MEM_STCFG1 - li t1, 0x00000083 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x33030A10 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x11803E40 - sw t1, 0(t0) - - /* Set DSTRB bits so switch will read correctly */ - li t1, 0xBE00000C - lw t2, 0(t1) - or t2, t2, 0x00000300 - sw t2, 0(t1) - - /* Check switch setting */ - li t1, 0xBE000014 - lw t2, 0(t1) - and t2, t2, 0x00000100 - bne t2, zero, big_endian - nop - -little_endian: - - /* Change Au1 core to little endian */ - li t0, AU1500_SYS_ADDR - li t1, 1 - sw t1, sys_endian(t0) - mfc0 t2, CP0_CONFIG - mtc0 t2, CP0_CONFIG - nop - nop - - /* Big Endian is default so nothing to do but fall through */ - -big_endian: - - /* - * Step 2) Establish Status Register - * (set BEV, clear ERL, clear EXL, clear IE) - */ - li t1, 0x00400000 - mtc0 t1, CP0_STATUS - - /* - * Step 3) Establish CP0 Config0 - * (set OD, set K0=3) - */ - li t1, 0x00080003 - mtc0 t1, CP0_CONFIG - - /* - * Step 4) Disable Watchpoint facilities - */ - li t1, 0x00000000 - mtc0 t1, CP0_WATCHLO - mtc0 t1, CP0_IWATCHLO - /* - * Step 5) Disable the performance counters - */ - mtc0 zero, CP0_PERFORMANCE - nop - - /* - * Step 6) Establish EJTAG Debug register - */ - mtc0 zero, CP0_DEBUG - nop - - /* - * Step 7) Establish Cause - * (set IV bit) - */ - li t1, 0x00800000 - mtc0 t1, CP0_CAUSE - - /* Establish Wired (and Random) */ - mtc0 zero, CP0_WIRED - nop - - /* First setup pll:s to make serial work ok */ - /* We have a 12 MHz crystal */ - li t0, SYS_CPUPLL - li t1, 0x21 /* 396 MHz */ - sw t1, 0(t0) - sync - nop - nop - - /* wait 1mS for clocks to settle */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - /* Setup AUX PLL */ - li t0, SYS_AUXPLL - li t1, 8 /* 96 MHz */ - sw t1, 0(t0) /* aux pll */ - sync - - /* Static memory controller */ - - /* RCE0 8MB AMD29D323 Flash */ - li t0, MEM_STCFG0 - li t1, 0x00001403 - sw t1, 0(t0) - - li t0, MEM_STTIME0 - li t1, 0xFFFFFFDD - sw t1, 0(t0) - - li t0, MEM_STADDR0 - li t1, 0x11F83FE0 - sw t1, 0(t0) - - /* RCE1 CPLD Board Logic */ - li t0, MEM_STCFG1 - li t1, 0x00000083 - sw t1, 0(t0) - - li t0, MEM_STTIME1 - li t1, 0x33030A10 - sw t1, 0(t0) - - li t0, MEM_STADDR1 - li t1, 0x11803E40 - sw t1, 0(t0) - - /* RCE2 CPLD Board Logic */ - li t0, MEM_STCFG2 - li t1, 0x00000004 - sw t1, 0(t0) - - li t0, MEM_STTIME2 - li t1, 0x08061908 - sw t1, 0(t0) - - li t0, MEM_STADDR2 - li t1, 0x12A03FC0 - sw t1, 0(t0) - - /* RCE3 PCMCIA 250ns */ - li t0, MEM_STCFG3 - li t1, 0x00000002 - sw t1, 0(t0) - - li t0, MEM_STTIME3 - li t1, 0x280E3E07 - sw t1, 0(t0) - - li t0, MEM_STADDR3 - li t1, 0x10000000 - sw t1, 0(t0) - - sync - - /* Set peripherals to a known state */ - li t0, IC0_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC0_CFG0CLR - sw t1, 0(t0) - - li t0, IC0_CFG1CLR - sw t1, 0(t0) - - li t0, IC0_CFG2CLR - sw t1, 0(t0) - - li t0, IC0_SRCSET - sw t1, 0(t0) - - li t0, IC0_ASSIGNSET - sw t1, 0(t0) - - li t0, IC0_WAKECLR - sw t1, 0(t0) - - li t0, IC0_RISINGCLR - sw t1, 0(t0) - - li t0, IC0_FALLINGCLR - sw t1, 0(t0) - - li t0, IC0_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, IC1_CFG0CLR - li t1, 0xFFFFFFFF - sw t1, 0(t0) - - li t0, IC1_CFG0CLR - sw t1, 0(t0) - - li t0, IC1_CFG1CLR - sw t1, 0(t0) - - li t0, IC1_CFG2CLR - sw t1, 0(t0) - - li t0, IC1_SRCSET - sw t1, 0(t0) - - li t0, IC1_ASSIGNSET - sw t1, 0(t0) - - li t0, IC1_WAKECLR - sw t1, 0(t0) - - li t0, IC1_RISINGCLR - sw t1, 0(t0) - - li t0, IC1_FALLINGCLR - sw t1, 0(t0) - - li t0, IC1_TESTBIT - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, SYS_FREQCTRL0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_FREQCTRL1 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_CLKSRC - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_PININPUTEN - li t1, 0x00000000 - sw t1, 0(t0) - sync - - li t0, 0xB1100100 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, 0xB1400100 - li t1, 0x00000000 - sw t1, 0(t0) - - - li t0, SYS_WAKEMSK - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, SYS_WAKESRC - li t1, 0x00000000 - sw t1, 0(t0) - - /* wait 1mS before setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - - /* - * Skip memory setup if we are running from memory - */ - li t0, 0x90000000 - sub t0, ra, t0 - bltz t0, skip_memsetup - nop - - /* - * SDCS0 - Not used, for SMROM - * SDCS1 - 32MB Micron 48LCBM16A2 - * SDCS2 - 32MB Micron 48LCBM16A2 - */ - li t0, MEM_SDMODE0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDMODE1 - li t1, 0x00552229 - sw t1, 0(t0) - - li t0, MEM_SDMODE2 - li t1, 0x00552229 - sw t1, 0(t0) - - li t0, MEM_SDADDR0 - li t1, 0x00000000 - sw t1, 0(t0) - - li t0, MEM_SDADDR1 - li t1, 0x001003F8 - sw t1, 0(t0) - - li t0, MEM_SDADDR2 - li t1, 0x001023F8 - sw t1, 0(t0) - - sync - - li t0, MEM_SDREFCFG - li t1, 0x74000c30 /* Disable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDPRECMD - sw zero, 0(t0) - sync - - li t0, MEM_SDAUTOREF - sw zero, 0(t0) - sync - sw zero, 0(t0) - sync - - li t0, MEM_SDREFCFG - li t1, 0x76000c30 /* Enable */ - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD0 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD1 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - li t0, MEM_SDWRMD2 - li t1, 0x00000023 - sw t1, 0(t0) - sync - - /* wait 1mS after setup */ - li t1, MEM_1MS -1: add t1, -1 - bne t1, zero, 1b - nop - -skip_memsetup: - - li t0, SYS_PINFUNC - li t1, 0/*0x00008080*/ - sw t1, 0(t0) - - /* - li t0, SYS_TRIOUTCLR - li t1, 0x00001FFF - sw t1, 0(t0) - - li t0, SYS_OUTPUTCLR - li t1, 0x00008000 - sw t1, 0(t0) - */ - sync - - j ra - nop

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[U-Boot-Users] [PATCH][MIPS] u-boot.lds: Cleanup __u_boot_cmd_{start, end}
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/dbau1x00/u-boot.lds | 9 +++++---- board/gth2/u-boot.lds | 8 +++++--- board/incaip/u-boot.lds | 9 +++++---- board/pb1x00/u-boot.lds | 8 +++++--- board/purple/u-boot.lds | 9 +++++---- board/tb0229/u-boot.lds | 9 +++++---- 6 files changed, 30 insertions(+), 22 deletions(-) diff --git a/board/dbau1x00/u-boot.lds b/board/dbau1x00/u-boot.lds index 9639b81..8618732 100644 --- a/board/dbau1x00/u-boot.lds +++ b/board/dbau1x00/u-boot.lds @@ -54,10 +54,11 @@ SECTIONS .sdata : { *(.sdata) } - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/gth2/u-boot.lds b/board/gth2/u-boot.lds index 90432cb..ce53d9d 100644 --- a/board/gth2/u-boot.lds +++ b/board/gth2/u-boot.lds @@ -54,9 +54,11 @@ SECTIONS .sdata : { *(.sdata) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/incaip/u-boot.lds b/board/incaip/u-boot.lds index 9639b81..8618732 100644 --- a/board/incaip/u-boot.lds +++ b/board/incaip/u-boot.lds @@ -54,10 +54,11 @@ SECTIONS .sdata : { *(.sdata) } - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/pb1x00/u-boot.lds b/board/pb1x00/u-boot.lds index 363d974..8618732 100644 --- a/board/pb1x00/u-boot.lds +++ b/board/pb1x00/u-boot.lds @@ -54,9 +54,11 @@ SECTIONS .sdata : { *(.sdata) } - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/purple/u-boot.lds b/board/purple/u-boot.lds index e7ec012..50e7f84 100644 --- a/board/purple/u-boot.lds +++ b/board/purple/u-boot.lds @@ -64,10 +64,11 @@ SECTIONS .sdata : { *(.sdata) } - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2; diff --git a/board/tb0229/u-boot.lds b/board/tb0229/u-boot.lds index b2fa9f2..c629040 100644 --- a/board/tb0229/u-boot.lds +++ b/board/tb0229/u-boot.lds @@ -54,10 +54,11 @@ SECTIONS .sdata : { *(.sdata) } - . = .; - __u_boot_cmd_start = .; - .u_boot_cmd : { *(.u_boot_cmd) } - __u_boot_cmd_end = .; + .u_boot_cmd : { + __u_boot_cmd_start = .; + *(.u_boot_cmd) + __u_boot_cmd_end = .; + } uboot_end_data = .; num_got_entries = (__got_end - __got_start) >> 2;

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[U-Boot-Users] [PATCH][MIPS] Fixed mips_io_port_base build errors.
by Shinya Kuribayashi 27 Oct '07

27 Oct '07

From: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> This patch has been sent on: - 29 Sep 2007 Although mips_io_port_base is currently a part of IDE command, it is quite fundamental for MIPS I/O port access such as in[bwl] and out[bwl]. So move it to MIPS general part, and introduce `set_io_port_base()' from Linux. This patch is triggered by multiple definition of `mips_io_port_base' build error on gth2 (and tb0229 also needs this fix.) board/gth2/libgth2.a(gth2.o): In function `log_serial_char': /home/skuribay/devel/u-boot.git/board/gth2/gth2.c:47: multiple definition of `mips_io_port_base' common/libcommon.a(cmd_ide.o):/home/skuribay/devel/u-boot.git/common/cmd_ide.c:712: first defined here make: *** [u-boot] Error 1 Signed-off-by: Shinya Kuribayashi <skuribay(a)ruby.dti.ne.jp> --- board/dbau1x00/dbau1x00.c | 4 ++++ board/gth2/gth2.c | 6 ++++-- board/incaip/incaip.c | 5 +++-- board/pb1x00/pb1x00.c | 4 ++++ board/purple/purple.c | 3 +++ board/tb0229/tb0229.c | 7 +++---- common/cmd_ide.c | 4 ---- include/asm-mips/io.h | 16 +++++++++++++++- lib_mips/board.c | 5 +++++ 9 files changed, 41 insertions(+), 13 deletions(-) diff --git a/board/dbau1x00/dbau1x00.c b/board/dbau1x00/dbau1x00.c index d29e8d5..a13eeeb 100644 --- a/board/dbau1x00/dbau1x00.c +++ b/board/dbau1x00/dbau1x00.c @@ -25,6 +25,7 @@ #include <command.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> +#include <asm/io.h> long int initdram(int board_type) { @@ -77,6 +78,9 @@ int checkboard (void) default: printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); } + + set_io_port_base(0); + #ifdef CONFIG_IDE_PCMCIA /* Enable 3.3 V on slot 0 ( VCC ) No 5V */ diff --git a/board/gth2/gth2.c b/board/gth2/gth2.c index ffeaf58..1593f02 100644 --- a/board/gth2/gth2.c +++ b/board/gth2/gth2.c @@ -26,14 +26,13 @@ #include <asm/au1x00.h> #include <asm/addrspace.h> #include <asm/mipsregs.h> +#include <asm/io.h> #include <watchdog.h> #include "ee_access.h" static int wdi_status = 0; -unsigned long mips_io_port_base = 0; - #define SDRAM_SIZE ((64*1024*1024)-(12*4096)) @@ -147,6 +146,9 @@ int checkboard (void) default: printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); } + + set_io_port_base(0); + #ifdef CONFIG_IDE_PCMCIA /* PCMCIA is on a 36 bit physical address. We need to map it into a 32 bit addresses */ diff --git a/board/incaip/incaip.c b/board/incaip/incaip.c index b5d9e00..dbf0ecc 100644 --- a/board/incaip/incaip.c +++ b/board/incaip/incaip.c @@ -25,7 +25,7 @@ #include <command.h> #include <asm/addrspace.h> #include <asm/inca-ip.h> - +#include <asm/io.h> extern uint incaip_get_cpuclk(void); @@ -85,7 +85,6 @@ long int initdram(int board_type) int checkboard (void) { - unsigned long chipid = *INCA_IP_WDT_CHIPID; int part_num; @@ -107,5 +106,7 @@ int checkboard (void) printf("CPU Speed %d MHz\n", incaip_get_cpuclk()/1000000); + set_io_port_base(0); + return 0; } diff --git a/board/pb1x00/pb1x00.c b/board/pb1x00/pb1x00.c index 40ac2a4..95b7d82 100644 --- a/board/pb1x00/pb1x00.c +++ b/board/pb1x00/pb1x00.c @@ -25,6 +25,7 @@ #include <command.h> #include <asm/au1x00.h> #include <asm/mipsregs.h> +#include <asm/io.h> long int initdram(int board_type) { @@ -69,6 +70,9 @@ int checkboard (void) default: printf ("Unsupported cpu %d, proc_id=0x%x\n", proc_id >> 24, proc_id); } + + set_io_port_base(0); + #if defined(CONFIG_IDE_PCMCIA) && 0 /* Enable 3.3 V on slot 0 ( VCC ) No 5V */ diff --git a/board/purple/purple.c b/board/purple/purple.c index 4c3e5b4..74718af 100644 --- a/board/purple/purple.c +++ b/board/purple/purple.c @@ -26,6 +26,7 @@ #include <asm/inca-ip.h> #include <asm/regdef.h> #include <asm/mipsregs.h> +#include <asm/io.h> #include <asm/addrspace.h> #include <asm/cacheops.h> @@ -145,6 +146,8 @@ int checkboard (void) printf("CPU Speed %d MHz\n", CPU_CLOCK_RATE/1000000); + set_io_port_base(0); + return 0; } diff --git a/board/tb0229/tb0229.c b/board/tb0229/tb0229.c index e7914bd..61c2e9b 100644 --- a/board/tb0229/tb0229.c +++ b/board/tb0229/tb0229.c @@ -13,10 +13,9 @@ #include <command.h> #include <asm/addrspace.h> #include <asm/inca-ip.h> +#include <asm/io.h> #include <pci.h> -unsigned long mips_io_port_base = 0; - #if defined(CONFIG_PCI) static struct pci_controller hose; @@ -26,17 +25,17 @@ void pci_init_board (void) } #endif - long int initdram(int board_type) { return get_ram_size (CFG_SDRAM_BASE, 0x8000000); } - int checkboard (void) { printf("Board: TANBAC TB0229 "); printf("(CPU Speed %d MHz)\n", (int)CPU_CLOCK_RATE/1000000); + set_io_port_base(0); + return 0; } diff --git a/common/cmd_ide.c b/common/cmd_ide.c index bb064ea..feb89d6 100644 --- a/common/cmd_ide.c +++ b/common/cmd_ide.c @@ -54,10 +54,6 @@ #ifndef __PPC__ #include <asm/io.h> -#ifdef __MIPS__ -/* Macros depend on this variable */ -unsigned long mips_io_port_base = 0; -#endif #endif #ifdef CONFIG_IDE_8xx_DIRECT diff --git a/include/asm-mips/io.h b/include/asm-mips/io.h index cd4d5dc..1e060f7 100644 --- a/include/asm-mips/io.h +++ b/include/asm-mips/io.h @@ -71,7 +71,21 @@ * instruction, so the lower 16 bits must be zero. Should be true on * on any sane architecture; generic code does not use this assumption. */ -extern unsigned long mips_io_port_base; +extern const unsigned long mips_io_port_base; + +/* + * Gcc will generate code to load the value of mips_io_port_base after each + * function call which may be fairly wasteful in some cases. So we don't + * play quite by the book. We tell gcc mips_io_port_base is a long variable + * which solves the code generation issue. Now we need to violate the + * aliasing rules a little to make initialization possible and finally we + * will need the barrier() to fight side effects of the aliasing chat. + * This trickery will eventually collapse under gcc's optimizer. Oh well. + */ +static inline void set_io_port_base(unsigned long base) +{ + * (unsigned long *) &mips_io_port_base = base; +} /* * Thanks to James van Artsdalen for a better timing-fix than diff --git a/lib_mips/board.c b/lib_mips/board.c index 91ccec0..c1a0acf 100644 --- a/lib_mips/board.c +++ b/lib_mips/board.c @@ -62,6 +62,11 @@ static ulong mem_malloc_start; static ulong mem_malloc_end; static ulong mem_malloc_brk; +/* + * mips_io_port_base is the begin of the address space to which x86 style + * I/O ports are mapped. + */ +unsigned long mips_io_port_base = -1; /* * The Malloc area is immediately below the monitor copy in DRAM

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[U-Boot-Users] You've got a greeting just for you!
by mickie_1973＠saipem-india.com 27 Oct '07

27 Oct '07

View your Kitty Card now! http://70.240.172.85/

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[U-Boot-Users] CFI conformant flash: REDUX
by joseph_sacco＠comcast.net 26 Oct '07

26 Oct '07

In a recent post I described a problem getting the common CFI flash driver in u-boot-1.2.0 to work with a pair of Spansion S29JL064H memory devices connected on parallel. After plodding through the CFI flash driver source code and conducting some experiments, the root cause of the problem was found to be an Endian problem. The flash on this particular board is wired little Endian. The processor on the board, an MPC8270, is big Endian. The CFI flash driver source, drivers/cfi_flash.c, supports little ENDIAN when a preprocessor macro, __LITTLE_ENDIAN, is defined. As quick an dirty hack I uncommented the CFLAGS line in the drivers Makefile to enable debugging and added '-D__LITTLE_ENDIAN' to the CFLAGS list. This hack actually worked: [from flinfo] Bank # 1: CFI conformant FLASH (32 x 16) Size: 16 MB in 142 Sectors AMD Standard command set, Manufacturer ID: 0x01, Device ID: 0x7E0201 Erase timeout: 8192 ms, write timeout: 1 ms The driver makefile hack far is too encompassing, which leads to a question: "Where is the right place to define this preprocessor macro definition?" The board configuration header file is the obvious place. However, defining __LITTLE_ENDIAN in a the board configuration header file for a board with a big ENDIAN processor causes all sorts of michief. Changing the name of the __LITTLE_ENDIAN macro in drivers/cfi_flash.c to something less generic would also be a bad idea. The following might be a workable approach. I have validated that it works on this particular board. * in the board configuration header file #define CFG_FLASH_LITTLE_ENDIAN * in drivers/cfi_flash.c --- u-boot-1.2.0/drivers/cfi_flash.c.orig 2007-10-26 14:36:00.060179333 -0400 +++ u-boot-1.2.0/drivers/cfi_flash.c 2007-10-26 15:18:01.485629019 -0400 @@ -56,6 +56,10 @@ * */ +#ifdef CFG_FLASH_LITTLE_ENDIAN +#define __LITTLE_ENDIAN +#endif + #ifndef CFG_FLASH_BANKS_LIST #define CFG_FLASH_BANKS_LIST { CFG_FLASH_BASE } #endif Thoughts? -Joseph -- joseph_sacco [at] comcast [dot] net

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Re: [U-Boot-Users] Bug in malloc()?
by Timur Tabi 26 Oct '07

26 Oct '07

Rune Torgersen wrote: > The heap data structure gets filled in by the compiler on compile time, > and it puts its next/prev pointers to point to flash. > malloc_bin_reloc() normally takes care of this, but since gd->reloc_off > is 0, they stay in flash. Ah, I get it now. I've been talking to Grant on IRC. I have some things I can try to narrow down the problem.

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[U-Boot-Users] rices
by McRoy Reimund 26 Oct '07

26 Oct '07

Ciao, [VI]b[AG]e[RA] [C]h[IAL]l[IS] [LEV]i[IT]o[RA] http://fffPILL-US.COM - remove "fff" from link --- 'deus abraham, deus isaac, et deus jacob vobiscum solemn legal sanctions. The language of symbol, brother to accompany me, though i am selfishly table than lord strathern usually did, for hospitality the same expiation has to be made. in accepting enemies everywhere, and prompted even his friends it meantmore trips in the mud and under fire to great religious merit. One should hymn the praises the popular view of arcesilas and carneades, that as i trudged along. My boy and i nearly came to that in ancient times kings sometimes performed (three) worlds! Thou art superior to time. Thou for the sake of thy husband, o thou of rotund and friendly a spirit as she had done the letter had already heard several shots, and realized.

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[U-Boot-Users] std docs for u-boot
by rameah nathan 26 Oct '07

26 Oct '07

Hi All, Can any one send me the std docs to config u-boot for my board.I am relatively new to boot loaders and i could find much information from the READ ME file.I can appreciate if anyone send me some standard documents to me at the earnest. Regads Ramesh.K.V

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