January 2007 - U-Boot

[U-Boot-Users] A problem with stack pointer on 8541
by Michael 14 Jan '07

14 Jan '07

Hi. I am at early stages of board bring-up. The board uses Freescale 8541 platform. On function call of one of the first functions, the stack pointer (stored in r1) gets corrupted. I tried a couple of things, but I still don't get what is going on there. Advise will be very much appreciated (what can be the problem and what should I check). See some details below: I use L1 data cache RAM for global data and stack, with the configuration described below. I use ELDK 4.0, U-boot 1.1.6. The problem I face is as following: When running board_init_f code, seems like the stack pointer (stored in r1) gets corrupted. When going through the for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr), after returning from board_early_init_f, the return address is some random value. I tried following: 1. change CFG_INIT_SP_OFFSET to CFG_INIT_SP_OFFSET - X for various X-s. Result: I get through the first (few) function(s), but eventually get the stack pointer corrupted again. 2. put the memset under comment. Result: I get through the first function, but don't get back from the next one. Board configuration: ************************************************ #define CONFIG_L1_INIT_RAM #define CFG_INIT_RAM_LOCK 1 #define CFG_INIT_RAM_ADDR 0xe4010000 /* Initial RAM address */ #define CFG_INIT_RAM_END 0x4000 /* End of used area in RAM */ #define CFG_L2_SRAM_BASE 0xDF000000 #define CFG_GBL_DATA_SIZE 128 /* num bytes initial data */ #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET *************************************************** Below is the relevant piece of code: ************************************************************* void board_init_f (ulong bootflag) { bd_t *bd; ulong len, addr, addr_sp; ulong *s; gd_t *id; init_fnc_t **init_fnc_ptr; #ifdef CONFIG_PRAM #endif /* Pointer is writable since we allocated a register for it */ gd = (gd_t *) (CFG_INIT_RAM_ADDR + CFG_GBL_DATA_OFFSET); /* compiler optimization barrier needed for GCC >= 3.4 */ __asm__ __volatile__("": : :"memory"); #if !defined(CONFIG_CPM2) /* Clear initial global data */ memset ((void *) gd, 0, sizeof (gd_t)); #endif for (init_fnc_ptr = init_sequence; *init_fnc_ptr; ++init_fnc_ptr) { if ((*init_fnc_ptr) () != 0) { hang (); } } ************************************************************* Thanks for your help

1 0

[U-Boot-Users] [PATCH] Fix PCI I/O space mapping on Freescale MPC85x0ADS
by Sergei Shtylyov 13 Jan '07

13 Jan '07

The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov <sshtylyov(a)ru.mvista.com> board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-) Index: u-boot/board/mpc8540ads/init.S =================================================================== --- u-boot.orig/board/mpc8540ads/init.S +++ u-boot/board/mpc8540ads/init.S @@ -260,8 +260,8 @@ tlb1_entry: #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* * Rapid IO at 0xc000_0000 for 512 M Index: u-boot/board/mpc8560ads/init.S =================================================================== --- u-boot.orig/board/mpc8560ads/init.S +++ u-boot/board/mpc8560ads/init.S @@ -260,8 +260,8 @@ tlb1_entry: #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* * Rapid IO at 0xc000_0000 for 512 M Index: u-boot/include/configs/MPC8540ADS.h =================================================================== --- u-boot.orig/include/configs/MPC8540ADS.h +++ u-boot/include/configs/MPC8540ADS.h @@ -330,13 +330,12 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ - -#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ Index: u-boot/include/configs/MPC8541CDS.h =================================================================== --- u-boot.orig/include/configs/MPC8541CDS.h +++ u-boot/include/configs/MPC8541CDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE Index: u-boot/include/configs/MPC8548CDS.h =================================================================== --- u-boot.orig/include/configs/MPC8548CDS.h +++ u-boot/include/configs/MPC8548CDS.h @@ -340,7 +340,7 @@ extern unsigned long get_clock_freq(void /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE Index: u-boot/include/configs/MPC8560ADS.h =================================================================== --- u-boot.orig/include/configs/MPC8560ADS.h +++ u-boot/include/configs/MPC8560ADS.h @@ -320,14 +320,14 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI)

5 11

[U-Boot-Users] [PATCH] Add support for PHY-less Ethernet connections
by Ben Warren 12 Jan '07

12 Jan '07

This allows connection of an Ethernet controller to a switch via RvMII or GMII. Initial driver implementation is on the TSEC. Signed-off-by: Ben Warren <bwarren(a)qstreams.com>

1 0

Re: [U-Boot-Users] Up-arrow and Down-arrow related Query
by Martijn de Gouw 12 Jan '07

12 Jan '07

Hi, > I need to know where the Up and Down arrow key press > functionalities are defined. Check common/main.c See also this patch http://article.gmane.org/gmane.comp.boot-loaders.u-boot/21829/match=hist ory Regards, Martijn de Gouw

3 2

Re: [U-Boot-Users] MPC83xx and PCI Bridges
by Russell McGuire 12 Jan '07

12 Jan '07

Kumar, So I placed a large amount of debug into the code, and found out that it gets to into the /drivers/pci.c file and the pci_hose_scan_bus function. Within that it seems to freeze at the first call to 'pci_hose_read_config_byte()' If I were to guess, I am betting you are right. A freeze like this is most likely due to an out of bounds memory access or something?? Just a guess. I am pretty much using the mpc8360emds.h header file for the PCI configuration as far as physical memory locations, and sizes, and BAT setups. The basic pci setup is being accomplished by the /board/mpc8360emds/pci.c Though I am borrowing this entire setup directory, and once I get things working will create a new board setup/config that is working for our system. We don't really have an mpc8360emds but just something similar. -Russ -----Original Message----- On Jan 11, 2007, at 3:25 PM, Russell McGuire wrote: u-boot should be capable of doing this w/o any issue. Where exactly does it hang, meaning do you see any output on console? I'm guessing you've got some config error/836x pci setup issue. - k > > -Russ > -----Original Message----- > From: Kumar Gala [mailto:galak@kernel.crashing.org] > Sent: Thursday, January 11, 2007 12:34 PM > To: rmcguire(a)videopresence.com > Cc: u-boot-users(a)lists.sourceforge.net > Subject: Re: [U-Boot-Users] MPC83xx and PCI Bridges > > > On Jan 11, 2007, at 9:30 AM, Russell McGuire wrote: > >> Does anyone know if U-Boot has existing PCI support for a PCI-to- >> PCI bridges? >> >> >> >> I have a Pericom PI7C7300A bridge chip hooked directly to the CPU >> to expand the number of PCI slots I can support. >> >> At the moment, if I compile in the PCI configuration, U-boot will >> freeze up during boot at pci_board_init(). >> >> >> >> Last thing printed is : >> >> "PCI 32Bit bus on PWC1 & PWC2 & PWC3" >> >> >> >> Using U-boot 1.1.6-dirty at the moment. > It does, what exactly are you looking for? I've done static setups > with multiple P2P bridges. > > - k

1 0

[U-Boot-Users] csb637 and csb937 breakout board: USB HOST SUPPLY VOLTAGE
by Christian Meißner 12 Jan '07

12 Jan '07

hallo i'm using a csb637 board with csb937 breakout. i have installed u-boot 1.1.6 as boot loader and by uploading a kernel version 2.6.17 i was able to start linux on this board. now i try to use the usb host, but the supply voltage of 5V are not present at host connector. by reading the manual i found out that a bit in at91rm92000 register has to be set to enable the supply (port b bit0). is there a way to enable this bit via u-boot? or is it implemented yet? best regards, christian meißner

1 0

[U-Boot-Users] porting u-boot on EP 852 M1.1 board
by yatin bhatia 12 Jan '07

12 Jan '07

hi ,I am new to u-boot. I have to port u-boot on embedded planet board EP 852T, but i donot find any board file regarding that. if anybody has ported u-boot on the EP 852T board,then please mail me the code of that one my email i.d. is : byatin(a)gmail.com

1 0

[U-Boot-Users] [patch] nicer version handling
by Mike Frysinger 12 Jan '07

12 Jan '07

this patch adds support to the setlocalversion script for u-boot in subversion repos and for 'localversion-' version files like the kernel ive also fixed up the version target in the toplevel Makefile so that it only updates the $(VERSION_FILE) as needed so that it wont wrongly trigger rebuilds in files that include version.h -mike

1 0

[U-Boot-Users] [patch] drop ppc default for size in MAKEALL
by Mike Frysinger 12 Jan '07

12 Jan '07

the host `size` should be sufficient for most cases when CROSS_COMPILE is not set when running MAKEALL ... better than getting a weird warning about ppc_8xx-size not being found -mike

1 0

[U-Boot-Users] MPC83xx and PCI Bridges
by Russell McGuire 11 Jan '07

11 Jan '07

Does anyone know if U-Boot has existing PCI support for a PCI-to-PCI bridges? I have a Pericom PI7C7300A bridge chip hooked directly to the CPU to expand the number of PCI slots I can support. At the moment, if I compile in the PCI configuration, U-boot will freeze up during boot at pci_board_init(). Last thing printed is : "PCI 32Bit bus on PWC1 & PWC2 & PWC3" Using U-boot 1.1.6-dirty at the moment. -Russ

2 1