June 2006 - U-Boot

[U-Boot-Users] [PATCH] Fix a typo in the file ./post/tests.c
by Aubrey Li 12 Jun '06

12 Jun '06

The patch fix a typo in the file ./post/tests.c Changelog entry: * Fix a typo in the file ./post/tests.c Patch by Aubrey.Li <aubrey.adi(a)gmail.com> Thanks, -Aubrey

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[U-Boot-Users] PROBLEM ABOUT PORTING U-BOOT-1.1.4 TO INTEL PXA255 BOARD
by Paradise 12 Jun '06

12 Jun '06

hi,u-boot-users I am trying to port u-boot-1.1.4 to my board,But i meet some problems. Main resources of the board: CPU : INTEL PXA255 400MHZ FLASH : INTEL TE28F128J3C150 32M SDRAM : SAMSUNG 64M Problem description : According to the Lubbock developing board and the manual of my board , i have modified some files of uboot and compiled correctly(u-boot.bin is about 108K). Because i have no any hardware emulator, so i write a simple program to trace the uboot running, i find it stop in board_init() function(/u-boot-1.1.4/board/xhyper255/xhyper255.c). int board_init (void) { DECLARE_GLOBAL_DATA_PTR; /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ /* arch number of cerf PXA Board */ gd->bd->bi_arch_number = MACH_TYPE_XHYPER255; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~It stops here!!!! /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; return(0); } The simple program writes as follows: asm("mov r11,#0x08300000;\ mov r0,#0x0F;\ strh r0,[r11];\ \ ldr r1,=0x40A00010;\ ldr r2,=0x40A0000C;\ mov r0,#0x0;\ str r0,[r1];\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ mov r0,#0x780000;\ str r0,[r2];\ \ ldr r1,=0x40A0001C;\ mov r0,#0x8;\ str r0,[r1];\ \ delay1:;\ ldr r10,=0x40A00014;\ ldr r0,[r10];\ tst r0,#0x8;\ beq delay1;\ ldr r11,=0x40A0001C;\ ldr r4,[r11];\ and r4,r4,#0x07;\ str r4,[r11];\ \ str r0,[r10];\ \ ldr r1,=0x40A00010;\ ldr r2,=0x40A0000C;\ mov r0,#0x0;\ str r0,[r1];\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ mov r0,#0x780000;\ str r0,[r2];\ \ ldr r1,=0x40A0001C;\ mov r0,#0x8;\ str r0,[r1];\ \ delay2:;\ ldr r10,=0x40A00014;\ ldr r0,[r10];\ tst r0,#0x8;\ beq delay2;\ \ ldr r11,=0x40A0001C;\ ldr r4,[r11];\ and r4,r4,#0x07;\ str r4,[r11];\ \ str r0,[r10]"); Appreciate any help. THANKS 　　　　　　　　Paradise 　　　　　　　　scut.paradise(a)gmail.com 　　　　　　　　　　2006-06-08

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[U-Boot-Users] HELP ABOUT PORTING U-BOOT-1.1.4 TO INTEL PXA255 BOARD
by Paradise 12 Jun '06

12 Jun '06

hi,u-boot-users I am trying to port u-boot-1.1.4 to my board,But i meet some problems. Main resources of the board: CPU : INTEL PXA255 400MHZ FLASH : INTEL TE28F128J3C150 32M SDRAM : SAMSUNG 64M Problem description : According to the Lubbock developing board and the manual of my board , i have modified some files of uboot and compiled correctly(u-boot.bin is about 108K). Because i have no any hardware emulator, so i write a simple program to trace the uboot running, i find it stop in board_init() function(/u-boot-1.1.4/board/xhyper255/xhyper255.c). int board_init (void) { DECLARE_GLOBAL_DATA_PTR; /* memory and cpu-speed are setup before relocation */ /* so we do _nothing_ here */ /* arch number of cerf PXA Board */ gd->bd->bi_arch_number = MACH_TYPE_XHYPER255; ~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~~It stops here!!!! /* adress of boot parameters */ gd->bd->bi_boot_params = 0xa0000100; return(0); } The simple program writes as follows: asm("mov r11,#0x08300000;\ mov r0,#0x0F;\ strh r0,[r11];\ \ ldr r1,=0x40A00010;\ ldr r2,=0x40A0000C;\ mov r0,#0x0;\ str r0,[r1];\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ mov r0,#0x780000;\ str r0,[r2];\ \ ldr r1,=0x40A0001C;\ mov r0,#0x8;\ str r0,[r1];\ \ delay1:;\ ldr r10,=0x40A00014;\ ldr r0,[r10];\ tst r0,#0x8;\ beq delay1;\ ldr r11,=0x40A0001C;\ ldr r4,[r11];\ and r4,r4,#0x07;\ str r4,[r11];\ \ str r0,[r10];\ \ ldr r1,=0x40A00010;\ ldr r2,=0x40A0000C;\ mov r0,#0x0;\ str r0,[r1];\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ nop;\ mov r0,#0x780000;\ str r0,[r2];\ \ ldr r1,=0x40A0001C;\ mov r0,#0x8;\ str r0,[r1];\ \ delay2:;\ ldr r10,=0x40A00014;\ ldr r0,[r10];\ tst r0,#0x8;\ beq delay2;\ \ ldr r11,=0x40A0001C;\ ldr r4,[r11];\ and r4,r4,#0x07;\ str r4,[r11];\ \ str r0,[r10]"); Appreciate any help. THANKS 　　　　　　　　Paradise 　　　　　　　　scut.paradise(a)gmail.com 　　　　　　　　　　2006-06-08

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[U-Boot-Users] how to mount ramdisk?
by cpjzjut 11 Jun '06

11 Jun '06

hi,all when mount ramdisk there throws a exception,can anyone tell me why? thank you. best regards bootargs=initrd 30800000 20000 root =/dev/ram0 init=/linuxrc console=ttyS0 NET4: Linux TCP/IP 1.0 for NET4.0 IP Protocols: ICMP, UDP, TCP, IGMP IP: routing cache hash table of 512 buckets, 4Kbytes TCP: Hash tables configured (established 4096 bind 4096) NET4: Unix domain sockets 1.0/SMP for Linux NET4.0. NetWinder Floating Point Emulator V0.95 (c) 1998-1999 Rebel.com Root-NFS: No NFS server available, giving up. VFS: Unable to mount root fs via NFS, trying floppy. request_module[block-major-2]: Root fs not mounted VFS: Cannot open root device "" or 02:00 Please append a correct "root=" boot option Kernel panic: VFS: Unable to mount root fs on 02:00

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[U-Boot-Users] Moving uboot to parallel flash trouble
by Roman Kolesnikov 11 Jun '06

11 Jun '06

I have a board similra to at91rm9200ek. I load uboot into ram and execute it. I copy uboot into flash and reboot. However, when I reboot, I experience a crash at the end. It only happens, after I press enter. I think that my environment variables get overwritten, but they should not have. I think it is my environment variables that cause my error. Please advice. Here is my sequence: Load uboot-1.1.2 into ram and execute it. Load uboot-1.1.4 into flash Reboot I get prompt and hit enter, then uboot 1.1.4 crashes. Please advice, Roman

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[U-Boot-Users] Intel 28F256J3C
by xuxian 10 Jun '06

10 Jun '06

Hi all, I try to make u-boot work on my board which is similar with OMAP5912OSK. But the flash we using is 28F256J3C. I have already added 28F256J3C's manufacture code and device id in the proper position of u-boot. But there are several questions I can't figure out. 1) How many sectors does 28F256J3C have? 256 or 259? How to divide 259 sectors in OSK which have two 16M flash. 2) What's the meaning of "Internal FLASH identification codes" in flash.h file. It defines like this: #define FLASH_28F320J3A 0x00C0 /* INTEL 28F320J3A ( 32M = 128K x 32)*/ #define FLASH_28F640J3A 0x00C2 /* INTEL 28F640J3A ( 64M = 128K x 64)*/ #define FLASH_28F128J3A 0x00C4 /* INTEL 28F128J3A (128M = 128K x 128)*/ But I can't find this kind of information on 28F256J3C's datasheet. And what the code should be in 28F256J3C? 3) Should I modify the read manufacture and device id command? I have some trouble with the following codes: /* Write auto select command: read Manufacturer ID */ addr[0x5555] = (FPW) 0x00AA00AA; addr[0x2AAA] = (FPW) 0x00550055; addr[0x5555] = (FPW) 0x00900090; Sorry for my English. Any help will be appreciated. Thank in advance. Best Regard, xuxian

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Re: [U-Boot-Users] Using at91 with a different parallel flash, request for help
by Roman Kolesnikov 10 Jun '06

10 Jun '06

Hello, The only difference I see is in the CFI address 13h becomes 3 for my chip instead of 2 for at91rm9200ek board parallel flash. I am not sure what altogether must be changed. As always with me, the experience always comes after the need. Thanks Roman Message: 8 Date: Fri, 09 Jun 2006 20:18:25 -0700 From: Roman Kolesnikov <romank(a)randrlabs.com> Subject: [U-Boot-Users] Using at91 with a different parallel flash request for help To: u-boot-users(a)lists.sourceforge.net Message-ID: <448A3A01.4060209(a)randrlabs.com> Content-Type: text/plain; charset=ISO-8859-1; format=flowed Hello, I am using a similar to at91rm9200ek board. The board is very similar to that of at91rm9200ek, except that the framebuffer is off and few other minor changes. I am also using an atmel parallel flash. It is 8 MB = 4M x16 by Atmel at49bv6416c. When I boot u boot 1.1.4 my sdram shows up (all 32MB) but my bank 1 shows 0. I am reading the board setup files and flash.c, but I am not shure what specifically to look for. Please advice, Roman

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[U-Boot-Users] Help U-Boot NFS filesystem.
by muqiyong 10 Jun '06

10 Jun '06

Hi all, I try to mount NFS filesystem onto my AT91RM9200DK board, But the eth0 device failed, from the boot message it looks that I didn't set the MAC addr: at91_ether: Your bootloader did not configure a MAC address. eth0: Link now 100-FullDuplex eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:00:00:00:00:00) ---------------------------------------------------------------------------- But I've set it in the U-Boot env: ---------------------------------------------------------------------------- U-Boot> printenv bootdelay=3 baudrate=115200 serverip=192.168.0.182 ipaddr=192.168.0.66 netmask=255.255.255.0 ethaddr=00:10:ec:00:87:73 bootargs=root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipaddr}:${serveri p}:${gatewayip}:${netmask}:${hostname}::off rootpath=/opt/eldk_arm/arm hostname=mqy gatewayip=192.168.0.182 bootfile=/tftpboot/uImage bootcmd=bootm 10080000 ok=ok stdin=serial stdout=serial stderr=serial Environment size: 403/65532 bytes U-Boot> --------------------------------------------------------------------------- And this is full boot message ---------------------------------------------------------------------------- - U-Boot 1.1.4 (May 29 2006 - 18:53:58) DRAM: 32 MB Atmel: ATM_ID_BV322DT (32Mbit) Flash: 4 MB In: serial Out: serial Err: serial U-Boot 1.1.4 (May 29 2006 - 18:53:58) DRAM: 32 MB Atmel: ATM_ID_BV322DT (32Mbit) Flash: 4 MB In: serial Out: serial Err: serial Hit any key to stop autoboot: 0 ## Booting image at 10080000 ... Image Name: Linux-2.6.16 Image Type: ARM Linux Kernel Image (uncompressed) Data Size: 1103380 Bytes = 1.1 MB Load Address: 20008000 Entry Point: 20008000 Verifying Checksum ... OK OK Starting kernel ... Uncompressing Linux............................................................. ............. done, booting the kernel. Linux version 2.6.16 (root@second) (gcc version 4.0.0 (DENX ELDK 4.0 4.0.0)) #16 Thu Jun 8 03:40:10 AQTT 2006 CPU: ARM920Tid(wb) [41129200] revision 0 (ARMv4T) Machine: Atmel AT91RM9200-DK Memory policy: ECC disabled, Data cache writeback Clocks: CPU 179 MHz, master 59 MHz, main 18.432 MHz CPU0: D VIVT write-back cache CPU0: I cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets CPU0: D cache: 16384 bytes, associativity 64, 32 byte lines, 8 sets Built 1 zonelists Kernel command line: root=/dev/nfs rw nfsroot=${serverip}:${rootpath} ip=${ipadd r}:${serverip}:${gatewayip}:${netmask}:${hostname}::off AT91: 128 gpio irqs in 4 banks PID hash table entries: 256 (order: 8, 4096 bytes) Console: colour dummy device 80x30 Dentry cache hash table entries: 8192 (order: 3, 32768 bytes) Inode-cache hash table entries: 4096 (order: 2, 16384 bytes) Memory: 32MB = 32MB total Memory: 30044KB available (1844K code, 402K data, 92K init) Mount-cache hash table entries: 512 CPU: Testing write buffer coherency: ok NET: Registered protocol family 16 usbcore: registered new driver usbfs usbcore: registered new driver hub NetWinder Floating Point Emulator V0.97 (double precision) Initializing Cryptographic API io scheduler noop registered io scheduler anticipatory registered (default) AT91 Real Time Clock driver. AT91 SPI driver loaded AT91 Watchdog Timer enabled (5 seconds, nowayout=1) at91_usart.0: ttyS0 at MMIO 0xfefff200 (irq = 1) is a AT91_SERIAL at91_usart.1: ttyS1 at MMIO 0xfffc4000 (irq = 7) is a AT91_SERIAL RAMDISK driver initialized: 16 RAM disks of 32768K size 1024 blocksize at91_ether: Your bootloader did not configure a MAC address. eth0: Link now 100-FullDuplex eth0: AT91 ethernet at 0xfefbc000 int=24 100-FullDuplex (00:00:00:00:00:00) eth0: Davicom 9196 PHY (Copper) physmap flash device: 200000 at 10000000 phys_mapped_flash: Found 1 x16 devices at 0x0 in 16-bit bank Amd/Fujitsu Extended Query Table at 0x0041 phys_mapped_flash: CFI does not contain boot bank location. Assuming top. number of CFI chips: 1 cfi_cmdset_0002: Disabling erase-suspend-program due to code brokenness. RedBoot partition parsing not available at91_cf: irqs det #64, io #0 at91_ohci at91_ohci: AT91 OHCI at91_ohci at91_ohci: new USB bus registered, assigned bus number 1 at91_ohci at91_ohci: irq 23, io mem 0x00300000 usb usb1: Product: AT91 OHCI usb usb1: Manufacturer: Linux 2.6.16 ohci_hcd usb usb1: SerialNumber: at91 usb usb1: configuration #1 chosen from 1 choice hub 1-0:1.0: USB hub found hub 1-0:1.0: 2 ports detected udc: at91_udc version 8 March 2005 mice: PS/2 mouse device common for all mice i2c /dev entries driver at91_i2c at91_i2c: AT91 i2c bus driver. NET: Registered protocol family 2 IP route cache hash table entries: 512 (order: -1, 2048 bytes) TCP established hash table entries: 2048 (order: 1, 8192 bytes) TCP bind hash table entries: 2048 (order: 1, 8192 bytes) TCP: Hash tables configured (established 2048 bind 2048) TCP reno registered TCP bic registered NET: Registered protocol family 1 NET: Registered protocol family 17 IP-Config: Failed to open eth0 IP-Config: No network devices available. Root-NFS: No NFS server available, giving up. VFS: Unable to mount root fs via NFS, trying floppy. VFS: Cannot open root device "nfs" or unknown-block(2,0) Please append a correct "root=" boot option Kernel panic - not syncing: VFS: Unable to mount root fs on unknown-block(2,0) Thanks a lot! KylongMu

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[U-Boot-Users] Using at91 with a different parallel flash request for help
by Roman Kolesnikov 10 Jun '06

10 Jun '06

Hello, I am using a similar to at91rm9200ek board. The board is very similar to that of at91rm9200ek, except that the framebuffer is off and few other minor changes. I am also using an atmel parallel flash. It is 8 MB = 4M x16 by Atmel at49bv6416c. When I boot u boot 1.1.4 my sdram shows up (all 32MB) but my bank 1 shows 0. I am reading the board setup files and flash.c, but I am not shure what specifically to look for. Please advice, Roman

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[U-Boot-Users] patch: Nios-II boards EP1C20, EP1S10 and EP1S40 part 2
by Scott McNutt 10 Jun '06

10 Jun '06

Part 2: Add Altera Nios-II boards EP1C20, EP1S10 and EP1S40 Regards, --Scott diff -Naurb u-boot-current/board/altera/ep1s40/Makefile u-boot-new/board/altera/ep1s40/Makefile --- u-boot-current/board/altera/ep1s40/Makefile 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/board/altera/ep1s40/Makefile 2005-08-11 12:10:57.000000000 -0400 @@ -0,0 +1,50 @@ +# +# (C) Copyright 2001-2004 +# Wolfgang Denk, DENX Software Engineering, wd(a)denx.de. +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +include $(TOPDIR)/config.mk + +LIB = lib$(BOARD).a + +COMOBJS := ../common/AMDLV065D.o ../common/epled.o + +OBJS := $(BOARD).o $(COMOBJS) + +SOBJS = + +$(LIB): $(OBJS) $(SOBJS) + $(AR) crv $@ $^ + +clean: + rm -f $(SOBJS) $(OBJS) + +distclean: clean + rm -f $(LIB) core *.bak .depend + +######################################################################### + +.depend: Makefile $(SOBJS:.o=.S) $(OBJS:.o=.c) + $(CC) -M $(CPPFLAGS) $(SOBJS:.o=.S) $(OBJS:.o=.c) > $@ + +-include .depend + +######################################################################### diff -Naurb u-boot-current/board/altera/ep1s40/config.mk u-boot-new/board/altera/ep1s40/config.mk --- u-boot-current/board/altera/ep1s40/config.mk 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/board/altera/ep1s40/config.mk 2005-08-11 12:09:47.000000000 -0400 @@ -0,0 +1,31 @@ +# +# (C) Copyright 2005, Psyent Corporation <www.psyent.com> +# Scott McNutt <smcnutt(a)psyent.com> +# +# See file CREDITS for list of people who contributed to this +# project. +# +# This program is free software; you can redistribute it and/or +# modify it under the terms of the GNU General Public License as +# published by the Free Software Foundation; either version 2 of +# the License, or (at your option) any later version. +# +# This program is distributed in the hope that it will be useful, +# but WITHOUT ANY WARRANTY; without even the implied warranty of +# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the +# GNU General Public License for more details. +# +# You should have received a copy of the GNU General Public License +# along with this program; if not, write to the Free Software +# Foundation, Inc., 59 Temple Place, Suite 330, Boston, +# MA 02111-1307 USA +# + +TEXT_BASE = 0x01fc0000 + +PLATFORM_CPPFLAGS += -mno-hw-div -mno-hw-mul +PLATFORM_CPPFLAGS += -I$(TOPDIR)/board/$(VENDOR)/include + +ifeq ($(debug),1) +PLATFORM_CPPFLAGS += -DDEBUG +endif diff -Naurb u-boot-current/board/altera/ep1s40/ep1s40.c u-boot-new/board/altera/ep1s40/ep1s40.c --- u-boot-current/board/altera/ep1s40/ep1s40.c 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/board/altera/ep1s40/ep1s40.c 2005-08-11 13:16:53.000000000 -0400 @@ -0,0 +1,35 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#include <common.h> + +int checkboard (void) +{ + puts ("BOARD : Altera EP-1S40\n"); + return 0; +} + +long int initdram (int board_type) +{ + return (0); +} diff -Naurb u-boot-current/board/altera/ep1s40/u-boot.lds u-boot-new/board/altera/ep1s40/u-boot.lds --- u-boot-current/board/altera/ep1s40/u-boot.lds 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/board/altera/ep1s40/u-boot.lds 2004-10-10 17:27:32.000000000 -0400 @@ -0,0 +1,136 @@ +/* + * (C) Copyright 2004, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + + +OUTPUT_FORMAT("elf32-littlenios2") +OUTPUT_ARCH(nios2) +ENTRY(_start) + +SECTIONS +{ + .text : + { + cpu/nios2/start.o (.text) + *(.text) + *(.text.*) + *(.gnu.linkonce.t*) + *(.rodata) + *(.rodata.*) + *(.gnu.linkonce.r*) + } + . = ALIGN (4); + _etext = .; + PROVIDE (etext = .); + + /* CMD TABLE - sandwich this in between text and data so + * the initialization code relocates the command table as + * well -- admittedly, this is just pure laziness ;-) + */ + __u_boot_cmd_start = .; + .u_boot_cmd : + { + *(.u_boot_cmd) + } + . = ALIGN(4); + __u_boot_cmd_end = .; + + /* INIT DATA sections - "Small" data (see the gcc -G option) + * is always gp-relative. Here we make all init data sections + * adjacent to simplify the startup code -- and provide + * the global pointer for gp-relative access. + */ + _data = .; + .data : + { + *(.data) + *(.data.*) + *(.gnu.linkonce.d*) + } + + . = ALIGN(16); + _gp = .; /* Global pointer addr */ + PROVIDE (gp = .); + + .sdata : + { + *(.sdata) + *(.sdata.*) + *(.gnu.linkonce.s.*) + } + . = ALIGN(4); + + _edata = .; + PROVIDE (edata = .); + + /* UNINIT DATA - Small uninitialized data is first so it's + * adjacent to sdata and can be referenced via gp. The normal + * bss follows. We keep it adjacent to simplify init code. + */ + __bss_start = .; + .sbss : + { + *(.sbss) + *(.sbss.*) + *(.gnu.linkonce.sb.*) + *(.scommon) + } + . = ALIGN(4); + .bss : + { + *(.bss) + *(.bss.*) + *(.dynbss) + *(COMMON) + *(.scommon) + } + . = ALIGN(4); + _end = .; + PROVIDE (end = .); + + /* DEBUG -- symbol table, string table, etc. etc. + */ + .stab 0 : { *(.stab) } + .stabstr 0 : { *(.stabstr) } + .stab.excl 0 : { *(.stab.excl) } + .stab.exclstr 0 : { *(.stab.exclstr) } + .stab.index 0 : { *(.stab.index) } + .stab.indexstr 0 : { *(.stab.indexstr) } + .comment 0 : { *(.comment) } + .debug 0 : { *(.debug) } + .line 0 : { *(.line) } + .debug_srcinfo 0 : { *(.debug_srcinfo) } + .debug_sfnames 0 : { *(.debug_sfnames) } + .debug_aranges 0 : { *(.debug_aranges) } + .debug_pubnames 0 : { *(.debug_pubnames) } + .debug_info 0 : { *(.debug_info) } + .debug_abbrev 0 : { *(.debug_abbrev) } + .debug_line 0 : { *(.debug_line) } + .debug_frame 0 : { *(.debug_frame) } + .debug_str 0 : { *(.debug_str) } + .debug_loc 0 : { *(.debug_loc) } + .debug_macinfo 0 : { *(.debug_macinfo) } + .debug_weaknames 0 : { *(.debug_weaknames) } + .debug_funcnames 0 : { *(.debug_funcnames) } + .debug_typenames 0 : { *(.debug_typenames) } + .debug_varnames 0 : { *(.debug_varnames) } +} diff -Naurb u-boot-current/include/configs/EP1C20.h u-boot-new/include/configs/EP1C20.h --- u-boot-current/include/configs/EP1C20.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/include/configs/EP1C20.h 2005-08-11 12:18:18.000000000 -0400 @@ -0,0 +1,199 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_EP1C20 1 /* EP1C20 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ +#define CONFIG_BOARD_EARLY_INIT_F 1 /* enable early board-spec. init*/ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ +#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB (only 1M mapped)*/ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 128k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 128*1024) + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ +#define CFG_FLASH_WORD_SIZE unsigned char /* flash word size */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_RESET_ADDR, since we assume the monitor is stored at the + * reset address, no? This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_RESET_ADDR + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * EPCS Device -- wne CFG_NIOS_EPCSBASE is defined code/commands for + * epcs device access is enabled. The base address is the epcs + * _register_ base address, NOT THE ADDRESS OF THE MEMORY BLOCK. + * The register base is currently at offset 0x600 from the memory base. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_EPCSBASE 0x02100200 /* EPCS register base */ + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * STATUS LED -- Provides a simple blinking led. For Nios2 each board + * must implement its own led routines -- leds are, after all, + * board-specific, no? + *----------------------------------------------------------------------*/ +#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_STATUS_LED /* Enable status driver */ + +#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_STATE 1 /* Blinking */ +#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ + +/*------------------------------------------------------------------------ + * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... + * and really doesn't need any additional clutter. So I choose the lazy + * way out to avoid changes there -- define the base address to ensure + * cache bypass so there's no need to monkey with inx/outx macros. + *----------------------------------------------------------------------*/ +#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include <cmd_confdefs.h> + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#endif /* __CONFIG_H */ diff -Naurb u-boot-current/include/configs/EP1S10.h u-boot-new/include/configs/EP1S10.h --- u-boot-current/include/configs/EP1S10.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/include/configs/EP1S10.h 2005-08-11 13:36:23.000000000 -0400 @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_EP1S10 1 /* EP1S10 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ +#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom + * of flash memory. This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * EPCS Device -- None for stratix. + *----------------------------------------------------------------------*/ +#undef CFG_NIOS_EPCSBASE + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * STATUS LED -- Provides a simple blinking led. For Nios2 each board + * must implement its own led routines -- since leds are board-specific. + *----------------------------------------------------------------------*/ +#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_STATUS_LED /* Enable status driver */ + +#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_STATE 1 /* Blinking */ +#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ + +/*------------------------------------------------------------------------ + * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... + * and really doesn't need any additional clutter. So I choose the lazy + * way out to avoid changes there -- define the base address to ensure + * cache bypass so there's no need to monkey with inx/outx macros. + *----------------------------------------------------------------------*/ +#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include <cmd_confdefs.h> + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#endif /* __CONFIG_H */ diff -Naurb u-boot-current/include/configs/EP1S40.h u-boot-new/include/configs/EP1S40.h --- u-boot-current/include/configs/EP1S40.h 1969-12-31 19:00:00.000000000 -0500 +++ u-boot-new/include/configs/EP1S40.h 2005-08-11 13:28:35.000000000 -0400 @@ -0,0 +1,193 @@ +/* + * (C) Copyright 2005, Psyent Corporation <www.psyent.com> + * Scott McNutt <smcnutt(a)psyent.com> + * + * See file CREDITS for list of people who contributed to this + * project. + * + * This program is free software; you can redistribute it and/or + * modify it under the terms of the GNU General Public License as + * published by the Free Software Foundation; either version 2 of + * the License, or (at your option) any later version. + * + * This program is distributed in the hope that it will be useful, + * but WITHOUT ANY WARRANTY; without even the implied warranty of + * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the + * GNU General Public License for more details. + * + * You should have received a copy of the GNU General Public License + * along with this program; if not, write to the Free Software + * Foundation, Inc., 59 Temple Place, Suite 330, Boston, + * MA 02111-1307 USA + */ + +#ifndef __CONFIG_H +#define __CONFIG_H + +/*------------------------------------------------------------------------ + * BOARD/CPU + *----------------------------------------------------------------------*/ +#define CONFIG_EP1S40 1 /* EP1S40 board */ +#define CONFIG_SYS_CLK_FREQ 50000000 /* 50 MHz core clk */ + +#define CFG_RESET_ADDR 0x00000000 /* Hard-reset address */ +#define CFG_EXCEPTION_ADDR 0x01000020 /* Exception entry point*/ +#define CFG_NIOS_SYSID_BASE 0x021208b8 /* System id address */ + +/*------------------------------------------------------------------------ + * CACHE -- the following will support II/s and II/f. The II/s does not + * have dcache, so the cache instructions will behave as NOPs. + *----------------------------------------------------------------------*/ +#define CFG_ICACHE_SIZE 4096 /* 4 KByte total */ +#define CFG_ICACHELINE_SIZE 32 /* 32 bytes/line */ +#define CFG_DCACHE_SIZE 2048 /* 2 KByte (II/f) */ +#define CFG_DCACHELINE_SIZE 4 /* 4 bytes/line (II/f) */ + +/*------------------------------------------------------------------------ + * MEMORY BASE ADDRESSES + *----------------------------------------------------------------------*/ +#define CFG_FLASH_BASE 0x00000000 /* FLASH base addr */ +#define CFG_FLASH_SIZE 0x00800000 /* 8 MByte */ +#define CFG_SDRAM_BASE 0x01000000 /* SDRAM base addr */ +#define CFG_SDRAM_SIZE 0x01000000 /* 16 MByte */ +#define CFG_SRAM_BASE 0x02000000 /* SRAM base addr */ +#define CFG_SRAM_SIZE 0x00100000 /* 1 MB */ + +/*------------------------------------------------------------------------ + * MEMORY ORGANIZATION + * -Monitor at top. + * -The heap is placed below the monitor. + * -Global data is placed below the heap. + * -The stack is placed below global data (&grows down). + *----------------------------------------------------------------------*/ +#define CFG_MONITOR_LEN (256 * 1024) /* Reserve 256k */ +#define CFG_GBL_DATA_SIZE 128 /* Global data size rsvd*/ +#define CFG_MALLOC_LEN (CFG_ENV_SIZE + 256*1024) /* 256k heap */ + +#define CFG_MONITOR_BASE TEXT_BASE +#define CFG_MALLOC_BASE (CFG_MONITOR_BASE - CFG_MALLOC_LEN) +#define CFG_GBL_DATA_OFFSET (CFG_MALLOC_BASE - CFG_GBL_DATA_SIZE) +#define CFG_INIT_SP CFG_GBL_DATA_OFFSET + +/*------------------------------------------------------------------------ + * FLASH (AM29LV065D) + *----------------------------------------------------------------------*/ +#define CFG_MAX_FLASH_SECT 128 /* Max # sects per bank */ +#define CFG_MAX_FLASH_BANKS 1 /* Max # of flash banks */ +#define CFG_FLASH_ERASE_TOUT 8000 /* Erase timeout (msec) */ +#define CFG_FLASH_WRITE_TOUT 100 /* Write timeout (msec) */ + +/*------------------------------------------------------------------------ + * ENVIRONMENT -- Put environment in sector CFG_MONITOR_LEN above + * CFG_FLASH_BASE, since we assume that u-boot is stored at the bottom + * of flash memory. This will keep the environment in user region + * of flash. NOTE: the monitor length must be multiple of sector size + * (which is common practice). + *----------------------------------------------------------------------*/ +#define CFG_ENV_IS_IN_FLASH 1 /* Environment in flash */ +#define CFG_ENV_SIZE (64 * 1024) /* 64 KByte (1 sector) */ +#define CONFIG_ENV_OVERWRITE /* Serial change Ok */ +#define CFG_ENV_ADDR (CFG_FLASH_BASE + CFG_MONITOR_LEN) + +/*------------------------------------------------------------------------ + * CONSOLE + *----------------------------------------------------------------------*/ +#if defined(CONFIG_CONSOLE_JTAG) +#define CFG_NIOS_CONSOLE 0x021208b0 /* JTAG UART base addr */ +#else +#define CFG_NIOS_CONSOLE 0x02120840 /* UART base addr */ +#endif + +#define CFG_NIOS_FIXEDBAUD 1 /* Baudrate is fixed */ +#define CONFIG_BAUDRATE 115200 /* Initial baudrate */ +#define CFG_BAUDRATE_TABLE {115200} /* It's fixed ;-) */ + +#define CFG_CONSOLE_INFO_QUIET 1 /* Suppress console info*/ + +/*------------------------------------------------------------------------ + * EPCS Device -- None for stratix. + *----------------------------------------------------------------------*/ +#undef CFG_NIOS_EPCSBASE + +/*------------------------------------------------------------------------ + * DEBUG + *----------------------------------------------------------------------*/ +#undef CONFIG_ROM_STUBS /* Stubs not in ROM */ + +/*------------------------------------------------------------------------ + * TIMEBASE -- + * + * The high res timer defaults to 1 msec. Since it includes the period + * registers, we can slow it down to 10 msec using TMRCNT. If the default + * period is acceptable, TMRCNT can be left undefined. + *----------------------------------------------------------------------*/ +#define CFG_NIOS_TMRBASE 0x02120820 /* Tick timer base addr */ +#define CFG_NIOS_TMRIRQ 3 /* Timer IRQ num */ +#define CFG_NIOS_TMRMS 10 /* 10 msec per tick */ +#define CFG_NIOS_TMRCNT (CFG_NIOS_TMRMS * (CONFIG_SYS_CLK_FREQ/1000)) +#define CFG_HZ (CONFIG_SYS_CLK_FREQ/(CFG_NIOS_TMRCNT + 1)) + +/*------------------------------------------------------------------------ + * STATUS LED -- Provides a simple blinking led. For Nios2 each board + * must implement its own led routines -- since leds are board-specific. + *----------------------------------------------------------------------*/ +#define CFG_LEDPIO_ADDR 0x02120870 /* LED PIO base addr */ +#define CONFIG_STATUS_LED /* Enable status driver */ + +#define STATUS_LED_BIT 1 /* Bit-0 on PIO */ +#define STATUS_LED_STATE 1 /* Blinking */ +#define STATUS_LED_PERIOD (500/CFG_NIOS_TMRMS) /* Every 500 msec */ + +/*------------------------------------------------------------------------ + * ETHERNET -- The header file for the SMC91111 driver hurts my eyes ... + * and really doesn't need any additional clutter. So I choose the lazy + * way out to avoid changes there -- define the base address to ensure + * cache bypass so there's no need to monkey with inx/outx macros. + *----------------------------------------------------------------------*/ +#define CONFIG_SMC91111_BASE 0x82110300 /* Base addr (bypass) */ +#define CONFIG_DRIVER_SMC91111 /* Using SMC91c111 */ +#undef CONFIG_SMC91111_EXT_PHY /* Internal PHY */ +#define CONFIG_SMC_USE_32_BIT /* 32-bit interface */ + +#define CONFIG_ETHADDR 08:00:3e:26:0a:5b +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 192.168.2.21 +#define CONFIG_SERVERIP 192.168.2.16 + +/*------------------------------------------------------------------------ + * COMMANDS + *----------------------------------------------------------------------*/ +#define CONFIG_COMMANDS (CFG_CMD_BDI | \ + CFG_CMD_DHCP | \ + CFG_CMD_ECHO | \ + CFG_CMD_ENV | \ + CFG_CMD_FLASH | \ + CFG_CMD_IMI | \ + CFG_CMD_IRQ | \ + CFG_CMD_LOADS | \ + CFG_CMD_LOADB | \ + CFG_CMD_MEMORY | \ + CFG_CMD_MISC | \ + CFG_CMD_NET | \ + CFG_CMD_PING | \ + CFG_CMD_RUN | \ + CFG_CMD_SAVES ) +#include <cmd_confdefs.h> + +/*------------------------------------------------------------------------ + * MISC + *----------------------------------------------------------------------*/ +#define CFG_LONGHELP /* Provide extended help*/ +#define CFG_PROMPT "==> " /* Command prompt */ +#define CFG_CBSIZE 256 /* Console I/O buf size */ +#define CFG_MAXARGS 16 /* Max command args */ +#define CFG_BARGSIZE CFG_CBSIZE /* Boot arg buf size */ +#define CFG_PBSIZE (CFG_CBSIZE+sizeof(CFG_PROMPT)+16) /* Print buf size */ +#define CFG_LOAD_ADDR CFG_SDRAM_BASE /* Default load address */ +#define CFG_MEMTEST_START CFG_SDRAM_BASE /* Start addr for test */ +#define CFG_MEMTEST_END CFG_INIT_SP - 0x00020000 + +#define CFG_HUSH_PARSER +#define CFG_PROMPT_HUSH_PS2 "> " + +#endif /* __CONFIG_H */

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