May 2006 - U-Boot

[U-Boot-Users] [PATCH] Update board NetStar
by Ladislav Michl 22 Jul '06

22 Jul '06

Just to sync my local tree with public one. Generated against testing-NAND branch. Signed-off-by: Ladislav Michl <ladis(a)linux-mips.org> CHANGELOG: * Update board NetStar Patch by Ladislav Michl, 3 Nov 2005 diff --git a/board/netstar/crcek.S b/board/netstar/crcek.S --- a/board/netstar/crcek.S +++ b/board/netstar/crcek.S @@ -13,6 +13,7 @@ * u32 - crc32 */ +#include <config.h> #include "crcek.h" /** @@ -39,7 +40,7 @@ .macro crcuj, offset, size mov r0, #0 ldr r1, \offset - ldr r2, [r1] + ldr r2, [r1], #4 cmp r2, r0 @ no data, no problem beq 2f tst r2, #3 @ unaligned size @@ -47,7 +48,6 @@ ldr r3, \size cmp r2, r3 @ bogus size bhi 2f - add r1, r1, #4 do_crc32 ldr r1, [r1] 2: @@ -55,16 +55,71 @@ .endm .macro wait, reg - mov \reg, #0x1000 + mov \reg, #0x100000 3: subs \reg, \reg, #0x1 bne 3b - .endm + .text .globl crcek crcek: - b crc2_bad + /* Enable I-cache */ + mrc p15, 0, r1, c0, c0, 0 @ read C15 ID register + mrc p15, 0, r1, c0, c0, 1 @ read C15 Cache information register + mrc p15, 0, r1, c1, c0, 0 @ read C15 Control register + orr r1, r1, #0x1000 @ enable I-cache, map interrupt vector 0xffff0000 + mcr p15, 0, r1, c1, c0, 0 @ write C15 Control register + mov r1, #0x00 + mcr p15, 0, r1, c7, c5, 0 @ Flush I-cache + nop + nop + nop + nop + + /* Setup clocking mode */ + ldr r0, MPU_CLKM_BASE @ base of CLOCK unit + ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status + bic r1, r1, #(7 << 11) @ clear clock select + orr r1, r1, #(2 << 11) @ set synchronous scalable + mov r2, #0 +loop: + cmp r2, #1 @ this loop will wait for at least 100 cycles + streqh r1, [r0, #0x18] @ before issuing next request from MPU + add r2, r2, #1 @ on the 1st run code is loaded into I-cache + cmp r2, #16 @ and second run will set clocking mode + bne loop + nop + + /* Setup clock dividers */ + ldr r1, CKCTL_VAL + orr r1, r1, #0x2000 @ enable DSP clock + strh r1, [r0] @ setup clock divisors + + /* Setup DPLL to generate requested freq */ + ldr r0, DPLL1_BASE @ base of DPLL1 register + mov r1, #0x0010 @ set PLL_ENABLE + orr r1, r1, #0x2000 @ set IOB to new locking + orr r1, r1, #(OMAP5910_DPLL_MUL << 7) @ setup multiplier CLKREF + orr r1, r1, #(OMAP5910_DPLL_DIV << 5) @ setup divider CLKREF + strh r1, [r0] @ write + +locking: + ldrh r1, [r0] @ get DPLL value + tst r1, #0x01 + beq locking @ while LOCK not set + + /* Enable clock */ + ldr r0, MPU_CLKM_BASE @ base of CLOCK unit + mov r1, #(1 << 10) @ disable idle mode do not check + @ nWAKEUP pin, other remain active + strh r1, [r0, #0x04] + ldr r1, EN_CLK_VAL + strh r1, [r0, #0x08] + mov r1, #0x003f @ FLASH.RP not enabled in idle and + strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) + + mov r6, #0 crcuj _LOADER1_OFFSET, _LOADER_SIZE bne crc1_bad @@ -76,9 +131,8 @@ crc1_bad: crc2_bad: ldr r3, _LOADER1_OFFSET ldr r4, _LOADER2_OFFSET - b boot_2nd - tst r6, #3 - beq one_is_bad @ one of them (or both) has bad crc + teq r6, #3 + bne one_is_bad @ one of them (or both) has bad crc ldr r1, [r3, #4] ldr r2, [r4, #4] cmp r1, r2 @ boot 2nd loader if versions differ @@ -90,6 +144,7 @@ one_is_bad: tst r6, #2 bne boot_2nd @ We are doomed, so let user know. +hell: ldr r0, GPIO_BASE @ configure GPIO pins ldr r1, GPIO_DIRECTION strh r1, [r0, #0x08] @@ -171,6 +226,15 @@ CRC32_TABLE: GPIO_BASE: .word 0xfffce000 +MPU_CLKM_BASE: + .word 0xfffece00 +DPLL1_BASE: + .word 0xfffecf00 + +CKCTL_VAL: + .word OMAP5910_ARM_CKCTL +EN_CLK_VAL: + .word OMAP5910_ARM_EN_CLK GPIO_DIRECTION: .word 0x0000ffe7 diff --git a/board/netstar/crcek.h b/board/netstar/crcek.h diff --git a/board/netstar/crcit.c b/board/netstar/crcit.c --- a/board/netstar/crcit.c +++ b/board/netstar/crcit.c @@ -77,7 +77,7 @@ int main(int argc, char **argv) } else if ((argc == 4) && (strcmp(argv[1], "-v") == 0)) { char *endptr, *nptr = argv[2]; unsigned ver = strtoul(nptr, &endptr, 0); - if (nptr != '\0' && endptr == '\0') + if (*nptr != '\0' && *endptr == '\0') return doit(argv[3], ver); } fprintf(stderr, "Usage: crcit [-v version] <image>\n"); diff --git a/board/netstar/eeprom.c b/board/netstar/eeprom.c --- a/board/netstar/eeprom.c +++ b/board/netstar/eeprom.c @@ -213,3 +213,4 @@ int eeprom(int argc, char *argv[]) return 0; } + diff --git a/board/netstar/nand.c b/board/netstar/nand.c --- a/board/netstar/nand.c +++ b/board/netstar/nand.c @@ -55,10 +55,11 @@ static int netstar_nand_ready(struct mtd void board_nand_init(struct nand_chip *nand) { - nand->options = NAND_SAMSUNG_LP_OPTIONS; + nand->options = NAND_SAMSUNG_LP_OPTIONS; nand->eccmode = NAND_ECC_SOFT; - nand->hwcontrol = netstar_nand_hwcontrol; + nand->hwcontrol = netstar_nand_hwcontrol; /* nand->dev_ready = netstar_nand_ready; */ nand->chip_delay = 18; } #endif + diff --git a/board/netstar/netstar.c b/board/netstar/netstar.c --- a/board/netstar/netstar.c +++ b/board/netstar/netstar.c @@ -27,7 +27,6 @@ int board_init(void) DECLARE_GLOBAL_DATA_PTR; /* arch number of NetStar board */ - /* TODO: use define from asm/mach-types.h */ gd->bd->bi_arch_number = 692; /* adress of boot parameters */ @@ -53,16 +52,13 @@ int dram_init(void) return 0; } -extern void partition_flash(void); - int misc_init_r(void) { return 0; } -extern void nand_init(void); - int board_late_init(void) { return 0; } + diff --git a/board/netstar/setup.S b/board/netstar/setup.S --- a/board/netstar/setup.S +++ b/board/netstar/setup.S @@ -58,10 +58,10 @@ VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) VAL_EMIFF_SDRAM_CONFIG: .word ((0 << 0) | (0 << 1) | (3 << 2) | (0xd << 4) | (0x246 << 8) | (0 << 24) | (0 << 26) | (0 << 27)) #endif -VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 +VAL_EMIFF_SDRAM_CONFIG2: .word 0x00000003 VAL_EMIFF_MRS: .word 0x00000037 -/* +/* * GPIO04 - Green LED (Red LED is connected to LED Pulse Generator) * GPIO07 - LAN91C111 reset */ @@ -106,7 +106,7 @@ MUX_CONFIG_OFFSETS: .align 1 .byte 0x00 @ FUNC_MUX_CTRL_0 .byte 0x04 @ FUNC_MUX_CTRL_1 - .byte 0x08 @ FUNC_MUX_CTRL_2 + .byte 0x08 @ FUNC_MUX_CTRL_2 .byte 0x10 @ FUNC_MUX_CTRL_3 .byte 0x14 @ FUNC_MUX_CTRL_4 .byte 0x18 @ FUNC_MUX_CTRL_5 @@ -145,25 +145,23 @@ platformsetup: nop /* Setup clocking mode */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ prepare base of CLOCK unit - ldrh r1, [r0, #0x18] @ get reset status + ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + ldrh r1, [r0, #0x18] @ ARM_SYST - get reset status bic r1, r1, #(7 << 11) @ clear clock select orr r1, r1, #(2 << 11) @ set synchronous scalable - mov r2, #0 @ set wait counter to 100 clock cycles - -icache_loop: - cmp r2, #0x01 - streqh r1, [r0, #0x18] - add r2, r2, #0x01 - cmp r2, #0x10 - bne icache_loop + mov r2, #0 +loop: + cmp r2, #1 @ this loop will wait for at least 100 cycles + streqh r1, [r0, #0x18] @ before issuing next request from MPU + add r2, r2, #1 @ on the 1st run code is loaded into I-cache + cmp r2, #16 @ and second run will set clocking mode + bne loop nop - /* Setup clock divisors */ - ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit + /* Setup clock dividers */ ldr r1, _OMAP5910_ARM_CKCTL orr r1, r1, #0x2000 @ enable DSP clock - strh r1, [r0, #0x00] @ setup clock divisors + strh r1, [r0] @ setup clock divisors /* Setup DPLL to generate requested freq */ ldr r0, OMAP5910_DPLL1_BASE @ base of DPLL1 register @@ -182,18 +180,17 @@ locking: ldr r0, OMAP5910_MPU_CLKM_BASE @ base of CLOCK unit mov r1, #(1 << 10) @ disable idle mode do not check @ nWAKEUP pin, other remain active - strh r1, [r0, #0x04] + strh r1, [r0, #0x04] ldr r1, _OMAP5910_ARM_EN_CLK strh r1, [r0, #0x08] mov r1, #0x003f @ FLASH.RP not enabled in idle and - @ max delayed ( 32 x CLKIN ) - strh r1, [r0, #0x0c] + strh r1, [r0, #0x0c] @ max delayed ( 32 x CLKIN ) /* Configure 5910 pins functions to match our board. */ ldr r0, MUX_CONFIG_BASE adr r1, MUX_CONFIG_VALUES adr r2, MUX_CONFIG_OFFSETS -next_mux_cfg: +next_mux_cfg: ldrb r3, [r2], #1 ldr r4, [r1], #4 cmp r3, #0xff @@ -240,15 +237,15 @@ next_mux_cfg: strh r1, [r0, #0x34] /* Setup clock divisors */ - ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register + ldr r0, OMAP5910_ULPD_PWR_MNG_BASE @ base of ULDPL DPLL1 register mov r1, #0x0010 @ set PLL_ENABLE - orr r1, r1, #0x2000 @ set IOB to new locking - strh r1, [r0] @ write + orr r1, r1, #0x2000 @ set IOB to new locking + strh r1, [r0] @ write ulocking: ldrh r1, [r0] @ get DPLL value - tst r1, #1 + tst r1, #1 beq ulocking @ while LOCK not set /* EMIF init */ @@ -257,7 +254,7 @@ ulocking: bic r1, r1, #0x0c @ pwr down disabled, flash WP orr r1, r1, #0x01 str r1, [r0, #0x0c] - + ldr r1, VAL_EMIFS_CS0_CONFIG str r1, [r0, #0x10] @ EMIFS_CS0_CONFIG ldr r1, VAL_EMIFS_CS1_CONFIG

2 1

[U-Boot-Users] PATCH for cmd_mem.c:do_mem_mtest()
by Andrew Dyer 22 Jul '06

22 Jul '06

Sorry the patch below isn't from git - I hope it's still acceptable. I've put a copy in the body and attached it incase gmail decides to line wrap the text. ChangeLog: * Patch by Andrew Dyer, 13 September 2005: if CFG_ALT_MEMTEST is defined without CFG_MEMTEST_SCRATCH, cmd_mem.c code will dereference a null pointer. Change the code to use the last word of the memory test area as the scratch location in this case. Print the scratch memory location used. Signed-off-by: Andrew Dyer <amdyer(a)gmail.com> Index: common/cmd_mem.c =================================================================== RCS file: /home/cvsroot/Projects/u-boot/common/cmd_mem.c,v retrieving revision 1.1.1.1 diff -p -u -r1.1.1.1 cmd_mem.c --- common/cmd_mem.c 28 Jun 2005 17:32:26 -0000 1.1.1.1 +++ common/cmd_mem.c 13 Sep 2005 10:40:26 -0000 @@ -707,7 +707,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int #if defined(CFG_MEMTEST_SCRATCH) vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH; #else - vu_long *dummy = NULL; + vu_long *dummy; #endif int j; int iterations = 1; @@ -747,7 +747,17 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int } #if defined(CFG_ALT_MEMTEST) + +#if !defined(CFG_MEMTEST_SCRATCH) + /* if no fixed scratch area is defined use + * the last location of the test area + */ + end--; + dummy = end; +#endif + printf ("Testing %08x ... %08x:\n", (uint)start, (uint)end); + printf ("using address %08x as scratch\n",dummy); PRINTF("%s:%d: start 0x%p end 0x%p\n", __FUNCTION__, __LINE__, start, end); -- Hardware, n.: The parts of a computer system that can be kicked.

6 16

[U-Boot-Users] My 3 patches
by luo.jinhua 22 Jul '06

22 Jul '06

Hi. Here is my 3 patches. sbc2410x.patch is for the new board -- SBC-2410X. I write this new hardware-specific configurations refer to smdk2410 configurations in U-Boot. File list: MAKEALL Makefile board/sbc2410x/Makefile board/sbc2410x/config.mk board/sbc2410x/flash.c board/sbc2410x/lowlevel_init.S board/sbc2410x/sbc2410x.c board/sbc2410x/u-boot.lds cpu/arm920t/s3c24x0/interrupts.c include/configs/sbc2410x.h This patch adds a new configuration option -- CONFIG_SBC2410X. cmdline_editing.patch implements cmdline-editing extension of readline. I pick codes heavily borrowed from vivi bootloader and integrate them into U-Boot. File list: common/main.c This patch adds a new configuration option -- CONFIG_CMDLINE_EDITING. nand_for_sbc2410x.patch adds nand support for SBC-2410X board. It do that by taking nand controller specific codes (from VCMA9 board) in place. File list: common/cmd_nand.c include/linux/mtd/nand.h include/linux/mtd/nand_ids.h more detail please review: http://sourceforge.net/mailarchive/forum.php?thread_id=8089177&forum_id=128… CHANGELOG item: * Add support for friendly-arm SBC-2410X board Patch by JinHua Luo, 1 Sep 2005 * Add to readline cmdline-editing extension Patch by JinHua Luo, 1 Sep 2005 * Add nand support for SBC-2410X Patch by JinHua Luo, 1 Sep 2005 CREDIT item (if proper): N: JinHua Luo E: luo.jinhua(a)gd-linux.com home_king(a)163.com D: Support for friendly-arm SBC-2410X board D: Add to readline cmdline-editing extension D: Add nand support for SBC-2410X W: www.gd-linux.com Best regards, luo.jinhua -- JinHua Luo, GuangDong Linux Center, <luo.jinhua(a)gd-linux.com>

3 3

[U-Boot-Users] i386 multi_image.
by David Updegraff 22 Jul '06

22 Jul '06

Hi. I think this is needed to correctly boot multi-part images if you are unfortuanate enough to be working on an i386 platform. -dbu. diff --git a/lib_i386/i386_linux.c b/lib_i386/i386_linux.c --- a/lib_i386/i386_linux.c +++ b/lib_i386/i386_linux.c @@ -150,6 +150,11 @@ void do_bootm_linux(cmd_tbl_t *cmdtp, in initrd_start = 0; initrd_end = 0; } + /* <dave(a)cray.com> : if multi-part img. need to advance base ptr */ + if ((hdr->ih_type==IH_TYPE_MULTI) && (len_ptr[1])) { + int i; + for (i=0, addr+=sizeof(int); len_ptr[i++]; addr+=sizeof(int)); + } base_ptr = load_zimage((void*)addr + sizeof(image_header_t), ntohl(hdr->ih_size), initrd_start, initrd_end-initrd_start, 0);

2 1

[U-Boot-Users] [Patch] KVME080 Support
by Sangmoon Kim 22 Jul '06

22 Jul '06

Hi, This patch adds support for KVME080 board. KVME080 is a VME board with MPC8245 CPU. It also patches drivers/cfi_flash.c. First, it adds CFG_FLASH_PROTECT_CLEAR because for some flash memories(such as 28F320C3) all banks are protected after reset. Second, it makes write_buff not to call flash_write_cfibuffer if buffer_size is1. Because for flash memories with buffer_size 1, buffer write is not supported. Third, it makes 64 bit writes to use FLASH_WRITE64 if FLASH_WRITE64 is defined. Because KVME080 needs it. Fourth, it makes flash_detect_cfi call FLASH_PORTWIDTH when changing portwidth if FLASH_PORTWIDTH is defined. Because on some CPUs (such as MPC8245), port width should be changed. Regards, Sangmoon Kim

2 3

[U-Boot-Users] MIPS LE build problems
by Wolfgang Denk 22 Jul '06

22 Jul '06

Dear Thomas, I always wondered what exactly was the reason why I was not able to build the dbau1x00 targets (especially the little endian dbau1550_el target using the ELDK toolchain). Also, I always wondered about the reference to a non-exitent cpu/mips/little/liblittle.a library. Is ther ea special reason for the current settings of build options for the dbau1x00 targets? Attached below is a patch which makes all dbau1x00 targets build fine with the current ELDK, and I believe these settings are more correct than the previous ones. If you don't protest I would like to merge this patch into the public source tree? Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Remember, there's a big difference between kneeling down and bending over. - Frank Zappa

6 31

[U-Boot-Users] parse bug in cmd_mii.c
by Andrew Dyer 22 Jul '06

22 Jul '06

I noticed that in do_mii() the code is dereferencing argv[1] without checking what value argc has. This leads to an exception if a command line like 'mii ' is given where argv[1] is NULL. I have a patch, but my cmd_mii.c is carrying around some other patches (some submitted to the list, some local). Is there a good way to separate out the patches I want to submit by themselves? -- Hardware, n.: The parts of a computer system that can be kicked.

2 4

[U-Boot-Users] [PATCH] 02-add-support-for-ps2-keyboard-on-tqm8540-board.patch
by Martin Krause 19 Jul '06

19 Jul '06

This patch replaces the patch add-support-for-ps2-keyboard-on-tqm8540-board.patch send to this list on Thu 17. Nov 2005. Add support for PS/2 keyboard on TQM8540 board Patch by Martin Krause, 02 Dez 2005 This is tested on a STK85XX baseboard. Make sure the PS/2 controller is programmed. Jumper Settings: X66 1-2, 9-10; X61 2-3 Signed-off-by: Martin Krause <martin.krause(a)tqs.de> CHANGELOG: * Add support for PS/2 keyboard on TQM8540 board Patch by Martin Krause, 02 Dez 2005

2 3

[U-Boot-Users] MPC8349EMDS port
by Kumar Gala 29 Jun '06

29 Jun '06

Wolfgang, I was looking at merging the EMDS and ADS ports for MPC834x and was wondering about a few things: * EMDS has TEXT_BASE @ 0xFE000000, and ADS at 0xFE700000 where do you end up programming u-boot at? (for example what is the flash command you use to reprogram a u-boot image on the board). * I had to rework the BATs to be able to cover everything properly which also meant moving a few things around. CFG_BCSR 0xF8000000 -> 0xE2400000 CFG_INIT_RAM_ADDR 0xE8000000 -> 0xFD000000 This is so we can fit everything into the 8 BATS and maintain proper WIMG settings. If you can explain the TEXT_BASE difference and how that works out and are ok with the changing of CFG_BCSR and CFG_INIT_RAM_ADDR then I'll push some patches to merge ADS & MDS, remove ADS, and we get PCI support on EMDS out of it. let me know. - kumar

3 6

[U-Boot-Users] usb storage class CTL timeout problem
by Winston Lin 23 Jun '06

23 Jun '06

Hi, Does anyone know why some USB mass storage devices work and some don't on the same board with the same u-boot 1.1.3? I was able to track the msg down to hc_interrupt() used by submit_common_msg() in ./cpu/mpc5xxx/usb_ohci.c file. The hc_interrupt() always return 0xff (SF) and the submit_common_msg() in its for-loop times out on SF eventually. Regards, Winston => usb reset (Re)start USB... USB: scanning bus for devices... 2 USB Devices found => usb scan Scan for storage device: scanning bus for storage devices... ERROR: CTL:TIMEOUT Device 0: Vendor: ChipsBnk Prod.: Flash Disk Rev: 2.00 Type: Removable Hard Disk Capacity: 125.6 MB = 0.1 GB (257344 x 512) => usb scan Scan for storage device: scanning bus for storage devices... ERROR: CTL:TIMEOUT ERROR: CTL:TIMEOUT ERROR: CTL:TIMEOUT ERROR: CTL:TIMEOUT ERROR: CTL:TIMEOUT

4 3