December 2006 - U-Boot

[U-Boot-Users] [GIT PULL] AVR32 relocation
by Haavard Skinnemoen 02 Mar '07

02 Mar '07

Hi Wolfgang, Please pull from the 'for-upstream' branch of git://www.atmel.no/~hskinnemoen/u-boot/avr32 for-upstream to receive the following updates: Haavard Skinnemoen (6): AVR32: Split start_u_boot into board_init_f and board_init_r AVR32: Use avr32-linux- cross-compilation prefix by default AVR32: Build position-independent u-boot AVR32: Clean up memory-map.h for at32ap7000 AVR32: Resource management rewrite AVR32: Relocate u-boot to SDRAM Makefile | 2 +- avr32_config.mk | 2 +- board/atmel/atstk1000/atstk1000.c | 13 + board/atmel/atstk1000/flash.c | 2 +- board/atmel/atstk1000/u-boot.lds | 21 +- cpu/at32ap/Makefile | 2 +- cpu/at32ap/at32ap7000/Makefile | 2 +- cpu/at32ap/at32ap7000/devices.c | 448 ------------------------ cpu/at32ap/at32ap7000/gpio.c | 77 ++++ cpu/at32ap/at32ap7000/hebi.c | 38 -- cpu/at32ap/cpu.c | 64 +++- cpu/at32ap/device.c | 126 ------- cpu/at32ap/entry.S | 3 +- cpu/at32ap/exception.c | 7 +- cpu/at32ap/hsdramc.c | 43 +-- cpu/at32ap/hsdramc1.h | 8 +- cpu/at32ap/hsmc3.h | 8 +- cpu/at32ap/interrupts.c | 14 +- cpu/at32ap/pio.c | 90 ++---- cpu/at32ap/pio2.h | 8 +- cpu/at32ap/pm.c | 127 +------- cpu/at32ap/sm.h | 8 +- cpu/at32ap/start.S | 113 +++++-- drivers/atmel_usart.c | 48 ++- drivers/atmel_usart.h | 8 +- include/asm-avr32/arch-at32ap7000/clk.h | 58 +++ include/asm-avr32/arch-at32ap7000/gpio.h | 210 +++++++++++ include/asm-avr32/arch-at32ap7000/hmatrix2.h | 8 +- include/asm-avr32/arch-at32ap7000/memory-map.h | 81 +++-- include/asm-avr32/arch-at32ap7000/platform.h | 146 -------- include/asm-avr32/global_data.h | 3 +- include/configs/atstk1002.h | 17 +- lib_avr32/avr32_linux.c | 4 +- lib_avr32/board.c | 139 +++++++- 34 files changed, 796 insertions(+), 1152 deletions(-) delete mode 100644 cpu/at32ap/at32ap7000/devices.c create mode 100644 cpu/at32ap/at32ap7000/gpio.c delete mode 100644 cpu/at32ap/at32ap7000/hebi.c delete mode 100644 cpu/at32ap/device.c create mode 100644 include/asm-avr32/arch-at32ap7000/clk.h create mode 100644 include/asm-avr32/arch-at32ap7000/gpio.h delete mode 100644 include/asm-avr32/arch-at32ap7000/platform.h After this, the avr32 port will relocate itself to the end of DRAM like the ppc port does. Attached is a combined diff with all the changes, for your reference (too big to include inline.) Quite a large number of files were touched. This is mostly early init code which assumed the .data and .bss sections were available. Now, I would like to use the cfi driver with the AT49BV6416 chip on atstk1000 instead of the custom driver, but unfortunately, it doesn't work. I'll have a closer look at it later (I think it's a combination of the geometry reversal issue and a special non-intel unlocking algorithm.) Thanks, Haavard

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[U-Boot-Users] fixup section problem.
by Txema Lopez 12 Feb '07

12 Feb '07

Hi, We are working in a MPC5200B based custom board and we are developping a tool to relocate a U-Boot (1.1.4 version) binary file to a different address in flash that it was linked. So, we have to change the GOT and FIXUP entries in the original file to point at the new address. Doing this work, we have found that, surprisingly, the FIXUP section in U-Boot is empty. When U-Boot is relocated from flash to sdram these lines in the file start.S have no effect: /* * Now adjust the fixups and the pointers to the fixups * in case we need to move ourselves again. */ 2: li r0,__fixup_entries@sectoff@l lwz r3,GOT(_FIXUP_TABLE_) cmpwi r0,0 mtctr r0 addi r3,r3,-4 beq 4f 3: lwzu r4,4(r3) lwzux r0,r4,r11 add r0,r0,r11 stw r10,0(r3) stw r0,0(r4) bdnz 3b 4: Looking into the sources we have found some places where the fixup elements seem to be relocated manually, i.e.: void malloc_bin_reloc (void) { DECLARE_GLOBAL_DATA_PTR; unsigned long *p = (unsigned long *)(&av_[2]); int i; for (i=2; i<(sizeof(av_)/sizeof(mbinptr)); ++i) { *p++ += gd->reloc_off; } } Is there any reason to leave the FIXUP section empty in U-Boot? Is it a bug?. Checking the u-boot.lds file for the IceCube board we have found that fhe fixup section is included in the TEXT section and in the RELOC section, but the linker generate code only for the TEXT section. If we put it only in the RELOC section the FIXUP is not empty, the pointers adjustement in the start.S seems to work properly and the malloc_bin_reloc() function would be not necessary. Does anynone know if I'am missing something? Any clue will be welcomed. Best regards,

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[U-Boot-Users] [PATCH] Fixed cfi flash read uchar bug.
by wei.zhang＠freescale.com 11 Feb '07

11 Feb '07

From: Zhang Wei <wei.zhang(a)freescale.com> For the flash of port width more than 8bit, a completetly read must be performed. For example, 16bit port width flash must perform a ushort read. Otherwise, some flashes will get error data. Signed-off-by: Zhang Wei <wei.zhang(a)freescale.com> --- drivers/cfi_flash.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-) diff --git a/drivers/cfi_flash.c b/drivers/cfi_flash.c index 9b10220..f02b047 100644 --- a/drivers/cfi_flash.c +++ b/drivers/cfi_flash.c @@ -250,9 +250,9 @@ #endif */ inline uchar flash_read_uchar (flash_info_t * info, uint offset) { - uchar *cp; + uchar cp[FLASH_CFI_64BIT]; - cp = flash_make_addr (info, 0, offset); + memcpy(cp, flash_make_addr (info, 0, offset), info->portwidth); #if defined(__LITTLE_ENDIAN) return (cp[0]); #else -- 1.4.0

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[U-Boot-Users] builtin OF tree dtb gone
by Joakim Tjernlund 22 Jan '07

22 Jan '07

While trying out the latest u-boot from my board I noticed that support for using a prebuilt OF tree compiled int u-boot is gone. The oftree_dtb symbol is gone and I can't find a replacement. Why was it removed and is there a replacement? If there isn't a replacement I request that one is added. Jocke

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[U-Boot-Users] [PATCH] Fix PCI I/O space mapping on Freescale MPC85x0ADS
by Sergei Shtylyov 13 Jan '07

13 Jan '07

The PCI I/O space mapping for Freescale MPC8540ADS board was broken by commit 52c7a68b8d587ebcf5a6b051b58b3d3ffa377ddc which failed to update the #define's describing the local address window used for the PCI I/O space accesses -- fix this and carry over the necessary changes into the MPC8560ADS code since the PCI I/O space mapping was also broken for this board (by the earlier commit 087454609e47295443af793a282cddcd91a5f49c). Add the comments clarifying how the PCI I/O space must be mapped to all the MPC85xx board config. headers. Signed-off-by: Sergei Shtylyov <sshtylyov(a)ru.mvista.com> board/mpc8540ads/init.S | 4 ++-- board/mpc8560ads/init.S | 4 ++-- include/configs/MPC8540ADS.h | 5 ++--- include/configs/MPC8541CDS.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8560ADS.h | 8 ++++---- 6 files changed, 12 insertions(+), 13 deletions(-) Index: u-boot/board/mpc8540ads/init.S =================================================================== --- u-boot.orig/board/mpc8540ads/init.S +++ u-boot/board/mpc8540ads/init.S @@ -260,8 +260,8 @@ tlb1_entry: #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* * Rapid IO at 0xc000_0000 for 512 M Index: u-boot/board/mpc8560ads/init.S =================================================================== --- u-boot.orig/board/mpc8560ads/init.S +++ u-boot/board/mpc8560ads/init.S @@ -260,8 +260,8 @@ tlb1_entry: #define LAWBAR2 ((CFG_LBC_SDRAM_BASE>>12) & 0xfffff) #define LAWAR2 (LAWAR_EN | LAWAR_TRGT_IF_LBC | (LAWAR_SIZE & LAWAR_SIZE_256M)) -#define LAWBAR3 ((CFG_PCI1_IO_BASE>>12) & 0xfffff) -#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_16M)) +#define LAWBAR3 ((CFG_PCI1_IO_PHYS>>12) & 0xfffff) +#define LAWAR3 (LAWAR_EN | LAWAR_TRGT_IF_PCIX | (LAWAR_SIZE & LAWAR_SIZE_1M)) /* * Rapid IO at 0xc000_0000 for 512 M Index: u-boot/include/configs/MPC8540ADS.h =================================================================== --- u-boot.orig/include/configs/MPC8540ADS.h +++ u-boot/include/configs/MPC8540ADS.h @@ -330,13 +330,12 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ - -#define CFG_PCI1_IO_BASE 0x0 +#define CFG_PCI1_IO_BASE 0x00000000 #define CFG_PCI1_IO_PHYS 0xe2000000 #define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ Index: u-boot/include/configs/MPC8541CDS.h =================================================================== --- u-boot.orig/include/configs/MPC8541CDS.h +++ u-boot/include/configs/MPC8541CDS.h @@ -334,7 +334,7 @@ extern unsigned long get_clock_freq(void /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE Index: u-boot/include/configs/MPC8548CDS.h =================================================================== --- u-boot.orig/include/configs/MPC8548CDS.h +++ u-boot/include/configs/MPC8548CDS.h @@ -340,7 +340,7 @@ extern unsigned long get_clock_freq(void /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE Index: u-boot/include/configs/MPC8560ADS.h =================================================================== --- u-boot.orig/include/configs/MPC8560ADS.h +++ u-boot/include/configs/MPC8560ADS.h @@ -320,14 +320,14 @@ /* * General PCI - * Addresses are mapped 1-1. + * Memory space is mapped 1-1, but I/O space must start from 0. */ #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x20000000 /* 512M */ -#define CFG_PCI1_IO_BASE 0xe2000000 -#define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE -#define CFG_PCI1_IO_SIZE 0x1000000 /* 16M */ +#define CFG_PCI1_IO_BASE 0x00000000 +#define CFG_PCI1_IO_PHYS 0xe2000000 +#define CFG_PCI1_IO_SIZE 0x100000 /* 1M */ #if defined(CONFIG_PCI)

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[U-Boot-Users] u-boot port for MicroBlaze
by Leonid 01 Jan '07

01 Jan '07

Does MicroBlaze u-boot port actually work on any Xilinx board? Which one? From Xilinx boards I only saw ML300 on u-boot tree and that one is PPC405 based. I am bringing up uClinux on Spartan-2e based custom board (similar to ML401) need bootloader and would appreciate any information how to port u-boot there. Thanks, Leonid.

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[U-Boot-Users] cpu POST hang
by Brandon Clarke 30 Dec '06

30 Dec '06

Hey All, I'm tyring to incorporate the u-boot cpu POST (cpu_post_test) into a custom board using an MPC8541E running the latest uboot version, and the board hangs when this particular POST test is run. Digging a little deeper I found that the system hangs in the cpu_post_exec_12 in the /post/cpu/asm.S file. Below is the code: /* void cpu_post_exec_12 (ulong *code, ulong *res, ulong op1, ulong op2); */ .global cpu_post_exec_12 cpu_post_exec_12: mflr r0 stwu r0, -4(r1) stwu r4, -4(r1) mtlr r3 mr r3, r5 mr r4, r6 blrl <-----------------hangs here lwz r4, 0(r1) stw r3, 0(r4) lwz r0, 4(r1) addi r1, r1, 8 mtlr r0 blr I commented out the first branch and the entire cpu post ran without hanging the system again. I need to incorporate this test into my board, but I don't want to comment this code without fully understanding it's functionality. Has anyone done any work on the cpu POST for an MPC85xx and run into similar problems and can someone point me to where I can find more details on what this code is doing? Thanks, Brandon Clarke __________________________________________________ Do You Yahoo!? Tired of spam? Yahoo! Mail has the best spam protection around http://mail.yahoo.com

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[U-Boot-Users] U-boot newbie: Bring-up issues on MPC8260 board
by raghuveer.murthy＠wipro.com 29 Dec '06

29 Dec '06

Hi, I am trying to bring u-boot up on a MPC8260 based board. It stops after showing the following output: ***************************************************************** U-Boot 1.1.4 (Dec 29 2006 - 18:31:04) MPC8260 Reset Status: External Soft, External Hard MPC8260 Clock Configuration - Bus-to-Core Mult 3x, VCO Div 2, 60x Bus Freq 33-100, Core Freq 100-300 - dfbrg 0, corecnf 0x08, busdf 3, cpmdf 1, plldf 0, pllmf 1 - vco_out 264000000, scc_clk 66000000, brg_clk 66000000 - cpu_clk 198000000, cpm_clk 132000000, bus_clk 66000000 CPU: MPC8260 (HiP3 Rev 01, Mask C.2 6K23A) at 198 MHz Board: EST PSI8260 DRAM: 64 MB ********************************************************************* Using the visionICE emulator, got the following exception: !HALT! - [msg90003] Target Stopped for unknown reason; PC = 0x00000200 Upon debugging, it was found that the code stops running after a couple of instructions into ram in the assembly code segment of "in_ram" in the "cpu/mpc8260/start.S" in the u-boot source directory. The snippet of code is below: in_ram: /* * Relocation Function, r14 point to got2+0x8000 * * Adjust got2 pointers, no need to check for 0, this code * already puts a few entries in the table. */ li r0,__got2_entries@sectoff@l la r3,GOT(_GOT2_TABLE_) lwz r11,GOT(_GOT2_TABLE_) mtctr r0 /* not updating correctly */ <--------------------- /* tried adding sync and isync here */ sub r11,r3,r11 addi r3,r3,-4 <---------------------- /* tried adding sync and isync here */ 1: lwzu r0,4(r3) add r0,r0,r11 stw r0,0(r3) bdnz 1b Since the "mtctr r0" is not updating properly, isync instruction was given at the 2 places mentioned above. But, this redirects the Program Counter to exception 0x00000200, either immediately after isync instruction or after a executing a single instruction. Please note that the icache is enabled. Is it anything to do with Instruction pipelining, or do I need to look into any specific Core register configuration. Kindly let me know what is going wrong here. Regards, Raghuveer

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[U-Boot-Users] MIPS32/MIPS24KE
by sathesh babu 29 Dec '06

29 Dec '06

Hi, Does u-boot have support for MIPS32 or MIPS24KE processor?. If it has can you give some pointer where can i locate the cache implementation specific code for MIPS32 or MPIS24KE. Regards, Sathesh Send free SMS to your Friends on Mobile from your Yahoo! Messenger. Download Now! http://messenger.yahoo.com/download.php

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[U-Boot-Users] MII, 8360E, National DP83865
by Russell McGuire 29 Dec '06

29 Dec '06

All, Trying to get the MII interface to work correctly with the National DP83865 PHY chip. At the moment, U-boot comes and up correctly pulls the PHY_ID down <0x20005c7a> and starts using the Generic PHY interface. However, when I later use the MII commands it will not report any devices so that I can query the rest of the registers. Example: Net : UEC : PHY is Generic MII (20005c7a) FSL UEC0 Uboot> mii device MII devices: Uboot> mii dump NULL device name! Uboot> Is there a #define I am missing that gives this a device name? -Russ

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