November 2005 - U-Boot

[U-Boot-Users] U-Boot Manual Missing Examples
by Anderson, Rachel E 15 Nov '05

15 Nov '05

I am attempting to boot a NetBSD kernel from U-Boot. It's working fine when the kernel is downloaded from a TFTP server and the root file system is loading via NFS. However, now I want to place the kernel in flash and have it relocate and run from RAM when the board starts up with the NFS file system. Eventually, I want to stick the file system in a RAM disk and have the whole thing stored in RAM. I assume that the process is basically the same as booting Linux so I have been using Section 7 of the U-Boot manual at http://www.denx.de/wiki/view/DULG/BootingEmbeddedLinux as a reference. However, several of the examples of U-Boot command line inputs are missing from the sections on Booting from Flash Memory and Running Standalone with a RAM Disk. Will these examples be added soon? If not, is there another mailing list that deals with these issues? Best regards, Rachel Anderson

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[U-Boot-Users] pci.c in MPC8349ADS
by David Updegraff 15 Nov '05

15 Nov '05

Hi. I wonder why PCI support was added to the MPC83xx in board/mpc8349ads as a board-specific thing, instead of a cpu-architecture-general thing in cpu/mpc83xx ? Aside from the I2C setup of the IO-expander, it seems that the remainder of PCI initialization is 83xx generic.. -dbu.

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[U-Boot-Users] Problem porting the POST instruction cache test to the MPC5200.
by Txema Lopez 15 Nov '05

15 Nov '05

Hi all, I'm trying to port the POST cache test to the MPC5200 and I've found some problems porting the cache_post_test5 function. I think the philosophy of the function (I think the comments are not updated) is to lock an instruction in the cache, modify the instruction position in memory with another instruction and verify that the instruction locked in the cache has been executed when we jump to the instruction . The locked instruction load the r3 register with a 0 value and the "new" instruction with a -1. When I debug the function with the gdb and the BDI2000 with the ddd front end I see in the Machine Code Window the intruction locked ( li r3, 0) but if I stepi the instruction the value in r3 will be -1. I can't understand what is happening. Who is telling the truth?. I think the problem seems to be with the lock proccess and I have a doubt: Must I activate the intruction MMU to lock the cache in a MPC5200? I have read the MPC5200 core manual and this aspect is not clear to me. How can I see the instruction cache with the gdb (or BDI2000) without write a specific function ?. Any clue will be welcomed. Attached my test cache file for the MPC5200 based on the cache_8xx.S file. Thanks in advance. Jose Maria Lopez. /* * Copyright (C) 2002 Wolfgang Denk <wd(a)denx.de> * * See file CREDITS for list of people who contributed to this * project. * * This program is free software; you can redistribute it and/or * modify it under the terms of the GNU General Public License as * published by the Free Software Foundation; either version 2 of * the License, or (at your option) any later version. * * This program is distributed in the hope that it will be useful, * but WITHOUT ANY WARRANTY; without even the implied warranty of * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the * GNU General Public License for more details. * * You should have received a copy of the GNU General Public License * along with this program; if not, write to the Free Software * Foundation, Inc., 59 Temple Place, Suite 330, Boston, * MA 02111-1307 USA */ #include <config.h> #ifdef CONFIG_POST #if defined(CONFIG_MPC5xxx) #include <post.h> #include <ppc_asm.tmpl> #include <ppc_defs.h> #include <asm/cache.h> #include <mpc5xxx.h> #if CONFIG_POST & CFG_POST_CACHE .text cache_post_dinvalidate: mfspr r5, HID0 mr r7, r5 lis r6, 0 ori r6, r6, HID0_DCI andc r5, r5, r6 ori r5, r5, HID0_DCE or r6, r6, r5 sync mtspr HID0, r6 sync mtspr HID0, r5 sync mtspr HID0, r7 blr cache_post_iinvalidate: mfspr r5, HID0 mr r7, r5 lis r6, 0 ori r6, r6, HID0_ICFI andc r5, r5, r6 ori r5, r5, HID0_ICE or r6, r6, r5 isync mtspr HID0, r6 isync mtspr HID0, r5 isync mtspr HID0, r7 blr cache_post_ddisable: mfspr r5, HID0 lis r6, 0 ori r6, r6, HID0_DCE andc r5, r5, r6 sync mtspr HID0, r5 blr cache_post_dwb: mfspr r5, HID0 ori r5, r5, HID0_DCE sync mtspr HID0, r5 blr cache_post_dwt: blr cache_post_idisable: mfspr r5, HID0 lis r6, 0 ori r6, r6, HID0_ICE andc r5, r5, r6 isync mtspr HID0, r5 blr cache_post_ienable: mfspr r5, HID0 ori r5, r5, HID0_ICE isync mtspr HID0, r5 blr cache_post_iunlock: mfspr r5, HID0 lis r6, 0 ori r6, r6, HID0_ILOCK andc r5, r5, r6 isync mtspr HID0, r5 blr cache_post_ilock: mfspr r5, HID0 ori r5, r5, HID0_ILOCK isync mtspr HID0, r5 blr mmu_post_denable: mfmsr r5 lis r6, MSR_DR@h ori r6, r6, MSR_DR@l or r5, r5, r6 SYNC mtmsr r5 SYNC blr mmu_post_ddisable: mfmsr r5 lis r6, MSR_DR@h ori r6, r6, MSR_DR@l andc r5, r5, r6 SYNC mtmsr r5 SYNC blr /* * turn on the data cache * switch the data cache to write-back or write-through mode * invalidate the data cache * write the negative pattern to a cached area * read the area * * The negative pattern must be read at the last step */ .global cache_post_test1 cache_post_test1: mflr r0 stw r0, 4(r1) stwu r3, -4(r1) stwu r4, -4(r1) bl cache_post_dwb bl cache_post_dinvalidate /* Write the negative pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0xff lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b /* Read the test area */ lwz r0, 0(r1) mtctr r0 lwz r4, 4(r1) subi r4, r4, 1 li r3, 0 1: lbzu r0, 1(r4) cmpli cr0, r0, 0xff beq 2f li r3, -1 b 3f 2: bdnz 1b 3: bl cache_post_ddisable bl cache_post_dinvalidate addi r1, r1, 8 lwz r0, 4(r1) mtlr r0 blr /* * turn on the data cache * switch the data cache to write-back or write-through mode * invalidate the data cache * write the zero pattern to a cached area * turn off the data cache * write the negative pattern to the area * turn on the data cache * read the area * * The negative pattern must be read at the last step */ .global cache_post_test2 cache_post_test2: mflr r0 stw r0, 4(r1) stwu r3, -4(r1) stwu r4, -4(r1) bl cache_post_dwb bl cache_post_dinvalidate /* Write the zero pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0 lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b bl cache_post_ddisable /* Write the negative pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0xff lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b bl cache_post_dwb /* Read the test area */ lwz r0, 0(r1) mtctr r0 lwz r4, 4(r1) subi r4, r4, 1 li r3, 0 1: lbzu r0, 1(r4) cmpli cr0, r0, 0xff beq 2f li r3, -1 b 3f 2: bdnz 1b 3: bl cache_post_ddisable bl cache_post_dinvalidate addi r1, r1, 8 lwz r0, 4(r1) mtlr r0 blr /* * turn on the data cache * switch the data cache to write-through mode * invalidate the data cache * write the zero pattern to a cached area * flush the data cache * write the negative pattern to the area * turn off the data cache * read the area * * The negative pattern must be read at the last step */ .global cache_post_test3 cache_post_test3: mflr r0 stw r0, 4(r1) stwu r3, -4(r1) stwu r4, -4(r1) bl cache_post_ddisable bl cache_post_dinvalidate /* Write the zero pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0 lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b bl mmu_post_denable bl cache_post_dwb bl cache_post_dinvalidate /* Write the negative pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0xff lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b bl cache_post_ddisable bl cache_post_dinvalidate bl mmu_post_ddisable /* Read the test area */ lwz r0, 0(r1) mtctr r0 lwz r4, 4(r1) subi r4, r4, 1 li r3, 0 1: lbzu r0, 1(r4) cmpli cr0, r0, 0xff beq 2f li r3, -1 b 3f 2: bdnz 1b 3: addi r1, r1, 8 lwz r0, 4(r1) mtlr r0 blr /* * turn on the data cache * switch the data cache to write-back mode * invalidate the data cache * write the negative pattern to a cached area * flush the data cache * write the zero pattern to the area * invalidate the data cache * read the area * * The negative pattern must be read at the last step */ .global cache_post_test4 cache_post_test4: mflr r0 stw r0, 4(r1) stwu r3, -4(r1) stwu r4, -4(r1) bl cache_post_ddisable bl cache_post_dinvalidate /* Write the negative pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0xff lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b bl cache_post_dwb bl cache_post_dinvalidate /* Write the zero pattern to the test area */ lwz r0, 0(r1) mtctr r0 li r0, 0 lwz r3, 4(r1) subi r3, r3, 1 1: stbu r0, 1(r3) bdnz 1b bl cache_post_ddisable bl cache_post_dinvalidate /* Read the test area */ lwz r0, 0(r1) mtctr r0 lwz r4, 4(r1) subi r4, r4, 1 li r3, 0 1: lbzu r0, 1(r4) cmpli cr0, r0, 0xff beq 2f li r3, -1 b 3f 2: bdnz 1b 3: addi r1, r1, 8 lwz r0, 4(r1) mtlr r0 blr cache_post_test5_1: li r3, 0 blr cache_post_test5_2: li r3, -1 blr /* * turn on the instruction cache * unlock the entire instruction cache * invalidate the instruction cache * lock a branch instruction in the instruction cache * replace the branch instruction with "nop" * jump to the branch instruction * check that the branch instruction was executed */ .global cache_post_test5 cache_post_test5: mflr r0 stw r0, 4(r1) bl cache_post_ienable bl cache_post_iunlock bl cache_post_iinvalidate /* Compute r9 = cache_post_test5_reloc */ bl cache_post_test5_reloc cache_post_test5_reloc: mflr r9 /* Copy the test instruction to cache_post_test5_data */ lis r3, (cache_post_test5_1 - cache_post_test5_reloc)@h ori r3, r3, (cache_post_test5_1 - cache_post_test5_reloc)@l add r3, r3, r9 lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l add r4, r4, r9 lwz r0, 0(r3) stw r0, 0(r4) bl cache_post_iinvalidate /* Lock the branch instruction */ bl cache_post_test5_data bl cache_post_ilock /* Replace the test instruction */ lis r3, (cache_post_test5_2 - cache_post_test5_reloc)@h ori r3, r3, (cache_post_test5_2 - cache_post_test5_reloc)@l add r3, r3, r9 lis r4, (cache_post_test5_data - cache_post_test5_reloc)@h ori r4, r4, (cache_post_test5_data - cache_post_test5_reloc)@l add r4, r4, r9 lwz r0, 0(r3) stw r0, 0(r4) bl cache_post_iinvalidate addi r4, r4, 8 mtlr r4 /* Execute to the test instruction */ cache_post_test5_data: nop blr bl cache_post_iunlock lwz r0, 4(r1) mtlr r0 blr cache_post_test6_1: li r3, -1 blr cache_post_test6_2: li r3, 0 blr /* * turn on the instruction cache * unlock the entire instruction cache * invalidate the instruction cache * lock a branch instruction in the instruction cache * replace the branch instruction with "nop" * jump to the branch instruction * check that the branch instruction was executed */ .global cache_post_test6 cache_post_test6: mflr r0 stw r0, 4(r1) bl cache_post_ienable bl cache_post_iunlock bl cache_post_iinvalidate /* Compute r9 = cache_post_test6_reloc */ bl cache_post_test6_reloc cache_post_test6_reloc: mflr r9 /* Copy the test instruction to cache_post_test6_data */ lis r3, (cache_post_test6_1 - cache_post_test6_reloc)@h ori r3, r3, (cache_post_test6_1 - cache_post_test6_reloc)@l add r3, r3, r9 lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l add r4, r4, r9 lwz r0, 0(r3) stw r0, 0(r4) bl cache_post_iinvalidate /* Replace the test instruction */ lis r3, (cache_post_test6_2 - cache_post_test6_reloc)@h ori r3, r3, (cache_post_test6_2 - cache_post_test6_reloc)@l add r3, r3, r9 lis r4, (cache_post_test6_data - cache_post_test6_reloc)@h ori r4, r4, (cache_post_test6_data - cache_post_test6_reloc)@l add r4, r4, r9 lwz r0, 0(r3) stw r0, 0(r4) bl cache_post_iinvalidate /* Execute to the test instruction */ cache_post_test6_data: nop lwz r0, 4(r1) mtlr r0 blr #endif /* CONFIG_MPC823 || MPC850 || MPC855 || MPC860 */ #endif /* CONFIG_POST & CFG_POST_CACHE */ #endif /* CONFIG_POST */

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[U-Boot-Users] how to add SMC1 interface in the default config file.
by M Ravi Prakash Reddy 15 Nov '05

15 Nov '05

Hi, i am porting linux on my custom board which consists of MPC8266. i'm using ads8266_config as default configuration file. but on my board there is an RS232 interface available which is connected to SMC1 inteface of the 8266 cpu. but in the ads8266 config file SMC interface is not available, may i know how to add SMC to the config file, what are dependencies. thanking u all, __________________________________________________________ Enjoy this Diwali with Y! India Click here http://in.promos.yahoo.com/fabmall/index.html

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RE: [U-Boot-Users] how to add SMC1 interface in the default config file.
by Rune Torgersen 15 Nov '05

15 Nov '05

> -----Original Message----- > From: M Ravi Prakash Reddy > Sent: Tuesday, November 15, 2005 07:10 > but on my board there is an RS232 interface available > which is connected to SMC1 inteface of the 8266 cpu. > but in the ads8266 config file SMC interface is not > available, may i know how to add SMC to the config > file, what are dependencies. edit include/configs/MPC8266ADS.h Change the lines that say: #undef CONFIG_CONS_ON_SMC /* define if console on SMC */ #define CONFIG_CONS_ON_SCC /* define if console on SCC */ to #define CONFIG_CONS_ON_SMC /* define if console on SMC */ #undef CONFIG_CONS_ON_SCC /* define if console on SCC */

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[U-Boot-Users] Ethernet Interface Initialization in U-boot
by Swapnil Ashok Narkhede 14 Nov '05

14 Nov '05

I am trying to enable the Ethernet Interface on the board. The ethernet controller is SMC91111. After U-boot boots, i set the environment variables ethaddr to an ethernet address generated using gen_eth_addr and set netdev to eth0. After saving the environment i try to issue DHCP command so that i can get the IP addr from DHCP server. but when i issue DHCP command i get the output as data abort and the board is reset. When i tried to debug this, i found that before calling eth_init () eth_halt() is called. Within eth_halt() is call to smc_close(),which has a call to smc_shutdown(). Within smc_shutdown initially there is a call smc_select_bank(2). Upon calling this macro the boot loader sends data abort and resets the board. The GPIO's are properly configured. The same driver for SMC91111 works on the pxa255- Accelent board. What could be wrong in this case. Please help me resolve the issue. Regards, Swapnil Narkhede Mob:- 0432025023 Email:- s3092131(a)student.rmit.edu.au School of Computer Science and Information Technology RMIT University, Melbourne

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RE: [U-Boot-Users] Network problem in u-boot.
by André Berggren 14 Nov '05

14 Nov '05

Hi! Yes the mac is valid. I use 100Mbps FD and bootp to get an adress. U-boot gets IP 172.18.22.66 and netmask is 255.255.255.0 I´ll try to enable debugging later and post the results. //Andre -----Original Message----- From: Stefan Roese [mailto:sr@denx.de] Sent: den 14 november 2005 16:20 To: u-boot-users(a)lists.sourceforge.net Cc: Wolfgang Denk; André Berggren Subject: Re: [U-Boot-Users] Network problem in u-boot. On Monday 14 November 2005 16:12, Wolfgang Denk wrote: > > The problem is that sometimes the network in u-boot stops, e.g. just > > getting TTT in a tftp transfer. I foud out that this occurs when another > > packet not involed in the tftp fransfer arrives. It could be a > > TCP-connect attempt from another host to u-boot or a ARP request. With a > > network sniffer I can se that u-boot still send data, but all data > > ariving is never processed. A reset of the board is needed to get it up > > and running again. > > > > The board is a custom bord whith AMCC440ep based on bamboo. > > I cannot confirm this. I just tested approx. 20 downloads on a bamboo > board without any such problems. > > What exactly is your network configuration? 10 / 100 Mbps? FD / HD? > IP addresses? Netmask? And do you use a valid MAC address? Did you try to enable debugging in the 4xx ethernet driver? If not, please do this and post some results here. Viele Grüße, Stefan ########################################### This message has been scanned by F-Secure Anti-Virus for Microsoft Exchange. For more information, connect to http://www.f-secure.com/

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[U-Boot-Users] Network problem in u-boot.
by André Berggren 14 Nov '05

14 Nov '05

Hi all! I make a new post on the same problem since I found out some new info. The problem is that sometimes the network in u-boot stops, e.g. just getting TTT in a tftp transfer. I foud out that this occurs when another packet not involed in the tftp fransfer arrives. It could be a TCP-connect attempt from another host to u-boot or a ARP request. With a network sniffer I can se that u-boot still send data, but all data ariving is never processed. A reset of the board is needed to get it up and running again. The board is a custom bord whith AMCC440ep based on bamboo. //André ########################################### This message has been scanned by F-Secure Anti-Virus for Microsoft Exchange. For more information, connect to http://www.f-secure.com/

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[U-Boot-Users] I-cache and D-cache size problem on MPC859
by Sette Agostino 14 Nov '05

14 Nov '05

Hello, Now I have the U-Boot for MPC859, but I am not sure this line is correct U-Boot 1.1.3 (Nov 11 2005 - 16:38:24) CPU: MPC859TxxZPnnA at 133 MHz: 16 kB I-Cache 8 kB D-Cache FEC present As far as I know, the I-Cache and the D-Cache of the MPC859 is 4 kB, as defined in the MPC866UM Appendix F. Here is the chapter which describe the cache F.3 Cache Control Registers The MPC859T bit fields and commands of the cache control and status registers (IC_CST and DC_CST) are implemented the same as for the MPC866P. However, the bit fields of the cache address registers (IC_ADR and DC_ADR) and the cache data port registers (IC_DAT and DC_DAT) must be used for the 4-Kbyte instruction and data caches. See Chapter 7, "Instruction and Data Caches." We think that the MPC859 probably has phisically the same cache size as the MPC866, but only 4 kB must be used. Anyway, my question is, must I worry about the data printed on the screen or can I leave as they are? I mean, are these information used in other part of the U-Boot or the Kernel? Thanks in advance. Best Regards Agostino Sette

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[U-Boot-Users] How to change bootdelay?If I set bootdelay=0
by dalalilala hellokity 14 Nov '05

14 Nov '05

Hi, It is so unwise..... I set the env "bootdelay=0" Boot more quickly, everything seem like perfect. But, I can't hit any key to stop autoboot. Who knows how can I do? I really want to hit any key to stop autoboot!!!! Thanks in advance -- ____________________________________________________ Get your own Hello Kitty email @ www.sanriotown.com

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