January 2005 - U-Boot

RE: [U-Boot-Users] Re: [PATCH] !CFG_MEMTEST_SCRATCH - do not dereference NULL ptr
by VanBaren, Gerald (AGRE) 30 May '05

30 May '05

> -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net] On Behalf > Of Ladislav Michl > Sent: Thursday, November 25, 2004 6:22 AM > To: u-boot-users(a)lists.sourceforge.net > Subject: [U-Boot-Users] Re: [PATCH] !CFG_MEMTEST_SCRATCH - do > not dereference NULL ptr > > On Mon, Nov 22, 2004 at 12:07:18PM +0100, Wolfgang Denk wrote: > > There is no explanation what it does or which problem it is > supposed > > to fix. > > When CFG_MEMTEST_SCRATCH is undefined alternate memory test > in do_mem_mtest (with CFG_ALT_MEMTEST defined) dereferences > null pointer. It defines: > vu_long *dummy = NULL; > and later does: > *dummy = ~val; > > > There is also no CHANGELOG entry. > > CHANGELOG > * Patch by Ladislav Michl, 22 November 2004 > - Fix NULL pointer dereference in alternate memory test > (CFG_ALT_MEMTEST) > when if no CFG_MEMTEST_SCRATCH area defined > > Index: common/cmd_mem.c > =================================================================== > RCS file: /cvsroot/u-boot/u-boot/common/cmd_mem.c,v > retrieving revision 1.19 > diff -p -u -r1.19 cmd_mem.c > --- common/cmd_mem.c 10 Oct 2004 23:27:33 -0000 1.19 > +++ common/cmd_mem.c 22 Nov 2004 11:21:43 -0000 > @@ -646,8 +646,9 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int > vu_long num_words; > #if defined(CFG_MEMTEST_SCRATCH) > vu_long *dummy = (vu_long*)CFG_MEMTEST_SCRATCH; > +#define write_dummy(val) do { *dummy = ~val; } while (0) > #else > - vu_long *dummy = NULL; > +#define write_dummy(val) do { } while (0) > #endif > int j; > int iterations = 1; > @@ -723,7 +724,7 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int > val = bitpattern[j]; > for(; val != 0; val <<= 1) { > *addr = val; > - *dummy = ~val; /* clear the test data > off of the bus */ > + write_dummy(~val); /* clear the test > data off of the bus */ > readback = *addr; > if(readback != val) { > printf ("FAILURE (data line): " > @@ -731,11 +732,11 @@ int do_mem_mtest (cmd_tbl_t *cmdtp, int > val, readback); > } > *addr = ~val; > - *dummy = val; > + write_dummy(val); > readback = *addr; > if(readback != ~val) { > printf ("FAILURE (data line): " > - "Is %08lx, should be %08lx\n", > + "is %08lx, should be %08lx\n", > readback, ~val); > } > } Ladislav: You are fixing the problem in the wrong way. You should point "dummy" at a location in RAM that is writable rather than "fixing" the code by suppressing the dummy write. Being pedantic here, dummy isn't NULL, it is a pointer to the RAM location 0x00000000 (which just happens to be the same as NULL ;-). Strictly speaking, the assignment should have been written "vu_long *dummy = 0x00000000;". The problem here is that the code assumes 0x00000000 is writable and apparently this isn't the case on your board. It obviously is a good assumption on the other boards supported by u-boot (at least the ones that use this POST code :-). The proper fix is, for your board, change the assignment "vu_long *dummy = 0x00000000;" to point to writable RAM on your board. Suppressing the write to 0x00000000 will make the memory test ineffective on all boards (bad, really bad). The purpose of the "*dummy = ~val" statement is to discharge the data bus lines. The problem this is addressing is when the previous line "*addr = val" is executed, the data bus has on it the value "val". Since there is inherent capacitance on the bus lines, that value will persist (float) on the bus for a finite time, longer than it takes for a processor to do the "readback = *addr". The result is that, if the memory doesn't respond and the bus drivers remain tristated, you will think the memory responded properly because you read the residual charge on the bus. The write of "~val" to dummy is a throw-away operation whose purpose is to put something other than "val" on the bus so that a read of the target location won't give a false positive if the memory isn't working properly. Where "dummy" points is immaterial as long as "~val" gets out on the data bus. Normally you would point it in your RAM space, but you actually could point it anywhere that causes a valid write cycle on the data bus. Regards, gvb ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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[U-Boot-Users] Patch for ADSVIX single board computer with PXA27x processor
by Robert Whaley 08 Apr '05

08 Apr '05

This patch adds support for the ADSVIX SBC with PXA27x processor.

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[U-Boot-Users] Patch to update pxa-regs.h for PXA27x chips
by Robert Whaley 06 Apr '05

06 Apr '05

This patch updates the pxa-regs.h file for PXA27x chips

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[U-Boot-Users] PPC4xx: SDRAM detection (bug?)
by llandre 06 Apr '05

06 Apr '05

I have a question about SDRAM detection code (cpu/ppc4xx/sdram.c). I tested it with the following configurations: Configuration #1: 32 MB (2 chips), SDRAM clk = 133 MHz Configuration #2: 32 MB (2 chips), SDRAM clk = 111 MHz and everything worked fine. Then I tried the following: Configuration #3: 64 MB (2 chips), SDRAM clk = 111 MHz and the SDRAM does not work. U-Boot executes fine until it jumps to SDRAM after relocation. In this case, two chips K4S561632E-TI75 have been used. In my understanding the default value (0x07f00000) for the RTR register is wrong because these chips have a 64 ms/8k cycle refresh. Thus this register should be 0x03780000. I tried to change it but SDRAM did not work anyway. I suspect it is necessary to fix the TR register too or that the value for RTR is wrong. Any suggestions/remarks? TIA and best regards, llandre DAVE Electronics System House - R&D Department web: http://www.dave-tech.it email: r&d2(a)dave-tech.it

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[U-Boot-Users] [PATCH] test command bug.
by Hiroshi Ito 06 Apr '05

06 Apr '05

Hello, I'm new to this list. u-boot-1.1.2 ( cvs version ) # if test -z "" ; then echo true; else echo false; fi false # if test -n "" ; then echo true; else echo false; fi true # The logic is reversed. patch is attached. -------- Hiroshi Ito Media Lab. Inc., URL http://www.mlb.co.jp ( Sorry, Japanese only. ) TEL +81-3-5294-7255 FAX +81-3-5294-7256

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[U-Boot-Users] PATCH: m68k/mcf5282 udelay support
by Mathias Küster 04 Apr '05

04 Apr '05

Hello, this patch add udelay support for the mcf5282 cpu. Best Regards, Mathias --- time.c.orig 2004-06-09 17:24:19.000000000 +0200 +++ time.c 2004-11-07 09:51:07.000000000 +0100 @@ -126,6 +126,28 @@ void udelay(unsigned long usec) { + volatile unsigned short *timerp; + uint tmp; + + timerp = (volatile unsigned short *) (CFG_MBAR + MCFTIMER_BASE3); + + while (usec > 0) { + if (usec > 65000) + tmp = 65000; + else + tmp = usec; + usec = usec - tmp; + + /* Set up TIMER 3 as timebase clock */ + timerp[MCFTIMER_PCSR] = MCFTIMER_PCSR_OVW; + timerp[MCFTIMER_PMR] = 0; + /* set period to 1 us */ + timerp[MCFTIMER_PCSR] = + (5 << 8) | MCFTIMER_PCSR_EN | MCFTIMER_PCSR_OVW; + + timerp[MCFTIMER_PMR] = tmp; + while (timerp[MCFTIMER_PCNTR] > 0); + } } void timer_init (void)

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[U-Boot-Users] PATCH: CSB472 board incorrect CPLD base address
by Tolunay Orkun 04 Apr '05

04 Apr '05

This patch fixes the incorrect chip select base address programming for on board Xilinx CPLD due to incorrect value documented in Table 7 of Cogent CSB472 H/W Reference Manual - 4/8/03. The value was in conflict with references in Table 1 and Table 2 in the very same manual. CHANGELOG: * Patch by Tolunay Orkun, 16 November 2004 - fix incorrect onboard Xilinx CPLD base address

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[U-Boot-Users] Patch: Add support for A&M Rattler boards
by Yuli Barcohen 04 Apr '05

04 Apr '05

The attached patch adds support for Analogue & Micro Rattler boards. It was tested on Rattler8248. CHANGELOG: Add support for Analogue & Micro Rattler boards. Tested on Rattler8248. -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] common/lcd.c patch
by Andre Renaud 04 Apr '05

04 Apr '05

There is a minor bug in common/lcd.c: if you do not define CONFIG_MPC823, it does not include watchdog.h, but WATCHDOG_RESET is used several times in the code outside of #ifdef blocks. Moving the #include statement out of the #ifdef block fixes it. I've attached what I think it the appropriate patch. Andre Renaud

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[U-Boot-Users] [PATCH] MPC8245 vs XPC8245
by Marc Leeman 04 Apr '05

04 Apr '05

-- ash nazg durbatulûk, ash nazg gimbatul, ash nazg thrakatulûk agh burzum-ishi krimpatul

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