January 2005 - U-Boot

RE: [U-Boot-Users] How to set the Ethernet Address for LXT971A.
by Bharath G - CTD , Chennai 15 Jan '05

15 Jan '05

Hi Prathima, If you want to configure your PHY, you will need see how your Processor is interfaced with the PHY.I use a MPC8270 based custom board and i use a FPGA to configure my PHY. If you are using the processors port pins for your PHY Management, see /common/miiphybb.c to use bit banging, Set your MACROS for bit banging in your include/configs/board-header-file.h . Hope this helps, Cheers, .Bharath. Everything has its beauty but not everyone sees it. Confucius -----Original Message----- From: Prathima_Kolar [mailto:Prathima_Kolar@Satyam.com] Sent: Saturday, January 15, 2005 10:47 AM To: u-boot-users(a)lists.sourceforge.net Subject: [U-Boot-Users] How to set the Ethernet Address for LXT971A. Hello All, I am customizing U-boot for the Ethernet interface in our 8266 based PMC Addin board. We are using the Intel LXT971A Ethernet chip. Can anyone please let me know how and where to set the Ethernet Address in U-boot? Thanks and Regards, Prathima Kolar. ************************************************************************** This email (including any attachments) is intended for the sole use of the intended recipient/s and may contain material that is CONFIDENTIAL AND PRIVATE COMPANY INFORMATION. Any review or reliance by others or copying or distribution or forwarding of any or all of the contents in this message is STRICTLY PROHIBITED. If you are not the intended recipient, please contact the sender by email and delete all copies; your cooperation in this regard is appreciated. ************************************************************************** ------------------------------------------------------- The SF.Net email is sponsored by: Beat the post-holiday blues Get a FREE limited edition SourceForge.net t-shirt from ThinkGeek. It's fun and FREE -- well, almost....http://www.thinkgeek.com/sfshirt _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users DISCLAIMER This message and any attachment(s) contained here are information that is confidential, proprietary to HCL Technologies and its customers. Contents may be privileged or otherwise protected by law. The information is solely intended for the individual or the entity it is addressed to. If you are not the intended recipient of this message, you are not authorized to read, forward, print, retain, copy or disseminate this message or any part of it. If you have received this e-mail in error, please notify the sender immediately by return e-mail and delete it from your computer

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[U-Boot-Users] MPC8540ADS BDI2000 Configuration File
by Jeff Stevens 14 Jan '05

14 Jan '05

Does anyone have a config file for the BDI2000 that is suitable for debugging U-Boot on an MPC8540ADS? Thanks, Jeff Stevens jsteve17(a)yahoo.com __________________________________ Do you Yahoo!? Yahoo! Mail - Helps protect you from nasty viruses. http://promotions.yahoo.com/new_mail

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Re: [U-Boot-Users] Problem with IXDP425 u-boot.
by Wolfgang Denk 14 Jan '05

14 Jan '05

Dear Herb, in message <1105551343.13808.475.camel(a)hr2600.symbium.com> you wrote: > > > > I'm using ELDK 3.1 from which I installed support for the > > > "arm-linux" target (not clearly documented I must say) which > > > > What exactly is "not clearly documented"? I'd like to improve this. > > > Wolfgang, the README file in ELDK3.1 says to specify a <cpu_family> so I > tried "XScale" and got a failure. I had to go to the "Working with ELDK" > section to find out that there is in fact ONLY ONE possible choice for > <cpu_family> and it is used by all ARM targets! I see. Will fix this ASAP. > Of course it makes me nervous, and when I look in u-boot.map it's not > attributed to the local u-boot tree! Here's the u-boot.map line: > > /opt/eldkarm31/usr/bin/../lib/gcc-lib/arm-linux/3.3.3/libgcc.a(_umodsi3.o) This is indeed an interesting hint. Especially when you look at this object file: -> arm-linux-objdump -D libgcc.a ... _umodsi3.o: file format elf32-littlearm ------------------------------------------^^^^^^^^^ Disassembly of section .text: 00000000 <__umodsi3>: 0: e3510000 cmp r1, #0 ; 0x0 4: 0a00002a beq b0 <__umodsi3+0xb0> 8: e3510001 cmp r1, #1 ; 0x1 c: 11500001 cmpne r0, r1 10: 03a00000 moveq r0, #0 ; 0x0 14: 312fff1e bxcc lr 18: e3a03001 mov r3, #1 ; 0x1 1c: e3510201 cmp r1, #268435456 ; 0x10000000 20: 31510000 cmpcc r1, r0 24: 31a01201 movcc r1, r1, lsl #4 28: 31a03203 movcc r3, r3, lsl #4 This explains why you see bogus code - this file is for little endian systems, while your board is built for bigendian mode. Mixing these two doesn't make much sense. > > > This is part of the software floating point support for IXP425. > > > > No, this has nothing to do with FP support. It's a simple division > > routine. > OK, then why does my IXP425 switch to Thumb mode when it executes: > > 28: e3510102 cmp r1, #-2147483648 ; 0x80000000 Because it doesn't understand that this is actually a "cmp r1, #0" instruction in wrong endianess. > Any ideas? Yes. Find out why we use libgcc.a(_umodsi3.o) instead of lib_arm/libarm.a(_umodsi3.o) when building for bigendian systems. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd(a)denx.de Let's say the docs present a simplified view of reality... :-) - Larry Wall in <6940(a)jpl-devvax.JPL.NASA.GOV>

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[U-Boot-Users] Hard Coded Configuration in OMAP5912OSK
by Michael Bendzick 14 Jan '05

14 Jan '05

I was working with the omap5912osk board today, and noticed that the include/configs/omap5912osk.h file contains the following lines: #define CONFIG_BOOTARGS "mem=32M console=ttyS0,115200n8 noinitrd \ root=/dev/nfs rw nfsroot=157.87.82.48:\ /home/mwd/myfs/target ip=dhcp" #define CONFIG_NETMASK 255.255.254.0 /* talk on MY local net */ #define CONFIG_IPADDR 156.117.97.156 /* static IP I currently own */ #define CONFIG_SERVERIP 156.117.97.139 /* current IP of my dev pc */ #define CONFIG_BOOTFILE "uImage" /* file to load */ Most of the bootargs should probably stay, but I really don't think that a single person's development environment should be reflected in the standard source. I intend on submitting a patch (to use the CFI driver) for this configuration file already, and I think I'll at least comment out the last 4 lines. For users of this board, is there something that would be more useful and generic to put in the bootargs? -Michael Bendzick

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[U-Boot-Users] Re: Questions about startup code for S3C44B0 CPU-core
by Andrea Scian 14 Jan '05

14 Jan '05

Hi Alex, >Hi Andrea, > thank you for your explanation but the stacks of EXCEPTION MODEs > which we discussed about >is still not very clear. U-boot here does not use interrupts,so there is >no need for such >initialization for interrupts,but we can"t insure that there is no core >exception.In case of >these exception,the system may go wrong. So I think that we should >initialize the stacks for >those exceptions. BTW, even if not used into the bootloader, interrupt vector are initialized by u-boot (take a look at cpu/s3c44b0/start.S) >And there is no initialization in linux, either.What should linux do in >case of these >exceptions. So there is the initialization in other common start codes of >s3c44b0x. Something is still not clear to me... could you please tell me where I can find some example of such code (or where this initialization is explained into the ARM or Samsung manual)? Thanks. Best Regards, Andrea Scian

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[U-Boot-Users] Global Data Pointer
by Peter Pearse 14 Jan '05

14 Jan '05

Hi I don't understand the way the global data pointer (gd) is implemented in u-boot. Why is declared as a local register variable (in functions that access it), rather than a global register variable? I know this more a gcc question, rather than u-boot, but perhaps someone in the group has time to enlighten me, or point me to some documentation. Regards Peter

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[U-Boot-Users] newbie problems?
by Eason Lee 14 Jan '05

14 Jan '05

Hello everybody, I'm a newbie for u-boot. I wanna port u-boot to a lubbock-like (pxa255) board, however I got some problems. 1, I don't understand what is TEXT_BASE mean in u-boot. My sdram start at 0xa0000000 and flash start at 0x00000000 in my board, so the TEXT_BASE seems to set 0xa0000000, is it correct? 2, Because I ported u-boot without using any BDI2000-like debugger, so there has anyother debugger methods for me. 3. Mybe, I shall study some extra references. Where can find it? Thanks in advance!! -- Eason

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[U-Boot-Users] MPC8540 Custom Board _start_e500
by Jeff Stevens 13 Jan '05

13 Jan '05

I am in the process of bringing up a custom SBC with an MPC8540. I am using the BDI2000 to debug. When I trace through the code, the system halts in _start_e500 in start.S where it invalidates MMU L1/L2. I have a Rev 1 processor, and the errata is included at the top of _start_e500. It seems to fail at isync. I have included some screen captures from the BDI2000 and the source. BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff14c Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff150 Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 BDI>ti - Core status is 0x0041 *** Core is stopped, no restart possible # PPC: timeout while waiting for halt BDI> Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : COP freeze Current PC : 0x00000000 Current CR : 0x00000000 Current MSR : 0x00000000 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 # Step timeout detected BDI> start.S /* * Invalidate MMU L1/L2 * * Note: There is a fixup earlier for Errata CPU4 on * Rev 1 parts that must precede this MMU invalidation. */ li r2, 0x001e mtspr MMUCSR0, r2 isync start.S objdump: 140: 38 20 20 00 li r1,8192 144: 7c 3f 63 a6 mtspr 415,r1 148: 38 40 00 1e li r2,30 14c: 7c 54 fb a6 mtiac1 r2 150: 4c 00 01 2c isync 154: 38 60 00 04 li r3,4 Could the initializationt that the BDI does be interfering here? Any help would be greatly appreciated. Thanks, Jeff Stevens __________________________________ Do you Yahoo!? Yahoo! Mail - 250MB free storage. Do more. Manage less. http://info.mail.yahoo.com/mail_250

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[U-Boot-Users] PATCH: Recognize PPC440GX Rev C
by Chris Love 13 Jan '05

13 Jan '05

CHANGELOG: * Patch by Chris Love, 13 January 2005 - Recognize PPC440GX Rev C -- Chris Love // Continuous Computing Corporation love(a)ccpu.com // http://www.ccpu.com --- u-boot.orig/include/asm-ppc/processor.h 2004-10-10 16:27:36.000000000 -0700 +++ u-boot/include/asm-ppc/processor.h 2005-01-13 08:45:14.000000000 -0800 @@ -718,6 +718,7 @@ #define PVR_440GP_RC 0x40120481 #define PVR_440GX_RA 0x51B21850 #define PVR_440GX_RB 0x51B21851 +#define PVR_440GX_RC 0x51B21892 #define PVR_405EP_RB 0x51210950 #define PVR_601 0x00010000 #define PVR_602 0x00050000 --- u-boot.orig/cpu/ppc4xx/cpu.c 2004-03-14 14:25:47.000000000 -0800 +++ u-boot/cpu/ppc4xx/cpu.c 2005-01-13 07:15:57.000000000 -0800 @@ -175,6 +175,9 @@ case PVR_440GX_RB: puts("X Rev. B"); break; + case PVR_440GX_RC: + puts("X Rev. C"); + break; default: printf ("UNKNOWN (PVR=%08x)", pvr); break;

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[U-Boot-Users] MPC8540 Custom Board _start_e500
by Jeff Stevens 13 Jan '05

13 Jan '05

I am in the process of bringing up a custom SBC with an MPC8540. I am using the BDI2000 to debug. When I trace through the code, the system halts in _start_e500 in start.S where it invalidates MMU L1/L2. I have a Rev 1 processor, and the errata is included at the top of _start_e500. It seems to fail at isync. I have included some screen captures from the BDI2000 and the source. BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff14c Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 BDI>ti Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : single step Current PC : 0xfffff150 Current CR : 0x40000000 Current MSR : 0x00000200 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 BDI>ti - Core status is 0x0041 *** Core is stopped, no restart possible # PPC: timeout while waiting for halt BDI> Target CPU : MPC8560/8540 Rev.2 Target state : halted Debug entry cause : COP freeze Current PC : 0x00000000 Current CR : 0x00000000 Current MSR : 0x00000000 Current LR : 0x00000000 Current CCSRBAR : 0x40000000 # Step timeout detected BDI> start.S /* * Invalidate MMU L1/L2 * * Note: There is a fixup earlier for Errata CPU4 on * Rev 1 parts that must precede this MMU invalidation. */ li r2, 0x001e mtspr MMUCSR0, r2 isync start.S objdump: 140: 38 20 20 00 li r1,8192 144: 7c 3f 63 a6 mtspr 415,r1 148: 38 40 00 1e li r2,30 14c: 7c 54 fb a6 mtiac1 r2 150: 4c 00 01 2c isync 154: 38 60 00 04 li r3,4 Could the initializationt that the BDI does be interfering here? Any help would be greatly appreciated. Thanks, Jeff Stevens __________________________________ Do you Yahoo!? The all-new My Yahoo! - Get yours free! http://my.yahoo.com

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