January 2005 - U-Boot

[U-Boot-Users] IXDP size comments and board reset issue
by Ara Avanesyan 20 Jan '05

20 Jan '05

Hi all, i am confused by the following comments: 1. board/ixdp425/flash.c switch (value) { case (FPW) INTEL_ID_28F128J3A: info->flash_id += FLASH_28F128J3A; info->sector_count = 128; info->size = 0x02000000; break; /* => 16 MB */ the comment shows 16 mb (correctly) while it's assigned 32 mb 2. configs/ixdp425.h /* * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 2 banks of DRAM */ defined 1 but commented 2 banks. am i missing something? Also I have another issue regarding to reset. After linux reboot, it calls hardware reset (arch_reset). My board hangs. The same linux build resets fine with RedBoot. Is there anything specific here? (i do not have debugger to debug it myself :( ) Thanks! Ara

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[U-Boot-Users] U-boot and linux memory map
by Terence Soh 20 Jan '05

20 Jan '05

Hi U-boot collective, I am using a NS9750 development board running U-boot. The booting sequence now is load via a SPI-EEPROM first which then loads the u-bootloader into the SDRAM and executes u-bootloader from SDRAM. I wish to boot from the flash instead and have some questions about the memory map. The documentation in ARM Linux recommended zImage to loaded to 0x8000 and InitRD to 0x800000. However, u-bootloader is gun-zipping the zImage to the SDRAM so is there memory address recommended for a unzipped Image? Similarly is there a recommended address for the INITRD? U-bootloader will be writing the ATAG parameters I think at 0x100. Is u-bootloader also going to setup the zero page exception vectors and page tables? Thank you in advance, Terence

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[U-Boot-Users] u-boot.lds questions
by Peter Asemann 19 Jan '05

19 Jan '05

I've "successfully" built my u-boot port (it doesn't throw warnings/error). To do so I just copied some u-boot.lds from some other port. I know that the u-boot.lds is a linker script that instructs the linker to put code elements together in some specific way. At least the first part does so. But the lower parts of the u-boot.lds I copied seem to be increasingly deep magic. So... what does the u-boot.lds do exactly and what happens if mine is wrong/broken? And why do I need it anyway? The built put out the following things in the main directory: -rwxr-x--- 1234997 Jan 19 12:51 u-boot -rwxr-x--- 171372 Jan 19 12:51 u-boot.bin -rw-r----- 94836 Jan 19 12:51 u-boot.map -rwxr-x--- 514202 Jan 19 12:51 u-boot.srec there are some parts that probably are important in board/esm (my board's directory) too: -rw-r----- 17000 Jan 17 16:05 esm.o -rw-r----- 17176 Jan 17 16:05 libesm.a Does that look reasonable/good? Peter Asemann

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[U-Boot-Users] Commad History Buffer Feature
by Mahesh Devagiri 19 Jan '05

19 Jan '05

Hi Sir/Madam, I am looking for command history buffer feature in uboot code; does the new version of uboot support the command history buffer feature? If so which file do I need to refer? (Command History Buffer capable of holding one or more of most recent commands) With Regards Mahesh Devagiri

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[U-Boot-Users] PCI Interrupt
by Marco Schramel 19 Jan '05

19 Jan '05

Hi, Our custom board is designed with a mpc8270. U-Boot is running on it. The pci-bridge on the 8270 seems to be initialized. The pci command works and shows me the bridge. On the pci-bus is a pci target connect. Its interrupt is routed to IRQ2. How i can tell U-Boot that my pci interrupt is IRQ2 ?? Thanks in advance Marco Schramel -- --------- Marco Schramel R&D Bartec GmbH Schulstr. 30 94239 Gotteszell, Germany www.bartec.de Marco.Schramel(a)go.bartec.de Phone: +49 (0)9929/301332 Fax: +49 (0)9929/301112

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[U-Boot-Users] MPC8540 DataTLBError
by Jeff Stevens 18 Jan '05

18 Jan '05

I have a custom board with an MPC8540 processor. U-Boot always ends up at 0xfff81400 (DataTLBError). I traced it through and found that the first time it enters DataTLBError is at the end of _start (in cpu/mpc85xx/start.S) in the loop (1:) where it is allocating the Initial RAM in data cache. I traped the CPU before that loop and then I placed an infinite loop right after that loop and it never gets there. I then traced back into _start right after that loop and told it to run again, and it went back into DataTLBError at a later point in the code. So is this a problem with my tlb1_entry table? I also read online that there was a patch submitted on 6/17/2004 to fix this, do I need this? I updated my U-Boot development tree today over CVS. Is that patch already in there? Any help would be greatly appreciated. Here is my tbl1_entry. All I did was alter the MPC8540ADS init.S file to get mine (I don't have any BCSRs or SDRAM on the LBC). tlb1_entry: entry_start /* * Number of TLB0 and TLB1 entries in the following table */ .long 12 #if (CFG_CCSRBAR_DEFAULT != CFG_CCSRBAR) /* * TLB0 4K Non-cacheable, guarded * 0xff700000 4K Initial CCSRBAR mapping * * This ends up at a TLB0 Index==0 entry, and must not collide * with other TLB0 Entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR_DEFAULT), 0,0,0,0,0,1,0,1,0,1) #else #error("Update the number of table entries in tlb1_entry") #endif /* * TLB0 16K Cacheable, non-guarded * 0xd001_0000 16K Temporary Global data for initialization * * Use four 4K TLB0 entries. These entries must be cacheable * as they provide the bootstrap memory before the memory * controler and real memory have been configured. * * These entries end up at TLB0 Indicies 0x10, 0x14, 0x18 and 0x1c, * and must not collide with other TLB0 entries. */ .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 4 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 8 * 1024), 0,0,0,0,0,1,0,1,0,1) .long TLB1_MAS0(0, 0, 0) .long TLB1_MAS1(1, 0, 0, 0, 0) .long TLB1_MAS2(E500_TLB_EPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_INIT_RAM_ADDR + 12 * 1024), 0,0,0,0,0,1,0,1,0,1) /* * TLB 0: 64M Non-cacheable, guarded * 0xfc000000 64M FLASH (First Half) * Out of reset this entry is only 4K. */ .long TLB1_MAS0(1, 0, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE), 0,0,0,0,0,1,0,1,0,1) /* * TLB 1: 64M Non-cacheable, guarded * 0xf8000000 64M FLASH (Second Half) */ .long TLB1_MAS0(1, 1, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_FLASH_BASE + 0x04000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_FLASH_BASE + 0x04000000), 0,0,0,0,0,1,0,1,0,1) /* * TLB 2: 256M Non-cacheable, guarded * 0x80000000 256M PCI1 MEM First half */ .long TLB1_MAS0(1, 2, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* * TLB 3: 256M Non-cacheable, guarded * 0x90000000 256M PCI1 MEM Second half */ .long TLB1_MAS0(1, 3, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_PCI1_MEM_BASE + 0x10000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_PCI1_MEM_BASE + 0x10000000), 0,0,0,0,0,1,0,1,0,1) /* * TLB 4: 256M Non-cacheable, guarded * 0xc0000000 256M Rapid IO MEM First half */ .long TLB1_MAS0(1, 4, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE), 0,0,0,0,0,1,0,1,0,1) /* * TLB 5: 256M Non-cacheable, guarded * 0xd0000000 256M Rapid IO MEM Second half */ .long TLB1_MAS0(1, 5, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_RIO_MEM_BASE + 0x10000000), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_RIO_MEM_BASE + 0x10000000), 0,0,0,0,0,1,0,1,0,1) /* * TLB 6: 64M Non-cacheable, guarded * 0xe000_0000 1M CCSRBAR * 0xe200_0000 16M PCI1 IO */ .long TLB1_MAS0(1, 6, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_64M) .long TLB1_MAS2(E500_TLB_EPN(CFG_CCSRBAR), 0,0,0,0,1,0,1,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_CCSRBAR), 0,0,0,0,0,1,0,1,0,1) #if !defined(CONFIG_SPD_EEPROM) /* * TLB 7: 256M DDR * 0x00000000 256M DDR System memory * Without SPD EEPROM configured DDR, this must be setup manually. * Make sure the TLB count at the top of this table is correct. * Likely it needs to be increased by two for these entries. */ #error("Update the number of table entries in tlb1_entry") .long TLB1_MAS0(1, 8, 0) .long TLB1_MAS1(1, 1, 0, 0, BOOKE_PAGESZ_256M) .long TLB1_MAS2(E500_TLB_EPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,0,0,0) .long TLB1_MAS3(E500_TLB_RPN(CFG_DDR_SDRAM_BASE), 0,0,0,0,0,1,0,1,0,1) #endif entry_end __________________________________ Do you Yahoo!? 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[U-Boot-Users] starting with u-boot
by Zhu Yong 17 Jan '05

17 Jan '05

Hi, I am a newbie to u-boot as well as embedded system development, I have problem to port u-boot to my board. I have a customized board with Motorola MC9328MXL processor, which is the same as mx1ads board. The hardware configurations as below: CPU: Motorola Dragon Ball MXL microcontroller (ARM920T CPU Core) CPU Core speed 192MHZ and System Speed 96MHz RAM: 8M bytes Ram address: 0x08000000 ---- 0x08800000 Flash: 2M Bytes For bootup, 0x00000000 -- 0x00200000 For normal working, 0x10000000 -- 0x10200000 I/O: 1 Serial at UART 1 1 USB slave No Ethernet According to the above configs, I did the following modification to mx1ads.h #define CFG_MEMTEST_START 0x08100000 /* memtest works on */ #define CFG_MEMTEST_END 0x08800000 /* 7 MB in DRAM */ #define CFG_LOAD_ADDR 0x08400000 /* default load address */ /*----------------------------------------------------------------------- * Physical Memory Map */ #define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of SDRAM */ #define PHYS_SDRAM_1 0x08000000 /* SDRAM on CSD0 */ #define PHYS_SDRAM_1_SIZE 0x00800000 /* 8 MB */ #define CFG_MAX_FLASH_BANKS 1 /* 1 bank of SyncFlash */ #define CFG_FLASH_BASE 0x00000000 /* SyncFlash on CSD1 */ #define FLASH_BANK_SIZE 0x00200000 /* 2 MB Total */ /*----------------------------------------------------------------------- * FLASH and environment organization */ #define CONFIG_SYNCFLASH 1 #define PHYS_FLASH_SIZE 0x00200000 #define CFG_MAX_FLASH_SECT (8) #define CFG_ENV_ADDR (CFG_FLASH_BASE+0x00080000) #define CFG_ENV_IS_IN_FLASH 1 #define CFG_ENV_SIZE 0x04000 /* Total Size of Environment Sector */ #define CFG_ENV_SECT_SIZE 0x040000 After compilation, I download the u-boot.bin to 0x08000000 with Trace32 Then set PC to 0x08000000 and run But how can I know it running ok? The serial port doesn't have any data ( I monitored with oscilloscope) And from the Trace32 Debugger, the CPU will keep looping at some point.

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[U-Boot-Users] u-boot-related but maybe off-topic question
by Peter Asemann 17 Jan '05

17 Jan '05

Ehm... first of all I want to beg for pardon for posting this maybe rather off-topic question. It's just that I'm not sure about how to program the memory controller of my MPC875 in the u-boot: Though it seems possible to issue only one refresh command each time the memory refresh timer expires, it seems to be common to have the refresh-timer expire more seldom and issue more refresh-commands in a row each time to compensate for this. Issuing a refresh-command is only possible in "all banks precharge" state, the sdram memory datasheet says. So what I need to know is: Which operations cause a memory bank to be "un-pre-charged"? I can't find that information anywhere, it's like it's so trivial that noone mentions it. Thanks for your time, Peter Asemann

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[U-Boot-Users] How to set the Ethernet Address for LXT971A.
by Prathima_Kolar 16 Jan '05

16 Jan '05

Hello All, I am customizing U-boot for the Ethernet interface in our 8266 based PMC Addin board. We are using the Intel LXT971A Ethernet chip. Can anyone please let me know how and where to set the Ethernet Address in U-boot? Thanks and Regards, Prathima Kolar. ************************************************************************** This email (including any attachments) is intended for the sole use of the intended recipient/s and may contain material that is CONFIDENTIAL AND PRIVATE COMPANY INFORMATION. Any review or reliance by others or copying or distribution or forwarding of any or all of the contents in this message is STRICTLY PROHIBITED. If you are not the intended recipient, please contact the sender by email and delete all copies; your cooperation in this regard is appreciated. **************************************************************************

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[U-Boot-Users] mpc4774
by Dave Laurin 16 Jan '05

16 Jan '05

I would like to use u-boot for a mpc4774 and I am looking for the gnu cross development tools to run on x86/linux. If someone has already set them up I would appreciate a link to the tools. Thank you

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