August 2004 - U-Boot

[U-Boot-Users] [PATCH] - Added 8 and 16 bit mode access for System ACE CF
by Sean Chang 30 Sep '04

30 Sep '04

Hi, If there is any problems please let me know and I'll be more than happy to fix it. This patch is applied against the u-boot 1.1.1 release. The CHANGELOG is below. Regards, Sean ======================================================================= CHANGELOG (ace_cmd.patch): Patch by Sean Chang, 9 Aug 2004: Added support for both 8 and 16 bit mode access to System ACE CF through MPU. =======================================================================

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[U-Boot-Users] [PATCH] - "saveenv" and "do_saveenv" compile synch
by Sean Chang 30 Sep '04

30 Sep '04

Hi, If there is any problems please let me know and I'll be more than happy to fix it. This patch is applied against the u-boot 1.1.1 release. The CHANGELOG is below. Regards, Sean ======================================================================= CHANGELOG (nvedit.patch): Patch by Sean Chang, 9 Aug 2004: Synch defines for saveenv and do_saveenv functions so they get compiled under the same statement. =======================================================================

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[U-Boot-Users] [PATCH] - I2C and EEPROM support for ML300
by Sean Chang 30 Sep '04

30 Sep '04

Hi, If there are any problems please let me know and I'll be more than happy to fix it. This patch is applied against the u-boot 1.1.1 release. The CHANGELOG is below: Regards, Sean ======================================================================= CHANGELOG (eeprom.patch): Patch by Sean Chang, 9 Aug 2004: Added I2C support for ML300. Added support for ML300 to read out its environment information stored on the EEPROM. Added support to use board specific parameters as part of U-Boot's environment information. Updated MLD files to support configuration for new features above. =======================================================================

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[U-Boot-Users] 440gx_enet.c patch for use with netconsole
by Travis Sawyer 30 Sep '04

30 Sep '04

This patch fixes the 440gx_enet driver for use with netconsole, as well as a ZMII/RMII bridge fix. The maintainer of the 405gp_enet driver may want to back port the 'netconsole' fix as well. These changes were tested on the IBM 440GX reference board (ocotea). CHANGELOG entry: * Patches by Travis Sawyer, 5 Aug 2004: - Remove incorrect bridge settings for eth group 6 - Add call to setup bridge in ppc_440x_eth_initialize - Fix ppc_440x_eth_init to reset the phy only if its the first time through, otherwise, just check the phy for the autonegotiated speed/duplex. This allows the use of netconsole - only print the speed/duplex the first time the phy is reset. Wolfgang: NetConsole is very much appreciated! -travis

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[U-Boot-Users] [PATCH] MPC85XX i2c patches
by Jon Loeliger 28 Sep '04

28 Sep '04

Wolfgang, Here is a patch for the cpu/mpc85xx/i2c.c file that converts some long reads into byte reads. I also removed the superfluous DEB() macro. Since this file was all crummy 2-space indented, I TAB-ified it all. Hope that is OK. * Patch by Jon Loeliger, 15-Jul-2004: Fixes MPC85xx I2C driver: - Matt McClintock's conversion from long to byte IO - Remove redundant DEB() debug macro. TAB indenting. This should apply with a patch -p2, likely. Thanks, jdl --- u-boot-public-cvs/u-boot-20040712/cpu/mpc85xx/i2c.c 2003-10-15 18:53:51.000000000 -0500 +++ internal-development/u-boot-pq3-merged/cpu/mpc85xx/i2c.c 2004-07-14 10:57:36.000000000 -0500 @@ -30,78 +30,57 @@ #include <common.h> #include <command.h> - -#define DEBUG - -#if defined(DEBUG) -#define DEB(x) x -#else -#define DEB(x) -#endif +#include <asm/io.h> #ifdef CONFIG_HARD_I2C #include <i2c.h> #define TIMEOUT (CFG_HZ/4) -#define I2C_Addr ((unsigned *)(CFG_CCSRBAR + 0x3000)) +#define I2C_Addr ((u8 *)(CFG_CCSRBAR + 0x3000)) #define I2CADR &I2C_Addr[0] -#define I2CFDR &I2C_Addr[1] -#define I2CCCR &I2C_Addr[2] -#define I2CCSR &I2C_Addr[3] -#define I2CCDR &I2C_Addr[4] -#define I2CDFSRR &I2C_Addr[5] +#define I2CFDR &I2C_Addr[4] +#define I2CCCR &I2C_Addr[8] +#define I2CCSR &I2C_Addr[12] +#define I2CCDR &I2C_Addr[16] +#define I2CDFSRR &I2C_Addr[20] #define I2C_READ 1 #define I2C_WRITE 0 -/* taken from linux include/asm-ppc/io.h */ -inline unsigned in_le32(volatile unsigned *addr) +void +i2c_init(int speed, int slaveadd) { - unsigned ret; + /* stop I2C controller */ + writeb(0x0, I2CCCR); - __asm__ __volatile__("lwbrx %0,0,%1;\n" - "twi 0,%0,0;\n" - "isync" : "=r" (ret) : - "r" (addr), "m" (*addr)); - return ret; -} + /* set clock */ + writeb(0x3f, I2CFDR); -inline void out_le32(volatile unsigned *addr, int val) -{ - __asm__ __volatile__("stwbrx %1,0,%2; eieio" : "=m" (*addr) : - "r" (val), "r" (addr)); -} + /* set default filter */ + writeb(0x10,I2CDFSRR); -#define writel(val, addr) out_le32(addr, val) -#define readl(addr) in_le32(addr) + /* write slave address */ + writeb(slaveadd, I2CADR); -void -i2c_init(int speed, int slaveadd) -{ - /* stop I2C controller */ - writel (0x0, I2CCCR); - /* set clock */ - writel (0x3f, I2CFDR); - /* set default filter */ - writel (0x10,I2CDFSRR); - /* write slave address */ - writel (slaveadd, I2CADR); - /* clear status register */ - writel (0x0, I2CCSR); - /* start I2C controller */ - writel (MPC85xx_I2CCR_MEN, I2CCCR); + /* clear status register */ + writeb(0x0, I2CCSR); + + /* start I2C controller */ + writeb(MPC85xx_I2CCR_MEN, I2CCCR); } static __inline__ int i2c_wait4bus (void) { - ulong timeval = get_timer (0); + ulong timeval = get_timer (0); - while (readl (I2CCSR) & MPC85xx_I2CSR_MBB) - if (get_timer (timeval) > TIMEOUT) - return -1; + while (readb(I2CCSR) & MPC85xx_I2CSR_MBB) { + if (get_timer (timeval) > TIMEOUT) { + return -1; + } + } return 0; } @@ -109,153 +88,151 @@ static __inline__ int i2c_wait (int write) { - u32 csr; - ulong timeval = get_timer (0); + u32 csr; + ulong timeval = get_timer (0); - do - { - csr = readl (I2CCSR); - - if (!(csr & MPC85xx_I2CSR_MIF)) - continue; - - writel (0x0, I2CCSR); - - if (csr & MPC85xx_I2CSR_MAL) - { - DEB(printf ("i2c_wait: MAL\n")); - return -1; - } + do { + csr = readb(I2CCSR); - if (!(csr & MPC85xx_I2CSR_MCF)) - { - DEB(printf ("i2c_wait: unfinished\n")); - return -1; - } + if (!(csr & MPC85xx_I2CSR_MIF)) + continue; - if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) - { - DEB(printf ("i2c_wait: No RXACK\n")); - return -1; - } + writeb(0x0, I2CCSR); + + if (csr & MPC85xx_I2CSR_MAL) { + debug("i2c_wait: MAL\n"); + return -1; + } + + if (!(csr & MPC85xx_I2CSR_MCF)) { + debug("i2c_wait: unfinished\n"); + return -1; + } + + if (write == I2C_WRITE && (csr & MPC85xx_I2CSR_RXAK)) { + debug("i2c_wait: No RXACK\n"); + return -1; + } - return 0; - } while (get_timer (timeval) < TIMEOUT); + return 0; + } while (get_timer (timeval) < TIMEOUT); - DEB(printf ("i2c_wait: timed out\n")); - return -1; + debug("i2c_wait: timed out\n"); + return -1; } static __inline__ int i2c_write_addr (u8 dev, u8 dir, int rsta) { - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | - (rsta?MPC85xx_I2CCR_RSTA:0), I2CCCR); + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX | + (rsta?MPC85xx_I2CCR_RSTA:0), + I2CCCR); - writel ((dev << 1) | dir, I2CCDR); + writeb((dev << 1) | dir, I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) - return 0; + if (i2c_wait (I2C_WRITE) < 0) + return 0; - return 1; + return 1; } static __inline__ int __i2c_write (u8 *data, int length) { - int i; + int i; - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, I2CCCR); + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | MPC85xx_I2CCR_MTX, + I2CCCR); - for (i=0; i < length; i++) - { - writel (data[i], I2CCDR); + for (i=0; i < length; i++) { + writeb(data[i], I2CCDR); - if (i2c_wait (I2C_WRITE) < 0) - break; - } + if (i2c_wait (I2C_WRITE) < 0) + break; + } - return i; + return i; } static __inline__ int __i2c_read (u8 *data, int length) { - int i; - - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), I2CCCR); - - /* dummy read */ - readl (I2CCDR); + int i; - for (i=0; i < length; i++) - { - if (i2c_wait (I2C_READ) < 0) - break; + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + ((length == 1) ? MPC85xx_I2CCR_TXAK : 0), + I2CCCR); + + /* dummy read */ + readb(I2CCDR); + + for (i=0; i < length; i++) { + if (i2c_wait (I2C_READ) < 0) + break; + + /* Generate ack on last next to last byte */ + if (i == length - 2) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | + MPC85xx_I2CCR_TXAK, + I2CCCR); + + /* Generate stop on last byte */ + if (i == length - 1) + writeb(MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - /* Generate ack on last next to last byte */ - if (i == length - 2) - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_MSTA | - MPC85xx_I2CCR_TXAK, I2CCCR); - - /* Generate stop on last byte */ - if (i == length - 1) - writel (MPC85xx_I2CCR_MEN | MPC85xx_I2CCR_TXAK, I2CCCR); - - data[i] = readl (I2CCDR); - } + data[i] = readb(I2CCDR); + } - return i; + return i; } int i2c_read (u8 dev, uint addr, int alen, u8 *data, int length) { - int i = 0; - u8 *a = (u8*)&addr; + int i = 0; + u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) - goto exit; + if (i2c_wait4bus () < 0) + goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; - if (i2c_write_addr (dev, I2C_READ, 1) == 0) - goto exit; + if (i2c_write_addr (dev, I2C_READ, 1) == 0) + goto exit; - i = __i2c_read (data, length); + i = __i2c_read (data, length); exit: - writel (MPC85xx_I2CCR_MEN, I2CCCR); + writeb(MPC85xx_I2CCR_MEN, I2CCCR); - return !(i == length); + return !(i == length); } int i2c_write (u8 dev, uint addr, int alen, u8 *data, int length) { - int i = 0; - u8 *a = (u8*)&addr; + int i = 0; + u8 *a = (u8*)&addr; - if (i2c_wait4bus () < 0) - goto exit; + if (i2c_wait4bus () < 0) + goto exit; - if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) - goto exit; + if (i2c_write_addr (dev, I2C_WRITE, 0) == 0) + goto exit; - if (__i2c_write (&a[4 - alen], alen) != alen) - goto exit; + if (__i2c_write (&a[4 - alen], alen) != alen) + goto exit; - i = __i2c_write (data, length); + i = __i2c_write (data, length); exit: - writel (MPC85xx_I2CCR_MEN, I2CCCR); + writeb(MPC85xx_I2CCR_MEN, I2CCCR); - return !(i == length); + return !(i == length); } int i2c_probe (uchar chip)

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[U-Boot-Users] PATCH for JSE configuration of its host bridge
by Stephen Williams 28 Sep '04

28 Sep '04

The attached patch tweaks the configuration of the PCI device class that the host system seeof if this board. The change is very simple and affects only the JSE. Patch is attached. CHANGELOG entry: * Patch by Stephen Williams, 15 July 2004 Set the PCI class code as part of PCI interface setup -- Steve Williams "The woods are lovely, dark and deep. steve at icarus.com But I have promises to keep, http://www.icarus.com and lines to code before I sleep, http://www.picturel.com And lines to code before I sleep." Index: board/jse/host_bridge.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/board/jse/host_bridge.c,v retrieving revision 1.1 diff -p -u -r1.1 host_bridge.c --- board/jse/host_bridge.c 15 Apr 2004 23:14:49 -0000 1.1 +++ board/jse/host_bridge.c 15 Jul 2004 19:30:52 -0000 @@ -40,9 +40,12 @@ void host_bridge_init (void) pci_dev_t dev = PCI_BDF (0, 10, 0); int rc; - u32 val32; - rc = pci_read_config_dword (dev, 0, &val32); + /* Set PCI Class code -- + The primary side sees this class code at 0x08 in the + primary config space. This must be something other then a + bridge, or MS Windows starts doing weird stuff to me. */ + pci_write_config_dword (dev, 0x48, 0x04800000); /* Set subsystem ID -- The primary side sees this value at 0x2c. We set it here so

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[U-Boot-Users] Patch: Dynamic clock settings for MPC866 and newer chips
by Yuli Barcohen 28 Sep '04

28 Sep '04

The attached patch makes it possible to set clock on MPC866/MPC885 series chips according to cpuclk environment variable. This is generalisation of Wolfgang's mechanism which was implemented for TQM866M board. CHANGELOG: Allow clock setting on MPC866/MPC885 series chips according to environment variable `cpuclk' -- ======================================================================== Yuli Barcohen | Phone +972-9-765-1788 | Software Project Leader yuli(a)arabellasw.com | Fax +972-9-765-7494 | Arabella Software, Israel ========================================================================

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[U-Boot-Users] [PATCH] drivers/cfi_flash.c Odd-Sized Buffered Writes
by Michael Bendzick 28 Sep '04

28 Sep '04

This patch takes care of a problem with function write_buff in drivers/cfi_flash.c driver when the CFG_FLASH_USE_BUFFER_WRITE setting is defined. --------------------- Description of problem: When writing to a flash buffer, only a multiple of the byte size of the flash chip port width is written. For example, if attempting to write 59 bytes when the port width is 16 bits, only 58 bytes get written to the buffer. The remaining byte is left to be handled as an individual byte write. However, the write_buff in cfi_flash.c did not take into account the rounding down of the number of bytes written with the buffered write. As a result, the handling of unaligned tail bytes would see 0 in cnt and think the full amount of data had been written. --------------------- The fix: The variable i is rounded down to the nearest multiple of the portwidth before incrementing/decrementing the source/destination/size variables. --------------------- Log Message: * Patch by Michael Bendzick, 15 Jul 2004: Fixes to drivers/cfi_flash.c: - Handling of writes with sizes that are not multiples of the byte size of the flash chip port width when CFG_FLASH_USE_BUFFER_WRITE is defined. - Fix minor comment typo. --------------------- The patch: Index: CHANGELOG =================================================================== RCS file: /cvsroot/u-boot/u-boot/CHANGELOG,v retrieving revision 1.342 diff -p -u -r1.342 CHANGELOG --- CHANGELOG 12 Jul 2004 22:34:51 -0000 1.342 +++ CHANGELOG 15 Jul 2004 15:26:24 -0000 @@ -2,6 +2,13 @@ Changes since U-Boot 1.1.1: ====================================================================== +* Patch by Michael Bendzick, 15 Jul 2004: + Fixes to drivers/cfi_flash.c: + - Handling of writes with sizes that are not multiples of the byte + size of the flash chip port width when CFG_FLASH_USE_BUFFER_WRITE + is defined. + - Fix minor comment typo. + * Patch by Michael Bendzick, 12 Jul 2004: fix output formatting in drivers/cfi_flash.c Index: drivers/cfi_flash.c =================================================================== RCS file: /cvsroot/u-boot/u-boot/drivers/cfi_flash.c,v retrieving revision 1.10 diff -p -u -r1.10 cfi_flash.c --- drivers/cfi_flash.c 12 Jul 2004 22:34:52 -0000 1.10 +++ drivers/cfi_flash.c 15 Jul 2004 15:26:37 -0000 @@ -517,6 +517,7 @@ int write_buff (flash_info_t * info, uch i = buffered_size > cnt ? cnt : buffered_size; if ((rc = flash_write_cfibuffer (info, wp, src, i)) != ERR_OK) return rc; + i -= (i % info->portwidth); wp += i; src += i; cnt -= i; @@ -1231,5 +1232,5 @@ static int flash_write_cfibuffer (flash_ flash_write_cmd (info, sector, 0, FLASH_CMD_CLEAR_STATUS); return retcode; } -#endif /* CFG_USE_FLASH_BUFFER_WRITE */ +#endif /* CFG_FLASH_USE_BUFFER_WRITE */ #endif /* CFG_FLASH_CFI */ --------------------- Example output demonstrating the problem & solution: (Tests performed on TI OMAP1510 Innovator, aka board/omap1510inn, with U-Boot build modified to use the cfi_flash.c driver. The file 59-bytes is 59 bytes grabbed from /dev/urandom.) [Old Driver] OMAP1510 Innovator # erase 1:2 Erase Flash Sectors 2-2 in Bank # 1 . done OMAP1510 Innovator # tftp 10000000 59-bytes TFTP from server 192.168.1.177; our IP address is 192.168.1.249 Filename '59-bytes'. Load address: 0x10000000 Loading: # done Bytes transferred = 59 (3b hex) OMAP1510 Innovator # cp.b 10000000 40000 $(filesize) Copy to Flash... done OMAP1510 Innovator # cmp.b 10000000 40000 $(filesize) byte at 0x1000003a (0x17) != byte at 0x0004003a (0xff) Total of 58 bytes were the same [New Driver] 1510 Innov. JMP10a # erase 1:2 Erase Flash Sectors 2-2 in Bank # 1 . done OMAP1510 Innovator # tftp 10000000 59-bytes TFTP from server 192.168.1.177; our IP address is 192.168.1.249 Filename '59-bytes'. Load address: 0x10000000 Loading: # done Bytes transferred = 59 (3b hex) OMAP1510 Innovator # cp.b 10000000 40000 $(filesize) Copy to Flash... done OMAP1510 Innovator # cmpb. 10000000 40000 $(filesize) Unknown command 'cmpb.' - try 'help' OMAP1510 Innovator # cmp.b 10000000 40000 $(filesize) Total of 59 bytes were the same --------------------- Testing: The following boards have CFG_FLASH_CFI_DRIVER and CFG_FLASH_USE_BUFFER_WRITE defined, making them the only boards to be affected by my patch. "OK" below indicates that it compiled properly. I don't have actual hardware to test though. assabet OK csb272 OK csb472 OK eXalion Not even unpatched from CVS compiled for me gcplus OK ppmc8260 OK sbc8560 ELDK didn't appear to compile for PPC 85xx, so this board remains untested. If someone can point me to a pre-made 85xx toolchain, I would gladly test it out. -Michael Bendzick Systems and Software Engineering Logic Product Development michael.b(a)logicpd.com 612-436-5122 www.logicpd.com

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[U-Boot-Users] Runtime switch from uart0 to uart1?
by Travis Sawyer 15 Sep '04

15 Sep '04

Greetings: After having read the README and some code, I was wondering if there is a way to switch, at runtime (rather than at compile time) from UART0 to UART1. The board is the ocotea, ppc440gx, u-boot 1.1.2, build tools from ELDK3 TIA, Travis

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[U-Boot-Users] Patch for Cirrus Logic EDB93xx
by llandre 02 Sep '04

02 Sep '04

Here http://www.dave-tech.it/download/misc/sw/edb93xx/u-boot-edb93xx-1 is available for download the patch for EDB93xx. It has been tested on EDB9312. Tha patch includes Steven Scholz's patch for ARM9-based SoCs. It seems that two builds (lpd7a400 and trab) got broken, but it is not clear why (see below). Any suggestions? *** lpd7a400 *** lib_arm/libarm.a(board.o)(.data+0x20): In function `mem_malloc_init': /home/llandre/devel/zephyr/sw/u-boot/u-boot/lib_arm/board.c:82: undefined reference to `checkcpu' make: *** [u-boot] Error 1 *** trab *** arm-linux-ld: ERROR: /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_udivsi3.oS) uses hardware FP, whereas trab_fkt uses software FP Success: failed to merge target specific data of file /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_udivsi3.oS) arm-linux-ld: ERROR: /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_umodsi3.oS) uses hardware FP, whereas trab_fkt uses software FP Success: failed to merge target specific data of file /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_umodsi3.oS) arm-linux-ld: ERROR: /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_dvmd_lnx.oS) uses hardware FP, whereas trab_fkt uses software FP Success: failed to merge target specific data of file /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_dvmd_lnx.oS) arm-linux-ld: ERROR: /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_udivdi3.oS) uses hardware FP, whereas trab_fkt uses software FP Success: failed to merge target specific data of file /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_udivdi3.oS) arm-linux-ld: ERROR: /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_clz.oS) uses hardware FP, whereas trab_fkt uses software FP Success: failed to merge target specific data of file /usr/local/arm/3.3.2/lib/gcc-lib/arm-linux/3.3.2/libgcc.a(_clz.oS) make[1]: *** [trab_fkt.srec] Error 1 make: *** [board/trab/libtrab.a] Error 2 Regards, llandre DAVE Electronics System House - R&D Department web: http://www.dave-tech.it email: r&d2(a)dave-tech.it

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