August 2004 - U-Boot

[U-Boot-Users] CF for NIOS
by Shlomo Kut 05 Aug '04

05 Aug '04

Hi, Has anybody done a Compact Flash. Port & test CF/FAT. If not can you offer any tips on how to do it. regards, Shlomo Kut Vyyo Ltd POB 45017 Jerusalem 91450 Israel +972-2-5889822

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[U-Boot-Users] passing bootargs to Linux on NIOS
by Thomas Brand 05 Aug '04

05 Aug '04

Hi, I'm currently implementing the bootm command for the NIOS processor from Altera. I'd like to pass boot arguments to the kernel. I tried to figure out how it works in other architectures, but I'm still clueless. I call the function theKernel(...) with some arguments like I have seen it in other implementations. Now my question is, how do I access these arguments in the kernel?. I know the NIOS processor is passing the first 4 arguments in registers when calling a function as a subroutine. But in the linux kernel in main.c is another call in the function start_kernel() for a kernel specific setup [setup_arch()] which will move the window-pointer and so change the registerfile. Therefore I cannot access the registers directly. Or should I just define a piece of memory to put the arguments in? It will be hard coded in the kernel then. Any hints? Every answer will be appreciated. Thomas

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[U-Boot-Users] bzip2 compression
by Marc Leeman 05 Aug '04

05 Aug '04

Did anyone get the bzip2 compression working for an 8245 processor? I think I am having a bit of a problem here :-/ I changed the board configuration to include the following #define CFG_MONITOR_LEN 0x00030000 #define CFG_MONITOR_BASE TEXT_BASE #define CFG_INIT_RAM_ADDR CFG_SDRAM_BASE + CFG_MONITOR_LEN #define CFG_INIT_RAM_END 0x2F00 #define CFG_GBL_DATA_SIZE 128 #define CFG_GBL_DATA_OFFSET (CFG_INIT_RAM_END - CFG_GBL_DATA_SIZE) #define CFG_INIT_SP_OFFSET CFG_GBL_DATA_OFFSET (copied from another 8245 board) and set #define CONFIG_BZIP2 I also set the size of the MALLOC section to #ifdef CONFIG_BZIP2 #define CFG_MALLOC_LEN ( 2500 * 1024) #else #define CFG_MALLOC_LEN (512 << 10) #endif Even though my requested malloc size (2500) falls in the 12M (CFG_INIT_RAM_END), booting a gzip compressed file works fine; while a dump after trying to boot a bzip2 compressed file shows nothing (memory is empty). The same with 4 MB (unless I am mistaking, the 'slower' alg bzip2 algorithm works?). I am certain that I am doing something stupid :) but still, ... Any pointers? Btw, I need the bzip2 compression because I only get 768 M in the kernel partition and repartitioning the flash would break backwards compatiblity. The 2.6.7 kernel jumped to some 800 M (up from 550 or so when compared to the 2.4.24). After all the warm encouragements over the last weeks towards the 2.6; I decided to take the jump :)

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Re: [U-Boot-Users] about to CONFIG_LOGBUFFER ..
by Wolfgang Denk 05 Aug '04

05 Aug '04

In message <4111F858.6080206(a)newmi.co.kr> you wrote: > > Ok! I know that log buffer address in U-boot. > How to know the log buffer address in Linux Kernel? > > Then, how to assign log buffer address for Linux Kernel. > The "do_syslog()" in Linux kernel, log_buffer is only static array variable. You need a modified / extended Linux kernel for this feature. Please see the linux-2.4 Linux kernel tree on our CVS server; search for CONFIG_LOGBUFFER. Best regards, Wolfgang Denk -- Software Engineering: Embedded and Realtime Systems, Embedded Linux Phone: (+49)-8142-4596-87 Fax: (+49)-8142-4596-88 Email: wd(a)denx.de "I used to think that the brain was the most wonderful organ in my body. Then I realized who was telling me this." - Emo Phillips

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[U-Boot-Users] about to CONFIG_LOGBUFFER ..
by Yongdae,Shin 05 Aug '04

05 Aug '04

I do not understand the CONFIG_LOGBUFFER. What's the CONFIG_LOGBUFFER? How to use the CONFIG_LOGBUFFER in U-Boot and Linux Kernel? Why that excluded log buffer in linux system memory?

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[U-Boot-Users] BDI2000 not good for ARM946?
by Shawn Jin 05 Aug '04

05 Aug '04

Hi, I know this is out of the topic of this mailing list. But I really need some comments on this issue and I know that this probably is the best place to get a quick feedback for BDI2000 since a lot of ppl here use it. Some people using BDI2000 to bring up ARM946 board have a little complaint that BDI2000 works flakey on their board. (It took them a week to figure out its configuration file and sometimes it just simply doesn't work.) However my experience on ppc bring-up tells me that BDI2000 works perfectly. So I'm wondering if this is an individual case for ARM bring-up. Or BDI2000 for ARM is not as good as for PPC? Please share your experience. Best regards, -Shawn.

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[U-Boot-Users] Having trouble programming u-boot to MPC8560ADS board
by Abhijeet Bisain 04 Aug '04

04 Aug '04

Hi, I hope this is the right forum to ask this question. I recently received the rev A board from Motorola with u-boot and Linux on it and everything is nice. But I need to run Montavista linux on it, so I configure u-boot to BOOTP and tftp a kernel from them. This works partially fine, I can telnet into the machine but there is no console on serial. So I was asked to put a u-boot binary from Montavista onto the board. I am using BDI2000 to program the flash but am running into difficulty. The config file I have is from Abatron and I haven't modified any Jumpers or switches on the board. When I program the flash with u-boot, BDI says it was successful, but the data read from the flash is incorrect. The data has the first, third, and the eighth bits of a 32 bit word high all the time. So a 0x00000000 is seen as 0xa1000000 and a 0x12345678 as 0xb3345678. I am attaching the BDI config file below. any help on this will be greatly appreciated. Thanks, Abhijeet ;bdiGDB configuration file for MPC8560ADS ; [INIT] ; ; Move the L2SRAM to the initial MMU page WM32 0xFF720000 0x68010000 ;L2CTL WM32 0xFF720100 0xFFFC0000 ;L2SRBAR0 WM32 0xFF720000 0xA8010000 ;L2CTL ; ; load TLB entries, helper code @ 0xfffff000 WM32 0xfffff000 0x7c0007a4 ;tlbwe WM32 0xfffff004 0x7c0004ac ;msync WM32 0xfffff008 0x48000000 ;loop ; ; 1MB TLB1 #1 0x40000000 - 0x400fffff WSPR 624 0x10010000 ;MAS0: WSPR 625 0x80000500 ;MAS1: WSPR 626 0x4000000a ;MAS2: WSPR 627 0x40000015 ;MAS3: WSPR 628 0x00000000 ;MAS4: EXEC 0xfffff000 ; ; 64 MB TLB1 #2 0xc0000000 - 0xc3ffffff WSPR 624 0x10020000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0xc0000008 ;MAS2: WSPR 627 0xc0000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #3 0x00000000 - 0x03ffffff WSPR 624 0x10030000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0x00000008 ;MAS2: WSPR 627 0x00000015 ;MAS3: EXEC 0xfffff000 ; ; 64 MB TLB1 #4 0x04000000 - 0x07ffffff WSPR 624 0x10040000 ;MAS0: WSPR 625 0x80000800 ;MAS1: WSPR 626 0x04000008 ;MAS2: WSPR 627 0x04000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #5 0xff000000 - 0xffffffff WSPR 624 0x10050000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xff00000a ;MAS2: WSPR 627 0xff000015 ;MAS3: EXEC 0xfffff000 ; ; 16 MB TLB1 #0 0xf0000000 - 0xf0ffffff WSPR 624 0x10000000 ;MAS0: WSPR 625 0x80000700 ;MAS1: WSPR 626 0xf0000008 ;MAS2: WSPR 627 0xf0000015 ;MAS3: EXEC 0xfffff000 ; ; Remove the L2SRAM from the initial MMU page WM32 0xFF720000 0x28010000 ;L2CTL WM32 0xFF720000 0x28000000 ;L2CTL ; ; Move CCSRBAR to 0x40000000 WM32 0xff700000 0x00040000 ;CCSRBAR to 0x40000000 ; ; Initialize LAWBAR's WM32 0x40000C08 0x00000000 ;LAWBAR0 : @0x00000000 WM32 0x40000C10 0x80f0001b ;LAWAR0 : DDR/SDRAM 256MB WM32 0x40000C28 0x000c0000 ;LAWBAR1 : @0xc0000000 WM32 0x40000C30 0x8040001d ;LAWAR1 : Local Bus 1GB ; ; Setup DDR (ADS Rev.Pilot , 128MB DDR) ;WM32 0x40002000 0x00000007 ;CS0_BNDS ;WM32 0x40002080 0x80000002 ;CS0_CONFIG ;WM32 0x40002108 0x37544321 ;TIMING_CFG_1 ;WM32 0x4000210C 0x00000800 ;TIMING_CFG_2 ;WM32 0x40002110 0x02000000 ;DDR_SDRAM_CFG ;WM32 0x40002118 0x00000062 ;DDR_SDRAM_MODE ;WM32 0x40002124 0x03a30000 ;DDR_SDRAM_IVAL ;DELAY 200 ;WM32 0x40002110 0xc2000000 ;DDR_SDRAM_CFG ; ; Setup DDR (ADS Rev.A , 256MB DDR) WM32 0x40002000 0x0000000f ;CS0_BNDS WM32 0x40002080 0x80000102 ;CS0_CONFIG WM32 0x40002108 0x36343321 ;TIMING_CFG_1 WM32 0x4000210C 0x00000800 ;TIMING_CFG_2 WM32 0x40002110 0x02008000 ;DDR_SDRAM_CFG WM32 0x40002118 0x00000062 ;DDR_SDRAM_MODE WM32 0x40002124 0x045b0100 ;DDR_SDRAM_IVAL DELAY 200 WM32 0x40002110 0xc2008000 ;DDR_SDRAM_CFG ; ; Setup Flash chip select WM32 0x40005000 0xff001801 ;BR0 WM32 0x40005004 0xff006ff7 ;OR0 ; Setup flash programming workspace in dual port RAM WSPR 63 0x40080000 ;IVPR to workspace WSPR 415 0x000007F0 ;IVOR15 : Debug exception WM32 0x400807F0 0x48000000 ;write valid instruction ; ; Setup for program execution WM32 0x40020000 0x28010000 ;L2CTL WM32 0x40020000 0x28000000 ;L2CTL WSPR 63 0x00000000 ;IVPR to workspace WSPR 406 0x0000700 ;IVOR6 : Program exception WSPR 415 0x0001500 ;IVOR15 : Debug exception WM32 0x00000700 0x48000000 ;write valid instruction WM32 0x00001500 0x48000000 ;write valid instruction ; ; Clear flash Lock-Bits WM32 0xFF800000 0x00600060 ;clear Lock-Bits command WM32 0xFF800000 0x00D000D0 DELAY 1000 ;needs up to 0.7 sec WM32 0xFF800000 0xFFFFFFFF ;set flash to read mode ; [TARGET] CPUTYPE 8560 ;the CPU type JTAGCLOCK 0 ;use 16 MHz JTAG clock STARTUP LOOP ;use boot loop in L2SRAM ;STARTUP HALT ;halt core while HRESET is asserted BREAKMODE SOFT ;SOFT or HARD, HARD uses PPC hardware breakpoint STEPMODE JTAG ;JTAG or HWBP, HWBP uses a hardware breakpoint WAKEUP 200 ;give reset time to complete POWERUP 5000 ;start delay after power-up detected in ms MEMACCESS SAP ;use SAP or CORE for JTAG memory accesses ;REGLIST E500 ;send registers in E500 sequence to GDB [HOST] IP 10.1.0.2 FILE /tftpboot/8560/u-boot.bin.8560ads FORMAT BIN LOAD MANUAL ;load code MANUAL or AUTO after reset DUMP /tftpboot/8560/e500.bin [FLASH] CHIPTYPE STRATAX16 CHIPSIZE 0x800000 ;The size of one flash chip in bytes BUSWIDTH 32 ;The width of the flash memory bus in bits (8 | 16 | 32) WORKSPACE 0x40080000 ;workspace in dual port RAM ;WORKSPACE 0xf0000000 ;workspace in L2SRAM FILE /tftpboot/8560/u-boot.bin.8560ads FORMAT BIN 0xFFF80000 ERASE 0xFFF80000 ERASE 0xFFFC0000 [REGS] FILE /tftpboot/8560/reg8560.def

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[U-Boot-Users] Reset command causes Bus Fault on MPC823
by Miller, John 04 Aug '04

04 Aug '04

Hi Folks Been working on getting u-boot's reset command to work correctly on my RPXlite. Kept on getting bus failures around line 181 of cpu/mpc8xx/cpu_init.c (version 1.1.1). I finally tried commenting out the following lines (figuring that I wasn't an 850 and wasn't rev A silicon) and am now able to perform a reset successfully at u-boot's command prompt. /************************************************************** * The following causes the RPXlite 823 with rev b2(?) silicon * to generate a bus fault when executing u-boot reset command. /* perform BR0 reset that MPC850 Rev. A can't guarantee * reg = memctl->memc_br0; reg &= BR_PS_MSK; /* Clear everything except Port Size bits * reg |= BR_V; /* then add just the "Bank Valid" bit * memctl->memc_br0 = reg; ***************************************************************/ Regards, John Miller

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[U-Boot-Users] Compact Flash Support for MPC8540
by Sudhakar 04 Aug '04

04 Aug '04

Hi all.. Can anyone provide me details about the coding for compact flash in mpc8540. How to start the coding ? I have collected some information based on toshiba's technical note {which describes Compact Flash support for 8260} But i need help regarding coding.. How to proceed.. thanks and Regards, Sudhakar V

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[U-Boot-Users] Question about new board directory layout
by Jon Loeliger 03 Aug '04

03 Aug '04

Wolfgang, Right now, code has been developed for two new boards from Freescale: the 8555CDS and the 8541CDS. These are the first introductions for a series of new boards in the "CDS" family. There are future variants of new boards within this family that will be introduced later. The CDS Architecture is a modular system that allows a "board" to be built from pluggable modules. There is a backplane into which a carrier card is plugged. The carrier card has components like flash and SDRAM on it. The carrier card also has a place where different CPU modules can be plugged into it. Together, the carrier card and the CPU module form the "board" concept. BOARD CPU MODULE CORE WHEN -------------------------------------- 8555CDS 8555 E500 NOW 8541CDS 8541 E500 NOW 85??CDS 85?? E500 PLAN 86??CDS 86?? 74xx(E600) PLAN I can not be more precise on either the 85?? or the 86?? boards and CPUs as their details are not public yet. I use them as examples of the issues that need to be addressed. Note that each of the board names above is an individual product that already can be or soon will be a product offered by Freescale. It is expected that there will be many products offered on this platform. The CPU support for the 85xxCDS boards is already available in the cpu/mpc85xx directory. Nothing needs to be done or modified for that. However, I need to introduce a directory structure for the new Freescale family of CDS boards. There is some amount of shared code that can be leveraged in these boards due to the carrier-card based architecture specifically around areas like the SDRAM, flash, etc. There is also board-specific code like init.S that must be present for each of the different cores. We would, of course, like to avoid duplicate code for the new CDS variants. Do you have a suggestion as to how we should properly introduce a directory structure for the CDS family and the individual boards? Thanks, jdl

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