July 2004 - U-Boot

RE: [U-Boot-Users] ppc4xx/serial.c
by Laurent Mohin 13 Jul '04

13 Jul '04

Hello, udiv = (clk + tmp / 2) / tmp; is a classical way of having the result of (clk/tmp) rounded off to the nearest amount eg 25.78 to 26. Laurent P.S : un petit aparté en français - N'envoie pas tes messages à la liste <u-boot-users-admin(a)lists.sourceforge.net>, sinon tu vas te faire disputer par Wolfgang Denk Seingier François-Xavier <Francois-Xavier.Seingier(a)thomson.net> 13/07/04 10:08 To: "Laurent Mohin" <laurent.mohin(a)acterna.com> cc: "U-Boot-Users \(E-mail\)" <u-boot-users(a)lists.sourceforge.net>, <u-boot-users-admin(a)lists.sourceforge.net> Subject: RE: [U-Boot-Users] ppc4xx/serial.c hello, > What's exactly your problem? > > Give us your cpu_freq value and desired baudrate so that we can help. > Actually, I modified the serial.c file so that udiv and bdiv are calculated as I explained in the previous post and it works. In fact, I was wondering if the original operations were correct? For example, I cannot figure out the meaning of udiv = (clk + tmp / 2) / tmp and all these operations are rather confusing 8-/ regards, François-Xavier SEINGIER

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Re: [U-Boot-Users] PXA255 and I2C
by Anders Larsen 13 Jul '04

13 Jul '04

Herb Radford <herbr(a)magma.ca> schreibt: >I'm having some difficulty getting the I2C bus working on a PXA255-based >board. I also find I'm somewhat confused by the documentation on the I2C >in >Intel's documents. >I'm using an M41ST85 for the RTC chip. When I attempt to read from the >RTC, >I get timeouts and when I check the SCK, I find there's no activity at >all. > >Digging into the documentation, it's not too clear how the GPIO's should >be >set for I2C. GP25 is the SSPTX pin which is (I assume) made bidirectional >(somehow) when the I2C is enabled. Should it and GP23 (SSPCK) be set to >alternate function 2 (I assume so)? Hi Herb, the I2C bus uses the SDA/SCL signals (pins A11/D11 - see chapter 9 in the PXA255 Processor Manual). It has nothing to do with the Network SSP (described in chapter 16) that uses the signals you mentioned above. > >I'm getting nothing on the I2C clock line when I transmit, but the I2C >data >line does go high when enabled. Probing the wrong pin? HTH, Cheers Anders

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AW: [U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards
by Martin Krause 13 Jul '04

13 Jul '04

Hi Olivier, > -----Ursprüngliche Nachricht----- > Von: Olivier Singla [mailto:olivier@singla.us] > Gesendet: Dienstag, 13. Juli 2004 04:12 > An: u-boot-users(a)lists.sourceforge.net > Betreff: [U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards > > I use a Lite5200 board (ref. board from Motorola). With the two PCI network > cards I tried (which I would want to use under Linux 2.4.25), u-boot crashes: Are these cards 3.3 V types? Have you inserted the cards in the right direction? Since the keys for 3.3 V and 5 V are symmetric, it is possible to insert a 5 V card upside down in a 3.3 V slot (at least if it is mechanically possible, like on the Lite5200 board). > Two others PCI cards, not network (Maxtor SATA and USB-2.0) did not bring > any issue with u-boot 1.1.1 > > Is there a known issue with the PCI on the MPC5200, and more specifically > with PCI network cards ? I also have problems with some PCI cards. Some are recognized, some not. I haven't found an explanation, yet. I guess it has something to do with some "3.3 V compatible" cards are not really compatible with 3.3 V only systems. It could as well be an errata in the MPC5200 described in the MPC5200 Errata Listing: ID 322: Violation of PCI Tval min time The PCI Timing Speci?cation de?nes the timing parameter Tval (CLK to Signal Valid Delay): Tval min 2 ns, max 11 ns (33MHz) Tval min 2 ns, max 6 ns (66MHz) When M66EN is asserted, the minimum speci?cation for Tval(min) may be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is deasserted. MPC5200 provides Tval min of 1 ns (instead of 2 ns), which is a violation of the Timing Speci?cation for 33MHz. Best Regards, Martin

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AW: [U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards
by Reinhard Meyer 13 Jul '04

13 Jul '04

Hello, Be highly cautious with PCI cards that claim 3.3V compatibility by having a notch in the 3.3V key position. Many of them still locally bridge the 5V and the VIO powers! Reinhard -----Ursprüngliche Nachricht----- Von: u-boot-users-admin(a)lists.sourceforge.net [mailto:u-boot-users-admin@lists.sourceforge.net] Im Auftrag von Martin Krause Gesendet: Dienstag, 13. Juli 2004 09:00 An: Olivier Singla Cc: u-boot-users(a)lists.sourceforge.net Betreff: AW: [U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards Hi Olivier, > -----Ursprüngliche Nachricht----- > Von: Olivier Singla [mailto:olivier@singla.us] > Gesendet: Dienstag, 13. Juli 2004 04:12 > An: u-boot-users(a)lists.sourceforge.net > Betreff: [U-Boot-Users] LITE5200 board: Bus Fault with 2 network cards > > I use a Lite5200 board (ref. board from Motorola). With the two PCI > network cards I tried (which I would want to use under Linux 2.4.25), u-boot crashes: Are these cards 3.3 V types? Have you inserted the cards in the right direction? Since the keys for 3.3 V and 5 V are symmetric, it is possible to insert a 5 V card upside down in a 3.3 V slot (at least if it is mechanically possible, like on the Lite5200 board). > Two others PCI cards, not network (Maxtor SATA and USB-2.0) did not > bring any issue with u-boot 1.1.1 > > Is there a known issue with the PCI on the MPC5200, and more > specifically with PCI network cards ? I also have problems with some PCI cards. Some are recognized, some not. I haven't found an explanation, yet. I guess it has something to do with some "3.3 V compatible" cards are not really compatible with 3.3 V only systems. It could as well be an errata in the MPC5200 described in the MPC5200 Errata Listing: ID 322: Violation of PCI Tval min time The PCI Timing Speci?cation de?nes the timing parameter Tval (CLK to Signal Valid Delay): Tval min 2 ns, max 11 ns (33MHz) Tval min 2 ns, max 6 ns (66MHz) When M66EN is asserted, the minimum speci?cation for Tval(min) may be reduced to 1 ns if a mechanism is provided to guarantee a minimum value of 2 ns when M66EN is deasserted. MPC5200 provides Tval min of 1 ns (instead of 2 ns), which is a violation of the Timing Speci?cation for 33MHz. Best Regards, Martin ------------------------------------------------------- This SF.Net email sponsored by Black Hat Briefings & Training. Attend Black Hat Briefings & Training, Las Vegas July 24-29 - digital self defense, top technical experts, no vendor pitches, unmatched networking opportunities. Visit www.blackhat.com _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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Re: [U-Boot-Users] ppc4xx/serial.c
by Laurent Mohin 13 Jul '04

13 Jul '04

François-Xavier, You're perfectly right. What's exactly your problem? Give us your cpu_freq value and desired baudrate so that we can help. Laurent Seingier François-Xavier <Francois-Xavier.Seingier(a)thomson.net> Sent by: u-boot-users-admin(a)lists.sourceforge.net 12/07/04 18:23 To: "U-Boot-Users \(E-mail\)" <u-boot-users(a)lists.sourceforge.net> cc: Subject: [U-Boot-Users] ppc4xx/serial.c hello, I've been going through the code of the function serial_init because I couldn't get the proper baudrate divisor. I must admit I don't understand the operations made to calculate udiv and bdiv... According to the 405gp user manual, these are the meanings of a few parameters. CFG_BASE_BAUD = SerClk / 16 bdiv = SerClk / (16 * baudrate) SerClk = cpu_freq / udiv As a result, udiv and bdiv should be generated as follows in serail_init: if external_clock: SerClk = CFG_EXT_SERIAL_CLK udiv = 1 else: SerClk = CFG_BASE_BAUD * 16 udiv = cpu_freq / serClk endif bdiv = SerClk / (16 * baudrate) Am I missing something? regards, François-Xavier SEINGIER ------------------------------------------------------- This SF.Net email sponsored by Black Hat Briefings & Training. Attend Black Hat Briefings & Training, Las Vegas July 24-29 - digital self defense, top technical experts, no vendor pitches, unmatched networking opportunities. Visit www.blackhat.com _______________________________________________ U-Boot-Users mailing list U-Boot-Users(a)lists.sourceforge.net https://lists.sourceforge.net/lists/listinfo/u-boot-users

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[U-Boot-Users] [patch] master read fix mpc8245
by Marc Leeman 13 Jul '04

13 Jul '04

Reading PPC Memory from another device with the PPC as PCI target device corrupts data due to interenal hardware buffering. Fix to disable these buffers with no performance influence. a detailed description is available upon request (pdf, mailinglist bounces).

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[U-Boot-Users] Errant Tab in drivers/cfi_flash.c
by Michael Bendzick 13 Jul '04

13 Jul '04

I noticed in the drivers/cfi_flash.c file, there's a minor error in text formatting that makes for an ugly display when running 'flinfo'. I tracked it down to line 465, where either "(RO)" or blank space is displayed, depending on the sector status. An errant tab is in there that looked like the two spaces that ought to be there, which caused my terminal program (Tera Term) to make the spacing between numbered sectors excessively wide, and also cause a blank line between every data-bearing line. The fix (note that I'm using [tab] and [space] here for clarity): Line 465... info->start[i], info->protect[i] ? "[space](RO)" : "[tab][space][space][space]"); ...should become... info->start[i], info->protect[i] ? "[space](RO)" : "[space][space][space][space][space]"); -Michael Bendzick Systems and Software Engineering Logic Product Development michael.b(a)logicpd.com 612-436-5122 www.logicpd.com

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[U-Boot-Users] Help with serial port set-up for PPC 8540
by Junita Ajith 13 Jul '04

13 Jul '04

Hi I am trying to write an Assembly code , just to set-up the UART , so as to send a few characters via the serial port. I am working on a 8540 Motorola PowerPC . As I am starting right from the scratch I dont have the boot -loader doing the board initializations for me and so have to have my own start.S file to do those . I just have set-up the necessary registers for UART and as I am not doing any high level coding I havent set up the MMU , TLB etc. But my code doesnt seem to work !!! I assumed that that CPU would direclty read from the Flash .I am new to this and so I need some advise of what all have to be done during board bring up, or where should I look for such documentation. Any help would be appreciated . Thanks Junita __________________________________ Do you Yahoo!? Take Yahoo! Mail with you! Get it on your mobile phone. http://mobile.yahoo.com/maildemo

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RE: [U-Boot-Users] Debugging U-Boot Under DDD
by VanBaren, Gerald (AGRE) 12 Jul '04

12 Jul '04

> -----Original Message----- > From: u-boot-users-admin(a)lists.sourceforge.net > [mailto:u-boot-users-admin@lists.sourceforge.net]On Behalf Of > Talib Alim > Sent: Monday, July 12, 2004 3:08 PM > To: U-Boot List > Subject: [U-Boot-Users] Debugging U-Boot Under DDD > > > This may be a trivial question, but I hope that someone can answer me. > I am bring up u-boot on 8xx. > > While doing source level debugging under ddd, whenever I do step, > stepi, next or nexti I see green instruction pointer jump all over the > code. e.g. it would go to first line, than third line, than 7 line. If > I look at machine code window, it is running in normal > predictable way. That is typically because the compiler optimizer has re-ordered your program. ddd is showing you which line is being executed and the machine code window shows sequential instructions, but those instructions are _not_ for sequential source lines. gvb ****************************************** The information contained in, or attached to, this e-mail, may contain confidential information and is intended solely for the use of the individual or entity to whom they are addressed and may be subject to legal privilege. If you have received this e-mail in error you should notify the sender immediately by reply e-mail, delete the message from your system and notify your system manager. Please do not copy it for any purpose, or disclose its contents to any other person. The views or opinions presented in this e-mail are solely those of the author and do not necessarily represent those of the company. The recipient should check this e-mail and any attachments for the presence of viruses. The company accepts no liability for any damage caused, directly or indirectly, by any virus transmitted in this email. ******************************************

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[U-Boot-Users] RE: [u-boot-users]: Relocation code on Nios
by Scott McNutt 12 Jul '04

12 Jul '04

>> I don"t understand this particular line of code: >> >> ld %g7, [%g7] This moves the value pointed to by %g7 into register %g7. %g7 points to the location that stores the address of _start. This is the address where u-boot is to be copied (the destination address). >> Per my understanding, %g7 keeps the return address. >> This address should point to the next instruction >> of code just after the delay slot of CALL or BSR >> used to call u-boot. Yes, you are correct. %g7 points to where the (link time) address of _start is stored (not the current execution address of _start). >> later this value (instruction bytes) is compared with >> %g5 that keeps the end of data segment according to >> u-boot.lds. I can"t understand why code address is >> being compared with instruction bytes. Please >> explain if possible - what does [%g7] keep and where >> am I wrong? This just lets you store u-boot in memory at any address. When you being execution, the code is simply copied to TEXT_BASE, that's all. This initial bsr just lets us know where we begin execution, the value in %g7 after the bsr is the target address plus 4. Currently, for convenience and simplicity, the u-boot code, data, and command table are currently located contiguously. There's no magic here ... just load the binary to some arbitrary address, then single step through the code -- it'll help you understand :-) Best Regards, --Scott

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