[U-Boot] Armada 385: PEX detection pulse width
Dear Adam,
On the mainline u-boot we found a commit which helps to fix a problem regarding PCIe and the Armada 370: http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0...
We currently facing a similar problem with the Armada 385 and PCIe. The problem also appears with two different Atheros chipsets one (AR9280) gets never detected and the other one gets detected most of the time but not always (QCA9882). With Intel modules on the other hand, we can't reproduce the issue. It's the same behaviour as described in the commit above, the link training fails and therefore the link is signalized as down. If a link is successfully established (QCA9882) we don't see any errors during communication.
Do you know if we have the same possibility on the Armada 385 to tune the PCI Express pulse width as you proposed it for the Armada 370? Unfortunately the PCIe Phy seems to be quite different to the one from the Armada 370.
Best regards Stefan
Hi Stefan,
In A385, the register to change the pulse width is 0xa0120 bits[7:6]. Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see if it solves the issue.
But, please note that we tested our platforms with the value 0x1 only and we cannot guarantee that after you change this value that it will work for all the devices/add in cards other than Atheros .
Thanks, Adam
-----Original Message----- From: Stefan Eichenberger [mailto:stefan.eichenberger@netmodule.com] Sent: Friday, April 21, 2017 11:51 AM To: Adam Shobash Cc: Assaf Hoffman; René Straub; sr@denx.de; u-boot@lists.denx.de Subject: [EXT] Armada 385: PEX detection pulse width
External Email
---------------------------------------------------------------------- Dear Adam,
On the mainline u-boot we found a commit which helps to fix a problem regarding PCIe and the Armada 370: http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0...
We currently facing a similar problem with the Armada 385 and PCIe. The problem also appears with two different Atheros chipsets one (AR9280) gets never detected and the other one gets detected most of the time but not always (QCA9882). With Intel modules on the other hand, we can't reproduce the issue. It's the same behaviour as described in the commit above, the link training fails and therefore the link is signalized as down. If a link is successfully established (QCA9882) we don't see any errors during communication.
Do you know if we have the same possibility on the Armada 385 to tune the PCI Express pulse width as you proposed it for the Armada 370? Unfortunately the PCIe Phy seems to be quite different to the one from the Armada 370.
Best regards Stefan
Hello Adam,
first of all thanks the quick reply. First trials with reduced pulse length, showed promising results. To better understand the root cause of the problem, it would be helpful if you explained us briefly what the register change actually performs. I/we understand that the problem is related to the process of Rx Detection (measuring voltage change on PCIe link after a common mode step). Maybe we can implement a board change (PCIe lane coupling capacitors) to improve the detection, even with the default pulse length of the A385.
Best regards -Rene
-----Original Message----- From: Adam Shobash [mailto:adams@marvell.com] Sent: Sonntag, 23. April 2017 19:29 To: Stefan Eichenberger Stefan.Eichenberger@netmodule.com Cc: Assaf Hoffman hoffman@marvell.com; Rene Straub Rene.Straub@netmodule.com; sr@denx.de; u-boot@lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width
Hi Stefan,
In A385, the register to change the pulse width is 0xa0120 bits[7:6]. Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see if it solves the issue.
But, please note that we tested our platforms with the value 0x1 only and we cannot guarantee that after you change this value that it will work for all the devices/add in cards other than Atheros .
Thanks, Adam
-----Original Message----- From: Stefan Eichenberger [mailto:stefan.eichenberger@netmodule.com] Sent: Friday, April 21, 2017 11:51 AM To: Adam Shobash Cc: Assaf Hoffman; René Straub; sr@denx.de; u-boot@lists.denx.de Subject: [EXT] Armada 385: PEX detection pulse width
External Email
---------------------------------------------------------------------- Dear Adam,
On the mainline u-boot we found a commit which helps to fix a problem regarding PCIe and the Armada 370: http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0...
We currently facing a similar problem with the Armada 385 and PCIe. The problem also appears with two different Atheros chipsets one (AR9280) gets never detected and the other one gets detected most of the time but not always (QCA9882). With Intel modules on the other hand, we can't reproduce the issue. It's the same behaviour as described in the commit above, the link training fails and therefore the link is signalized as down. If a link is successfully established (QCA9882) we don't see any errors during communication.
Do you know if we have the same possibility on the Armada 385 to tune the PCI Express pulse width as you proposed it for the Armada 370? Unfortunately the PCIe Phy seems to be quite different to the one from the Armada 370.
Best regards Stefan
Hi Rene,
These bits that I have sent changes the pulse width of the "detection pulse" during the detect state, and purpose of it is to measure the slew rate of the common mode voltage change and according to the slew rate it is decided whether there is a Termination(usually it is the Rx impedance of the peer device) connected to the transmitter or not. Now, the slew rate is affected from several things: 1.) The Rx DC impedance of the peer device - which the spec requires to be between 40 to 60 ohm single ended. 2.) The DC block capacitors , Marvell recommends to use 100nF(and the PCIE spec requires to use between 75nF to 220nF). 3.) And in Marvell devices it depends also in the sample point.
And, as you suggested I believe that if you change the coupling capacitors to a higher value(150nF/200nF) and keep the default value of the sample point it will also help. The default settings of the sample point + using 100nF capacitors in Marvell devices are good for devices that meet the spec, so we recommend to not change any settings, but we noticed in some Atheros wifi devices that Marvell devices are not able to detect their terminations and only for these devices you can change the sample point(or the capacitors as you suggested).
Thanks, Adam
-----Original Message----- From: Rene Straub [mailto:Rene.Straub@netmodule.com] Sent: Tuesday, April 25, 2017 8:44 AM To: Adam Shobash; Stefan Eichenberger Cc: Assaf Hoffman; sr@denx.de; u-boot@lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width
Hello Adam,
first of all thanks the quick reply. First trials with reduced pulse length, showed promising results. To better understand the root cause of the problem, it would be helpful if you explained us briefly what the register change actually performs. I/we understand that the problem is related to the process of Rx Detection (measuring voltage change on PCIe link after a common mode step). Maybe we can implement a board change (PCIe lane coupling capacitors) to improve the detection, even with the default pulse length of the A385.
Best regards -Rene
-----Original Message----- From: Adam Shobash [mailto:adams@marvell.com] Sent: Sonntag, 23. April 2017 19:29 To: Stefan Eichenberger Stefan.Eichenberger@netmodule.com Cc: Assaf Hoffman hoffman@marvell.com; Rene Straub Rene.Straub@netmodule.com; sr@denx.de; u-boot@lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width
Hi Stefan,
In A385, the register to change the pulse width is 0xa0120 bits[7:6]. Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see if it solves the issue.
But, please note that we tested our platforms with the value 0x1 only and we cannot guarantee that after you change this value that it will work for all the devices/add in cards other than Atheros .
Thanks, Adam
-----Original Message----- From: Stefan Eichenberger [mailto:stefan.eichenberger@netmodule.com] Sent: Friday, April 21, 2017 11:51 AM To: Adam Shobash Cc: Assaf Hoffman; René Straub; sr@denx.de; u-boot@lists.denx.de Subject: [EXT] Armada 385: PEX detection pulse width
External Email
---------------------------------------------------------------------- Dear Adam,
On the mainline u-boot we found a commit which helps to fix a problem regarding PCIe and the Armada 370: http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0...
We currently facing a similar problem with the Armada 385 and PCIe. The problem also appears with two different Atheros chipsets one (AR9280) gets never detected and the other one gets detected most of the time but not always (QCA9882). With Intel modules on the other hand, we can't reproduce the issue. It's the same behaviour as described in the commit above, the link training fails and therefore the link is signalized as down. If a link is successfully established (QCA9882) we don't see any errors during communication.
Do you know if we have the same possibility on the Armada 385 to tune the PCI Express pulse width as you proposed it for the Armada 370? Unfortunately the PCIe Phy seems to be quite different to the one from the Armada 370.
Best regards Stefan
+ Torsten
-----Original Message----- From: Adam Shobash Sent: Tuesday, April 25, 2017 10:26 AM To: Rene Straub; Stefan Eichenberger Cc: Assaf Hoffman; sr@denx.de; u-boot@lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width
Hi Rene,
These bits that I have sent changes the pulse width of the "detection pulse" during the detect state, and purpose of it is to measure the slew rate of the common mode voltage change and according to the slew rate it is decided whether there is a Termination(usually it is the Rx impedance of the peer device) connected to the transmitter or not. Now, the slew rate is affected from several things: 1.) The Rx DC impedance of the peer device - which the spec requires to be between 40 to 60 ohm single ended. 2.) The DC block capacitors , Marvell recommends to use 100nF(and the PCIE spec requires to use between 75nF to 220nF). 3.) And in Marvell devices it depends also in the sample point.
And, as you suggested I believe that if you change the coupling capacitors to a higher value(150nF/200nF) and keep the default value of the sample point it will also help. The default settings of the sample point + using 100nF capacitors in Marvell devices are good for devices that meet the spec, so we recommend to not change any settings, but we noticed in some Atheros wifi devices that Marvell devices are not able to detect their terminations and only for these devices you can change the sample point(or the capacitors as you suggested).
Thanks, Adam
-----Original Message----- From: Rene Straub [mailto:Rene.Straub@netmodule.com] Sent: Tuesday, April 25, 2017 8:44 AM To: Adam Shobash; Stefan Eichenberger Cc: Assaf Hoffman; sr@denx.de; u-boot@lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width
Hello Adam,
first of all thanks the quick reply. First trials with reduced pulse length, showed promising results. To better understand the root cause of the problem, it would be helpful if you explained us briefly what the register change actually performs. I/we understand that the problem is related to the process of Rx Detection (measuring voltage change on PCIe link after a common mode step). Maybe we can implement a board change (PCIe lane coupling capacitors) to improve the detection, even with the default pulse length of the A385.
Best regards -Rene
-----Original Message----- From: Adam Shobash [mailto:adams@marvell.com] Sent: Sonntag, 23. April 2017 19:29 To: Stefan Eichenberger Stefan.Eichenberger@netmodule.com Cc: Assaf Hoffman hoffman@marvell.com; Rene Straub Rene.Straub@netmodule.com; sr@denx.de; u-boot@lists.denx.de Subject: RE: [EXT] Armada 385: PEX detection pulse width
Hi Stefan,
In A385, the register to change the pulse width is 0xa0120 bits[7:6]. Default value is 0x1(pulse width=2us) , you can try and change it to 0x0 to see if it solves the issue.
But, please note that we tested our platforms with the value 0x1 only and we cannot guarantee that after you change this value that it will work for all the devices/add in cards other than Atheros .
Thanks, Adam
-----Original Message----- From: Stefan Eichenberger [mailto:stefan.eichenberger@netmodule.com] Sent: Friday, April 21, 2017 11:51 AM To: Adam Shobash Cc: Assaf Hoffman; René Straub; sr@denx.de; u-boot@lists.denx.de Subject: [EXT] Armada 385: PEX detection pulse width
External Email
---------------------------------------------------------------------- Dear Adam,
On the mainline u-boot we found a commit which helps to fix a problem regarding PCIe and the Armada 370: http://git.denx.de/?p=u-boot.git;a=commit;h=6bbe0924a799d33c1a8c9de38b60a5e0...
We currently facing a similar problem with the Armada 385 and PCIe. The problem also appears with two different Atheros chipsets one (AR9280) gets never detected and the other one gets detected most of the time but not always (QCA9882). With Intel modules on the other hand, we can't reproduce the issue. It's the same behaviour as described in the commit above, the link training fails and therefore the link is signalized as down. If a link is successfully established (QCA9882) we don't see any errors during communication.
Do you know if we have the same possibility on the Armada 385 to tune the PCI Express pulse width as you proposed it for the Armada 370? Unfortunately the PCIe Phy seems to be quite different to the one from the Armada 370.
Best regards Stefan
participants (4)
-
Adam Shobash -
Assaf Hoffman -
Rene Straub -
Stefan Eichenberger