[U-Boot] [RFC PATCH] Fix bug in T4240QDS code. Don't access nonexistent registers
The code in misc_init_r() verifies actual SERDES clocks versus expected. It supposes that the number of clocks is MAX_SERDES. However, the number of pllcr0 registers is only SRDS_MAX_BANK. This clearly results in access to wrong memory. I don't have the datasheet to design a correct solution, but at least let's change it to access only the existing registers.
Signed-off-by: Vasili Galka vvv444@gmail.com Cc: York Sun yorksun@freescale.com --- board/freescale/t4qds/t4240qds.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..6646042 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -662,7 +662,7 @@ int misc_init_r(void) } }
- for (i = 0; i < MAX_SERDES; i++) { + for (i = 0; i < SRDS_MAX_BANK; i++) { u32 pllcr0 = srds_regs->bank[i].pllcr0; u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) {
On 06/16/2014 07:41 AM, Vasili Galka wrote:
The code in misc_init_r() verifies actual SERDES clocks versus expected. It supposes that the number of clocks is MAX_SERDES. However, the number of pllcr0 registers is only SRDS_MAX_BANK. This clearly results in access to wrong memory. I don't have the datasheet to design a correct solution, but at least let's change it to access only the existing registers.
Signed-off-by: Vasili Galka vvv444@gmail.com Cc: York Sun yorksun@freescale.com
board/freescale/t4qds/t4240qds.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..6646042 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -662,7 +662,7 @@ int misc_init_r(void) } }
- for (i = 0; i < MAX_SERDES; i++) {
- for (i = 0; i < SRDS_MAX_BANK; i++) { u32 pllcr0 = srds_regs->bank[i].pllcr0; u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) {
Thanks for fixing it.
York
This patch points out a bug in T4240QDS code. But the fix is not correct.
Shaohui, please take a closer look and submit a patch to fix it. I believe the code should check each Bank of each SerDes (totally 8 clocks).
Thanks Vasili for pointing out.
York
On 06/16/2014 07:41 AM, Vasili Galka wrote:
The code in misc_init_r() verifies actual SERDES clocks versus expected. It supposes that the number of clocks is MAX_SERDES. However, the number of pllcr0 registers is only SRDS_MAX_BANK. This clearly results in access to wrong memory. I don't have the datasheet to design a correct solution, but at least let's change it to access only the existing registers.
Signed-off-by: Vasili Galka vvv444@gmail.com Cc: York Sun yorksun@freescale.com
board/freescale/t4qds/t4240qds.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..6646042 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -662,7 +662,7 @@ int misc_init_r(void) } }
- for (i = 0; i < MAX_SERDES; i++) {
- for (i = 0; i < SRDS_MAX_BANK; i++) { u32 pllcr0 = srds_regs->bank[i].pllcr0; u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) {
Shaohui,
Never mind. You sent the patch already http://patchwork.ozlabs.org/patch/364807/.
York
On 07/22/2014 02:16 PM, York Sun wrote:
This patch points out a bug in T4240QDS code. But the fix is not correct.
Shaohui, please take a closer look and submit a patch to fix it. I believe the code should check each Bank of each SerDes (totally 8 clocks).
Thanks Vasili for pointing out.
York
On 06/16/2014 07:41 AM, Vasili Galka wrote:
The code in misc_init_r() verifies actual SERDES clocks versus expected. It supposes that the number of clocks is MAX_SERDES. However, the number of pllcr0 registers is only SRDS_MAX_BANK. This clearly results in access to wrong memory. I don't have the datasheet to design a correct solution, but at least let's change it to access only the existing registers.
Signed-off-by: Vasili Galka vvv444@gmail.com Cc: York Sun yorksun@freescale.com
board/freescale/t4qds/t4240qds.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..6646042 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -662,7 +662,7 @@ int misc_init_r(void) } }
- for (i = 0; i < MAX_SERDES; i++) {
- for (i = 0; i < SRDS_MAX_BANK; i++) { u32 pllcr0 = srds_regs->bank[i].pllcr0; u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) {
U-Boot mailing list U-Boot@lists.denx.de http://lists.denx.de/mailman/listinfo/u-boot
Hi, York,
There is already a patch sent upstream to fix this bug, the state is under review. http://patchwork.ozlabs.org/patch/364807/
Best Regards, Shaohui Xie
-----Original Message----- From: Sun York-R58495 Sent: Wednesday, July 23, 2014 5:16 AM To: Xie Shaohui-B21989 Cc: Vasili Galka; u-boot@lists.denx.de; Zang Roy-R61911 Subject: Re: [RFC PATCH] Fix bug in T4240QDS code. Don't access nonexistent registers
This patch points out a bug in T4240QDS code. But the fix is not correct.
Shaohui, please take a closer look and submit a patch to fix it. I believe the code should check each Bank of each SerDes (totally 8 clocks).
Thanks Vasili for pointing out.
York
On 06/16/2014 07:41 AM, Vasili Galka wrote:
The code in misc_init_r() verifies actual SERDES clocks versus expected. It supposes that the number of clocks is MAX_SERDES. However, the number of pllcr0 registers is only SRDS_MAX_BANK. This clearly results in access to wrong memory. I don't have the datasheet to design a correct solution, but at least let's change it to access only the existing registers.
Signed-off-by: Vasili Galka vvv444@gmail.com Cc: York Sun yorksun@freescale.com
board/freescale/t4qds/t4240qds.c | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/board/freescale/t4qds/t4240qds.c b/board/freescale/t4qds/t4240qds.c index fe1bc7f..6646042 100644 --- a/board/freescale/t4qds/t4240qds.c +++ b/board/freescale/t4qds/t4240qds.c @@ -662,7 +662,7 @@ int misc_init_r(void) } }
- for (i = 0; i < MAX_SERDES; i++) {
- for (i = 0; i < SRDS_MAX_BANK; i++) { u32 pllcr0 = srds_regs->bank[i].pllcr0; u32 expected = pllcr0 & SRDS_PLLCR0_RFCK_SEL_MASK; if (expected != actual[i]) {
participants (3)
-
Shaohui Xie -
Vasili Galka -
York Sun