[U-Boot] [PATCH] update VCMA9 port
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - various cleanups and coding style fixes
Signed-off-by: David Mueller d.mueller@elsoft.ch
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..59c25f9 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS := vcma9.o flash.o cmd_vcma9.o +COBJS := vcma9.o cmd_vcma9.o COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..0f02b7e 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,7 +43,7 @@ static uchar cs8900_chksum(ushort data)
DECLARE_GLOBAL_DATA_PTR;
-extern void print_vcma9_info(void); +extern void vcma9_print_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); extern int vcma9_nanderase(void); @@ -60,7 +60,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk index e345913..fef5308 100644 --- a/board/mpl/vcma9/config.mk +++ b/board/mpl/vcma9/config.mk @@ -1,5 +1,5 @@ # -# (C) Copyright 2002, 2003 +# (C) Copyright 2002, 2003, 2010 # David Mueller, ELSOFT AG, d.mueller@elsoft.ch # # MPL VCMA9 board with S3C2410X (ARM920T) cpu @@ -7,18 +7,10 @@ # see http://www.mpl.ch/ for more information about the MPL VCMA9 #
-# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# # Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 # optionally with a ramdisk at 3040'0000 # -# we load ourself to 33F8'0000 +# NOR flash is mapped at address 0 # -# download area is 3080'0000 -# -
-#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 +CONFIG_SYS_TEXT_BASE = 0x0 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..cb1518b 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h>
-/* some parameters for the board */ +/* register definitions */
+#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02
+/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7)
-#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */
+/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */
+/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */
-#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */
#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */
#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */
/* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/
_TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE:
.globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
/* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
+ /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr
.ltorg /* the literal pools origin */
-CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..b6b49f5 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger mgroeger@sysgo.de * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,53 @@
#include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h>
#include "vcma9.h" #include "../common/common_util.h"
DECLARE_GLOBAL_DATA_PTR;
-#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */
-int board_init(void) +int board_early_init_f(void) { struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); + + return 0; +}
+int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
@@ -134,113 +87,32 @@ int board_init(void) }
/* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */
-static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); }
-static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; }
-static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; }
-static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; }
-static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +120,9 @@ static u8 Get_SDRAM_ChipNr(void) } }
-static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +130,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +142,21 @@ static const char * Get_SDRAM_ChipGeom(void) } }
-static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); }
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; }
-/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +174,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -}
- -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; }
-/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif
-/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#");
- if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } }
@@ -360,3 +216,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..baaea85 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -29,106 +29,17 @@
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +void vcma9_print_info(void); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..a82012f 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,21 +33,21 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
-/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG
/* * BOOTP options @@ -57,7 +57,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
- /* * Command line configuration. */ @@ -68,146 +67,154 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND
+#define BOARD_LATE_INIT
#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + /*********************************************************** * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
+/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16
/* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
/************************************************************ - * USB support + * USB support (currently only works with D-cache off) ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION
/* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************ * RTC ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +#define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1
#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif
/* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
#define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
-/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000
/* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA
/************************************************************ * Ident ************************************************************/ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2010 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG
/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ #endif
/*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
@@ -215,36 +222,60 @@ * FLASH and environment organization */
-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19)
-/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 #endif
+#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* + * File system + */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
Dear =?UTF-8?q?David=20M=C3=BCller?=,
In message 1292926154-19802-1-git-send-email-d.mueller@elsoft.ch you wrote:
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following:
- do the necessary adjustments to support the ARM relocation feature
- use the CFI flash driver (and removing the old one)
- various cleanups and coding style fixes
...
diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk index e345913..fef5308 100644 --- a/board/mpl/vcma9/config.mk +++ b/board/mpl/vcma9/config.mk
...
-#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 +CONFIG_SYS_TEXT_BASE = 0x0
Please move this line into your board config file, and drop the config.mk file.
diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..cb1518b 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@
- Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and
Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl)
- Modified for the Samsung SMDK2410 by
- (C) Copyright 2002
I understand this file was created using copy & paste; why do you think it is legal to remove the original copyright notice?
- Modified for MPL VCMA9 by
- David Mueller, ELSOFT AG, d.mueller@elsoft.ch
We don't need this here. This information is present in the commit logs.
Best regards,
Wolfgang Denk
Wolfgang Denk schrieb:
Please move this line into your board config file, and drop the config.mk file.
Ok, will be done.
- Modified for the Samsung SMDK2410 by
- (C) Copyright 2002
- Modified for MPL VCMA9 by
- David Mueller, ELSOFT AG, d.mueller@elsoft.ch
I understand this file was created using copy & paste; why do you think it is legal to remove the original copyright notice?
The actual patch looks like this:
- * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005
As you can see, i don't remove any copyright notice (just extending it) and i fix an obviously bad reference to SMDK2410.
Dave
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - remove the unneeded config.mk file - various cleanups and coding style fixes
Signed-off-by: David Müller d.mueller@elsoft.ch
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..59c25f9 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS := vcma9.o flash.o cmd_vcma9.o +COBJS := vcma9.o cmd_vcma9.o COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..0f02b7e 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,7 +43,7 @@ static uchar cs8900_chksum(ushort data)
DECLARE_GLOBAL_DATA_PTR;
-extern void print_vcma9_info(void); +extern void vcma9_print_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); extern int vcma9_nanderase(void); @@ -60,7 +60,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk deleted file mode 100644 index e345913..0000000 --- a/board/mpl/vcma9/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002, 2003 -# David Mueller, ELSOFT AG, d.mueller@elsoft.ch -# -# MPL VCMA9 board with S3C2410X (ARM920T) cpu -# -# see http://www.mpl.ch/ for more information about the MPL VCMA9 -# - -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3040'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3080'0000 -# - - -#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..cb1518b 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h>
-/* some parameters for the board */ +/* register definitions */
+#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02
+/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7)
-#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */
+/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */
+/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */
-#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */
#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */
#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */
/* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/
_TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE:
.globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
/* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
+ /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr
.ltorg /* the literal pools origin */
-CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..b6b49f5 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger mgroeger@sysgo.de * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,53 @@
#include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h>
#include "vcma9.h" #include "../common/common_util.h"
DECLARE_GLOBAL_DATA_PTR;
-#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */
-int board_init(void) +int board_early_init_f(void) { struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); + + return 0; +}
+int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
@@ -134,113 +87,32 @@ int board_init(void) }
/* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */
-static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); }
-static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; }
-static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; }
-static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; }
-static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +120,9 @@ static u8 Get_SDRAM_ChipNr(void) } }
-static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +130,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +142,21 @@ static const char * Get_SDRAM_ChipGeom(void) } }
-static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); }
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; }
-/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +174,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -}
- -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; }
-/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif
-/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#");
- if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } }
@@ -360,3 +216,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..baaea85 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -29,106 +29,17 @@
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +void vcma9_print_info(void); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..e56abba 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,21 +33,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
-/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_TEXT_BASE 0x0
-#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG
/* * BOOTP options @@ -57,7 +59,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
- /* * Command line configuration. */ @@ -68,146 +69,154 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND
+#define BOARD_LATE_INIT
#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + /*********************************************************** * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
+/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16
/* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
/************************************************************ - * USB support + * USB support (currently only works with D-cache off) ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION
/* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************ * RTC ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +#define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1
#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif
/* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
#define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
-/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000
/* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA
/************************************************************ * Ident ************************************************************/ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2010 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG
/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ #endif
/*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
@@ -215,36 +224,60 @@ * FLASH and environment organization */
-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19)
-/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 #endif
+#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* + * File system + */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
Dear =?UTF-8?q?David=20M=C3=BCller?=,
In message 1294732049-1877-1-git-send-email-d.mueller@elsoft.ch you wrote:
--===============1318198764==
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following:
- do the necessary adjustments to support the ARM relocation feature
- use the CFI flash driver (and removing the old one)
- remove the unneeded config.mk file
- various cleanups and coding style fixes
Signed-off-by: David Müller d.mueller@elsoft.ch
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile
NAK. I'm not going to review that. Please stick to the rules. When submitting a new version of the patch you are supposed to descibe what has been changed. For details please see http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
Best regards,
Wolfgang Denk
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - various cleanups and coding style fixes - remove the unneeded config.mk file
Signed-off-by: David Müller d.mueller@elsoft.ch ---
Changes for V2: - delete config.mk
Changes for V3: - adjust patch meta info
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..59c25f9 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS := vcma9.o flash.o cmd_vcma9.o +COBJS := vcma9.o cmd_vcma9.o COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..0f02b7e 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,7 +43,7 @@ static uchar cs8900_chksum(ushort data)
DECLARE_GLOBAL_DATA_PTR;
-extern void print_vcma9_info(void); +extern void vcma9_print_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); extern int vcma9_nanderase(void); @@ -60,7 +60,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk deleted file mode 100644 index e345913..0000000 --- a/board/mpl/vcma9/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002, 2003 -# David Mueller, ELSOFT AG, d.mueller@elsoft.ch -# -# MPL VCMA9 board with S3C2410X (ARM920T) cpu -# -# see http://www.mpl.ch/ for more information about the MPL VCMA9 -# - -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3040'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3080'0000 -# - - -#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..cb1518b 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h>
-/* some parameters for the board */ +/* register definitions */
+#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02
+/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7)
-#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */
+/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */
+/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */
-#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */
#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */
#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */
/* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/
_TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE:
.globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
/* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
+ /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr
.ltorg /* the literal pools origin */
-CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 (not implemented yet) */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..b6b49f5 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger mgroeger@sysgo.de * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,53 @@
#include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h>
#include "vcma9.h" #include "../common/common_util.h"
DECLARE_GLOBAL_DATA_PTR;
-#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */
-int board_init(void) +int board_early_init_f(void) { struct s3c24x0_clock_power * const clk_power = s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr); + + return 0; +}
+int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
@@ -134,113 +87,32 @@ int board_init(void) }
/* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */
-static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); }
-static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; }
-static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; }
-static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; }
-static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +120,9 @@ static u8 Get_SDRAM_ChipNr(void) } }
-static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +130,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +142,21 @@ static const char * Get_SDRAM_ChipGeom(void) } }
-static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); }
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; }
-/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +174,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -}
- -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; }
-/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif
-/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#");
- if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } }
@@ -360,3 +216,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..baaea85 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -29,106 +29,17 @@
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +void vcma9_print_info(void); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..e56abba 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,21 +33,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
-/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_TEXT_BASE 0x0
-#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000
+#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ + +#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG
/* * BOOTP options @@ -57,7 +59,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
- /* * Command line configuration. */ @@ -68,146 +69,154 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND
+#define BOARD_LATE_INIT
#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + /*********************************************************** * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
+/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16
/* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
/************************************************************ - * USB support + * USB support (currently only works with D-cache off) ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION
/* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************ * RTC ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +#define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1
#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif
/* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +#define CONFIG_DISPLAY_CPUINFO /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
#define CONFIG_SYS_ALT_MEMTEST #define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */
-/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000
/* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA
/************************************************************ * Ident ************************************************************/ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2010 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG
/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128*1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ #endif
/*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
@@ -215,36 +224,60 @@ * FLASH and environment organization */
-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif - +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45 #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19)
-/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
-#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ +/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 #endif
+#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 - -#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* + * File system + */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO + +/* additions for new relocation code, must added to all boards */ +#undef CONFIG_SYS_ARM_WITHOUT_RELOC +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + +#define CONFIG_BOARD_EARLY_INIT_F
#endif /* __CONFIG_H */
Dear David Müller,
On 11 January 2011 21:22, David Müller d.mueller@elsoft.ch wrote:
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - various cleanups and coding style fixes - remove the unneeded config.mk file
If so, you should separate the patch.
Thanks Minkyu Kang
Dear Minkyu Kang,
In message AANLkTikYZ=4e0w2rD+3fHoOWh8Y-gv+EJXOXUPDT-BFQ@mail.gmail.com you wrote:
On 11 January 2011 21:22, David M=FCller d.mueller@elsoft.ch wrote:
This patch brings the VCMA9 port in sync with the latest U-Boot version by doing the following:
...
If so, you should separate the patch.
You you ask for such changes, could you please also update the patch status in patchwork to "Changes Requested"? Thanks!
[This applies to all other custodians as well! Thanks!]
Best regards,
Wolfgang Denk
Dear Wolfgang Denk,
On 12 April 2011 04:24, Wolfgang Denk wd@denx.de wrote:
Dear Minkyu Kang,
You you ask for such changes, could you please also update the patch status in patchwork to "Changes Requested"? Thanks!
[This applies to all other custodians as well! Thanks!]
Best regards,
Wolfgang Denk
OK, I will.
Thanks Minkyu Kang
This patch serie brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - remove the unneeded config.mk file - various cleanups/coding style fixes
---
board/mpl/vcma9/Makefile | 2 +- board/mpl/vcma9/cmd_vcma9.c | 4 +- board/mpl/vcma9/config.mk | 24 -- board/mpl/vcma9/flash.c | 432 ------------------------------ board/mpl/vcma9/lowlevel_init.S | 549 ++++++++++++++++++++++++++++++--------- board/mpl/vcma9/vcma9.c | 284 ++++++--------------- board/mpl/vcma9/vcma9.h | 117 +-------- include/configs/VCMA9.h | 232 ++++++++++------- 8 files changed, 654 insertions(+), 990 deletions(-)
Changes for V2: - delete config.mk
Changes for V3: - adjust patch meta info
Changes for V4: - split patch into smaller pieces - prefix patches with VCMA9 - additional tabulator cleanup in VCMA9.h - remove unneeded #undef CONFIG_SYS_ARM_WITHOUT_RELOC in VCMA9.h
Signed-off-by: David Müller d.mueller@elsoft.ch
--- include/configs/VCMA9.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..b723908 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -247,4 +247,10 @@
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
+/* additions for new relocation code, must added to all boards */ +#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + + #endif /* __CONFIG_H */
Dear =?UTF-8?q?David=20M=C3=BCller?=,
In message 1302600759-28219-2-git-send-email-d.mueller@elsoft.ch you wrote:
--===============0390427290==
Signed-off-by: David Müller d.mueller@elsoft.ch
include/configs/VCMA9.h | 6 ++++++ 1 files changed, 6 insertions(+), 0 deletions(-)
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..b723908 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -247,4 +247,10 @@
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
+/* additions for new relocation code, must added to all boards */
I don't see much sense in such a comment. "New relocation code" is not generally meaningful, and "must be added" is not only missing a "be" but also redundant as you just added the code.
Best regards,
Wolfgang Denk
Dear =?UTF-8?q?David=20M=C3=BCller?=,
In message 1302600759-28219-2-git-send-email-d.mueller@elsoft.ch you wrote:
Signed-off-by: David Müller d.mueller@elsoft.ch
Actually the Subject: is wrong. No part in this patch "activates" anything - you just add some missing definitions to fix build problems.
Best regards,
Wolfgang Denk
Signed-off-by: David Müller d.mueller@elsoft.ch
--- board/mpl/vcma9/config.mk | 24 ------------------------ include/configs/VCMA9.h | 2 ++ 2 files changed, 2 insertions(+), 24 deletions(-) delete mode 100644 board/mpl/vcma9/config.mk
diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk deleted file mode 100644 index e345913..0000000 --- a/board/mpl/vcma9/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002, 2003 -# David Mueller, ELSOFT AG, d.mueller@elsoft.ch -# -# MPL VCMA9 board with S3C2410X (ARM920T) cpu -# -# see http://www.mpl.ch/ for more information about the MPL VCMA9 -# - -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3040'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3080'0000 -# - - -#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index b723908..50af634 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -38,6 +38,8 @@ #define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define CONFIG_SYS_TEXT_BASE 0x0 + /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
Signed-off-by: David Müller d.mueller@elsoft.ch
--- board/mpl/vcma9/Makefile | 2 +- board/mpl/vcma9/flash.c | 432 ---------------------------------------------- board/mpl/vcma9/vcma9.c | 12 ++ include/configs/VCMA9.h | 28 +-- 4 files changed, 22 insertions(+), 452 deletions(-) delete mode 100644 board/mpl/vcma9/flash.c
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..59c25f9 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS := vcma9.o flash.o cmd_vcma9.o +COBJS := vcma9.o cmd_vcma9.o COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..171a128 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -360,3 +360,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 50af634..0a634d5 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -105,6 +105,7 @@ /*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
/* @@ -211,32 +212,21 @@ #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*----------------------------------------------------------------------- * FLASH and environment organization */
-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19)
#if 0 #define CONFIG_ENV_IS_IN_FLASH 1
Signed-off-by: David Müller d.mueller@elsoft.ch
--- board/mpl/vcma9/cmd_vcma9.c | 4 +- board/mpl/vcma9/lowlevel_init.S | 549 ++++++++++++++++++++++++++++++--------- board/mpl/vcma9/vcma9.c | 272 +++++--------------- board/mpl/vcma9/vcma9.h | 117 +-------- include/configs/VCMA9.h | 200 +++++++++------ 5 files changed, 626 insertions(+), 516 deletions(-)
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..0f02b7e 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,7 +43,7 @@ static uchar cs8900_chksum(ushort data)
DECLARE_GLOBAL_DATA_PTR;
-extern void print_vcma9_info(void); +extern void vcma9_print_info(void); extern int vcma9_cantest(int); extern int vcma9_nandtest(void); extern int vcma9_nanderase(void); @@ -60,7 +60,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..dadaac7 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h>
-/* some parameters for the board */ +/* register definitions */
+#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02
+/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7)
-#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */
+/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */
+/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */
-#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */
#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */
#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */
/* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/
_TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE:
.globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
/* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
+ /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr
.ltorg /* the literal pools origin */
-CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 171a128..e63625b 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger mgroeger@sysgo.de * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,51 @@
#include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h>
#include "vcma9.h" #include "../common/common_util.h"
DECLARE_GLOBAL_DATA_PTR;
-#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */
-int board_init(void) +int board_early_init_f(void) { - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
+ return 0; +} + +int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
@@ -134,113 +85,32 @@ int board_init(void) }
/* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */
-static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); }
-static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; }
-static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; }
-static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; }
-static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +118,9 @@ static u8 Get_SDRAM_ChipNr(void) } }
-static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +128,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +140,21 @@ static const char * Get_SDRAM_ChipGeom(void) } }
-static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); }
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; }
-/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +172,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -}
- -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; }
-/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif
-/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#");
- if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } }
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..baaea85 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -29,106 +29,17 @@
extern int mem_test(unsigned long start, unsigned long ramsize,int mode);
-void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +void vcma9_print_info(void); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 0a634d5..8e086a7 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,23 +33,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
#define CONFIG_SYS_TEXT_BASE 0x0
-/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG
/* * BOOTP options @@ -59,7 +59,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
- /* * Command line configuration. */ @@ -70,147 +69,155 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND
+#define BOARD_LATE_INIT
#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " +#define CONFIG_CMDLINE_EDITING + /*********************************************************** * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
+/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16
/* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
/************************************************************ - * USB support + * USB support (currently only works with D-cache off) ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION
/* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
/************************************************************ * RTC ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +#define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1
#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif
/* * Miscellaneous configurable options */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ - -#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/*be activated as soon as s3c24x0 has print_cpuinfo support */ +/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */ + +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x30800000
-/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000
/* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA
/************************************************************ * Ident ************************************************************/ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2010 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG
/*----------------------------------------------------------------------- * Stack sizes * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ #endif
/*----------------------------------------------------------------------- * Physical Memory Map */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
@@ -223,26 +230,55 @@ #define CONFIG_FLASH_CFI_LEGACY #define CONFIG_SYS_FLASH_LEGACY_512Kx16 #define CONFIG_FLASH_SHOW_PROGRESS 45 - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_SECT (19)
-#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#endif +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* + * NAND configuration + */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 +#endif
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* + * File system + */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_JFFS2 +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO
/* additions for new relocation code, must added to all boards */ #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_BOARD_EARLY_INIT_F
-#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */
Dear =?UTF-8?q?David=20M=C3=BCller?=,
In message 1302600759-28219-5-git-send-email-d.mueller@elsoft.ch you wrote:
--===============1758926862==
Signed-off-by: David Müller d.mueller@elsoft.ch
board/mpl/vcma9/cmd_vcma9.c | 4 +- board/mpl/vcma9/lowlevel_init.S | 549 ++++++++++++++++++++++++++++++--------- board/mpl/vcma9/vcma9.c | 272 +++++--------------- board/mpl/vcma9/vcma9.h | 117 +-------- include/configs/VCMA9.h | 200 +++++++++------ 5 files changed, 626 insertions(+), 516 deletions(-)
Where is the change log that shows what has been changed with this new patch version? Please see http://www.denx.de/wiki/view/U-Boot/Patches#Sending_updated_patch_versions
-extern void print_vcma9_info(void); +extern void vcma9_print_info(void);
Please get rid of all such externs - move the prototype declarations to appropriate header files. Please fix globally.
Best regards,
Wolfgang Denk
This patch serie brings the VCMA9 port in sync with the latest U-Boot version by doing the following: - do the necessary adjustments to support the ARM relocation feature - use the CFI flash driver (and removing the old one) - remove the unneeded config.mk file - various cleanups/coding style fixes
---
board/mpl/vcma9/Makefile | 4 +- board/mpl/vcma9/cmd_vcma9.c | 56 +---- board/mpl/vcma9/config.mk | 24 -- board/mpl/vcma9/flash.c | 432 ------------------------------ board/mpl/vcma9/lowlevel_init.S | 549 ++++++++++++++++++++++++++++++--------- board/mpl/vcma9/vcma9.c | 284 ++++++--------------- board/mpl/vcma9/vcma9.h | 121 ++-------- include/configs/VCMA9.h | 256 ++++++++++--------- 8 files changed, 661 insertions(+), 1065 deletions(-)
Changes for V2: - delete config.mk
Changes for V3: - adjust patch meta info
Changes for V4: - split patch into smaller pieces - prefix patches with VCMA9 - additional tabulator cleanup in VCMA9.h - remove unneeded #undef CONFIG_SYS_ARM_WITHOUT_RELOC in VCMA9.h
Changes for V5: - remove unneeded comment and change subject - remove dead debug code and move externs into header file
Signed-off-by: David Müller d.mueller@elsoft.ch
--- include/configs/VCMA9.h | 5 +++++ 1 files changed, 5 insertions(+), 0 deletions(-)
Changes for V5: - remove unneeded comment and change subject
diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index ebe9e42..3cd1bc3 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -247,4 +247,9 @@
#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
+#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 +#define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ + GENERATED_GBL_DATA_SIZE) + + #endif /* __CONFIG_H */
Signed-off-by: David Müller d.mueller@elsoft.ch
--- board/mpl/vcma9/config.mk | 24 ------------------------ include/configs/VCMA9.h | 2 ++ 2 files changed, 2 insertions(+), 24 deletions(-) delete mode 100644 board/mpl/vcma9/config.mk
diff --git a/board/mpl/vcma9/config.mk b/board/mpl/vcma9/config.mk deleted file mode 100644 index e345913..0000000 --- a/board/mpl/vcma9/config.mk +++ /dev/null @@ -1,24 +0,0 @@ -# -# (C) Copyright 2002, 2003 -# David Mueller, ELSOFT AG, d.mueller@elsoft.ch -# -# MPL VCMA9 board with S3C2410X (ARM920T) cpu -# -# see http://www.mpl.ch/ for more information about the MPL VCMA9 -# - -# -# MPL VCMA9 has 1 bank of minimal 16 MB DRAM -# from 0x30000000 -# -# Linux-Kernel is expected to be at 3000'8000, entry 3000'8000 -# optionally with a ramdisk at 3040'0000 -# -# we load ourself to 33F8'0000 -# -# download area is 3080'0000 -# - - -#CONFIG_SYS_TEXT_BASE = 0x30F80000 -CONFIG_SYS_TEXT_BASE = 0x33F80000 diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 3cd1bc3..1962674 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -38,6 +38,8 @@ #define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ #define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */
+#define CONFIG_SYS_TEXT_BASE 0x0 + /* input clock of PLL */ #define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */
Signed-off-by: David Müller d.mueller@elsoft.ch
--- board/mpl/vcma9/Makefile | 2 +- board/mpl/vcma9/flash.c | 432 ---------------------------------------------- board/mpl/vcma9/vcma9.c | 12 ++ include/configs/VCMA9.h | 28 +-- 4 files changed, 22 insertions(+), 452 deletions(-) delete mode 100644 board/mpl/vcma9/flash.c
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 27cef1d..59c25f9 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,7 +28,7 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS := vcma9.o flash.o cmd_vcma9.o +COBJS := vcma9.o cmd_vcma9.o COBJS += ../common/common_util.o
SOBJS := lowlevel_init.o diff --git a/board/mpl/vcma9/flash.c b/board/mpl/vcma9/flash.c deleted file mode 100644 index 7abf9cf..0000000 --- a/board/mpl/vcma9/flash.c +++ /dev/null @@ -1,432 +0,0 @@ -/* - * (C) Copyright 2002 - * Sysgo Real-Time Solutions, GmbH <www.elinos.com> - * Alex Zuepke azu@sysgo.de - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> - -ulong myflush (void); - - -#define FLASH_BANK_SIZE PHYS_FLASH_SIZE -#define MAIN_SECT_SIZE 0x10000 /* 64 KB */ - -flash_info_t flash_info[CONFIG_SYS_MAX_FLASH_BANKS]; - - -#define CMD_READ_ARRAY 0x000000F0 -#define CMD_UNLOCK1 0x000000AA -#define CMD_UNLOCK2 0x00000055 -#define CMD_ERASE_SETUP 0x00000080 -#define CMD_ERASE_CONFIRM 0x00000030 -#define CMD_PROGRAM 0x000000A0 -#define CMD_UNLOCK_BYPASS 0x00000020 - -#define MEM_FLASH_ADDR1 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x00000555 << 1))) -#define MEM_FLASH_ADDR2 (*(volatile u16 *)(CONFIG_SYS_FLASH_BASE + (0x000002AA << 1))) - -#define BIT_ERASE_DONE 0x00000080 -#define BIT_RDY_MASK 0x00000080 -#define BIT_PROGRAM_ERROR 0x00000020 -#define BIT_TIMEOUT 0x80000000 /* our flag */ - -#define READY 1 -#define ERR 2 -#define TMO 4 - -/*----------------------------------------------------------------------- - */ - -ulong flash_init (void) -{ - int i, j; - ulong size = 0; - - for (i = 0; i < CONFIG_SYS_MAX_FLASH_BANKS; i++) { - ulong flashbase = 0; - - flash_info[i].flash_id = -#if defined(CONFIG_AMD_LV400) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV400B & FLASH_TYPEMASK); -#elif defined(CONFIG_AMD_LV800) - (AMD_MANUFACT & FLASH_VENDMASK) | - (AMD_ID_LV800B & FLASH_TYPEMASK); -#else -#error "Unknown flash configured" -#endif - flash_info[i].size = FLASH_BANK_SIZE; - flash_info[i].sector_count = CONFIG_SYS_MAX_FLASH_SECT; - memset (flash_info[i].protect, 0, CONFIG_SYS_MAX_FLASH_SECT); - if (i == 0) - flashbase = PHYS_FLASH_1; - else - panic ("configured too many flash banks!\n"); - for (j = 0; j < flash_info[i].sector_count; j++) { - if (j <= 3) { - /* 1st one is 16 KB */ - if (j == 0) { - flash_info[i].start[j] = - flashbase + 0; - } - - /* 2nd and 3rd are both 8 KB */ - if ((j == 1) || (j == 2)) { - flash_info[i].start[j] = - flashbase + 0x4000 + (j - - 1) * - 0x2000; - } - - /* 4th 32 KB */ - if (j == 3) { - flash_info[i].start[j] = - flashbase + 0x8000; - } - } else { - flash_info[i].start[j] = - flashbase + (j - 3) * MAIN_SECT_SIZE; - } - } - size += flash_info[i].size; - } - - flash_protect (FLAG_PROTECT_SET, - CONFIG_SYS_FLASH_BASE, - CONFIG_SYS_FLASH_BASE + monitor_flash_len - 1, - &flash_info[0]); - - flash_protect (FLAG_PROTECT_SET, - CONFIG_ENV_ADDR, - CONFIG_ENV_ADDR + CONFIG_ENV_SIZE - 1, &flash_info[0]); - - return size; -} - -/*----------------------------------------------------------------------- - */ -void flash_print_info (flash_info_t * info) -{ - int i; - - switch (info->flash_id & FLASH_VENDMASK) { - case (AMD_MANUFACT & FLASH_VENDMASK): - puts ("AMD: "); - break; - default: - puts ("Unknown Vendor "); - break; - } - - switch (info->flash_id & FLASH_TYPEMASK) { - case (AMD_ID_LV400B & FLASH_TYPEMASK): - puts ("1x Amd29LV400BB (4Mbit)\n"); - break; - case (AMD_ID_LV800B & FLASH_TYPEMASK): - puts ("1x Amd29LV800BB (8Mbit)\n"); - break; - default: - puts ("Unknown Chip Type\n"); - goto Done; - break; - } - - printf (" Size: %ld MB in %d Sectors\n", - info->size >> 20, info->sector_count); - - puts (" Sector Start Addresses:"); - for (i = 0; i < info->sector_count; i++) { - if ((i % 5) == 0) { - puts ("\n "); - } - printf (" %08lX%s", info->start[i], - info->protect[i] ? " (RO)" : " "); - } - puts ("\n"); - -Done: ; -} - -/*----------------------------------------------------------------------- - */ - -int flash_erase (flash_info_t * info, int s_first, int s_last) -{ - ushort result; - int iflag, cflag, prot, sect; - int rc = ERR_OK; - int chip; - - /* first look for protection bits */ - - if (info->flash_id == FLASH_UNKNOWN) - return ERR_UNKNOWN_FLASH_TYPE; - - if ((s_first < 0) || (s_first > s_last)) { - return ERR_INVAL; - } - - if ((info->flash_id & FLASH_VENDMASK) != - (AMD_MANUFACT & FLASH_VENDMASK)) { - return ERR_UNKNOWN_FLASH_VENDOR; - } - - prot = 0; - for (sect = s_first; sect <= s_last; ++sect) { - if (info->protect[sect]) { - prot++; - } - } - if (prot) - return ERR_PROTECTED; - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - /* Start erase on unprotected sectors */ - for (sect = s_first; sect <= s_last && !ctrlc (); sect++) { - printf ("Erasing sector %2d ... ", sect); - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - if (info->protect[sect] == 0) { /* not protected */ - vu_short *addr = (vu_short *) (info->start[sect]); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_ERASE_SETUP; - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - *addr = CMD_ERASE_CONFIRM; - - /* wait until flash is ready */ - chip = 0; - - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > - CONFIG_SYS_FLASH_ERASE_TOUT) { - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - chip = TMO; - break; - } - - if (!chip - && (result & 0xFFFF) & BIT_ERASE_DONE) - chip = READY; - - if (!chip - && (result & 0xFFFF) & BIT_PROGRAM_ERROR) - chip = ERR; - - } while (!chip); - - MEM_FLASH_ADDR1 = CMD_READ_ARRAY; - - if (chip == ERR) { - rc = ERR_PROG_ERROR; - goto outahere; - } - if (chip == TMO) { - rc = ERR_TIMOUT; - goto outahere; - } - - puts ("ok.\n"); - } else { /* it was protected */ - - puts ("protected!\n"); - } - } - - if (ctrlc ()) - puts ("User Interrupt!\n"); - - outahere: - /* allow flash to settle - wait 10 ms */ - udelay_masked (10000); - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash - */ - -static int write_hword (flash_info_t * info, ulong dest, ushort data) -{ - vu_short *addr = (vu_short *) dest; - ushort result; - int rc = ERR_OK; - int cflag, iflag; - int chip; - - /* - * Check if Flash is (sufficiently) erased - */ - result = *addr; - if ((result & data) != data) - return ERR_NOT_ERASED; - - - /* - * Disable interrupts which might cause a timeout - * here. Remember that our exception vectors are - * at address 0 in the flash, and we don't want a - * (ticker) exception to happen while the flash - * chip is in programming mode. - */ - cflag = icache_status (); - icache_disable (); - iflag = disable_interrupts (); - - MEM_FLASH_ADDR1 = CMD_UNLOCK1; - MEM_FLASH_ADDR2 = CMD_UNLOCK2; - MEM_FLASH_ADDR1 = CMD_PROGRAM; - *addr = data; - - /* arm simple, non interrupt dependent timer */ - reset_timer_masked (); - - /* wait until flash is ready */ - chip = 0; - do { - result = *addr; - - /* check timeout */ - if (get_timer_masked () > CONFIG_SYS_FLASH_ERASE_TOUT) { - chip = ERR | TMO; - break; - } - if (!chip && ((result & 0x80) == (data & 0x80))) - chip = READY; - - if (!chip && ((result & 0xFFFF) & BIT_PROGRAM_ERROR)) { - result = *addr; - - if ((result & 0x80) == (data & 0x80)) - chip = READY; - else - chip = ERR; - } - - } while (!chip); - - *addr = CMD_READ_ARRAY; - - if (chip == ERR || *addr != data) - rc = ERR_PROG_ERROR; - - if (iflag) - enable_interrupts (); - - if (cflag) - icache_enable (); - - return rc; -} - -/*----------------------------------------------------------------------- - * Copy memory to flash. - */ - -int write_buff (flash_info_t * info, uchar * src, ulong addr, ulong cnt) -{ - ulong cp, wp; - int l; - int i, rc; - ushort data; - - wp = (addr & ~1); /* get lower word aligned address */ - - /* - * handle unaligned start bytes - */ - if ((l = addr - wp) != 0) { - data = 0; - for (i = 0, cp = wp; i < l; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - for (; i < 2 && cnt > 0; ++i) { - data = (data >> 8) | (*src++ << 8); - --cnt; - ++cp; - } - for (; cnt == 0 && i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - wp += 2; - } - - /* - * handle word aligned part - */ - while (cnt >= 2) { - data = *((vu_short *) src); - if ((rc = write_hword (info, wp, data)) != 0) { - return (rc); - } - src += 2; - wp += 2; - cnt -= 2; - } - - if (cnt == 0) { - return ERR_OK; - } - - /* - * handle unaligned tail bytes - */ - data = 0; - for (i = 0, cp = wp; i < 2 && cnt > 0; ++i, ++cp) { - data = (data >> 8) | (*src++ << 8); - --cnt; - } - for (; i < 2; ++i, ++cp) { - data = (data >> 8) | (*(uchar *) cp << 8); - } - - return write_hword (info, wp, data); -} diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 978e6fd..171a128 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -360,3 +360,15 @@ int board_eth_init(bd_t *bis) return rc; } #endif + +/* + * Hardcoded flash setup: + * Flash 0 is a non-CFI AMD AM29F400BB flash. + */ +ulong board_flash_get_legacy(ulong base, int banknum, flash_info_t *info) +{ + info->portwidth = FLASH_CFI_16BIT; + info->chipwidth = FLASH_CFI_BY16; + info->interface = FLASH_CFI_X16; + return 1; +} diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 1962674..11a61e2 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -105,6 +105,7 @@ /*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/
#define CONFIG_SYS_MONITOR_LEN (256 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE #define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */
/* @@ -211,32 +212,21 @@ #define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ #define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
-#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1 +#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
/*----------------------------------------------------------------------- * FLASH and environment organization */
-#define CONFIG_AMD_LV400 1 /* uncomment this if you have a LV400 flash */ -#if 0 -#define CONFIG_AMD_LV800 1 /* uncomment this if you have a LV800 flash */ -#endif +#define CONFIG_SYS_FLASH_CFI +#define CONFIG_FLASH_CFI_DRIVER +#define CONFIG_FLASH_CFI_LEGACY +#define CONFIG_SYS_FLASH_LEGACY_512Kx16 +#define CONFIG_FLASH_SHOW_PROGRESS 45
#define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#ifdef CONFIG_AMD_LV800 -#define PHYS_FLASH_SIZE 0x00100000 /* 1MB */ -#define CONFIG_SYS_MAX_FLASH_SECT (19) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x0F0000) /* addr of environment */ -#endif -#ifdef CONFIG_AMD_LV400 -#define PHYS_FLASH_SIZE 0x00080000 /* 512KB */ -#define CONFIG_SYS_MAX_FLASH_SECT (11) /* max number of sectors on one chip */ -#define CONFIG_ENV_ADDR (CONFIG_SYS_FLASH_BASE + 0x070000) /* addr of environment */ -#endif - -/* timeout values are in ticks */ -#define CONFIG_SYS_FLASH_ERASE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Erase */ -#define CONFIG_SYS_FLASH_WRITE_TOUT (5*CONFIG_SYS_HZ) /* Timeout for Flash Write */ +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_MAX_FLASH_SECT (19)
#if 0 #define CONFIG_ENV_IS_IN_FLASH 1
Signed-off-by: David Müller d.mueller@elsoft.ch
--- board/mpl/vcma9/Makefile | 4 +- board/mpl/vcma9/cmd_vcma9.c | 56 +---- board/mpl/vcma9/lowlevel_init.S | 549 ++++++++++++++++++++++++++++++--------- board/mpl/vcma9/vcma9.c | 272 +++++--------------- board/mpl/vcma9/vcma9.h | 121 ++-------- include/configs/VCMA9.h | 223 +++++++++-------- 6 files changed, 634 insertions(+), 591 deletions(-)
Changes for V5: - remove dead debug code and move externs into header file
diff --git a/board/mpl/vcma9/Makefile b/board/mpl/vcma9/Makefile index 59c25f9..6228762 100644 --- a/board/mpl/vcma9/Makefile +++ b/board/mpl/vcma9/Makefile @@ -28,8 +28,8 @@ endif
LIB = $(obj)lib$(BOARD).o
-COBJS := vcma9.o cmd_vcma9.o -COBJS += ../common/common_util.o +COBJS := ../common/common_util.o +COBJS += $(BOARD).o cmd_$(BOARD).o
SOBJS := lowlevel_init.o
diff --git a/board/mpl/vcma9/cmd_vcma9.c b/board/mpl/vcma9/cmd_vcma9.c index 0d5f46e..fa49918 100644 --- a/board/mpl/vcma9/cmd_vcma9.c +++ b/board/mpl/vcma9/cmd_vcma9.c @@ -43,15 +43,6 @@ static uchar cs8900_chksum(ushort data)
DECLARE_GLOBAL_DATA_PTR;
-extern void print_vcma9_info(void); -extern int vcma9_cantest(int); -extern int vcma9_nandtest(void); -extern int vcma9_nanderase(void); -extern int vcma9_nandread(ulong); -extern int vcma9_nandwrite(ulong); -extern int vcma9_dactest(int); -extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]); - /* ------------------------------------------------------------------------- */
int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) @@ -60,7 +51,7 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) char cs8900_name[10]; if (strcmp(argv[1], "info") == 0) { - print_vcma9_info(); + vcma9_print_info(); return 0; } #if defined(CONFIG_CS8900) @@ -133,48 +124,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) return 0; } #endif -#if 0 - if (strcmp(argv[1], "cantest") == 0) { - if (argc >= 3) - vcma9_cantest(strcmp(argv[2], "s") ? 0 : 1); - else - vcma9_cantest(0); - return 0; - } - if (strcmp(argv[1], "nandtest") == 0) { - vcma9_nandtest(); - return 0; - } - if (strcmp(argv[1], "nanderase") == 0) { - vcma9_nanderase(); - return 0; - } - if (strcmp(argv[1], "nandread") == 0) { - ulong offset = 0; - - if (argc >= 3) - offset = simple_strtoul(argv[2], NULL, 16); - - vcma9_nandread(offset); - return 0; - } - if (strcmp(argv[1], "nandwrite") == 0) { - ulong offset = 0; - - if (argc >= 3) - offset = simple_strtoul(argv[2], NULL, 16); - - vcma9_nandwrite(offset); - return 0; - } - if (strcmp(argv[1], "dactest") == 0) { - if (argc >= 3) - vcma9_dactest(strcmp(argv[2], "s") ? 0 : 1); - else - vcma9_dactest(0); - return 0; - } -#endif
return (do_mplcommon(cmdtp, flag, argc, argv)); } @@ -182,5 +131,6 @@ int do_vcma9(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) U_BOOT_CMD( vcma9, 6, 1, do_vcma9, "VCMA9 specific commands", - "flash mem [SrcAddr]\n - updates U-Boot with image in memory" + "flash mem [SrcAddr] - updates U-Boot with image in memory\n" + "vcma9 info - displays board information" ); diff --git a/board/mpl/vcma9/lowlevel_init.S b/board/mpl/vcma9/lowlevel_init.S index 062e868..dadaac7 100644 --- a/board/mpl/vcma9/lowlevel_init.S +++ b/board/mpl/vcma9/lowlevel_init.S @@ -4,9 +4,9 @@ * Copyright (C) 1999 2000 2001 Erik Mouw (J.A.K.Mouw@its.tudelft.nl) and * Jan-Derk Bakker (J.D.Bakker@its.tudelft.nl) * - * Modified for the Samsung SMDK2410 by - * (C) Copyright 2002 + * Modified for MPL VCMA9 by * David Mueller, ELSOFT AG, d.mueller@elsoft.ch + * (C) Copyright 2002, 2003, 2004, 2005 * * See file CREDITS for list of people who contributed to this * project. @@ -32,12 +32,21 @@ #include <version.h>
-/* some parameters for the board */ +/* register definitions */
+#define PLD_BASE 0x28000000 +#define MISC_REG 0x103 +#define SDRAM_REG 0x106 #define BWSCON 0x48000000 -#define PLD_BASE 0x2C000000 -#define SDRAM_REG 0x2C000106 +#define CLKBASE 0x4C000000 +#define LOCKTIME 0x0 +#define MPLLCON 0x4 +#define UPLLCON 0x8 +#define GPIOBASE 0x56000000 +#define GSTATUS1 0xB0 +#define FASTCPU 0x02
+/* some parameters for the board */ /* BWSCON */ #define DW8 (0x0) #define DW16 (0x1) @@ -48,83 +57,160 @@ /* BANKSIZE */ #define BURST_EN (0x1<<7)
-#define B1_BWSCON (DW16) -#define B2_BWSCON (DW32) -#define B3_BWSCON (DW32) -#define B4_BWSCON (DW16 + WAIT + UBLB) -#define B5_BWSCON (DW8 + UBLB) -#define B6_BWSCON (DW32) -#define B7_BWSCON (DW32) - -/* BANK0CON */ -#define B0_Tacs 0x0 /* 0clk */ -#define B0_Tcos 0x1 /* 1clk */ -/*#define B0_Tcos 0x0 0clk */ -#define B0_Tacc 0x7 /* 14clk */ -/*#define B0_Tacc 0x5 8clk */ -#define B0_Tcoh 0x0 /* 0clk */ -#define B0_Tah 0x0 /* 0clk */ -#define B0_Tacp 0x0 /* page mode is not used */ -#define B0_PMC 0x0 /* page mode disabled */ - -/* BANK1CON */ -#define B1_Tacs 0x0 /* 0clk */ -#define B1_Tcos 0x1 /* 1clk */ -/*#define B1_Tcos 0x0 0clk */ -#define B1_Tacc 0x7 /* 14clk */ -/*#define B1_Tacc 0x5 8clk */ -#define B1_Tcoh 0x0 /* 0clk */ -#define B1_Tah 0x0 /* 0clk */ -#define B1_Tacp 0x0 /* page mode is not used */ -#define B1_PMC 0x0 /* page mode disabled */ +/* BANK0CON 200 */ +#define B0_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B0_Tcoh_200 0x0 /* 0clk */ +#define B0_Tcah_200 0x3 /* 4clk (or0x01 1clk) */ +#define B0_Tacp_200 0x0 /* page mode is not used */ +#define B0_PMC_200 0x0 /* page mode disabled */ + +/* BANK0CON 250 */ +#define B0_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B0_Tcoh_250 0x0 /* 0clk */ +#define B0_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_250 0x0 /* page mode is not used */ +#define B0_PMC_250 0x0 /* page mode disabled */ + +/* BANK0CON 266 */ +#define B0_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B0_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B0_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B0_Tcoh_266 0x0 /* 0clk */ +#define B0_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B0_Tacp_266 0x0 /* page mode is not used */ +#define B0_PMC_266 0x0 /* page mode disabled */ + +/* BANK1CON 200 */ +#define B1_Tacs_200 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_200 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_200 0x5 /* 8clk (or 0x6 10clk) */ +#define B1_Tcoh_200 0x0 /* 0clk */ +#define B1_Tcah_200 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_200 0x0 /* page mode is not used */ +#define B1_PMC_200 0x0 /* page mode disabled */ + +/* BANK1CON 250 */ +#define B1_Tacs_250 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_250 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_250 0x5 /* 8clk (or 0x7 14clk) */ +#define B1_Tcoh_250 0x0 /* 0clk */ +#define B1_Tcah_250 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_250 0x0 /* page mode is not used */ +#define B1_PMC_250 0x0 /* page mode disabled */ + +/* BANK1CON 266 */ +#define B1_Tacs_266 0x0 /* 0clk (or 0x1 1clk) */ +#define B1_Tcos_266 0x1 /* 1clk (or 0x2 2clk) */ +#define B1_Tacc_266 0x6 /* 10clk (or 0x7 14clk) */ +#define B1_Tcoh_266 0x0 /* 0clk */ +#define B1_Tcah_266 0x3 /* 4clk (or 0x1 1clk) */ +#define B1_Tacp_266 0x0 /* page mode is not used */ +#define B1_PMC_266 0x0 /* page mode disabled */
+/* BANK2CON 200 + 250 + 266 */ #define B2_Tacs 0x3 /* 4clk */ #define B2_Tcos 0x3 /* 4clk */ #define B2_Tacc 0x7 /* 14clk */ #define B2_Tcoh 0x3 /* 4clk */ -#define B2_Tah 0x3 /* 4clk */ +#define B2_Tcah 0x3 /* 4clk */ #define B2_Tacp 0x0 /* page mode is not used */ #define B2_PMC 0x0 /* page mode disabled */
+/* BANK3CON 200 + 250 + 266 */ #define B3_Tacs 0x3 /* 4clk */ #define B3_Tcos 0x3 /* 4clk */ #define B3_Tacc 0x7 /* 14clk */ #define B3_Tcoh 0x3 /* 4clk */ -#define B3_Tah 0x3 /* 4clk */ +#define B3_Tcah 0x3 /* 4clk */ #define B3_Tacp 0x0 /* page mode is not used */ #define B3_PMC 0x0 /* page mode disabled */
-#define B4_Tacs 0x3 /* 4clk */ -#define B4_Tcos 0x1 /* 1clk */ -#define B4_Tacc 0x7 /* 14clk */ -#define B4_Tcoh 0x1 /* 1clk */ -#define B4_Tah 0x0 /* 0clk */ -#define B4_Tacp 0x0 /* page mode is not used */ -#define B4_PMC 0x0 /* page mode disabled */ - -#define B5_Tacs 0x0 /* 0clk */ -#define B5_Tcos 0x3 /* 4clk */ -#define B5_Tacc 0x5 /* 8clk */ -#define B5_Tcoh 0x2 /* 2clk */ -#define B5_Tah 0x1 /* 1clk */ -#define B5_Tacp 0x0 /* page mode is not used */ -#define B5_PMC 0x0 /* page mode disabled */ +/* BANK4CON 200 */ +#define B4_Tacs_200 0x1 /* 1clk */ +#define B4_Tcos_200 0x3 /* 4clk */ +#define B4_Tacc_200 0x7 /* 14clk */ +#define B4_Tcoh_200 0x3 /* 4clk */ +#define B4_Tcah_200 0x2 /* 2clk */ +#define B4_Tacp_200 0x0 /* page mode is not used */ +#define B4_PMC_200 0x0 /* page mode disabled */ + +/* BANK4CON 250 */ +#define B4_Tacs_250 0x1 /* 1clk */ +#define B4_Tcos_250 0x3 /* 4clk */ +#define B4_Tacc_250 0x7 /* 14clk */ +#define B4_Tcoh_250 0x3 /* 4clk */ +#define B4_Tcah_250 0x2 /* 2clk */ +#define B4_Tacp_250 0x0 /* page mode is not used */ +#define B4_PMC_250 0x0 /* page mode disabled */ + +/* BANK4CON 266 */ +#define B4_Tacs_266 0x1 /* 1clk */ +#define B4_Tcos_266 0x3 /* 4clk */ +#define B4_Tacc_266 0x7 /* 14clk */ +#define B4_Tcoh_266 0x3 /* 4clk */ +#define B4_Tcah_266 0x2 /* 2clk */ +#define B4_Tacp_266 0x0 /* page mode is not used */ +#define B4_PMC_266 0x0 /* page mode disabled */ + +/* BANK5CON 200 */ +#define B5_Tacs_200 0x0 /* 0clk */ +#define B5_Tcos_200 0x3 /* 4clk */ +#define B5_Tacc_200 0x4 /* 6clk */ +#define B5_Tcoh_200 0x3 /* 4clk */ +#define B5_Tcah_200 0x1 /* 1clk */ +#define B5_Tacp_200 0x0 /* page mode is not used */ +#define B5_PMC_200 0x0 /* page mode disabled */ + +/* BANK5CON 250 */ +#define B5_Tacs_250 0x0 /* 0clk */ +#define B5_Tcos_250 0x3 /* 4clk */ +#define B5_Tacc_250 0x5 /* 8clk */ +#define B5_Tcoh_250 0x3 /* 4clk */ +#define B5_Tcah_250 0x1 /* 1clk */ +#define B5_Tacp_250 0x0 /* page mode is not used */ +#define B5_PMC_250 0x0 /* page mode disabled */ + +/* BANK5CON 266 */ +#define B5_Tacs_266 0x0 /* 0clk */ +#define B5_Tcos_266 0x3 /* 4clk */ +#define B5_Tacc_266 0x5 /* 8clk */ +#define B5_Tcoh_266 0x3 /* 4clk */ +#define B5_Tcah_266 0x1 /* 1clk */ +#define B5_Tacp_266 0x0 /* page mode is not used */ +#define B5_PMC_266 0x0 /* page mode disabled */
#define B6_MT 0x3 /* SDRAM */ -#define B6_Trcd 0x1 /* 3clk */ +#define B6_Trcd_200 0x0 /* 2clk */ +#define B6_Trcd_250 0x1 /* 3clk */ +#define B6_Trcd_266 0x1 /* 3clk */ #define B6_SCAN 0x2 /* 10bit */
#define B7_MT 0x3 /* SDRAM */ -#define B7_Trcd 0x1 /* 3clk */ +#define B7_Trcd_200 0x0 /* 2clk */ +#define B7_Trcd_250 0x1 /* 3clk */ +#define B7_Trcd_266 0x1 /* 3clk */ #define B7_SCAN 0x2 /* 10bit */
/* REFRESH parameter */ #define REFEN 0x1 /* Refresh enable */ #define TREFMD 0x0 /* CBR(CAS before RAS)/Auto refresh */ -#define Trp 0x0 /* 2clk */ -#define Trc 0x3 /* 7clk */ -#define Tchr 0x2 /* 3clk */ -#define REFCNT 1113 /* period=15.6us, HCLK=60Mhz, (2048+1-15.6*60) */ +#define Trp_200 0x0 /* 2clk */ +#define Trp_250 0x1 /* 3clk */ +#define Trp_266 0x1 /* 3clk */ +#define Tsrc_200 0x1 /* 5clk */ +#define Tsrc_250 0x2 /* 6clk */ +#define Tsrc_266 0x3 /* 7clk */ + +/* period=15.6us, HCLK=100Mhz, (2048+1-15.6*100) */ +#define REFCNT_200 489 +/* period=15.6us, HCLK=125Mhz, (2048+1-15.6*125) */ +#define REFCNT_250 99 +/* period=15.6us, HCLK=133Mhz, (2048+1-15.6*133) */ +#define REFCNT_266 0 /**************************************/
_TEXT_BASE: @@ -132,81 +218,304 @@ _TEXT_BASE:
.globl lowlevel_init lowlevel_init: + /* use r0 to relocate DATA read/write to flash rather than memory ! */ + ldr r0, _TEXT_BASE + ldr r13, =BWSCON + + /* enable minimal access to PLD */ + ldr r1, [r13] /* load default BWSCON */ + orr r1, r1, #(DW8 + UBLB) << 20 /* set necessary CS attrs */ + str r1, [r13] /* set BWSCON */ + ldr r1, =0x7FF0 /* select slowest timing */ + str r1, [r13, #0x18] /* set BANKCON5 */ + + ldr r1, =PLD_BASE + ldr r2, =SETUPDATA + ldrb r1, [r1, #MISC_REG] + sub r2, r2, r0 + tst r1, #FASTCPU /* FASTCPU available ? */ + addeq r2, r2, #SETUPENTRY_SIZE + /* memory control configuration */ - /* make r0 relative the current location so that it */ - /* reads SMRDATA out of FLASH rather than memory ! */ - ldr r0, =CSDATA - ldr r1, _TEXT_BASE - sub r0, r0, r1 - ldr r1, =BWSCON /* Bus Width Status Controller */ - add r2, r0, #CSDATA_END-CSDATA + /* r2 = pointer into timing table */ + /* r13 = pointer to MEM controller regs (starting with BWSCON) */ + add r3, r2, #CSDATA_OFFSET + add r4, r3, #CSDATAENTRY_SIZE 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
/* PLD access is now possible */ - /* r0 == SDRAMDATA */ - /* r1 == SDRAM controller regs */ - ldr r2, =PLD_BASE - ldrb r3, [r2, #SDRAM_REG-PLD_BASE] - mov r4, #SDRAMDATA1_END-SDRAMDATA + /* r3 = SDRAMDATA + /* r13 = pointer to MEM controller regs */ + ldr r1, =PLD_BASE + mov r4, #SDRAMENTRY_SIZE + ldrb r1, [r1, #SDRAM_REG] /* calculate start and end point */ - mla r0, r3, r4, r0 - add r2, r0, r4 + mla r3, r4, r1, r3 + add r4, r3, r4 0: - ldr r3, [r0], #4 - str r3, [r1], #4 - cmp r2, r0 + ldr r1, [r3], #4 + str r1, [r13], #4 + cmp r3, r4 bne 0b
+ /* setup MPLL registers */ + ldr r1, =CLKBASE + ldr r4, =0xFFFFFF + add r3, r2, #4 /* r3 points to PLL values */ + str r4, [r1, #LOCKTIME] + ldmia r3, {r4,r5} + str r5, [r1, #UPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + + str r4, [r1, #MPLLCON] /* writing PLL register */ + /* !! order seems to be important !! */ + /* a little delay */ + ldr r3, =0x4000 +0: + subs r3, r3, #1 + bne 0b + /* everything is fine now */ mov pc, lr
.ltorg /* the literal pools origin */
-CSDATA: - .word (0+(B1_BWSCON<<4)+(B2_BWSCON<<8)+(B3_BWSCON<<12)+(B4_BWSCON<<16)+(B5_BWSCON<<20)+(B6_BWSCON<<24)+(B7_BWSCON<<28)) - .word ((B0_Tacs<<13)+(B0_Tcos<<11)+(B0_Tacc<<8)+(B0_Tcoh<<6)+(B0_Tah<<4)+(B0_Tacp<<2)+(B0_PMC)) - .word ((B1_Tacs<<13)+(B1_Tcos<<11)+(B1_Tacc<<8)+(B1_Tcoh<<6)+(B1_Tah<<4)+(B1_Tacp<<2)+(B1_PMC)) - .word ((B2_Tacs<<13)+(B2_Tcos<<11)+(B2_Tacc<<8)+(B2_Tcoh<<6)+(B2_Tah<<4)+(B2_Tacp<<2)+(B2_PMC)) - .word ((B3_Tacs<<13)+(B3_Tcos<<11)+(B3_Tacc<<8)+(B3_Tcoh<<6)+(B3_Tah<<4)+(B3_Tacp<<2)+(B3_PMC)) - .word ((B4_Tacs<<13)+(B4_Tcos<<11)+(B4_Tacc<<8)+(B4_Tcoh<<6)+(B4_Tah<<4)+(B4_Tacp<<2)+(B4_PMC)) - .word ((B5_Tacs<<13)+(B5_Tcos<<11)+(B5_Tacc<<8)+(B5_Tcoh<<6)+(B5_Tah<<4)+(B5_Tacp<<2)+(B5_PMC)) -CSDATA_END: - -SDRAMDATA: -/* 4Mx8x4 */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 -SDRAMDATA1_END: - -/* 8Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 2Mx8x4 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 - -/* 4Mx8x2 (not implemented yet) */ - .word ((B6_MT<<15)+(B6_Trcd<<2)+(B6_SCAN)) - .word ((B7_MT<<15)+(B7_Trcd<<2)+(B7_SCAN)) - .word ((REFEN<<23)+(TREFMD<<22)+(Trp<<20)+(Trc<<18)+(Tchr<<16)+REFCNT) - .word 0x32 + BURST_EN - .word 0x30 - .word 0x30 +#define MK_BWSCON(bws1, bws2, bws3, bws4, bws5, bws6, bws7) \ + ((bws1) << 4) + \ + ((bws2) << 8) + \ + ((bws3) << 12) + \ + ((bws4) << 16) + \ + ((bws5) << 20) + \ + ((bws6) << 24) + \ + ((bws7) << 28) + +#define MK_BANKCON(tacs, tcos, tacc, tcoh, tcah, tacp, pmc) \ + ((tacs) << 13) + \ + ((tcos) << 11) + \ + ((tacc) << 8) + \ + ((tcoh) << 6) + \ + ((tcah) << 4) + \ + ((tacp) << 2) + \ + (pmc) + +#define MK_BANKCON_SDRAM(trcd, scan) \ + ((0x03) << 15) + \ + ((trcd) << 2) + \ + (scan) + +#define MK_SDRAM_REFRESH(enable, trefmd, trp, tsrc, cnt) \ + ((enable) << 23) + \ + ((trefmd) << 22) + \ + ((trp) << 20) + \ + ((tsrc) << 18) + \ + (cnt) + +SETUPDATA: + .word 0x32410002 + /* PLL values (MDIV, PDIV, SDIV) for 250 MHz */ + .word (0x75 << 12) + (0x01 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 250 MHz*/ +0: + .equiv CSDATA_OFFSET, (. - SETUPDATA) + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_250, \ + B0_Tcos_250, \ + B0_Tacc_250, \ + B0_Tcoh_250, \ + B0_Tcah_250, \ + B0_Tacp_250, \ + B0_PMC_250) + + .word MK_BANKCON(B1_Tacs_250, \ + B1_Tcos_250, \ + B1_Tacc_250, \ + B1_Tcoh_250, \ + B1_Tcah_250, \ + B1_Tacp_250, \ + B1_PMC_250) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_250, \ + B4_Tcos_250, \ + B4_Tacc_250, \ + B4_Tcoh_250, \ + B4_Tcah_250, \ + B4_Tacp_250, \ + B4_PMC_250) + + .word MK_BANKCON(B5_Tacs_250, \ + B5_Tcos_250, \ + B5_Tacc_250, \ + B5_Tcoh_250, \ + B5_Tcah_250, \ + B5_Tacp_250, \ + B5_PMC_250) + + .equiv CSDATAENTRY_SIZE, (. - 0b) + /* 4Mx8x4 */ +0: + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + .equiv SDRAMENTRY_SIZE, (. - 0b) + + /* 8Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 */ + .word MK_BANKCON_SDRAM(B6_Trcd_250, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_250, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_250, Tsrc_250, REFCNT_250) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPENTRY_SIZE, (. - SETUPDATA) + + .word 0x32410000 + /* PLL values (MDIV, PDIV, SDIV) for 200 MHz (Fout = 202.8MHz) */ + .word (0xA1 << 12) + (0x03 << 4) + (0x01 << 0) + /* PLL values for USB clock */ + .word (0x48 << 12) + (0x03 << 4) + (0x02 << 0) + + /* timing for 200 MHz and default*/ + .word MK_BWSCON(DW16, \ + DW32, \ + DW32, \ + DW16 + WAIT + UBLB, \ + DW8 + UBLB, \ + DW32, \ + DW32) + + .word MK_BANKCON(B0_Tacs_200, \ + B0_Tcos_200, \ + B0_Tacc_200, \ + B0_Tcoh_200, \ + B0_Tcah_200, \ + B0_Tacp_200, \ + B0_PMC_200) + + .word MK_BANKCON(B1_Tacs_200, \ + B1_Tcos_200, \ + B1_Tacc_200, \ + B1_Tcoh_200, \ + B1_Tcah_200, \ + B1_Tacp_200, \ + B1_PMC_200) + + .word MK_BANKCON(B2_Tacs, \ + B2_Tcos, \ + B2_Tacc, \ + B2_Tcoh, \ + B2_Tcah, \ + B2_Tacp, \ + B2_PMC) + + .word MK_BANKCON(B3_Tacs, \ + B3_Tcos, \ + B3_Tacc, \ + B3_Tcoh, \ + B3_Tcah, \ + B3_Tacp, \ + B3_PMC) + + .word MK_BANKCON(B4_Tacs_200, \ + B4_Tcos_200, \ + B4_Tacc_200, \ + B4_Tcoh_200, \ + B4_Tcah_200, \ + B4_Tacp_200, \ + B4_PMC_200) + + .word MK_BANKCON(B5_Tacs_200, \ + B5_Tcos_200, \ + B5_Tacc_200, \ + B5_Tcoh_200, \ + B5_Tcah_200, \ + B5_Tacp_200, \ + B5_PMC_200) + + /* 4Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 8Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 2Mx8x4 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + /* 4Mx8x2 */ + .word MK_BANKCON_SDRAM(B6_Trcd_200, B6_SCAN) + .word MK_BANKCON_SDRAM(B7_Trcd_200, B7_SCAN) + .word MK_SDRAM_REFRESH(REFEN, TREFMD, Trp_200, Tsrc_200, REFCNT_200) + .word 0x32 + BURST_EN + .word 0x30 + .word 0x30 + + .equiv SETUPDATA_SIZE, (. - SETUPDATA) diff --git a/board/mpl/vcma9/vcma9.c b/board/mpl/vcma9/vcma9.c index 171a128..e63625b 100644 --- a/board/mpl/vcma9/vcma9.c +++ b/board/mpl/vcma9/vcma9.c @@ -3,7 +3,7 @@ * Sysgo Real-Time Solutions, GmbH <www.elinos.com> * Marius Groeger mgroeger@sysgo.de * - * (C) Copyright 2002 + * (C) Copyright 2002, 2010 * David Mueller, ELSOFT AG, d.mueller@elsoft.ch * * See file CREDITS for list of people who contributed to this @@ -27,100 +27,51 @@
#include <common.h> #include <netdev.h> -#include <asm/arch/s3c24x0_cpu.h> -#include <stdio_dev.h> #include <i2c.h> +#include <asm/io.h> +#include <asm/arch/s3c24x0_cpu.h>
#include "vcma9.h" #include "../common/common_util.h"
DECLARE_GLOBAL_DATA_PTR;
-#define FCLK_SPEED 1 - -#if FCLK_SPEED==0 /* Fout = 203MHz, Fin = 12MHz for Audio */ -#define M_MDIV 0xC3 -#define M_PDIV 0x4 -#define M_SDIV 0x1 -#elif FCLK_SPEED==1 /* Fout = 202.8MHz */ -#define M_MDIV 0xA1 -#define M_PDIV 0x3 -#define M_SDIV 0x1 -#endif - -#define USB_CLOCK 1 - -#if USB_CLOCK==0 -#define U_M_MDIV 0xA1 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x1 -#elif USB_CLOCK==1 -#define U_M_MDIV 0x48 -#define U_M_PDIV 0x3 -#define U_M_SDIV 0x2 -#endif - -static inline void delay(unsigned long loops) -{ - __asm__ volatile ("1:\n" - "subs %0, %1, #1\n" - "bne 1b":"=r" (loops):"0" (loops)); -} - /* * Miscellaneous platform dependent initialisations */
-int board_init(void) +int board_early_init_f(void) { - struct s3c24x0_clock_power * const clk_power = - s3c24x0_get_base_clock_power(); struct s3c24x0_gpio * const gpio = s3c24x0_get_base_gpio();
- /* to reduce PLL lock time, adjust the LOCKTIME register */ - clk_power->locktime = 0xFFFFFF; - - /* configure MPLL */ - clk_power->mpllcon = ((M_MDIV << 12) + (M_PDIV << 4) + M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (4000); - - /* configure UPLL */ - clk_power->upllcon = ((U_M_MDIV << 12) + (U_M_PDIV << 4) + U_M_SDIV); - - /* some delay between MPLL and UPLL */ - delay (8000); - /* set up the I/O ports */ - gpio->gpacon = 0x007FFFFF; - gpio->gpbcon = 0x002AAAAA; - gpio->gpbup = 0x000002BF; - gpio->gpccon = 0xAAAAAAAA; - gpio->gpcup = 0x0000FFFF; - gpio->gpdcon = 0xAAAAAAAA; - gpio->gpdup = 0x0000FFFF; - gpio->gpecon = 0xAAAAAAAA; - gpio->gpeup = 0x000037F7; - gpio->gpfcon = 0x00000000; - gpio->gpfup = 0x00000000; - gpio->gpgcon = 0xFFEAFF5A; - gpio->gpgup = 0x0000F0DC; - gpio->gphcon = 0x0028AAAA; - gpio->gphup = 0x00000656; - - /* setup correct IRQ modes for NIC */ - /* rising edge mode */ - gpio->extint2 = (gpio->extint2 & ~(7<<8)) | (4<<8); - - /* select USB port 2 to be host or device (fix to host for now) */ - gpio->misccr |= 0x08; - - /* init serial */ - gd->baudrate = CONFIG_BAUDRATE; - gd->have_console = 1; - serial_init(); + writel(0x007FFFFF, &gpio->gpacon); + writel(0x002AAAAA, &gpio->gpbcon); + writel(0x000002BF, &gpio->gpbup); + writel(0xAAAAAAAA, &gpio->gpccon); + writel(0x0000FFFF, &gpio->gpcup); + writel(0xAAAAAAAA, &gpio->gpdcon); + writel(0x0000FFFF, &gpio->gpdup); + writel(0xAAAAAAAA, &gpio->gpecon); + writel(0x000037F7, &gpio->gpeup); + writel(0x00000000, &gpio->gpfcon); + writel(0x00000000, &gpio->gpfup); + writel(0xFFEAFF5A, &gpio->gpgcon); + writel(0x0000F0DC, &gpio->gpgup); + writel(0x0028AAAA, &gpio->gphcon); + writel(0x00000656, &gpio->gphup); + + /* setup correct IRQ modes for NIC (rising edge mode) */ + writel((readl(&gpio->extint2) & ~(7<<8)) | (4<<8), &gpio->extint2); + + /* select USB port 2 to be host or device (setup as host for now) */ + writel(readl(&gpio->misccr) | 0x08, &gpio->misccr);
+ return 0; +} + +int board_init(void) +{ /* arch number of VCMA9-Board */ gd->bd->bi_arch_number = MACH_TYPE_MPL_VCMA9;
@@ -134,113 +85,32 @@ int board_init(void) }
/* - * NAND flash initialization. - */ -#if defined(CONFIG_CMD_NAND) -extern ulong -nand_probe(ulong physadr); - - -static inline void NF_Reset(void) -{ - int i; - - NF_SetCE(NFCE_LOW); - NF_Cmd(0xFF); /* reset command */ - for(i = 0; i < 10; i++); /* tWB = 100ns. */ - NF_WaitRB(); /* wait 200~500us; */ - NF_SetCE(NFCE_HIGH); -} - - -static inline void NF_Init(void) -{ -#if 0 /* a little bit too optimistic */ -#define TACLS 0 -#define TWRPH0 3 -#define TWRPH1 0 -#else -#define TACLS 0 -#define TWRPH0 4 -#define TWRPH1 2 -#endif - - NF_Conf((1<<15)|(0<<14)|(0<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0)); - /*nand->NFCONF = (1<<15)|(1<<14)|(1<<13)|(1<<12)|(1<<11)|(TACLS<<8)|(TWRPH0<<4)|(TWRPH1<<0); */ - /* 1 1 1 1, 1 xxx, r xxx, r xxx */ - /* En 512B 4step ECCR nFCE=H tACLS tWRPH0 tWRPH1 */ - - NF_Reset(); -} - -void -nand_init(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - NF_Init(); -#ifdef DEBUG - printf("NAND flash probing at 0x%.8lX\n", (ulong)nand); -#endif - printf ("%4lu MB\n", nand_probe((ulong)nand) >> 20); -} -#endif - -/* * Get some Board/PLD Info */
-static u8 Get_PLD_ID(void) +static u8 get_pld_reg(enum vcma9_pld_regs reg) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->ID); + return readb(VCMA9_PLD_BASE + reg); }
-static u8 Get_PLD_BOARD(void) +static u8 get_pld_version(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->BOARD); + return (get_pld_reg(VCMA9_PLD_ID) >> 4) & 0x0F; }
-static u8 Get_PLD_SDRAM(void) +static u8 get_pld_revision(void) { - VCMA9_PLD * const pld = VCMA9_get_base_PLD(); - - return(pld->SDRAM); + return get_pld_reg(VCMA9_PLD_ID) & 0x0F; }
-static u8 Get_PLD_Version(void) +static uchar get_board_pcb(void) { - return((Get_PLD_ID() >> 4) & 0x0F); + return ((get_pld_reg(VCMA9_PLD_BOARD) >> 4) & 0x03) + 'A'; }
-static u8 Get_PLD_Revision(void) +static u8 get_nr_chips(void) { - return(Get_PLD_ID() & 0x0F); -} - -#if 0 /* not used */ -static int Get_Board_Config(void) -{ - u8 config = Get_PLD_BOARD() & 0x03; - - if (config == 3) - return 1; - else - return 0; -} -#endif - -static uchar Get_Board_PCB(void) -{ - return(((Get_PLD_BOARD() >> 4) & 0x03) + 'A'); -} - -static u8 Get_SDRAM_ChipNr(void) -{ - switch ((Get_PLD_SDRAM() >> 4) & 0x0F) { + switch ((get_pld_reg(VCMA9_PLD_SDRAM) >> 4) & 0x0F) { case 0: return 4; case 1: return 1; case 2: return 2; @@ -248,9 +118,9 @@ static u8 Get_SDRAM_ChipNr(void) } }
-static ulong Get_SDRAM_ChipSize(void) +static ulong get_chip_size(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return 16 * (1024*1024); case 1: return 32 * (1024*1024); case 2: return 8 * (1024*1024); @@ -258,9 +128,10 @@ static ulong Get_SDRAM_ChipSize(void) default: return 0; } } -static const char * Get_SDRAM_ChipGeom(void) + +static const char *get_chip_geom(void) { - switch (Get_PLD_SDRAM() & 0x0F) { + switch (get_pld_reg(VCMA9_PLD_SDRAM) & 0x0F) { case 0: return "4Mx8x4"; case 1: return "8Mx8x4"; case 2: return "2Mx8x4"; @@ -269,23 +140,21 @@ static const char * Get_SDRAM_ChipGeom(void) } }
-static void Show_VCMA9_Info(char *board_name, char *serial) +static void vcma9_show_info(char *board_name, char *serial) { printf("Board: %s SN: %s PCB Rev: %c PLD(%d,%d)\n", - board_name, serial, Get_Board_PCB(), Get_PLD_Version(), Get_PLD_Revision()); - printf("SDRAM: %d chips %s\n", Get_SDRAM_ChipNr(), Get_SDRAM_ChipGeom()); + board_name, serial, + get_board_pcb(), get_pld_version(), get_pld_revision()); + printf("SDRAM: %d chips %s\n", get_nr_chips(), get_chip_geom()); }
int dram_init(void) { - gd->bd->bi_dram[0].start = PHYS_SDRAM_1; - gd->bd->bi_dram[0].size = Get_SDRAM_ChipSize() * Get_SDRAM_ChipNr(); - + /* dram_init must store complete ramsize in gd->ram_size */ + gd->ram_size = get_chip_size() * get_nr_chips(); return 0; }
-/* ------------------------------------------------------------------------- */ - /* * Check Board Identity: */ @@ -303,50 +172,35 @@ int checkboard(void) puts ("### No HW ID - assuming VCMA9"); } else { b->serial_name[5] = 0; - Show_VCMA9_Info(b->serial_name, &b->serial_name[6]); + vcma9_show_info(b->serial_name, &b->serial_name[6]); } } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } - /*printf("\n");*/ - return(0); -}
- -int last_stage_init(void) -{ - checkboard(); - stdio_print_current_devices(); - check_env(); return 0; }
-/*************************************************************************** - * some helping routines - */ -#if !CONFIG_USB_KEYBOARD -int overwrite_console(void) +int board_late_init(void) { - /* return TRUE if console should be overwritten */ + /* + * check if environment is healthy, otherwise restore values + * from shadow copy + */ + check_env(); return 0; } -#endif
-/************************************************************************ -* Print VCMA9 Info -************************************************************************/ -void print_vcma9_info(void) +void vcma9_print_info(void) { - char s[50]; - int i; + char *s = getenv("serial#");
- if ((i = getenv_f("serial#", s, 32)) < 0) { + if (!s) { puts ("### No HW ID - assuming VCMA9"); - printf("i %d", i*24); } else { s[5] = 0; - Show_VCMA9_Info(s, &s[6]); + vcma9_show_info(s, &s[6]); } }
diff --git a/board/mpl/vcma9/vcma9.h b/board/mpl/vcma9/vcma9.h index 94fd2fa..7c44194 100644 --- a/board/mpl/vcma9/vcma9.h +++ b/board/mpl/vcma9/vcma9.h @@ -27,108 +27,19 @@
#include <asm/arch/s3c24x0_cpu.h>
-extern int mem_test(unsigned long start, unsigned long ramsize,int mode); - -void print_vcma9_info(void); - -#if defined(CONFIG_CMD_NAND) -typedef enum { - NFCE_LOW, - NFCE_HIGH -} NFCE_STATE; - -static inline void NF_Conf(u16 conf) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF = conf; -} - -static inline void NF_Cmd(u8 cmd) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCMD = cmd; -} - -static inline void NF_CmdW(u8 cmd) -{ - NF_Cmd(cmd); - udelay(1); -} - -static inline void NF_Addr(u8 addr) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFADDR = addr; -} - -static inline void NF_SetCE(NFCE_STATE s) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - switch (s) { - case NFCE_LOW: - nand->NFCONF &= ~(1<<11); - break; - - case NFCE_HIGH: - nand->NFCONF |= (1<<11); - break; - } -} - -static inline void NF_WaitRB(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - while (!(nand->NFSTAT & (1<<0))); -} - -static inline void NF_Write(u8 data) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFDATA = data; -} - -static inline u8 NF_Read(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFDATA); -} - -static inline void NF_Init_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - nand->NFCONF |= (1<<12); -} - -static inline u32 NF_Read_ECC(void) -{ - struct s3c2410_nand * const nand = s3c2410_get_base_nand(); - - return(nand->NFECC); -} - -#endif - -/* VCMA9 PLD regsiters */ -typedef struct { - u8 ID; - u8 NIC; - u8 CAN; - u8 MISC; - u8 GPCD; - u8 BOARD; - u8 SDRAM; -} /*__attribute__((__packed__))*/ VCMA9_PLD; - -#define VCMA9_PLD_BASE 0x2C000100 -static inline VCMA9_PLD *VCMA9_get_base_PLD(void) -{ - return (VCMA9_PLD * const)VCMA9_PLD_BASE; -} +extern void vcma9_print_info(void); +extern int do_mplcommon(cmd_tbl_t *cmdtp, int flag, + int argc, char *const argv[]); + +/* VCMA9 PLD registers */ +enum vcma9_pld_regs { + VCMA9_PLD_ID, + VCMA9_PLD_NIC, + VCMA9_PLD_CAN, + VCMA9_PLD_MISC, + VCMA9_PLD_GPCD, + VCMA9_PLD_BOARD, + VCMA9_PLD_SDRAM +}; + +#define VCMA9_PLD_BASE (0x2C000100) diff --git a/include/configs/VCMA9.h b/include/configs/VCMA9.h index 11a61e2..740cb75 100644 --- a/include/configs/VCMA9.h +++ b/include/configs/VCMA9.h @@ -33,23 +33,23 @@ * High Level Configuration Options * (easy to change) */ -#define CONFIG_ARM920T 1 /* This is an ARM920T Core */ -#define CONFIG_S3C24X0 1 /* in a SAMSUNG S3C24x0-type SoC */ -#define CONFIG_S3C2410 1 /* specifically a SAMSUNG S3C2410 SoC */ -#define CONFIG_VCMA9 1 /* on a MPL VCMA9 Board */ +#define CONFIG_ARM920T /* This is an ARM920T Core */ +#define CONFIG_S3C24X0 /* in a SAMSUNG S3C24x0-type SoC */ +#define CONFIG_S3C2410 /* specifically a SAMSUNG S3C2410 SoC */ +#define CONFIG_VCMA9 /* on a MPL VCMA9 Board */
#define CONFIG_SYS_TEXT_BASE 0x0
-/* input clock of PLL */ -#define CONFIG_SYS_CLK_FREQ 12000000/* VCMA9 has 12MHz input clock */ +#define CONFIG_SYS_ARM_CACHE_WRITETHROUGH
-#define USE_920T_MMU 1 -#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */ +/* input clock of PLL (VCMA9 has 12MHz input clock) */ +#define CONFIG_SYS_CLK_FREQ 12000000
-#define CONFIG_CMDLINE_TAG 1 /* enable passing of ATAGs */ -#define CONFIG_SETUP_MEMORY_TAGS 1 -#define CONFIG_INITRD_TAG 1 +#undef CONFIG_USE_IRQ /* we don't need IRQ/FIQ stuff */
+#define CONFIG_CMDLINE_TAG /* enable passing of ATAGs */ +#define CONFIG_SETUP_MEMORY_TAGS +#define CONFIG_INITRD_TAG
/* * BOOTP options @@ -59,7 +59,6 @@ #define CONFIG_BOOTP_GATEWAY #define CONFIG_BOOTP_HOSTNAME
- /* * Command line configuration. */ @@ -70,178 +69,198 @@ #define CONFIG_CMD_I2C #define CONFIG_CMD_USB #define CONFIG_CMD_REGINFO -#define CONFIG_CMD_FAT #define CONFIG_CMD_DATE #define CONFIG_CMD_ELF #define CONFIG_CMD_DHCP #define CONFIG_CMD_PING #define CONFIG_CMD_BSP +#define CONFIG_CMD_NAND
+#define BOARD_LATE_INIT
#define CONFIG_SYS_HUSH_PARSER #define CONFIG_SYS_PROMPT_HUSH_PS2 "> " -/*********************************************************** +#define CONFIG_CMDLINE_EDITING + +/* * I2C stuff: * the MPL VCMA9 is equipped with an ATMEL 24C256 EEPROM at * address 0x50 with 16bit addressing - ***********************************************************/ -#define CONFIG_HARD_I2C /* I2C with hardware support */ + */ +#define CONFIG_HARD_I2C /* I2C with hardware support */ #define CONFIG_SYS_I2C_SPEED 100000 /* I2C speed */ #define CONFIG_SYS_I2C_SLAVE 0x7F /* I2C slave addr */
+/* we use the built-in I2C controller */ +#define CONFIG_DRIVER_S3C24X0_I2C + #define CONFIG_SYS_I2C_EEPROM_ADDR 0x50 #define CONFIG_SYS_I2C_EEPROM_ADDR_LEN 2 -#define CONFIG_ENV_IS_IN_EEPROM 1 /* use EEPROM for environment vars */ -#define CONFIG_ENV_OFFSET 0x000 /* environment starts at offset 0 */ -#define CONFIG_ENV_SIZE 0x800 /* 2KB should be more than enough */ +/* use EEPROM for environment vars */ +#define CONFIG_ENV_IS_IN_EEPROM 1 +/* environment starts at offset 0 */ +#define CONFIG_ENV_OFFSET 0x000 +/* 2KB should be more than enough */ +#define CONFIG_ENV_SIZE 0x800
#undef CONFIG_SYS_I2C_EEPROM_ADDR_OVERFLOW -#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 /* 64 bytes page write mode on 24C256 */ +/* 64 bytes page write mode on 24C256 */ +#define CONFIG_SYS_EEPROM_PAGE_WRITE_BITS 6 #define CONFIG_SYS_EEPROM_PAGE_WRITE_DELAY_MS 10
/* - * Size of malloc() pool - */ -/*#define CONFIG_MALLOC_SIZE (CONFIG_ENV_SIZE + 128*1024)*/ - -#define CONFIG_SYS_MONITOR_LEN (256 * 1024) -#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE -#define CONFIG_SYS_MALLOC_LEN (1024 * 1024) /* BUNZIP2 needs a lot of RAM */ - -/* * Hardware drivers */ #define CONFIG_NET_MULTI -#define CONFIG_CS8900 /* we have a CS8900 on-board */ -#define CONFIG_CS8900_BASE 0x20000300 -#define CONFIG_CS8900_BUS16 /* the Linux driver does accesses as shorts */ - -#define CONFIG_DRIVER_S3C24X0_I2C 1 /* we use the buildin I2C controller */ +#define CONFIG_CS8900 /* we have a CS8900 on-board */ +#define CONFIG_CS8900_BASE 0x20000300 +#define CONFIG_CS8900_BUS16
/* * select serial console configuration */ #define CONFIG_S3C24X0_SERIAL -#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */ +#define CONFIG_SERIAL1 1 /* we use SERIAL 1 on VCMA9 */
-/************************************************************ - * USB support - ************************************************************/ -#define CONFIG_USB_OHCI 1 -#define CONFIG_USB_KEYBOARD 1 -#define CONFIG_USB_STORAGE 1 -#define CONFIG_DOS_PARTITION 1 +/* USB support (currently only works with D-cache off) */ +#define CONFIG_USB_OHCI +#define CONFIG_USB_KEYBOARD +#define CONFIG_USB_STORAGE +#define CONFIG_DOS_PARTITION
/* Enable needed helper functions */ -#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */ +#define CONFIG_SYS_STDIO_DEREGISTER /* needs stdio_deregister */
-/************************************************************ - * RTC - ************************************************************/ -#define CONFIG_RTC_S3C24X0 1 +/* RTC */ +#define CONFIG_RTC_S3C24X0
/* allow to overwrite serial and ethaddr */ #define CONFIG_ENV_OVERWRITE
-#define CONFIG_BAUDRATE 9600 +#define CONFIG_BAUDRATE 9600
-#define CONFIG_BOOTDELAY 5 -/* autoboot (do NOT change this set environment variable "bootdelay" to -1 instead) */ -/* #define CONFIG_BOOT_RETRY_TIME -10 /XXX* feature is available but not enabled */ -#define CONFIG_ZERO_BOOTDELAY_CHECK /* check console even if bootdelay = 0 */ +#define CONFIG_BOOTDELAY 5 +#define CONFIG_BOOT_RETRY_TIME -1 +#define CONFIG_RESET_TO_RETRY +#define CONFIG_ZERO_BOOTDELAY_CHECK
-#define CONFIG_NETMASK 255.255.255.0 -#define CONFIG_IPADDR 10.0.0.110 -#define CONFIG_SERVERIP 10.0.0.1 +#define CONFIG_NETMASK 255.255.255.0 +#define CONFIG_IPADDR 10.0.0.110 +#define CONFIG_SERVERIP 10.0.0.1
#if defined(CONFIG_CMD_KGDB) -#define CONFIG_KGDB_BAUDRATE 115200 /* speed to run kgdb serial port */ +/* speed to run kgdb serial port */ +#define CONFIG_KGDB_BAUDRATE 115200 /* what's this ? it's not used anywhere */ -#define CONFIG_KGDB_SER_INDEX 1 /* which serial port to use */ +#define CONFIG_KGDB_SER_INDEX 2 /* which serial port to use */ #endif
-/* - * Miscellaneous configurable options - */ -#define CONFIG_SYS_LONGHELP /* undef to save memory */ -#define CONFIG_SYS_PROMPT "VCMA9 # " /* Monitor Command Prompt */ -#define CONFIG_SYS_CBSIZE 256 /* Console I/O Buffer Size */ -#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) /* Print Buffer Size */ -#define CONFIG_SYS_MAXARGS 16 /* max number of command args */ -#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE /* Boot Argument Buffer Size */ +/* Miscellaneous configurable options */ +#define CONFIG_SYS_LONGHELP /* undef to save memory */ +#define CONFIG_SYS_PROMPT "VCMA9 # " +#define CONFIG_SYS_CBSIZE 256 +/* Print Buffer Size */ +#define CONFIG_SYS_PBSIZE (CONFIG_SYS_CBSIZE+sizeof(CONFIG_SYS_PROMPT)+16) +#define CONFIG_SYS_MAXARGS 16 +/* Boot Argument Buffer Size */ +#define CONFIG_SYS_BARGSIZE CONFIG_SYS_CBSIZE + +/* to be activated as soon as s3c24x0 has print_cpuinfo support */ +/*#define CONFIG_DISPLAY_CPUINFO*/ /* Display cpu info */ +#define CONFIG_DISPLAY_BOARDINFO /* Display board info */
-#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ -#define CONFIG_SYS_MEMTEST_END 0x30F80000 /* 15.5 MB in DRAM */ +#define CONFIG_SYS_MEMTEST_START 0x30000000 /* memtest works on */ +#define CONFIG_SYS_MEMTEST_END 0x31FFFFFF /* 32 MB in DRAM */
#define CONFIG_SYS_ALT_MEMTEST -#define CONFIG_SYS_LOAD_ADDR 0x30800000 /* default load address */ +#define CONFIG_SYS_LOAD_ADDR 0x30800000
-/* we configure PWM Timer 4 to 1us ~ 1MHz */ -/*#define CONFIG_SYS_HZ 1000000 */ -#define CONFIG_SYS_HZ 1562500 +/* we configure PWM Timer 4 to 1ms 1000Hz */ +#define CONFIG_SYS_HZ 1000
/* valid baudrates */ #define CONFIG_SYS_BAUDRATE_TABLE { 9600, 19200, 38400, 57600, 115200 }
-/* support BZIP2 compression */ -#define CONFIG_BZIP2 1 +/* support additional compression methods */ +#define CONFIG_BZIP2 +#define CONFIG_LZO +#define CONFIG_LZMA
-/************************************************************ - * Ident - ************************************************************/ +/* Ident */ /*#define VERSION_TAG "released"*/ #define VERSION_TAG "unstable" -#define CONFIG_IDENT_STRING "\n(c) 2003 by MPL AG Switzerland, MEV-10080-001 " VERSION_TAG +#define CONFIG_IDENT_STRING "\n(c) 2003 - 2011 by MPL AG Switzerland, " \ + "MEV-10080-001 " VERSION_TAG
-/*----------------------------------------------------------------------- +/* * Stack sizes - * * The stack sizes are set up in start.S using the settings below */ -#define CONFIG_STACKSIZE (128*1024) /* regular stack */ +#define CONFIG_STACKSIZE (128 * 1024) /* regular stack */ #ifdef CONFIG_USE_IRQ -#define CONFIG_STACKSIZE_IRQ (4*1024) /* IRQ stack */ -#define CONFIG_STACKSIZE_FIQ (4*1024) /* FIQ stack */ +#define CONFIG_STACKSIZE_IRQ (4 * 1024) /* IRQ stack */ +#define CONFIG_STACKSIZE_FIQ (4 * 1024) /* FIQ stack */ #endif
-/*----------------------------------------------------------------------- - * Physical Memory Map - */ -#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ -#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ -#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */ +/* Physical Memory Map */ +#define CONFIG_NR_DRAM_BANKS 1 /* we have 1 bank of DRAM */ +#define PHYS_SDRAM_1 0x30000000 /* SDRAM Bank #1 */ +#define PHYS_FLASH_1 0x00000000 /* Flash Bank #1 */
#define CONFIG_SYS_FLASH_BASE PHYS_FLASH_1
-/*----------------------------------------------------------------------- - * FLASH and environment organization - */ +/* FLASH and environment organization */
#define CONFIG_SYS_FLASH_CFI #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_FLASH_CFI_LEGACY #define CONFIG_SYS_FLASH_LEGACY_512Kx16 #define CONFIG_FLASH_SHOW_PROGRESS 45 - #define CONFIG_SYS_MAX_FLASH_BANKS 1 /* max number of memory banks */ -#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } +#define CONFIG_SYS_FLASH_BANKS_LIST { CONFIG_SYS_FLASH_BASE } #define CONFIG_SYS_MAX_FLASH_SECT (19)
-#if 0 -#define CONFIG_ENV_IS_IN_FLASH 1 -#define CONFIG_ENV_SIZE 0x10000 /* Total Size of Environment Sector */ -#endif +/* + * Size of malloc() pool + * BZIP2 / LZO / LZMA need a lot of RAM + */ +#define CONFIG_SYS_MALLOC_LEN (4 * 1024 * 1024) +#define CONFIG_SYS_MONITOR_LEN (512 * 1024) +#define CONFIG_SYS_MONITOR_BASE CONFIG_SYS_FLASH_BASE
+/* NAND configuration */ +#ifdef CONFIG_CMD_NAND +#define CONFIG_NAND_S3C2410 +#define CONFIG_SYS_S3C2410_NAND_HWECC +#define CONFIG_SYS_MAX_NAND_DEVICE 1 +#define NAND_MAX_CHIPS 1 +#define CONFIG_SYS_NAND_BASE 0x4E000000 +#define CONFIG_S3C24XX_CUSTOM_NAND_TIMING +#define CONFIG_S3C24XX_TACLS 1 +#define CONFIG_S3C24XX_TWRPH0 5 +#define CONFIG_S3C24XX_TWRPH1 3 +#endif
-#define CONFIG_SYS_JFFS2_FIRST_BANK 0 -#define CONFIG_SYS_JFFS2_NUM_BANKS 1 +#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000
-#define MULTI_PURPOSE_SOCKET_ADDR 0x08000000 +/* File system */ +#define CONFIG_CMD_FAT +#define CONFIG_CMD_EXT2 +#define CONFIG_CMD_UBI +#define CONFIG_CMD_UBIFS +#define CONFIG_CMD_JFFS2 +#define CONFIG_YAFFS2 +#define CONFIG_RBTREE +#define CONFIG_MTD_DEVICE /* needed for mtdparts commands */ +#define CONFIG_MTD_PARTITIONS +#define CONFIG_CMD_MTDPARTS +#define CONFIG_LZO
#define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_SP_ADDR (CONFIG_SYS_SDRAM_BASE + 0x1000 - \ GENERATED_GBL_DATA_SIZE)
+#define CONFIG_BOARD_EARLY_INIT_F
-#endif /* __CONFIG_H */ +#endif /* __CONFIG_H */
participants (4)
-
"David Müller (ELSOFT AG)" -
David Müller
-
Minkyu Kang -
Wolfgang Denk