[PATCH 00/10] rockchip: rk3588: add support for DFU in SPL
This series adds support for DFU in SPL for rockchip rk3588 on rock5b board.
Namely, when SPL is loaded via rockusb (thus via USB), having the `same-as-spl` boot order item, after having detected that it was loaded from USB, it will lookup the gadget USB node in DT and boot via DFU.
Some changes were required namely: - DFU needs environment, hence adding environment variables into DFU - added bootph-all to nodes such that they are available in SPL - insert gadget into boot order
I had to port one patch for DWC3 from Linux, and include in this series the patches that are floating from Venkatesh that fixup the DWC3 (https://marc.info/?l=u-boot&m=168351919807081&w=2 ) I know that Marek NAKed them and I am fine with it, also this patch `usb: dwc3: Increase DWC3 controller halt timeout` is in the same bucket so Marek you can NAK this one as well, no problem, I am just sending out all the series so maybe the rockchip part for the gadget can be picked up and if people want to use the DFU SPL gadget can also manually pick the DWC3 patches. The branch with all the patches is available here :
https://gitlab.collabora.com/hardware-enablement/rockchip-3588/u-boot
The series also depends on my previous usb3 series:
https://marc.info/?l=u-boot&m=168535453215908&w=2
Thanks!
I am resending because I forgot to CC the list.
Eugen Hristev (7): rockchip: allow env defines for SPL build usb: dwc3: Increase DWC3 controller halt timeout ARM: dts: rockchip: rk3588-rock-5b-u-boot: add bootph-all to gadget nodes ARM: mach-rockchip: spl-boot-order: add possibility to DFU ARM: mach-rockchip: rk3588: add gadget device to the boot order rockchip: rk3588: prepare env for DFU configs: rockchip: rock5b-rk3588: enable DFU and related configs
Venkatesh Yadav Abbarapu (3): usb: dwc3: core: improve reset sequence usb: dwc3: gadget: Don't send unintended link state change usb: dwc3: core: Only handle soft-reset in DCTL
arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 6 +++++ arch/arm/mach-rockchip/rk3588/rk3588.c | 1 + arch/arm/mach-rockchip/spl-boot-order.c | 3 +++ configs/rock5b-rk3588_defconfig | 17 ++++++++++--- drivers/usb/dwc3/core.c | 32 +++++++++++++++---------- drivers/usb/dwc3/gadget.c | 20 +++++++--------- drivers/usb/dwc3/gadget.h | 14 +++++++++++ include/configs/rk3588_common.h | 9 ++++++- include/configs/rockchip-common.h | 4 ---- 9 files changed, 75 insertions(+), 31 deletions(-)
For environment in SPL, all these defines are required, otherwise build fails:
[...] include/env_default.h:120:9: note: in expansion of macro ‘CFG_EXTRA_ENV_SETTINGS’ 120 | CFG_EXTRA_ENV_SETTINGS | ^~~~~~~~~~~~~~~~~~~~~~ In file included from env/common.c:32: [...]
Environment in SPL is needed e.g. for DFU, as dfu_alt is kept as env variable.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- include/configs/rockchip-common.h | 4 ---- 1 file changed, 4 deletions(-)
diff --git a/include/configs/rockchip-common.h b/include/configs/rockchip-common.h index 9121bba37384..be20b135066e 100644 --- a/include/configs/rockchip-common.h +++ b/include/configs/rockchip-common.h @@ -11,8 +11,6 @@ #define CFG_CPUID_OFFSET 0x7 #endif
-#ifndef CONFIG_SPL_BUILD - #define BOOT_TARGETS "mmc1 mmc0 nvme scsi usb pxe dhcp spi"
#ifdef CONFIG_ARM64 @@ -28,6 +26,4 @@ "name=boot,size=112M,bootable,uuid=${uuid_gpt_boot};" \ "name=rootfs,size=-,uuid="ROOT_UUID
-#endif - #endif /* _ROCKCHIP_COMMON_H_ */
From: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com
[ Felipe: Ported from Linux kernel commit f59dcab17629 ("usb: dwc3: core: improve reset sequence") ]
According to Synopsys Databook, we shouldn't be relying on GCTL.CORESOFTRESET bit as that's only for debugging purposes. Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode.
Host side block will be reset by XHCI driver if necessary. Note that this reduces amount of time spent on dwc3_probe() by a long margin.
We're still gonna wait for reset to finish for a long time (default to 1ms max), but tests show that the reset polling loop executed at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000 times in a row).
Without proper core reset, observing random issues like when the USB(DWC3) is in device mode, the host device is not able to detect the USB device.
Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com [eugen.hristev@collabora.com: keep the PHY resets code] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com ---
Just resending for consistency with my series. I readded the PHY resets code because it breaks my PHYs if it's being removed
Marek, I know you NAKed this, that's fine, I am simply adding this patch (and the others here) for consistency
drivers/usb/dwc3/core.c | 31 +++++++++++++++++++------------ 1 file changed, 19 insertions(+), 12 deletions(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index 5a8c29424578..bdfe51c3df96 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -60,17 +60,24 @@ static void dwc3_set_mode(struct dwc3 *dwc, u32 mode) static int dwc3_core_soft_reset(struct dwc3 *dwc) { u32 reg; + int retries = 1000;
- /* Before Resetting PHY, put Core in Reset */ - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg |= DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + /* + * We're resetting only the device side because, if we're in host mode, + * XHCI driver will reset the host block. If dwc3 was configured for + * host-only mode, then we can return early. + */ + if (dwc->dr_mode == USB_DR_MODE_HOST) + return 0; + + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + reg |= DWC3_DCTL_CSFTRST; + dwc3_writel(dwc->regs, DWC3_DCTL, reg);
/* Assert USB3 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0)); reg |= DWC3_GUSB3PIPECTL_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB3PIPECTL(0), reg); - /* Assert USB2 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB2PHYCFG(0)); reg |= DWC3_GUSB2PHYCFG_PHYSOFTRST; @@ -88,14 +95,14 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc) reg &= ~DWC3_GUSB2PHYCFG_PHYSOFTRST; dwc3_writel(dwc->regs, DWC3_GUSB2PHYCFG(0), reg);
- mdelay(100); - - /* After PHYs are stable we can take Core out of reset state */ - reg = dwc3_readl(dwc->regs, DWC3_GCTL); - reg &= ~DWC3_GCTL_CORESOFTRESET; - dwc3_writel(dwc->regs, DWC3_GCTL, reg); + do { + reg = dwc3_readl(dwc->regs, DWC3_DCTL); + if (!(reg & DWC3_DCTL_CSFTRST)) + return 0; + udelay(1); + } while (--retries);
- return 0; + return -ETIMEDOUT; }
/*
On 6/22/23 12:58, Eugen Hristev wrote:
From: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com
[ Felipe: Ported from Linux kernel commit f59dcab17629 ("usb: dwc3: core: improve reset sequence") ]
According to Synopsys Databook, we shouldn't be relying on GCTL.CORESOFTRESET bit as that's only for debugging purposes. Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode.
Host side block will be reset by XHCI driver if necessary. Note that this reduces amount of time spent on dwc3_probe() by a long margin.
We're still gonna wait for reset to finish for a long time (default to 1ms max), but tests show that the reset polling loop executed at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000 times in a row).
Without proper core reset, observing random issues like when the USB(DWC3) is in device mode, the host device is not able to detect the USB device.
Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com [eugen.hristev@collabora.com: keep the PHY resets code] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Just resending for consistency with my series. I readded the PHY resets code because it breaks my PHYs if it's being removed
Marek, I know you NAKed this, that's fine, I am simply adding this patch (and the others here) for consistency
Please sync the DWC3 patchset with Linux first, else this is a NAK.
Please do not make the DWC3 driver an unmaintainable mess.
I already explained this to AMD/Xilinx, multiple times, they
ignored all my requests without even trying, so my NAK still stands.
The sync should be easy and mechanical.
Please do not try to sneak those patches in as part of another series.
Hi Marek,
I know, I saw the discussion. I am adding the patch in case someone
wants to use it. Definitely I am not trying to sneak anything. Read the cover letter as well if you have doubts.
I tried asking intel just now to fix what AMD couldn't, so let's see.
I will try to do it myself, if I have some spare time in the following months, if nobody does it.
^^ I am resending the conversation above as I forgot to CC the mailing list on the initial thread
On 6/22/23 12:00, Eugen Hristev wrote:
On 6/22/23 12:58, Eugen Hristev wrote:
From: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com
[ Felipe: Ported from Linux kernel commit f59dcab17629 ("usb: dwc3: core: improve reset sequence") ]
According to Synopsys Databook, we shouldn't be relying on GCTL.CORESOFTRESET bit as that's only for debugging purposes. Instead, let's use DCTL.CSFTRST if we're OTG or PERIPHERAL mode.
Host side block will be reset by XHCI driver if necessary. Note that this reduces amount of time spent on dwc3_probe() by a long margin.
We're still gonna wait for reset to finish for a long time (default to 1ms max), but tests show that the reset polling loop executed at most 19 times (modprobe dwc3 && modprobe -r dwc3 executed 1000 times in a row).
Without proper core reset, observing random issues like when the USB(DWC3) is in device mode, the host device is not able to detect the USB device.
Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com [eugen.hristev@collabora.com: keep the PHY resets code] Signed-off-by: Eugen Hristev eugen.hristev@collabora.com
Just resending for consistency with my series. I readded the PHY resets code because it breaks my PHYs if it's being removed
Marek, I know you NAKed this, that's fine, I am simply adding this patch (and the others here) for consistency
Please sync the DWC3 patchset with Linux first, else this is a NAK.
Please do not make the DWC3 driver an unmaintainable mess.
I already explained this to AMD/Xilinx, multiple times, they
ignored all my requests without even trying, so my NAK still stands.
The sync should be easy and mechanical.
Please do not try to sneak those patches in as part of another series.
Hi Marek,
I know, I saw the discussion. I am adding the patch in case someone
wants to use it. Definitely I am not trying to sneak anything. Read the cover letter as well if you have doubts.
I tried asking intel just now to fix what AMD couldn't, so let's see.
I will try to do it myself, if I have some spare time in the following months, if nobody does it.
^^ I am resending the conversation above as I forgot to CC the mailing list on the initial thread
I appreciate it. It really should be easy to do.
From: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com
[ Nguyen/Felipe/Greg: Ported from Linux kernel commit 5b738211fb59 ("usb: dwc3: gadget: Don't send unintended link state change") ]
DCTL.ULSTCHNGREQ is a write-only field. When doing a read-modify-write to DCTL, the driver must make sure that there's no unintended link state change request from whatever is read from DCTL.ULSTCHNGREQ. Set link state change to no-action when the driver writes to DCTL.
Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com --- drivers/usb/dwc3/gadget.c | 16 +++++++--------- drivers/usb/dwc3/gadget.h | 14 ++++++++++++++ 2 files changed, 21 insertions(+), 9 deletions(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index eb416b832aad..24a2c455b0a4 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -62,7 +62,7 @@ int dwc3_gadget_set_test_mode(struct dwc3 *dwc, int mode) return -EINVAL; }
- dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg);
return 0; } @@ -1382,7 +1382,7 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) dwc->pullups_connected = false; }
- dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg);
do { reg = dwc3_readl(dwc->regs, DWC3_DSTS); @@ -2047,10 +2047,8 @@ static void dwc3_gadget_disconnect_interrupt(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg &= ~DWC3_DCTL_INITU1ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); - reg &= ~DWC3_DCTL_INITU2ENA; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg);
dwc3_disconnect_gadget(dwc); dwc->start_config_issued = false; @@ -2099,7 +2097,7 @@ static void dwc3_gadget_reset_interrupt(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg &= ~DWC3_DCTL_TSTCTRL_MASK; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg); dwc->test_mode = false;
dwc3_stop_active_transfers(dwc); @@ -2215,11 +2213,11 @@ static void dwc3_gadget_conndone_interrupt(struct dwc3 *dwc) if (dwc->has_lpm_erratum && dwc->revision >= DWC3_REVISION_240A) reg |= DWC3_DCTL_LPM_ERRATA(dwc->lpm_nyet_threshold);
- dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg); } else { reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg &= ~DWC3_DCTL_HIRD_THRES_MASK; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg); }
dep = dwc->eps[0]; @@ -2327,7 +2325,7 @@ static void dwc3_gadget_linksts_change_interrupt(struct dwc3 *dwc,
reg &= ~u1u2;
- dwc3_writel(dwc->regs, DWC3_DCTL, reg); + dwc3_gadget_dctl_write_safe(dwc, reg); break; default: /* do nothing */ diff --git a/drivers/usb/dwc3/gadget.h b/drivers/usb/dwc3/gadget.h index 7806ce59a27f..b48ec6b2372f 100644 --- a/drivers/usb/dwc3/gadget.h +++ b/drivers/usb/dwc3/gadget.h @@ -104,4 +104,18 @@ static inline u32 dwc3_gadget_ep_get_transfer_index(struct dwc3 *dwc, u8 number) return DWC3_DEPCMD_GET_RSC_IDX(res_id); }
+/** + * dwc3_gadget_dctl_write_safe - write to DCTL safe from link state change + * @dwc: pointer to our context structure + * @value: value to write to DCTL + * + * Use this function when doing read-modify-write to DCTL. It will not + * send link state change request. + */ +static inline void dwc3_gadget_dctl_write_safe(struct dwc3 *dwc, u32 value) +{ + value &= ~DWC3_DCTL_ULSTCHNGREQ_MASK; + dwc3_writel(dwc->regs, DWC3_DCTL, value); +} + #endif /* __DRIVERS_USB_DWC3_GADGET_H */
From: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com
[ Nguyen/Greg: Ported from Linux kernel commit f4fd84ae0765a ("usb: dwc3: core: Only handle soft-reset in DCTL") ]
Make sure not to set run_stop bit or link state change request while initiating soft-reset. Register read-modify-write operation may unintentionally start the controller before the initialization completes with its previous DCTL value, which can cause initialization failure.
Signed-off-by: Venkatesh Yadav Abbarapu venkatesh.abbarapu@amd.com --- drivers/usb/dwc3/core.c | 3 ++- 1 file changed, 2 insertions(+), 1 deletion(-)
diff --git a/drivers/usb/dwc3/core.c b/drivers/usb/dwc3/core.c index bdfe51c3df96..06ca3fc96842 100644 --- a/drivers/usb/dwc3/core.c +++ b/drivers/usb/dwc3/core.c @@ -72,7 +72,8 @@ static int dwc3_core_soft_reset(struct dwc3 *dwc)
reg = dwc3_readl(dwc->regs, DWC3_DCTL); reg |= DWC3_DCTL_CSFTRST; - dwc3_writel(dwc->regs, DWC3_DCTL, reg); + reg &= ~DWC3_DCTL_RUN_STOP; + dwc3_gadget_dctl_write_safe(dwc, reg);
/* Assert USB3 PHY reset */ reg = dwc3_readl(dwc->regs, DWC3_GUSB3PIPECTL(0));
Since EP0 transactions need to be completed before the controller halt sequence is finished, this may take some time depending on the host and the enabled functions. Increase the controller halt timeout, so that we give the controller sufficient time to handle EP0 transfers.
Signed-off-by: Wesley Cheng quic_wcheng@quicinc.com Link: https://lore.kernel.org/r/20220901193625.8727-4-quic_wcheng@quicinc.com Cherry-picked from Linux: 461ee467507c ("usb: dwc3: Increase DWC3 controller halt timeout") Signed-off-by: Eugen Hristev eugen.hristev@collabora.com ---
Sent for consistency, I know Marek does not accept any patches to DWC3
drivers/usb/dwc3/gadget.c | 4 ++-- 1 file changed, 2 insertions(+), 2 deletions(-)
diff --git a/drivers/usb/dwc3/gadget.c b/drivers/usb/dwc3/gadget.c index 24a2c455b0a4..a86680719108 100644 --- a/drivers/usb/dwc3/gadget.c +++ b/drivers/usb/dwc3/gadget.c @@ -1356,7 +1356,7 @@ static int dwc3_gadget_set_selfpowered(struct usb_gadget *g, static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) { u32 reg; - u32 timeout = 500; + u32 timeout = 2000;
reg = dwc3_readl(dwc->regs, DWC3_DCTL); if (is_on) { @@ -1385,6 +1385,7 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) dwc3_gadget_dctl_write_safe(dwc, reg);
do { + mdelay(2); reg = dwc3_readl(dwc->regs, DWC3_DSTS); if (is_on) { if (!(reg & DWC3_DSTS_DEVCTRLHLT)) @@ -1396,7 +1397,6 @@ static int dwc3_gadget_run_stop(struct dwc3 *dwc, int is_on, int suspend) timeout--; if (!timeout) return -ETIMEDOUT; - udelay(1); } while (1);
dev_vdbg(dwc->dev, "gadget %s data soft-%s\n",
Add bootph-all to gadget nodes to have the gadget available in SPL.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- arch/arm/dts/rk3588-rock-5b-u-boot.dtsi | 6 ++++++ 1 file changed, 6 insertions(+)
diff --git a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi index 5a3292699640..f453aeeaf526 100644 --- a/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi +++ b/arch/arm/dts/rk3588-rock-5b-u-boot.dtsi @@ -221,10 +221,12 @@ };
&u2phy0 { + bootph-all; status = "okay"; };
&u2phy0_otg { + bootph-all; rockchip,typec-vbus-det; status = "okay"; }; @@ -271,6 +273,7 @@ };
&usbdp_phy0 { + bootph-all; orientation-switch; svid = <0xff01>; sbu1-dc-gpios = <&gpio4 RK_PA6 GPIO_ACTIVE_HIGH>; @@ -293,14 +296,17 @@ };
&usbdp_phy0_u3 { + bootph-all; status = "okay"; };
&usbdrd3_0 { + bootph-all; status = "okay"; };
&usbdrd_dwc3_0 { + bootph-all; dr_mode = "otg"; usb-role-switch;
Add DFU as a possible SPL boot media if the boot device is a gadget device.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- arch/arm/mach-rockchip/spl-boot-order.c | 3 +++ 1 file changed, 3 insertions(+)
diff --git a/arch/arm/mach-rockchip/spl-boot-order.c b/arch/arm/mach-rockchip/spl-boot-order.c index 93b8e7de4d0d..89bbe449e86c 100644 --- a/arch/arm/mach-rockchip/spl-boot-order.c +++ b/arch/arm/mach-rockchip/spl-boot-order.c @@ -66,6 +66,9 @@ static int spl_node_to_boot_device(int node) } else if (!uclass_get_device_by_of_offset(UCLASS_SPI_FLASH, node, &parent)) { return BOOT_DEVICE_SPI; + } else if (!uclass_get_device_by_of_offset(UCLASS_USB_GADGET_GENERIC, + node, &parent)) { + return BOOT_DEVICE_DFU; }
/*
In case SPL was booted from USB, add the gadget as the boot device for the 'same-as-spl' boot order next device.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- arch/arm/mach-rockchip/rk3588/rk3588.c | 1 + 1 file changed, 1 insertion(+)
diff --git a/arch/arm/mach-rockchip/rk3588/rk3588.c b/arch/arm/mach-rockchip/rk3588/rk3588.c index b1f535fad505..c95268e18801 100644 --- a/arch/arm/mach-rockchip/rk3588/rk3588.c +++ b/arch/arm/mach-rockchip/rk3588/rk3588.c @@ -42,6 +42,7 @@ const char * const boot_devices[BROM_LAST_BOOTSOURCE + 1] = { [BROM_BOOTSOURCE_SPINOR] = "/spi@fe2b0000/flash@0", [BROM_BOOTSOURCE_SD] = "/mmc@fe2c0000", [BROM_BOOTSOURCE_SPINOR_RK3588] = "/spi@fe2b0000/flash@0", + [BROM_BOOTSOURCE_USB] = "/usbdrd3_0/usb@fc000000", };
static struct mm_region rk3588_mem_map[] = {
Prepare env variables for DFU
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- include/configs/rk3588_common.h | 9 ++++++++- 1 file changed, 8 insertions(+), 1 deletion(-)
diff --git a/include/configs/rk3588_common.h b/include/configs/rk3588_common.h index 46389d087d29..48414fe946a0 100644 --- a/include/configs/rk3588_common.h +++ b/include/configs/rk3588_common.h @@ -7,6 +7,7 @@ #ifndef __CONFIG_RK3588_COMMON_H #define __CONFIG_RK3588_COMMON_H
+#include <linux/stringify.h> #include "rockchip-common.h"
#define CFG_IRAM_BASE 0xff000000 @@ -31,6 +32,12 @@ "partitions=" PARTS_DEFAULT \ ENV_MEM_LAYOUT_SETTINGS \ ROCKCHIP_DEVICE_SETTINGS \ - "boot_targets=" BOOT_TARGETS "\0" + "boot_targets=" BOOT_TARGETS "\0" \ + "dfu_alt_info=ram ram0=ram ram " \ + __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) " " \ + __stringify(CONFIG_SYS_DFU_DATA_BUF_SIZE) "\0" \ + "dfu_alt_info_ram=u-boot.itb ram " \ + __stringify(CONFIG_SPL_LOAD_FIT_ADDRESS) " " \ + __stringify(CONFIG_SYS_DFU_DATA_BUF_SIZE)
#endif /* __CONFIG_RK3588_COMMON_H */
Enable DFU and related configs, expand stack and buffers to hold downloaded image.
Signed-off-by: Eugen Hristev eugen.hristev@collabora.com --- configs/rock5b-rk3588_defconfig | 17 ++++++++++++++--- 1 file changed, 14 insertions(+), 3 deletions(-)
diff --git a/configs/rock5b-rk3588_defconfig b/configs/rock5b-rk3588_defconfig index 3f28a68f0c94..2ad61b4873cc 100644 --- a/configs/rock5b-rk3588_defconfig +++ b/configs/rock5b-rk3588_defconfig @@ -4,6 +4,7 @@ CONFIG_SYS_HAS_NONCACHED_MEMORY=y CONFIG_COUNTER_FREQUENCY=24000000 CONFIG_ARCH_ROCKCHIP=y CONFIG_TEXT_BASE=0x00a00000 +CONFIG_SYS_MALLOC_F_LEN=0x500000 CONFIG_SPL_LIBCOMMON_SUPPORT=y CONFIG_SPL_LIBGENERIC_SUPPORT=y CONFIG_NR_DRAM_BANKS=2 @@ -16,9 +17,9 @@ CONFIG_ROCKCHIP_RK3588=y CONFIG_SPL_ROCKCHIP_COMMON_BOARD=y CONFIG_ROCKCHIP_SPI_IMAGE=y CONFIG_SPL_SERIAL=y -CONFIG_SPL_STACK_R_ADDR=0x600000 +CONFIG_SPL_STACK_R_ADDR=0x1000000 CONFIG_TARGET_ROCK5B_RK3588=y -CONFIG_SPL_STACK=0x400000 +CONFIG_SPL_STACK=0x1000000 CONFIG_DEBUG_UART_BASE=0xFEB50000 CONFIG_DEBUG_UART_CLOCK=24000000 CONFIG_SPL_SPI_FLASH_SUPPORT=y @@ -30,6 +31,7 @@ CONFIG_FIT=y CONFIG_FIT_VERBOSE=y CONFIG_SPL_FIT_SIGNATURE=y CONFIG_SPL_LOAD_FIT=y +CONFIG_SPL_LOAD_FIT_ADDRESS=0x50000000 CONFIG_OF_BOARD_SETUP=y CONFIG_DEFAULT_FDT_FILE="rockchip/rk3588-rock-5b.dtb" # CONFIG_DISPLAY_CPUINFO is not set @@ -42,9 +44,15 @@ CONFIG_SPL_BSS_MAX_SIZE=0x4000 # CONFIG_SPL_RAW_IMAGE_SUPPORT is not set # CONFIG_SPL_SHARES_INIT_SP_ADDR is not set CONFIG_SPL_STACK_R=y +CONFIG_SPL_STACK_R_MALLOC_SIMPLE_LEN=0x300000 +CONFIG_SPL_ENV_SUPPORT=y +CONFIG_SPL_RAM_SUPPORT=y CONFIG_SPL_SPI_LOAD=y CONFIG_SYS_SPI_U_BOOT_OFFS=0x60000 +CONFIG_SPL_USB_GADGET=y +CONFIG_SPL_DFU=y CONFIG_SPL_ATF=y +CONFIG_CMD_DFU=y CONFIG_CMD_GPIO=y CONFIG_CMD_GPT=y CONFIG_CMD_I2C=y @@ -57,10 +65,12 @@ CONFIG_CMD_REGULATOR=y # CONFIG_SPL_DOS_PARTITION is not set CONFIG_SPL_OF_CONTROL=y CONFIG_OF_LIVE=y -CONFIG_OF_SPL_REMOVE_PROPS="clock-names interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" +CONFIG_OF_SPL_REMOVE_PROPS="interrupt-parent assigned-clocks assigned-clock-rates assigned-clock-parents" CONFIG_SPL_REGMAP=y CONFIG_SPL_SYSCON=y CONFIG_SPL_CLK=y +CONFIG_DFU_RAM=y +CONFIG_SYS_DFU_DATA_BUF_SIZE=0x200000 # CONFIG_USB_FUNCTION_FASTBOOT is not set CONFIG_ROCKCHIP_GPIO=y CONFIG_SYS_I2C_ROCKCHIP=y @@ -91,6 +101,7 @@ CONFIG_ROCKCHIP_SFC=y CONFIG_SYSRESET=y CONFIG_USB=y CONFIG_DM_USB_GADGET=y +CONFIG_SPL_DM_USB_GADGET=y CONFIG_USB_XHCI_HCD=y # CONFIG_USB_XHCI_DWC3_OF_SIMPLE is not set CONFIG_USB_EHCI_HCD=y
participants (2)
-
Eugen Hristev -
Marek Vasut