Still trying to wrap my head around PCI and I wonder if I need to do some HW init in u-boot in order to use the PCI controller in Linux? Obviously I need to pass PCI settings in the OF tree, but other than that?
Jocke
Scott Wood scottwood@freescale.com wrote on 23/04/2009 18:40:01:
On Thu, Apr 23, 2009 at 03:32:11PM +0200, Joakim Tjernlund wrote:
Still trying to wrap my head around PCI and I wonder if I need to do
some
HW init in u-boot in order to use the PCI controller in Linux?
Yes. See pci_init_board() in mpc8323erdb for an example.
Thanks Scott, this was very helpful.
I am trying to map the "ranges" property in the OF tree and I am looking at the dts files in the kernel tree. There are three that comes somewhat close but they all have somewhat different "ranges" propery:
mpc832x_mds.dts: ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
mpc832x_rdb.dts: ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
mpc8313erdb.dts: ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
Don't understand how I should do here. Just select the mpc832x_rdb.dts "ranges" and define my base addresses similarly? #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_MMIO_BASE 0x90000000 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0xd0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x4000000 /* 64M */
Jocke
On Apr 24, 2009, at 9:11 AM, Joakim Tjernlund wrote:
Scott Wood scottwood@freescale.com wrote on 23/04/2009 18:40:01:
On Thu, Apr 23, 2009 at 03:32:11PM +0200, Joakim Tjernlund wrote:
Still trying to wrap my head around PCI and I wonder if I need to do
some
HW init in u-boot in order to use the PCI controller in Linux?
Yes. See pci_init_board() in mpc8323erdb for an example.
Thanks Scott, this was very helpful.
I am trying to map the "ranges" property in the OF tree and I am looking at the dts files in the kernel tree. There are three that comes somewhat close but they all have somewhat different "ranges" propery:
mpc832x_mds.dts: ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
this is PCI MMIO non-prefetch @ 0x90000000 (cpu & pci) of size 256M
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000
this is PCI MMIO prefetch @ 0x80000000 (cpu & pci) of size 256M
0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;
this is PCI IO @ @ cpu phy 0xd0000000 pci io 0x0 of size 1M
mpc832x_rdb.dts: ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
mpc8313erdb.dts: ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
Don't understand how I should do here. Just select the mpc832x_rdb.dts "ranges" and define my base addresses similarly? #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_MMIO_BASE 0x90000000 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0xd0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x4000000 /* 64M */
this is overkill for IO, 64k is the max. (its probably inherited when we didn't know better).
- k
Kumar Gala galak@kernel.crashing.org wrote on 27/04/2009 16:12:35:
From:
Kumar Gala galak@kernel.crashing.org
To:
Joakim Tjernlund joakim.tjernlund@transmode.se
Cc:
Scott Wood scottwood@freescale.com, u-boot@lists.denx.de
Date:
27/04/2009 16:15
Subject:
Re: [U-Boot] PCI on mpc832x?
On Apr 24, 2009, at 9:11 AM, Joakim Tjernlund wrote:
Scott Wood scottwood@freescale.com wrote on 23/04/2009 18:40:01:
On Thu, Apr 23, 2009 at 03:32:11PM +0200, Joakim Tjernlund wrote:
Still trying to wrap my head around PCI and I wonder if I need to do
some
HW init in u-boot in order to use the PCI controller in Linux?
Yes. See pci_init_board() in mpc8323erdb for an example.
Thanks Scott, this was very helpful.
I am trying to map the "ranges" property in the OF tree and I am looking at the dts files in the kernel tree. There are three that comes somewhat close but they all have somewhat different "ranges" propery:
mpc832x_mds.dts: ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000
this is PCI MMIO non-prefetch @ 0x90000000 (cpu & pci) of size 256M
0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000this is PCI MMIO prefetch @ 0x80000000 (cpu & pci) of size 256M
0x01000000 0x0 0x00000000 0xd0000000 0x0 0x00100000>;this is PCI IO @ @ cpu phy 0xd0000000 pci io 0x0 of size 1M
mpc832x_rdb.dts: ranges = <0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x01000000 0x0 0xd0000000 0xd0000000 0x0 0x04000000>;
mpc8313erdb.dts: ranges = <0x02000000 0x0 0x90000000 0x90000000 0x0 0x10000000 0x42000000 0x0 0x80000000 0x80000000 0x0 0x10000000 0x01000000 0x0 0x00000000 0xe2000000 0x0 0x00100000>;
Don't understand how I should do here. Just select the mpc832x_rdb.dts "ranges" and define my base addresses similarly? #define CFG_PCI1_MEM_BASE 0x80000000 #define CFG_PCI1_MEM_PHYS CFG_PCI1_MEM_BASE #define CFG_PCI1_MEM_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_MMIO_BASE 0x90000000 #define CFG_PCI1_MMIO_PHYS CFG_PCI1_MMIO_BASE #define CFG_PCI1_MMIO_SIZE 0x10000000 /* 256M */ #define CFG_PCI1_IO_BASE 0xd0000000 #define CFG_PCI1_IO_PHYS CFG_PCI1_IO_BASE #define CFG_PCI1_IO_SIZE 0x4000000 /* 64M */
this is overkill for IO, 64k is the max. (its probably inherited when we didn't know better).
I think I got the mapping of memory space now, thanks.
A few questions though. I have noted that some boards map the PCI IO space to 0x0 and some use the same address space as the CPU. If I use the CPU address space as PCI IO space I get(in linux): PCI 0000:00 Cannot reserve Legacy IO [0x00-0xfff] I don't understand what is best to do here, stay on 0x0 or move to CPU address space?
with CONFIG_PCI_QUIRKS=y Linux prints: PCI: Bus scan for 0000:00 returning with max=00 pci_bus 0000:00: resource 0 io: [0x00-0xfffff] pci_bus 0000:00: resource 1 mem: [0x80000000-0x8fffffff] pci_bus 0000:00: resource 2 mem: [0x90000000-0x9fffffff]
But if I turn off CONFIG_PCI_QUIRKS I get: PCI: Bus scan for 0000:00 returning with max=00 PCI: Cannot allocate resource region 0 of device 0000:00:00.0, will remap PCI: Cannot allocate resource region 2 of device 0000:00:00.0, will remap pci 0000:00:00.0: BAR 2: got res [0x80000000-0x87ffffff] bus [0x80000000-0x87ffffff] flags 0x2002120c pci 0000:00:00.0: BAR 2: moved to bus [0x80000000-0x87ffffff] flags 0x2120c pci 0000:00:00.0: BAR 0: got res [0x90000000-0x901fffff] bus [0x90000000-0x901fffff] flags 0x20020200 pci 0000:00:00.0: BAR 0: moved to bus [0x90000000-0x901fffff] flags 0x20200 pci_bus 0000:00: resource 0 io: [0x00-0xfffff] pci_bus 0000:00: resource 1 mem: [0x80000000-0x8fffffff] pci_bus 0000:00: resource 2 mem: [0x90000000-0x9fffffff]
The BAR ... printout feels a bit off. Why do I need quirks on for a clean boot?
Jocke
I think I got the mapping of memory space now, thanks.
A few questions though. I have noted that some boards map the PCI IO space to 0x0 and some use the same address space as the CPU. If I use the CPU address space as PCI IO space I get(in linux): PCI 0000:00 Cannot reserve Legacy IO [0x00-0xfff] I don't understand what is best to do here, stay on 0x0 or move to CPU address space?
PCI IO should normally be at 0 in the "PCI address space" and can be at any CPU physical address.
with CONFIG_PCI_QUIRKS=y Linux prints: PCI: Bus scan for 0000:00 returning with max=00 pci_bus 0000:00: resource 0 io: [0x00-0xfffff] pci_bus 0000:00: resource 1 mem: [0x80000000-0x8fffffff] pci_bus 0000:00: resource 2 mem: [0x90000000-0x9fffffff]
But if I turn off CONFIG_PCI_QUIRKS I get: PCI: Bus scan for 0000:00 returning with max=00 PCI: Cannot allocate resource region 0 of device 0000:00:00.0, will remap PCI: Cannot allocate resource region 2 of device 0000:00:00.0, will remap pci 0000:00:00.0: BAR 2: got res [0x80000000-0x87ffffff] bus [0x80000000-0x87ffffff] flags 0x2002120c pci 0000:00:00.0: BAR 2: moved to bus [0x80000000-0x87ffffff] flags 0x2120c pci 0000:00:00.0: BAR 0: got res [0x90000000-0x901fffff] bus [0x90000000-0x901fffff] flags 0x20020200 pci 0000:00:00.0: BAR 0: moved to bus [0x90000000-0x901fffff] flags 0x20200 pci_bus 0000:00: resource 0 io: [0x00-0xfffff] pci_bus 0000:00: resource 1 mem: [0x80000000-0x8fffffff] pci_bus 0000:00: resource 2 mem: [0x90000000-0x9fffffff]
The BAR ... printout feels a bit off. Why do I need quirks on for a clean boot?
Quirks are required for FSL based PCI controllers. I know I've got a change in current kernels to do:
config FSL_PCI bool select PPC_INDIRECT_PCI select PCI_QUIRKS
- k
Kumar Gala galak@kernel.crashing.org wrote on 29/04/2009 14:35:19:
I think I got the mapping of memory space now, thanks.
A few questions though. I have noted that some boards map the PCI IO space to 0x0 and some use the same address space as the CPU. If I use the CPU address space as PCI IO space I get(in linux): PCI 0000:00 Cannot reserve Legacy IO [0x00-0xfff] I don't understand what is best to do here, stay on 0x0 or move to CPU address space?
PCI IO should normally be at 0 in the "PCI address space" and can be at any CPU physical address.
with CONFIG_PCI_QUIRKS=y Linux prints: PCI: Bus scan for 0000:00 returning with max=00 pci_bus 0000:00: resource 0 io: [0x00-0xfffff] pci_bus 0000:00: resource 1 mem: [0x80000000-0x8fffffff] pci_bus 0000:00: resource 2 mem: [0x90000000-0x9fffffff]
But if I turn off CONFIG_PCI_QUIRKS I get: PCI: Bus scan for 0000:00 returning with max=00 PCI: Cannot allocate resource region 0 of device 0000:00:00.0, will remap PCI: Cannot allocate resource region 2 of device 0000:00:00.0, will remap pci 0000:00:00.0: BAR 2: got res [0x80000000-0x87ffffff] bus [0x80000000-0x87ffffff] flags 0x2002120c pci 0000:00:00.0: BAR 2: moved to bus [0x80000000-0x87ffffff] flags 0x2120c pci 0000:00:00.0: BAR 0: got res [0x90000000-0x901fffff] bus [0x90000000-0x901fffff] flags 0x20020200 pci 0000:00:00.0: BAR 0: moved to bus [0x90000000-0x901fffff] flags 0x20200 pci_bus 0000:00: resource 0 io: [0x00-0xfffff] pci_bus 0000:00: resource 1 mem: [0x80000000-0x8fffffff] pci_bus 0000:00: resource 2 mem: [0x90000000-0x9fffffff]
The BAR ... printout feels a bit off. Why do I need quirks on for a clean boot?
Quirks are required for FSL based PCI controllers. I know I've got a change in current kernels to do:
I see. It is a pity though as: size drivers/pci/quirks.o text data bss dec hex filename 14130 8 20 14158 374e drivers/pci/quirks.o adds almost 14KB code just for being able to use the FSL PCI controller.
Jocke
participants (4)
-
Joakim Tjernlund -
Joakim Tjernlund
-
Kumar Gala -
Scott Wood