[U-Boot] [PATCH] samsung: fix DMC1_MEM_CFG for s3c64xx
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to contorl CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is obsearved that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com --- include/s3c6400.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/s3c6400.h b/include/s3c6400.h index e527c08..7229ea6 100644 --- a/include/s3c6400.h +++ b/include/s3c6400.h @@ -817,7 +817,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* Chip1, Burst4, Row/Column bit */ #define DMC1_MEM_CFG2 0xB45 #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
Dear Seunghyeon Rhee,
2009/11/28 "Seunghyeon Rhee (이승현)" seunghyeon@lpmtec.com:
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to contorl CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is obsearved that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com
include/s3c6400.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/s3c6400.h b/include/s3c6400.h index e527c08..7229ea6 100644 --- a/include/s3c6400.h +++ b/include/s3c6400.h @@ -817,7 +817,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* Chip1, Burst4, Row/Column bit */ #define DMC1_MEM_CFG2 0xB45 #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ -- 1.6.2.5
-- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657
Please rebase this patch. s3c6400.h is moved to include/asm-arm/arch-s3c64xx/s3c6400.h
Thanks Minkyu Kang
Minkyu Kang 쓴 글:
Dear Seunghyeon Rhee,
2009/11/28 "Seunghyeon Rhee (이승현)" seunghyeon@lpmtec.com:
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to contorl CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is obsearved that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com
include/s3c6400.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/s3c6400.h b/include/s3c6400.h index e527c08..7229ea6 100644 --- a/include/s3c6400.h +++ b/include/s3c6400.h @@ -817,7 +817,7 @@ /*-----------------------------------------------------------------------
- Physical Memory Map
*/ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* Chip1, Burst4, Row/Column bit */ #define DMC1_MEM_CFG2 0xB45 #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
1.6.2.5
-- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657
Please rebase this patch. s3c6400.h is moved to include/asm-arm/arch-s3c64xx/s3c6400.h
Thanks Minkyu Kang
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com --- include/asm-arm/arch-s3c64xx/s3c6400.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h index e527c08..10b3324 100644 --- a/include/asm-arm/arch-s3c64xx/s3c6400.h +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -817,9 +817,9 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ #define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
Minkyu Kang worte:
Dear Seunghyeon Rhee,
2009/11/28 "Seunghyeon Rhee" seunghyeon@lpmtec.com:
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to contorl CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is obsearved that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com
include/s3c6400.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/s3c6400.h b/include/s3c6400.h index e527c08..7229ea6 100644 --- a/include/s3c6400.h +++ b/include/s3c6400.h @@ -817,7 +817,7 @@ /*-----------------------------------------------------------------------
- Physical Memory Map
*/ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* Chip1, Burst4, Row/Column bit */ #define DMC1_MEM_CFG2 0xB45 #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */
#define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
1.6.2.5
-- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657
Please rebase this patch. s3c6400.h is moved to include/asm-arm/arch-s3c64xx/s3c6400.h
Thanks Minkyu Kang
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com --- include/asm-arm/arch-s3c64xx/s3c6400.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h index e527c08..10b3324 100644 --- a/include/asm-arm/arch-s3c64xx/s3c6400.h +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -817,9 +817,9 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ #define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
Dear Seunghyyeon Rhee,
2009/12/3 Seunghyeon Rhee seunghyeon@lpmtec.com:
Minkyu Kang worte:
Dear Seunghyeon Rhee,
2009/11/28 "Seunghyeon Rhee" seunghyeon@lpmtec.com:
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to contorl CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is obsearved that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com
include/s3c6400.h | 2 +- 1 files changed, 1 insertions(+), 1 deletions(-)
diff --git a/include/s3c6400.h b/include/s3c6400.h index e527c08..7229ea6 100644 --- a/include/s3c6400.h +++ b/include/s3c6400.h @@ -817,7 +817,7 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* Chip1, Burst4, Row/Column bit */ #define DMC1_MEM_CFG2 0xB45 #define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */ -- 1.6.2.5
-- Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657
Please rebase this patch. s3c6400.h is moved to include/asm-arm/arch-s3c64xx/s3c6400.h
Thanks Minkyu Kang
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com
include/asm-arm/arch-s3c64xx/s3c6400.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/include/asm-arm/arch-s3c64xx/s3c6400.h b/include/asm-arm/arch-s3c64xx/s3c6400.h index e527c08..10b3324 100644 --- a/include/asm-arm/arch-s3c64xx/s3c6400.h +++ b/include/asm-arm/arch-s3c64xx/s3c6400.h @@ -817,9 +817,9 @@ /*----------------------------------------------------------------------- * Physical Memory Map */ -#define DMC1_MEM_CFG 0x80010012 /* Chip1, Burst4, Row/Column bit */ +#define DMC1_MEM_CFG 0x00010012 /* burst 4, 13-bit row, 10-bit col */ #define DMC1_MEM_CFG2 0xB45 -#define DMC1_CHIP0_CFG 0x150F8 /* 0x4000_0000 ~ 0x43ff_ffff (64MB) */ +#define DMC1_CHIP0_CFG 0x150F8 /* 0x5000_0000~0x57ff_ffff (128 MiB) */ #define DMC_DDR_32_CFG 0x0 /* 32bit, DDR */
/* Memory Parameters */
1.6.2.5
Seunghyeon Rhee, Ph.D. / Director LPM Technology Inc. T +82-70-8255-6007 F +82-2-6442-6462 M +82-10-2790-0657
applied to u-boot-samsung
Thanks Minkyu Kang
Dear Minkyu Kang,
In message 1f3430fb0912031616t6910a3d9yce8621afe0631e18@mail.gmail.com you wrote:
...
applied to u-boot-samsung
Thanks for clean9ing up the original poster's mess of a commit message. But please feel free to reject such horribly formatted submissions.
Best regards,
Wolfgang Denk
Dear Wolfgang,
2009/12/5 Wolfgang Denk wd@denx.de:
Dear Minkyu Kang,
In message 1f3430fb0912031616t6910a3d9yce8621afe0631e18@mail.gmail.com you wrote:
...
applied to u-boot-samsung
Thanks for clean9ing up the original poster's mess of a commit message. But please feel free to reject such horribly formatted submissions.
Ok. I will. Thanks in advice.
Best regards,
Wolfgang Denk
-- DENX Software Engineering GmbH, MD: Wolfgang Denk & Detlev Zundel HRB 165235 Munich, Office: Kirchenstr.5, D-82194 Groebenzell, Germany Phone: (+49)-8142-66989-10 Fax: (+49)-8142-66989-80 Email: wd@denx.de Der Irrtum wiederholt sich immerfort in der Tat. Deshalb muß man das Wahre unermüdlich in Worten wiederholen. - Goethe
Minkyu Kang
Dear Seunghyeon Rhee,
In message 4B17094D.2090300@lpmtec.com you wrote:
Dear Seunghyeon Rhee,
2009/11/28 "Seunghyeon Rhee" seunghyeon@lpmtec.com:
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit
...
Please rebase this patch. s3c6400.h is moved to include/asm-arm/arch-s3c64xx/s3c6400.h
Thanks Minkyu Kang
The MSB of DMC1_MEM_CFG can be set to '1' for separate CKE control for S3C6400. In the configuration of SMDK6400, however, two 16-bit mDDR (SAMSUNG K4X51163) chips are used in parallel to form 32-bit memory bus and there is no need to control CKE for each chip separately. AFAIK, CKE1 is not at all connected. Only CKE0 is used. Futhermore, it should be '0' always for S3C6410. When tested with a board which has a S3C6410 and the same memory configuration, a side effect is observed that u-boot command "reset" doesn't work leading to system hang. Leaving the bit clear is safe in most cases.
Signed-off-by: Seunghyeon Rhee seunghyeon@lpmtec.com
include/asm-arm/arch-s3c64xx/s3c6400.h | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
Is this a patch re-submission or what? If yes, then please:
1) add a version to the subject (like "[PATCH v2]" 2) add a description of what has been changed below (!) the "---" line 3) and make sure thsat the commit message can be used - the one above is definitely unusable.
Best regards,
Wolfgang Denk
participants (4)
-
"Seunghyeon Rhee (이승현)" -
Minkyu Kang -
Seunghyeon Rhee
-
Wolfgang Denk