Signed-off-by: Andreas Müller schnitzeltony@gmx.de --- board/overo/overo.c | 14 +++++++------- 1 files changed, 7 insertions(+), 7 deletions(-)

diff --git a/board/overo/overo.c b/board/overo/overo.c index 3c60b06..4a20c7f 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -119,7 +119,7 @@ int get_board_revision(void) gpio_get_value(113) << 1 | gpio_get_value(112); } else { - printf("Error: unable to acquire board revision GPIOs\n"); + puts("Error: unable to acquire board revision GPIOs\n"); revision = -1; }

@@ -151,7 +151,7 @@ int get_sdio2_config(void)

gpio_direction_input(130); } else { - printf("Error: unable to acquire sdio2 clk GPIOs\n"); + puts("Error: unable to acquire sdio2 clk GPIOs\n"); sdio_direct = -1; }

@@ -200,15 +200,15 @@ int misc_init_r(void)

switch (get_sdio2_config()) { case 0: - printf("Tranceiver detected on mmc2\n"); + puts("Tranceiver detected on mmc2\n"); MUX_OVERO_SDIO2_TRANSCEIVER(); break; case 1: - printf("Direct connection on mmc2\n"); + puts("Direct connection on mmc2\n"); MUX_OVERO_SDIO2_DIRECT(); break; default: - printf("Unable to detect mmc2 connection type\n"); + puts("Unable to detect mmc2 connection type\n"); }

switch (get_expansion_id()) { @@ -269,10 +269,10 @@ int misc_init_r(void) setenv("defaultdisplay", "dvi"); break; case GUMSTIX_NO_EEPROM: - printf("No EEPROM on expansion board\n"); + puts("No EEPROM on expansion board\n"); break; default: - printf("Unrecognized expansion board\n"); + puts("Unrecognized expansion board\n"); }

if (expansion_config.content == 1)

At old overo boards TWL4030 RTC irq is connected to gpio112. Unfortunately this pin is also used for revision detection. Therefore we need to send shut-up to TWL4030 to avoid reading wrong revision. In SPL this must be done before SDRAM is set up because the type of SDRAM is revision dependent. By this patch it is ensured that all variables used by omap24xx_i2c.c are located in SRAM.

Signed-off-by: Andreas Müller schnitzeltony@gmx.de --- drivers/i2c/omap24xx_i2c.c | 13 +++++++++---- 1 files changed, 9 insertions(+), 4 deletions(-)

diff --git a/drivers/i2c/omap24xx_i2c.c b/drivers/i2c/omap24xx_i2c.c index 271ed60..44290b4 100644 --- a/drivers/i2c/omap24xx_i2c.c +++ b/drivers/i2c/omap24xx_i2c.c @@ -35,10 +35,15 @@ static void wait_for_bb(void); static u16 wait_for_pin(void); static void flush_fifo(void);

-static struct i2c *i2c_base = (struct i2c *)I2C_DEFAULT_BASE; - -static unsigned int bus_initialized[I2C_BUS_MAX]; -static unsigned int current_bus; +/* + * For SPL boot some boards need i2c before SDRAM is initialised so force + * variables to live in SRAM + */ +static struct i2c __attribute__ ((section (".data"))) *i2c_base = + (struct i2c *)I2C_DEFAULT_BASE; +static unsigned int __attribute__ ((section (".data"))) bus_initialized[I2C_BUS_MAX] = + { [0 ... (I2C_BUS_MAX-1)] = 0 }; +static unsigned int __attribute__ ((section (".data"))) current_bus = 0;

void i2c_init(int speed, int slaveadd) {

* implementation based on ti beagleboard/omap3evm * timing data and i2c workaround for revision 0 boards taken from x-loader * run-tested with overo revision 0 and 1 / boot from NAND and SDcard

Signed-off-by: Andreas Müller schnitzeltony@gmx.de --- arch/arm/cpu/armv7/omap-common/spl.c | 4 ++ arch/arm/include/asm/arch-omap3/mem.h | 26 +++++++++++++++ board/overo/config.mk | 28 ----------------- board/overo/overo.c | 55 ++++++++++++++++++++++++++++++++- board/overo/overo.h | 5 +++ include/configs/omap3_overo.h | 53 +++++++++++++++++++++++++++++++ 6 files changed, 142 insertions(+), 29 deletions(-) delete mode 100644 board/overo/config.mk

diff --git a/arch/arm/cpu/armv7/omap-common/spl.c b/arch/arm/cpu/armv7/omap-common/spl.c index 74fea4f..1220eb5 100644 --- a/arch/arm/cpu/armv7/omap-common/spl.c +++ b/arch/arm/cpu/armv7/omap-common/spl.c @@ -170,10 +170,13 @@ void preloader_console_init(void)

printf("\nU-Boot SPL %s (%s - %s)\n", u_boot_rev, U_BOOT_DATE, U_BOOT_TIME); +#if !defined(CONFIG_OMAP3_OVERO) omap_rev_string(rev_string_buffer); printf("Texas Instruments %s\n", rev_string_buffer); +#endif }

+#if !defined(CONFIG_OMAP3_OVERO) void __omap_rev_string(char *str) { sprintf(str, "Revision detection unimplemented"); @@ -181,3 +184,4 @@ void __omap_rev_string(char *str)

void omap_rev_string(char *str) __attribute__((weak, alias("__omap_rev_string"))); +#endif diff --git a/arch/arm/include/asm/arch-omap3/mem.h b/arch/arm/include/asm/arch-omap3/mem.h index 5fd02d4..4ca929e 100644 --- a/arch/arm/include/asm/arch-omap3/mem.h +++ b/arch/arm/include/asm/arch-omap3/mem.h @@ -123,6 +123,32 @@ enum { V_MCFG_BANKALLOCATION_RBC | \ V_MCFG_B32NOT16_32 | V_MCFG_DEEPPD_EN | V_MCFG_RAMTYPE_DDR

+/* Hynix part of Overo (165MHz optimized) 6.06ns */ +#define HYNIX_TDAL_165 6 +#define HYNIX_TDPL_165 3 +#define HYNIX_TRRD_165 2 +#define HYNIX_TRCD_165 3 +#define HYNIX_TRP_165 3 +#define HYNIX_TRAS_165 7 +#define HYNIX_TRC_165 10 +#define HYNIX_TRFC_165 21 +#define HYNIX_V_ACTIMA_165 \ + ACTIM_CTRLA(HYNIX_TRFC_165, HYNIX_TRC_165, \ + HYNIX_TRAS_165, HYNIX_TRP_165, \ + HYNIX_TRCD_165, HYNIX_TRRD_165, \ + HYNIX_TDPL_165, HYNIX_TDAL_165) + +#define HYNIX_TWTR_165 1 +#define HYNIX_TCKE_165 1 +#define HYNIX_TXP_165 2 +#define HYNIX_XSR_165 24 +#define HYNIX_V_ACTIMB_165 \ + ACTIM_CTRLB(HYNIX_TWTR_165, HYNIX_TCKE_165, \ + HYNIX_TXP_165, HYNIX_XSR_165) + +#define HYNIX_RASWIDTH_165 0x2 +#define HYNIX_V_MCFG_165(size) MCFG((size), HYNIX_RASWIDTH_165) + /* Hynix part of AM/DM37xEVM (200MHz optimized) */ #define HYNIX_TDAL_200 6 #define HYNIX_TDPL_200 3 diff --git a/board/overo/config.mk b/board/overo/config.mk deleted file mode 100644 index e7c471c..0000000 --- a/board/overo/config.mk +++ /dev/null @@ -1,28 +0,0 @@ -# -# Overo uses OMAP3 (ARM-CortexA8) cpu -# -# See file CREDITS for list of people who contributed to this -# project. -# -# This program is free software; you can redistribute it and/or -# modify it under the terms of the GNU General Public License as -# published by the Free Software Foundation; either version 2 of -# the License, or (at your option) any later version. -# -# This program is distributed in the hope that it will be useful, -# but WITHOUT ANY WARRANTY; without even the implied warranty of -# MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the -# GNU General Public License for more details. -# -# You should have received a copy of the GNU General Public License -# along with this program; if not, write to the Free Software -# Foundation, Inc., 59 Temple Place, Suite 330, Boston, -# MA 02111-1307 USA -# -# Physical Address: -# 8000'0000 (bank0) -# A000/0000 (bank1) -# Linux-Kernel is expected to be at 8000'8000, entry 8000'8000 -# (mem base + reserved) - -CONFIG_SYS_TEXT_BASE = 0x80008000 diff --git a/board/overo/overo.c b/board/overo/overo.c index 4a20c7f..5583f98 100644 --- a/board/overo/overo.c +++ b/board/overo/overo.c @@ -31,6 +31,7 @@ #include <common.h> #include <netdev.h> #include <twl4030.h> +#include <linux/mtd/nand.h> #include <asm/io.h> #include <asm/arch/mmc_host_def.h> #include <asm/arch/mux.h> @@ -107,6 +108,20 @@ int get_board_revision(void) { int revision;

+#ifdef CONFIG_DRIVER_OMAP34XX_I2C + unsigned char data; + + /* board revisions <= R2410 connect 4030 irq_1 to gpio112 */ + /* these boards should return a revision number of 0 */ + /* the code below forces a 4030 RTC irq to ensure that gpio112 is low */ + i2c_set_bus_num(TWL4030_I2C_BUS); + data = 0x01; + i2c_write(0x4B, 0x29, 1, &data, 1); + data = 0x0c; + i2c_write(0x4B, 0x2b, 1, &data, 1); + i2c_read(0x4B, 0x2a, 1, &data, 1); +#endif + if (!gpio_request(112, "") && !gpio_request(113, "") && !gpio_request(115, "")) { @@ -126,6 +141,44 @@ int get_board_revision(void) return revision; }

+#ifdef CONFIG_SPL_BUILD +/* + * Routine: get_board_mem_timings + * Description: If we use SPL then there is no x-loader nor config header + * so we have to setup the DDR timings ourself on both banks. + */ +void get_board_mem_timings(u32 *mcfg, u32 *ctrla, u32 *ctrlb, u32 *rfr_ctrl, + u32 *mr) +{ + *mr = MICRON_V_MR_165; + switch (get_board_revision()) { + case REVISION_0: /* Micron 1286MB/256MB, 1/2 banks of 128MB */ + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case REVISION_1: /* Micron 256MB/512MB, 1/2 banks of 256MB */ + *mcfg = MICRON_V_MCFG_165(256 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + case REVISION_2: /* Hynix 256MB/512MB, 1/2 banks of 256MB */ + *mcfg = HYNIX_V_MCFG_165(256 << 20); + *ctrla = HYNIX_V_ACTIMA_165; + *ctrlb = HYNIX_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + break; + default: + *mcfg = MICRON_V_MCFG_165(128 << 20); + *ctrla = MICRON_V_ACTIMA_165; + *ctrlb = MICRON_V_ACTIMB_165; + *rfr_ctrl = SDP_3430_SDRC_RFR_CTRL_165MHz; + } +} +#endif + /* * Routine: get_sdio2_config * Description: Return information about the wifi module connection @@ -337,7 +390,7 @@ int board_eth_init(bd_t *bis) return rc; }

-#ifdef CONFIG_GENERIC_MMC +#if defined(CONFIG_GENERIC_MMC) && !defined(CONFIG_SPL_BUILD) int board_mmc_init(bd_t *bis) { omap_mmc_init(0); diff --git a/board/overo/overo.h b/board/overo/overo.h index 915f15b..b41b628 100644 --- a/board/overo/overo.h +++ b/board/overo/overo.h @@ -33,6 +33,11 @@ const omap3_sysinfo sysinfo = { #endif };

+/* overo revisions */ +#define REVISION_0 0x0 +#define REVISION_1 0x1 +#define REVISION_2 0x2 + /* * IEN - Input Enable * IDIS - Input Disable diff --git a/include/configs/omap3_overo.h b/include/configs/omap3_overo.h index 8f2e69d..37947c8 100644 --- a/include/configs/omap3_overo.h +++ b/include/configs/omap3_overo.h @@ -285,6 +285,13 @@

#endif /* (CONFIG_CMD_NET) */

+/* + * 1MB into the SDRAM to allow for SPL's bss at the beginning of SDRAM + * 64 bytes before this address should be set aside for u-boot.img's + * header. That is 0x800FFFC0--0x80100000 should not be used for any + * other needs. + */ +#define CONFIG_SYS_TEXT_BASE 0x80100000 #define CONFIG_SYS_SDRAM_BASE PHYS_SDRAM_1 #define CONFIG_SYS_INIT_RAM_ADDR 0x4020f800 #define CONFIG_SYS_INIT_RAM_SIZE 0x800 @@ -294,4 +301,50 @@

#define CONFIG_SYS_CACHELINE_SIZE 64

+/* Defines for SPL */ +#define CONFIG_SPL +#define CONFIG_SPL_NAND_SIMPLE +#define CONFIG_SPL_TEXT_BASE 0x40200800 +#define CONFIG_SPL_MAX_SIZE (45 * 1024) +#define CONFIG_SPL_STACK LOW_LEVEL_SRAM_STACK + +#define CONFIG_SPL_BSS_START_ADDR 0x80000000 +#define CONFIG_SPL_BSS_MAX_SIZE 0x80000 /* 512 KB */ + +#define CONFIG_SYS_MMCSD_RAW_MODE_U_BOOT_SECTOR 0x300 /* address 0x60000 */ +#define CONFIG_SYS_U_BOOT_MAX_SIZE_SECTORS 0x200 /* 256 KB */ +#define CONFIG_SYS_MMC_SD_FAT_BOOT_PARTITION 1 +#define CONFIG_SPL_FAT_LOAD_PAYLOAD_NAME "u-boot.img" + +#define CONFIG_SPL_LIBCOMMON_SUPPORT +#define CONFIG_SPL_LIBDISK_SUPPORT +#define CONFIG_SPL_I2C_SUPPORT +#define CONFIG_SPL_LIBGENERIC_SUPPORT +#define CONFIG_SPL_MMC_SUPPORT +#define CONFIG_SPL_FAT_SUPPORT +#define CONFIG_SPL_SERIAL_SUPPORT +#define CONFIG_SPL_NAND_SUPPORT +#define CONFIG_SPL_POWER_SUPPORT +#define CONFIG_SPL_LDSCRIPT "$(CPUDIR)/omap-common/u-boot-spl.lds" +#define CONFIG_SYS_SPL_MALLOC_START 0x80208000 +#define CONFIG_SYS_SPL_MALLOC_SIZE 0x100000 + +/* NAND boot config */ +#define CONFIG_SYS_NAND_5_ADDR_CYCLE +#define CONFIG_SYS_NAND_PAGE_COUNT 64 +#define CONFIG_SYS_NAND_PAGE_SIZE 2048 +#define CONFIG_SYS_NAND_OOBSIZE 64 +#define CONFIG_SYS_NAND_BLOCK_SIZE (128*1024) +#define CONFIG_SYS_NAND_BAD_BLOCK_POS NAND_LARGE_BADBLOCK_POS +#define CONFIG_SYS_NAND_ECCPOS {2, 3, 4, 5, 6, 7, 8, 9,\ + 10, 11, 12, 13} +#define CONFIG_SYS_NAND_ECCSIZE 512 +#define CONFIG_SYS_NAND_ECCBYTES 3 +#define CONFIG_SYS_NAND_ECCSTEPS (CONFIG_SYS_NAND_PAGE_SIZE / \ + CONFIG_SYS_NAND_ECCSIZE) +#define CONFIG_SYS_NAND_ECCTOTAL (CONFIG_SYS_NAND_ECCBYTES * \ + CONFIG_SYS_NAND_ECCSTEPS) +#define CONFIG_SYS_NAND_U_BOOT_START CONFIG_SYS_TEXT_BASE +#define CONFIG_SYS_NAND_U_BOOT_OFFS 0x80000 + #endif /* __CONFIG_H */