[U-Boot] [PATCH 00/13] Go to common initdram() on 85xx-based boards
This patch series consists of a bunch of cleanups that allow us to use a common initdram() on all of the non-corenet 85xx-based boards. Also, switch to using phys_size_t to represent the size of memory returned.
Most of these patches are just code rearranges or renaming things to get a common scheme in place. There are also lots of cleanups - the various initdram() implementations had a variety of issues that I have hopefully fixed.
This is a large patch series, and I've had to hack on a bunch of different boards that I know nothing about, so I'd appreciate any review commentary. I have tested this on 8572DS and confirmed that the results of a MAKEALL powerpc are the same before and after this series.
Cheers, Becky
arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 + arch/powerpc/cpu/mpc85xx/cpu.c | 58 ++++++++++++++++++ arch/powerpc/cpu/mpc85xx/tlb.c | 6 ++- arch/powerpc/include/asm/fsl_ddr_sdram.h | 13 ++++ arch/powerpc/include/asm/fsl_lbc.h | 7 ++ board/atum8548/atum8548.c | 25 +-------- board/freescale/mpc8536ds/mpc8536ds.c | 21 ------- board/freescale/mpc8540ads/mpc8540ads.c | 52 +---------------- board/freescale/mpc8540ads/tlb.c | 19 ------ board/freescale/mpc8541cds/mpc8541cds.c | 43 -------------- board/freescale/mpc8544ds/mpc8544ds.c | 17 ------ board/freescale/mpc8548cds/mpc8548cds.c | 38 ------------ board/freescale/mpc8555cds/mpc8555cds.c | 45 -------------- board/freescale/mpc8560ads/mpc8560ads.c | 52 +---------------- board/freescale/mpc8560ads/tlb.c | 19 ------ board/freescale/mpc8568mds/mpc8568mds.c | 38 ------------ board/freescale/mpc8569mds/mpc8569mds.c | 36 ------------ board/freescale/mpc8572ds/mpc8572ds.c | 19 ------ board/freescale/p1022ds/p1022ds.c | 13 ---- board/freescale/p1_p2_rdb/ddr.c | 15 +----- board/freescale/p2020ds/p2020ds.c | 34 ++--------- board/mpc8540eval/mpc8540eval.c | 52 +--------------- board/pm854/law.c | 5 +- board/pm854/pm854.c | 62 +------------------- board/pm854/tlb.c | 18 +----- board/pm856/law.c | 5 +- board/pm856/pm856.c | 57 +------------------ board/pm856/tlb.c | 18 +----- board/sbc8548/sbc8548.c | 45 +-------------- board/sbc8548/tlb.c | 34 ++++------- board/sbc8560/sbc8560.c | 93 +----------------------------- board/socrates/sdram.c | 15 +----- board/stx/stxgp3/stxgp3.c | 32 ---------- board/stx/stxssa/stxssa.c | 33 ----------- board/tqc/tqm85xx/sdram.c | 70 +++++++---------------- board/tqc/tqm85xx/tlb.c | 47 --------------- board/xes/common/Makefile | 2 - board/xes/common/fsl_8xxx_ddr.c | 46 --------------- board/xes/xpedite517x/xpedite517x.c | 13 ++++ doc/README.mpc85xxads | 4 +- include/configs/MPC8536DS.h | 1 - include/configs/MPC8540EVAL.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 7 -- include/configs/MPC8572DS.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/PM854.h | 8 +-- include/configs/PM856.h | 8 +-- include/configs/SBC8540.h | 5 +- include/configs/TQM85xx.h | 6 ++- include/configs/sbc8560.h | 5 +- include/configs/stxgp3.h | 5 +- include/configs/stxssa.h | 1 - 54 files changed, 185 insertions(+), 1092 deletions(-)
Modeled after the MPC8540DS code; this will allow us to use a common initdram() once that is available. There should be no functional change.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/mpc8540eval/mpc8540eval.c | 64 +++++++++++++++++++++----------------- 1 files changed, 35 insertions(+), 29 deletions(-)
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index 054d644..f1ab360 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -64,41 +64,15 @@ int checkboard (void) return (0); }
-phys_size_t initdram (int board_type) +void sdram_init(void) { - long dram_size = 0; - -#if !defined(CONFIG_RAM_AS_FLASH) +#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); sys_info_t sysinfo; uint temp_lbcdll = 0; -#endif -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif
-#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0;
- /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - return dram_size; -#endif - -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus is not emulating flash */ get_sys_info(&sysinfo); /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & LCRR_CLKDIV) < 66000000) { @@ -132,6 +106,38 @@ phys_size_t initdram (int board_type) lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; asm("sync"); #endif +} + +phys_size_t initdram(int board_type) +{ + long dram_size = 0; + +#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) + volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); +#endif + +#if defined(CONFIG_DDR_DLL) + uint temp_ddrdll = 0; + + /* Work around to stabilize DDR DLL */ + temp_ddrdll = gur->ddrdllcr; + gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; + asm("sync;isync;msync"); +#endif + +#if defined(CONFIG_SPD_EEPROM) + dram_size = fsl_ddr_sdram(); + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; +#else + dram_size = fixed_sdram(); +#endif + +#if defined(CONFIG_SYS_RAMBOOT) + return dram_size; +#endif + + sdram_init();
#if defined(CONFIG_DDR_ECC) {
Also, change this code to use phys_size_t instead of long int. Using common naming for this function will enable us to use the common initdram() for 85xx going forward. Other than the type change, this is just a code rearrange.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/tqc/tqm85xx/sdram.c | 37 +++++++++++++++++++++++-------------- 1 files changed, 23 insertions(+), 14 deletions(-)
diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 503c5e5..260cd1c 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -65,6 +65,7 @@ sdram_conf_t ddr_cs_conf[] = { #define N_DDR_CS_CONF (sizeof(ddr_cs_conf) / sizeof(ddr_cs_conf[0]))
int cas_latency (void); +static phys_size_t sdram_setup(int);
/* * Autodetect onboard DDR SDRAM on 85xx platforms @@ -73,7 +74,26 @@ int cas_latency (void); * so this should be extended for other future boards * using this routine! */ -long int sdram_setup (int casl) +phys_size_t fixed_sdram(void) +{ + int casl = 0; + phys_size_t dram_size = 0; + + casl = cas_latency(); + dram_size = sdram_setup(casl); + if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { + /* + * Try again with default CAS latency + */ + printf("Problem with CAS lantency, using default CL %d/10!\n", + CONFIG_DDR_DEFAULT_CL); + dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + puts(" "); + } + return dram_size; +} + +static phys_size_t sdram_setup(int casl) { int i; volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); @@ -376,8 +396,7 @@ long int sdram_setup (int casl)
phys_size_t initdram (int board_type) { - long dram_size = 0; - int casl; + phys_size_t dram_size = 0;
#if defined(CONFIG_DDR_DLL) /* @@ -407,17 +426,7 @@ phys_size_t initdram (int board_type) } #endif
- casl = cas_latency (); - dram_size = sdram_setup (casl); - if ((dram_size == 0) && (casl != CONFIG_DDR_DEFAULT_CL)) { - /* - * Try again with default CAS latency - */ - printf ("Problem with CAS lantency, using default CL %d/10!\n", - CONFIG_DDR_DEFAULT_CL); - dram_size = sdram_setup (CONFIG_DDR_DEFAULT_CL); - puts (" "); - } + dram_size = fixed_sdram();
return dram_size; }
Some platforms might want to override the default wimge=0 for DDR. Add CONFIG_DDR_TLB_WIMGE for those platforms to use. This will initially only be used by TQM85xx, but could be useful for other boards or testing going forward.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/tlb.c | 6 +++++- 1 files changed, 5 insertions(+), 1 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/tlb.c b/arch/powerpc/cpu/mpc85xx/tlb.c index e3a71ae..513aaaa 100644 --- a/arch/powerpc/cpu/mpc85xx/tlb.c +++ b/arch/powerpc/cpu/mpc85xx/tlb.c @@ -250,10 +250,14 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) { int i; unsigned int tlb_size; + unsigned int wimge = 0; unsigned int ram_tlb_address = (unsigned int)CONFIG_SYS_DDR_SDRAM_BASE; unsigned int max_cam = (mfspr(SPRN_TLB1CFG) >> 16) & 0xf; u64 size, memsize = (u64)memsize_in_meg << 20;
+#ifdef CONFIG_DDR_TLB_WIMGE + wimge = CONFIG_DDR_TLB_WIMGE; +#endif size = min(memsize, CONFIG_MAX_MEM_MAPPED);
/* Convert (4^max) kB to (2^max) bytes */ @@ -277,7 +281,7 @@ setup_ddr_tlbs_phys(phys_addr_t p_addr, unsigned int memsize_in_meg) tlb_size = (camsize - 10) / 2;
set_tlb(1, ram_tlb_address, p_addr, - MAS3_SX|MAS3_SW|MAS3_SR, 0, + MAS3_SX|MAS3_SW|MAS3_SR, wimge, 0, ram_tlb_index, tlb_size, 1);
size -= 1ULL << camsize;
This will help us go to a fixed initdram() for all 85xx boards going forward. sdram_setup() had an argument that it didn't need, since the value was #defined.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/socrates/sdram.c | 4 ++-- 1 files changed, 2 insertions(+), 2 deletions(-)
diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index 029ba02..ef897b2 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@ * so this should be extended for other future boards * using this routine! */ -long int sdram_setup(int casl) +long int fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -85,7 +85,7 @@ phys_size_t initdram (int board_type) dram_size = setup_ddr_tlbs(dram_size / 0x100000); dram_size *= 0x100000; #else - dram_size = sdram_setup(CONFIG_DDR_DEFAULT_CL); + dram_size = fixed_sdram(); #endif return dram_size; }
This isn't used - delete it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/MPC8569MDS.h | 6 ------ 1 files changed, 0 insertions(+), 6 deletions(-)
diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index c7973b4..720b5b6 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -262,12 +262,6 @@ extern unsigned long get_clock_freq(void); #define CONFIG_SYS_OR3_PRELIM CONFIG_NAND_OR_PRELIM /* NAND Options */ #endif
-/* - * SDRAM on the LocalBus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */ - #define CONFIG_SYS_LBC_LCRR 0x00000004 /* LB clock ratio reg */ #define CONFIG_SYS_LBC_LBCR 0x00040000 /* LB config reg */ #define CONFIG_SYS_LBC_LSRT 0x20000000 /* LB sdram refresh timer */
As far as I can tell, this board doesn't actually configure the LBC for SDRAM. I've renamed this to avoid confusion (and to make the initdram() cleanup easier later.)
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/pm854/law.c | 5 ++--- board/pm854/tlb.c | 4 ++-- include/configs/PM854.h | 6 +----- 3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/board/pm854/law.c b/board/pm854/law.c index ac21d7a..bea9259 100644 --- a/board/pm854/law.c +++ b/board/pm854/law.c @@ -35,7 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf000_0000 0xf7ff_ffff LBC 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M * @@ -49,8 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index 5e74e2d..dadb75c 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -93,9 +93,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM + * 0xf000_0000 64M LBC */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 1e2089f..39283b2 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -123,11 +123,7 @@ #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
-/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ +#define CONFIG_SYS_LBC_BASE 0xf0000000 /* Localbus */
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of 32 MB FLASH */ #define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
This board does not actually configure anything for SDRAM - change the name to avoid confusion and make it easier to go to a common initdram going forward.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- board/pm856/law.c | 5 ++--- board/pm856/tlb.c | 4 ++-- include/configs/PM856.h | 6 +----- 3 files changed, 5 insertions(+), 10 deletions(-)
diff --git a/board/pm856/law.c b/board/pm856/law.c index ac21d7a..bea9259 100644 --- a/board/pm856/law.c +++ b/board/pm856/law.c @@ -35,7 +35,7 @@ * 0xc000_0000 0xdfff_ffff RapidIO 512M * 0xe000_0000 0xe000_ffff CCSR 1M * 0xe200_0000 0xe2ff_ffff PCI1 IO 16M - * 0xf000_0000 0xf7ff_ffff SDRAM 128M + * 0xf000_0000 0xf7ff_ffff LBC 128M * 0xf800_0000 0xf80f_ffff BCSR 1M * 0xfc00_0000 0xffff_ffff FLASH (boot bank) 64M * @@ -49,8 +49,7 @@ struct law_entry law_table[] = { SET_LAW(CONFIG_SYS_DDR_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_DDR), #endif SET_LAW(CONFIG_SYS_PCI1_MEM_PHYS, LAW_SIZE_512M, LAW_TRGT_IF_PCI), - /* This is not so much the SDRAM map as it is the whole localbus map. */ - SET_LAW(CONFIG_SYS_LBC_SDRAM_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), + SET_LAW(CONFIG_SYS_LBC_BASE, LAW_SIZE_256M, LAW_TRGT_IF_LBC), SET_LAW(CONFIG_SYS_PCI1_IO_PHYS, LAW_SIZE_16M, LAW_TRGT_IF_PCI), SET_LAW(CONFIG_SYS_RIO_MEM_BASE, LAW_SIZE_512M, LAW_TRGT_IF_RIO), }; diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index 5e74e2d..dadb75c 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -93,9 +93,9 @@ struct fsl_e_tlb_entry tlb_table[] = {
/* * TLB 6: 64M Cacheable, non-guarded - * 0xf000_0000 64M LBC SDRAM + * 0xf000_0000 64M LBC */ - SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, + SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1),
diff --git a/include/configs/PM856.h b/include/configs/PM856.h index d3e8f41..dbce6c4 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -125,11 +125,7 @@ #define CONFIG_SYS_DDR_MODE 0x00000062 /* DLL,normal,seq,4/2.5 */ #define CONFIG_SYS_DDR_INTERVAL 0x045b0100 /* autocharge,no open page */
-/* - * SDRAM on the Local Bus - */ -#define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ -#define CONFIG_SYS_LBC_SDRAM_SIZE 0 /* LBC SDRAM is 0 MB */ +#define CONFIG_SYS_LBC_BASE 0xf0000000 /* Localbus */
#define CONFIG_SYS_FLASH_BASE 0xfe000000 /* start of FLASH 32M */ #define CONFIG_SYS_BR0_PRELIM 0xfe001801 /* port size 32bit */
This is for boards that use the SDRAM mode on the LBC but don't require any additional setup.
I'm merging all the initdram() calls into a single function for 85xx, and have to be able to distinguish between boards that require an sdram_init() function, and those that do not. We could have defined an empty sdram_init() but I hate doing that.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/sbc8560.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 101c5d9..65d8eba 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -136,6 +136,9 @@
#undef CONFIG_CLOCKS_IN_MHZ
+/* No sdram_init() required - some boards require additional setup */ +#define CONFIG_SYS_LBC_NO_SDRAM_INIT + #if defined(CONFIG_RAM_AS_FLASH) #define CONFIG_SYS_LBC_SDRAM_BASE 0xfc000000 /* Localbus SDRAM */ #define CONFIG_SYS_FLASH_BASE 0xf8000000 /* start of FLASH 8M */
This is needed to distinguish between boards with lbc sdram that require additional initialization and those that do not.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/stxgp3.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index c2497ad..f4cd138 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -82,6 +82,9 @@ #define CONFIG_SYS_LBC_SDRAM_BASE 0xf0000000 /* Localbus SDRAM */ #define CONFIG_SYS_LBC_SDRAM_SIZE 256 /* LBC SDRAM is 64MB */
+/* No sdram_init() required - some boards require additional setup */ +#define CONFIG_SYS_LBC_NO_SDRAM_INIT + #define CONFIG_SYS_FLASH_BASE 0xff000000 /* start of FLASH 16M */ #define CONFIG_SYS_BR0_PRELIM 0xff001801 /* port size 32bit */
This is used to distinguish between boards that require extra setup to use LBC sdram, and those that don't
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/SBC8540.h | 3 +++ 1 files changed, 3 insertions(+), 0 deletions(-)
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index fd9bacc..7c1d0bd 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -151,6 +151,9 @@ #endif #define CONFIG_SYS_LBC_SDRAM_SIZE 64 /* LBC SDRAM is 64MB */
+/* No sdram_init() required - some boards require additional setup */ +#define CONFIG_SYS_LBC_NO_SDRAM_INIT + /* local bus definitions */ #define CONFIG_SYS_BR1_PRELIM 0xe4001801 /* 64M, 32-bit flash */ #define CONFIG_SYS_OR1_PRELIM 0xfc000ff7
Neither of these parts should have the erratum this is meant to work around. Delete it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- include/configs/MPC8568MDS.h | 1 - include/configs/MPC8569MDS.h | 1 - 2 files changed, 0 insertions(+), 2 deletions(-)
diff --git a/include/configs/MPC8568MDS.h b/include/configs/MPC8568MDS.h index 281918b..7817fba 100644 --- a/include/configs/MPC8568MDS.h +++ b/include/configs/MPC8568MDS.h @@ -82,7 +82,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8569MDS.h b/include/configs/MPC8569MDS.h index 720b5b6..4cae94d 100644 --- a/include/configs/MPC8569MDS.h +++ b/include/configs/MPC8569MDS.h @@ -122,7 +122,6 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
Correct initdram to use phys_size_t to represent the size of dram; instead of changing this all over the place, and correcting all the other random errors I've notived, create a common initdram that is used by all non-corenet 85xx parts. Most of the initdram() functions were identical, with 2 common differences:
1) DDR tlbs for the fixed_sdram case were set up in initdram() on some boards, and were part of the tlb_table on others. I have changed them all over to the initdram() method - we shouldn't be accessing dram before this point so they don't need to be done sooner, and this seems cleaner.
2) Parts that require the DDR11 erratum workaround had different implementations - I have adopted the version from the Freescale errata document. It also looks like some of the versions were buggy, and, depending on timing, could have resulted in the DDR controller being disabled. This seems bad.
The xpedite boards had a common/fsl_8xxx_ddr.c; with this change only the 517 board uses this so I have moved the ddr code into that board's directory in xpedite517x.c
The ATUM8548 board didn't appear to set up any tlbs in the fixed_sdram case; this patch fixes that.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cpu.c | 58 ++++++++++++++++++ arch/powerpc/include/asm/fsl_ddr_sdram.h | 13 ++++ arch/powerpc/include/asm/fsl_lbc.h | 7 ++ board/atum8548/atum8548.c | 25 +-------- board/freescale/mpc8536ds/mpc8536ds.c | 21 ------- board/freescale/mpc8540ads/mpc8540ads.c | 52 +---------------- board/freescale/mpc8540ads/tlb.c | 19 ------ board/freescale/mpc8541cds/mpc8541cds.c | 43 -------------- board/freescale/mpc8544ds/mpc8544ds.c | 17 ------ board/freescale/mpc8548cds/mpc8548cds.c | 38 ------------ board/freescale/mpc8555cds/mpc8555cds.c | 45 -------------- board/freescale/mpc8560ads/mpc8560ads.c | 52 +---------------- board/freescale/mpc8560ads/tlb.c | 19 ------ board/freescale/mpc8568mds/mpc8568mds.c | 38 ------------ board/freescale/mpc8569mds/mpc8569mds.c | 36 ------------ board/freescale/mpc8572ds/mpc8572ds.c | 19 ------ board/freescale/p1022ds/p1022ds.c | 13 ---- board/freescale/p1_p2_rdb/ddr.c | 15 +----- board/freescale/p2020ds/p2020ds.c | 34 ++--------- board/mpc8540eval/mpc8540eval.c | 52 +---------------- board/pm854/pm854.c | 62 +------------------- board/pm854/tlb.c | 14 ----- board/pm856/pm856.c | 57 +------------------ board/pm856/tlb.c | 14 ----- board/sbc8548/sbc8548.c | 45 +-------------- board/sbc8548/tlb.c | 34 ++++------- board/sbc8560/sbc8560.c | 93 +----------------------------- board/socrates/sdram.c | 15 +----- board/stx/stxgp3/stxgp3.c | 32 ---------- board/stx/stxssa/stxssa.c | 33 ----------- board/tqc/tqm85xx/sdram.c | 37 ------------ board/tqc/tqm85xx/tlb.c | 47 --------------- board/xes/common/Makefile | 2 - board/xes/common/fsl_8xxx_ddr.c | 46 --------------- board/xes/xpedite517x/xpedite517x.c | 13 ++++ include/configs/TQM85xx.h | 4 + 36 files changed, 124 insertions(+), 1040 deletions(-) delete mode 100644 board/xes/common/fsl_8xxx_ddr.c
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index 55ee36d..f242baf 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -34,6 +34,7 @@ #include <asm/io.h> #include <asm/mmu.h> #include <asm/fsl_law.h> +#include <asm/fsl_lbc.h> #include <post.h> #include <asm/processor.h> #include <asm/fsl_ddr_sdram.h> @@ -286,6 +287,63 @@ void mpc85xx_reginfo(void) print_lbc_regs(); }
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = 0; + + puts("Initializing\n"); + +#if defined(CONFIG_DDR_DLL) + { + ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); + unsigned int x = 10; + unsigned int i; + + /* + * Work around to stabilize DDR DLL + */ + out_be32(&gur->ddrdllcr, 0x81000000); + asm("sync;isync;msync"); + udelay(200); + while (in_be32(&gur->ddrdllcr) != 0x81000100) { + setbits_be32(&gur->devdisr, 0x00010000); + for (i = 0; i < x; i++) + ; + clrbits_be32(&gur->devdisr, 0x00010000); + x++; + } + } +#endif + +#if defined(CONFIG_SPD_EEPROM) || defined(CONFIG_DDR_SPD) + dram_size = fsl_ddr_sdram(); +#else + dram_size = fixed_sdram(); +#endif + dram_size = setup_ddr_tlbs(dram_size / 0x100000); + dram_size *= 0x100000; + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* + * Initialize and enable DDR ECC. + */ + ddr_enable_ecc(dram_size); +#endif + + /* + * Initialize SDRAM if needed. + */ +#if defined(CONFIG_SYS_LBC_SDRAM_BASE) && !defined(CONFIG_SYS_LBC_NO_SDRAM_INIT) + sdram_init(); +#endif + + puts(" DDR: "); + return dram_size; +} +#endif + #if CONFIG_POST & CONFIG_SYS_POST_MEMORY
/* Board-specific functions defined in each board's ddr.c */ diff --git a/arch/powerpc/include/asm/fsl_ddr_sdram.h b/arch/powerpc/include/asm/fsl_ddr_sdram.h index 17d4b31..8ceae18 100644 --- a/arch/powerpc/include/asm/fsl_ddr_sdram.h +++ b/arch/powerpc/include/asm/fsl_ddr_sdram.h @@ -214,6 +214,19 @@ typedef struct memctl_options_s {
extern phys_size_t fsl_ddr_sdram(void);
+/* + * The 85xx boards have a common prototype for fixed_sdram so put the + * declaration here. + */ +#ifdef CONFIG_MPC85xx +extern phys_size_t fixed_sdram(void); +#endif + +#if defined(CONFIG_DDR_ECC) +extern void ddr_enable_ecc(unsigned int dram_size); +#endif + + typedef struct fixed_ddr_parm{ int min_freq; int max_freq; diff --git a/arch/powerpc/include/asm/fsl_lbc.h b/arch/powerpc/include/asm/fsl_lbc.h index 82d24ab..be41ee6 100644 --- a/arch/powerpc/include/asm/fsl_lbc.h +++ b/arch/powerpc/include/asm/fsl_lbc.h @@ -16,6 +16,13 @@ #include <config.h> #include <common.h>
+/* 85xx boards have a common prototype for this so put the declaration here */ +#ifdef CONFIG_MPC85xx +#if defined(CONFIG_SYS_LBC_SDRAM_BASE) && !defined(CONFIG_SYS_LBC_NO_SDRAM_INIT) +extern void sdram_init(void); +#endif +#endif + /* BR - Base Registers */ #define BR0 0x5000 /* Register offset to immr */ diff --git a/board/atum8548/atum8548.c b/board/atum8548/atum8548.c index 9403e4b..d719292 100644 --- a/board/atum8548/atum8548.c +++ b/board/atum8548/atum8548.c @@ -37,8 +37,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram(void); - int board_early_init_f (void) { return 0; @@ -67,7 +65,7 @@ int checkboard (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -96,27 +94,6 @@ long int fixed_sdram (void) } #endif /* !defined(CONFIG_SPD_EEPROM) */
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_SPD_EEPROM) - puts("fsl_ddr_sdram\n"); - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - puts("fixed_sdram\n"); - dram_size = fixed_sdram (); -#endif - - puts(" DDR: "); - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram(void) diff --git a/board/freescale/mpc8536ds/mpc8536ds.c b/board/freescale/mpc8536ds/mpc8536ds.c index cf92ba1..ee5b668 100644 --- a/board/freescale/mpc8536ds/mpc8536ds.c +++ b/board/freescale/mpc8536ds/mpc8536ds.c @@ -42,8 +42,6 @@
#include "../common/sgmii_riser.h"
-phys_size_t fixed_sdram(void); - int board_early_init_f (void) { #ifdef CONFIG_MMC @@ -98,25 +96,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_SPD_EEPROM) /* * Fixed sdram init -- doesn't use serial presence detect. diff --git a/board/freescale/mpc8540ads/mpc8540ads.c b/board/freescale/mpc8540ads/mpc8540ads.c index d354a26..deab811 100644 --- a/board/freescale/mpc8540ads/mpc8540ads.c +++ b/board/freescale/mpc8540ads/mpc8540ads.c @@ -39,8 +39,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
int checkboard (void) { @@ -61,54 +59,6 @@ int checkboard (void) return 0; }
- -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -232,7 +182,7 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8540ads/tlb.c b/board/freescale/mpc8540ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8540ads/tlb.c +++ b/board/freescale/mpc8540ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8541cds/mpc8541cds.c b/board/freescale/mpc8541cds/mpc8541cds.c index 59ec604..59df2bd 100644 --- a/board/freescale/mpc8541cds/mpc8541cds.c +++ b/board/freescale/mpc8541cds/mpc8541cds.c @@ -42,7 +42,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/* * I/O Port configuration table @@ -242,48 +241,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8544ds/mpc8544ds.c b/board/freescale/mpc8544ds/mpc8544ds.c index 31c3fad..35d81db 100644 --- a/board/freescale/mpc8544ds/mpc8544ds.c +++ b/board/freescale/mpc8544ds/mpc8544ds.c @@ -67,23 +67,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - - dram_size = fsl_ddr_sdram(); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #ifdef CONFIG_PCI1 static struct pci_controller pci1_hose; #endif diff --git a/board/freescale/mpc8548cds/mpc8548cds.c b/board/freescale/mpc8548cds/mpc8548cds.c index 14c902c..230cbd1 100644 --- a/board/freescale/mpc8548cds/mpc8548cds.c +++ b/board/freescale/mpc8548cds/mpc8548cds.c @@ -41,7 +41,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void);
int checkboard (void) { @@ -74,43 +73,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8555cds/mpc8555cds.c b/board/freescale/mpc8555cds/mpc8555cds.c index edaba26..5fe7f13 100644 --- a/board/freescale/mpc8555cds/mpc8555cds.c +++ b/board/freescale/mpc8555cds/mpc8555cds.c @@ -40,7 +40,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -void sdram_init(void);
/* * I/O Port configuration table @@ -240,50 +239,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8560ads/mpc8560ads.c b/board/freescale/mpc8560ads/mpc8560ads.c index 1761431..38f59d1 100644 --- a/board/freescale/mpc8560ads/mpc8560ads.c +++ b/board/freescale/mpc8560ads/mpc8560ads.c @@ -44,8 +44,6 @@ extern void ddr_enable_ecc(unsigned int dram_size);
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void);
/* @@ -266,54 +264,6 @@ int checkboard (void) return 0; }
- -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* - * Work around to stabilize DDR DLL - */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - /* - * Initialize SDRAM. - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -437,7 +387,7 @@ sdram_init(void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/freescale/mpc8560ads/tlb.c b/board/freescale/mpc8560ads/tlb.c index a9925d5..adcc0ad 100644 --- a/board/freescale/mpc8560ads/tlb.c +++ b/board/freescale/mpc8560ads/tlb.c @@ -106,25 +106,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_BCSR, CONFIG_SYS_BCSR, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, 0, 7, BOOKE_PAGESZ_16K, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 8, 9: 128M DDR - * 0x00000000 64M DDR System memory - * 0x04000000 64M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ -#error("Update the number of table entries in tlb1_entry") - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_64M, 1), - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, CONFIG_SYS_DDR_SDRAM_BASE + 0x4000000, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 9, BOOKE_PAGESZ_64M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/freescale/mpc8568mds/mpc8568mds.c b/board/freescale/mpc8568mds/mpc8568mds.c index d74fcac..ee4c807 100644 --- a/board/freescale/mpc8568mds/mpc8568mds.c +++ b/board/freescale/mpc8568mds/mpc8568mds.c @@ -100,7 +100,6 @@ const qe_iop_conf_t qe_iop_conf_tab[] = { };
void local_bus_init(void); -void sdram_init(void);
int board_early_init_f (void) { @@ -137,43 +136,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay(200); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ diff --git a/board/freescale/mpc8569mds/mpc8569mds.c b/board/freescale/mpc8569mds/mpc8569mds.c index dc0884e..12a417c 100644 --- a/board/freescale/mpc8569mds/mpc8569mds.c +++ b/board/freescale/mpc8569mds/mpc8569mds.c @@ -44,8 +44,6 @@ #include "../common/pq-mds-pib.h" #endif
-phys_size_t fixed_sdram(void); - const qe_iop_conf_t qe_iop_conf_tab[] = { /* QE_MUX_MDC */ {2, 31, 1, 0, 1}, /* QE_MUX_MDC */ @@ -244,40 +242,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - volatile ccsr_gur_t *gur = - (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - out_be32(&gur->ddrdllcr, 0x81000000); - udelay(200); -#endif - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_SPD_EEPROM) phys_size_t fixed_sdram(void) { diff --git a/board/freescale/mpc8572ds/mpc8572ds.c b/board/freescale/mpc8572ds/mpc8572ds.c index 120f35c..796aacf 100644 --- a/board/freescale/mpc8572ds/mpc8572ds.c +++ b/board/freescale/mpc8572ds/mpc8572ds.c @@ -38,8 +38,6 @@
#include "../common/sgmii_riser.h"
-long int fixed_sdram(void); - int checkboard (void) { u8 vboot; @@ -73,23 +71,6 @@ int checkboard (void) return 0; }
-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_SPD_EEPROM - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -}
#if !defined(CONFIG_SPD_EEPROM) /* diff --git a/board/freescale/p1022ds/p1022ds.c b/board/freescale/p1022ds/p1022ds.c index 7cb549b..e3e8300 100644 --- a/board/freescale/p1022ds/p1022ds.c +++ b/board/freescale/p1022ds/p1022ds.c @@ -76,19 +76,6 @@ int checkboard(void) return 0; }
-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing....\n"); - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000) * 0x100000; - - puts(" DDR: "); - return dram_size; -} - #define CONFIG_TFP410_I2C_ADDR 0x38
/* Masks for the SSI_TDM and AUDCLK bits of the ngPIXIS BRDCFG1 register. */ diff --git a/board/freescale/p1_p2_rdb/ddr.c b/board/freescale/p1_p2_rdb/ddr.c index 15b46b0..e54fde2 100644 --- a/board/freescale/p1_p2_rdb/ddr.c +++ b/board/freescale/p1_p2_rdb/ddr.c @@ -239,19 +239,6 @@ phys_size_t fixed_sdram (void)
fsl_ddr_set_memctl_regs(&ddr_cfg_regs, 0);
+ set_ddr_laws(0, ddr_size, LAW_TRGT_IF_DDR_1); return ddr_size; } - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - dram_size = fixed_sdram(); - set_ddr_laws(0, dram_size, LAW_TRGT_IF_DDR_1); - - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts("DDR: "); - return dram_size; -} diff --git a/board/freescale/p2020ds/p2020ds.c b/board/freescale/p2020ds/p2020ds.c index b507677..1fa215e 100644 --- a/board/freescale/p2020ds/p2020ds.c +++ b/board/freescale/p2020ds/p2020ds.c @@ -43,8 +43,6 @@
DECLARE_GLOBAL_DATA_PTR;
-phys_size_t fixed_sdram(void); - int checkboard(void) { u8 sw; @@ -72,31 +70,6 @@ int checkboard(void) const char *board_hwconfig = "foo:bar=baz"; const char *cpu_hwconfig = "foo:bar=baz";
-phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = 0; - - puts("Initializing...."); - -#ifdef CONFIG_DDR_SPD - dram_size = fsl_ddr_sdram(); -#else - dram_size = fixed_sdram(); - - if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, - dram_size, - LAW_TRGT_IF_DDR) < 0) { - printf("ERROR setting Local Access Windows for DDR\n"); - return 0; - }; -#endif - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - - puts(" DDR: "); - return dram_size; -} - #if !defined(CONFIG_DDR_SPD) /* * Fixed sdram init -- doesn't use serial presence detect. @@ -172,6 +145,13 @@ phys_size_t fixed_sdram(void) udelay(500); #endif
+ if (set_ddr_laws(CONFIG_SYS_DDR_SDRAM_BASE, + CONFIG_SYS_SDRAM_SIZE * 1024 * 1024, + LAW_TRGT_IF_DDR) < 0) { + printf("ERROR setting Local Access Windows for DDR\n"); + return 0; + }; + return CONFIG_SYS_SDRAM_SIZE * 1024 * 1024; }
diff --git a/board/mpc8540eval/mpc8540eval.c b/board/mpc8540eval/mpc8540eval.c index f1ab360..63a0035 100644 --- a/board/mpc8540eval/mpc8540eval.c +++ b/board/mpc8540eval/mpc8540eval.c @@ -31,8 +31,6 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-long int fixed_sdram (void); - int board_pre_init (void) { #if defined(CONFIG_PCI) @@ -108,54 +106,6 @@ void sdram_init(void) #endif }
-phys_size_t initdram(int board_type) -{ - long dram_size = 0; - -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif - -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - -#if defined(CONFIG_SYS_RAMBOOT) - return dram_size; -#endif - - sdram_init(); - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -194,7 +144,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/pm854.c b/board/pm854/pm854.c index 0b8ea81..bbaf4fd 100644 --- a/board/pm854/pm854.c +++ b/board/pm854/pm854.c @@ -34,14 +34,7 @@ #include <asm/fsl_ddr_sdram.h> #include <spd_sdram.h>
-#if defined(CONFIG_DDR_ECC) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram(void); -
int board_early_init_f (void) { @@ -73,59 +66,6 @@ int checkboard (void) return 0; }
- -phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -225,7 +165,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm854/tlb.c b/board/pm854/tlb.c index dadb75c..482eb38 100644 --- a/board/pm854/tlb.c +++ b/board/pm854/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/pm856/pm856.c b/board/pm856/pm856.c index 4e059b0..3791216 100644 --- a/board/pm856/pm856.c +++ b/board/pm856/pm856.c @@ -41,7 +41,6 @@ extern void ddr_enable_ecc(unsigned int dram_size); #endif
void local_bus_init(void); -long int fixed_sdram(void);
/* * I/O Port configuration table @@ -228,60 +227,6 @@ int checkboard (void) }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i,x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm("sync;isync;msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) - { - gur->devdisr = gur->devdisr | 0x00010000; - asm("sync;isync;msync"); - for (i=0; i<x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm("sync;isync;msync"); - x++; - } - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if defined(CONFIG_DDR_ECC) - /* - * Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - puts(" DDR: "); - return dram_size; -} - - /* * Initialize Local Bus */ @@ -380,7 +325,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { #ifndef CONFIG_SYS_RAMBOOT volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); diff --git a/board/pm856/tlb.c b/board/pm856/tlb.c index dadb75c..482eb38 100644 --- a/board/pm856/tlb.c +++ b/board/pm856/tlb.c @@ -98,20 +98,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY(1, CONFIG_SYS_LBC_BASE, CONFIG_SYS_LBC_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if !defined(CONFIG_SPD_EEPROM) - /* - * TLB 7: 256M DDR - * 0x00000000 256M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_256M, 1), -#endif };
int num_tlb_entries = ARRAY_SIZE(tlb_table); diff --git a/board/sbc8548/sbc8548.c b/board/sbc8548/sbc8548.c index 272428f..2d24890 100644 --- a/board/sbc8548/sbc8548.c +++ b/board/sbc8548/sbc8548.c @@ -42,8 +42,6 @@ DECLARE_GLOBAL_DATA_PTR;
void local_bus_init(void); -void sdram_init(void); -long int fixed_sdram (void);
int board_early_init_f (void) { @@ -68,47 +66,6 @@ int checkboard (void) return 0; }
-phys_size_t -initdram(int board_type) -{ - long dram_size = 0; - - puts("Initializing\n"); - -#if defined(CONFIG_DDR_DLL) - { - /* - * Work around to stabilize DDR DLL MSYNC_IN. - * Errata DDR9 seems to have been fixed. - * This is now the workaround for Errata DDR11: - * Override DLL = 1, Course Adj = 1, Tap Select = 0 - */ - - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - - out_be32(&gur->ddrdllcr, 0x81000000); - asm("sync;isync;msync"); - udelay(200); - } -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - - /* - * SDRAM Initialization - */ - sdram_init(); - - puts(" DDR: "); - return dram_size; -} - /* * Initialize Local Bus */ @@ -267,7 +224,7 @@ testdram(void) * fixed_sdram init -- doesn't use serial presence detect. * assumes 256MB DDR2 SDRAM SODIMM, without ECC, running at DDR400 speed. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
diff --git a/board/sbc8548/tlb.c b/board/sbc8548/tlb.c index 38bdeb3..bb4c052 100644 --- a/board/sbc8548/tlb.c +++ b/board/sbc8548/tlb.c @@ -65,44 +65,34 @@ struct fsl_e_tlb_entry tlb_table[] = { 0, 1, BOOKE_PAGESZ_1G, 1),
/* - * TLB 2: 256M Cacheable, non-guarded - * 0x0 256M DDR SDRAM - */ -#if !defined(CONFIG_SPD_EEPROM) - SET_TLB_ENTRY(1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 2, BOOKE_PAGESZ_256M, 1), -#endif - - /* - * TLB 3: 64M Non-cacheable, guarded + * TLB 2: 64M Non-cacheable, guarded * 0xe0000000 1M CCSRBAR * 0xe2000000 8M PCI1 IO * 0xe2800000 8M PCIe IO */ SET_TLB_ENTRY(1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 3, BOOKE_PAGESZ_64M, 1), + 0, 2, BOOKE_PAGESZ_64M, 1),
/* - * TLB 4: 64M Cacheable, non-guarded + * TLB 3: 64M Cacheable, non-guarded * 0xf0000000 64M LBC SDRAM First half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE, CONFIG_SYS_LBC_SDRAM_BASE, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 4, BOOKE_PAGESZ_64M, 1), + 0, 3, BOOKE_PAGESZ_64M, 1),
/* - * TLB 5: 64M Cacheable, non-guarded + * TLB 4: 64M Cacheable, non-guarded * 0xf4000000 64M LBC SDRAM Second half */ SET_TLB_ENTRY(1, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, CONFIG_SYS_LBC_SDRAM_BASE + 0x4000000, MAS3_SX|MAS3_SW|MAS3_SR, 0, - 0, 5, BOOKE_PAGESZ_64M, 1), + 0, 4, BOOKE_PAGESZ_64M, 1),
/* - * TLB 6: 16M Cacheable, non-guarded + * TLB 5: 16M Cacheable, non-guarded * 0xf8000000 1M 7-segment LED display * 0xf8100000 1M User switches * 0xf8300000 1M Board revision @@ -110,24 +100,24 @@ struct fsl_e_tlb_entry tlb_table[] = { */ SET_TLB_ENTRY(1, CONFIG_SYS_EPLD_BASE, CONFIG_SYS_EPLD_BASE, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 6, BOOKE_PAGESZ_16M, 1), + 0, 5, BOOKE_PAGESZ_16M, 1),
/* - * TLB 7: 4M Non-cacheable, guarded + * TLB 6: 4M Non-cacheable, guarded * 0xfb800000 4M 1st 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH, CONFIG_SYS_ALT_FLASH, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 7, BOOKE_PAGESZ_4M, 1), + 0, 6, BOOKE_PAGESZ_4M, 1),
/* - * TLB 8: 4M Non-cacheable, guarded + * TLB 7: 4M Non-cacheable, guarded * 0xfbc00000 4M 2nd 4MB block of 64MB user FLASH */ SET_TLB_ENTRY(1, CONFIG_SYS_ALT_FLASH + 0x400000, CONFIG_SYS_ALT_FLASH + 0x400000, MAS3_SX|MAS3_SW|MAS3_SR, MAS2_I|MAS2_G, - 0, 8, BOOKE_PAGESZ_4M, 1), + 0, 7, BOOKE_PAGESZ_4M, 1),
};
diff --git a/board/sbc8560/sbc8560.c b/board/sbc8560/sbc8560.c index 77abde5..53278d3 100644 --- a/board/sbc8560/sbc8560.c +++ b/board/sbc8560/sbc8560.c @@ -38,8 +38,6 @@ #include <libfdt.h> #include <fdt_support.h>
-long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -263,95 +261,6 @@ int checkboard (void) }
-phys_size_t initdram (int board_type) -{ - long dram_size = 0; - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) - volatile fsl_lbc_t *lbc = LBC_BASE_ADDR; - sys_info_t sysinfo; - uint temp_lbcdll = 0; -#endif -#endif /* 0 */ -#if !defined(CONFIG_RAM_AS_FLASH) || defined(CONFIG_DDR_DLL) - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); -#endif -#if defined(CONFIG_DDR_DLL) - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); -#endif - -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram (); -#endif - -#if 0 -#if !defined(CONFIG_RAM_AS_FLASH) /* LocalBus SDRAM is not emulating flash */ - get_sys_info(&sysinfo); - /* if localbus freq is less than 66MHz,we use bypass mode,otherwise use DLL */ - if(sysinfo.freqSystemBus/(CONFIG_SYS_LBC_LCRR & 0x0f) < 66000000) { - lbc->lcrr = (CONFIG_SYS_LBC_LCRR & 0x0fffffff)| 0x80000000; - } else { -#if defined(CONFIG_MPC85xx_REV1) /* need change CLKDIV before enable DLL */ - lbc->lcrr = 0x10000004; /* default CLKDIV is 8, change it to 4 temporarily */ -#endif - lbc->lcrr = CONFIG_SYS_LBC_LCRR & 0x7fffffff; - udelay(200); - temp_lbcdll = gur->lbcdllcr; - gur->lbcdllcr = ((temp_lbcdll & 0xff) << 16 ) | 0x80000000; - asm("sync;isync;msync"); - } - set_lbc_or(2, CONFIG_SYS_OR2_PRELIM); /* 64MB SDRAM */ - set_lbc_br(2, CONFIG_SYS_BR2_PRELIM); - lbc->lbcr = CONFIG_SYS_LBC_LBCR; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_1; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_2; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_3; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_4; - asm("sync"); - (unsigned int) * (ulong *)0 = 0x000000ff; - lbc->lsdmr = CONFIG_SYS_LBC_LSDMR_5; - asm("sync"); - lbc->lsrt = CONFIG_SYS_LBC_LSRT; - asm("sync"); - lbc->mrtpr = CONFIG_SYS_LBC_MRTPR; - asm("sync"); -#endif -#endif - -#if defined(CONFIG_DDR_ECC) - { - /* Initialize all of memory for ECC, then - * enable errors */ - volatile ccsr_ddr_t *ddr= (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR); - - dma_meminit(CONFIG_MEM_INIT_VALUE, dram_size); - - /* Enable errors for ECC */ - ddr->err_disable = 0x00000000; - asm("sync;isync;msync"); - } -#endif - - return dram_size; -} - - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { @@ -390,7 +299,7 @@ int testdram (void) /************************************************************************* * fixed sdram init -- doesn't use serial presence detect. ************************************************************************/ -long int fixed_sdram (void) +phys_size_t fixed_sdram(void) {
#define CONFIG_SYS_DDR_CONTROL 0xc2000000 diff --git a/board/socrates/sdram.c b/board/socrates/sdram.c index ef897b2..c8235f4 100644 --- a/board/socrates/sdram.c +++ b/board/socrates/sdram.c @@ -39,7 +39,7 @@ * so this should be extended for other future boards * using this routine! */ -long int fixed_sdram(void) +phys_size_t fixed_sdram(void) { volatile ccsr_ddr_t *ddr = (void *)(CONFIG_SYS_MPC85xx_DDR_ADDR);
@@ -77,19 +77,6 @@ long int fixed_sdram(void) } #endif
-phys_size_t initdram (int board_type) -{ - long dram_size = 0; -#if defined(CONFIG_SPD_EEPROM) - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#else - dram_size = fixed_sdram(); -#endif - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/stx/stxgp3/stxgp3.c b/board/stx/stxgp3/stxgp3.c index 25d5211..63068a5 100644 --- a/board/stx/stxgp3/stxgp3.c +++ b/board/stx/stxgp3/stxgp3.c @@ -40,8 +40,6 @@ #include <spd_sdram.h> #include <miiphy.h>
-long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -277,36 +275,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} -
#if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) diff --git a/board/stx/stxssa/stxssa.c b/board/stx/stxssa/stxssa.c index 1e0acab..a630cc8 100644 --- a/board/stx/stxssa/stxssa.c +++ b/board/stx/stxssa/stxssa.c @@ -41,8 +41,6 @@ #include <miiphy.h> #include <netdev.h>
-long int fixed_sdram (void); - /* * I/O Port configuration table * @@ -294,37 +292,6 @@ show_activity(int flag) next_led_update += (get_tbclk() / 4); }
-phys_size_t -initdram (int board_type) -{ - long dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - uint temp_ddrdll = 0; - - /* Work around to stabilize DDR DLL */ - temp_ddrdll = gur->ddrdllcr; - gur->ddrdllcr = ((temp_ddrdll & 0xff) << 16) | 0x80000000; - asm("sync;isync;msync"); - } -#endif - - dram_size = fsl_ddr_sdram(); - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; - -#if defined(CONFIG_DDR_ECC) - /* Initialize and enable DDR ECC. - */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} - - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/sdram.c b/board/tqc/tqm85xx/sdram.c index 260cd1c..b2d3185 100644 --- a/board/tqc/tqm85xx/sdram.c +++ b/board/tqc/tqm85xx/sdram.c @@ -394,43 +394,6 @@ static phys_size_t sdram_setup(int casl) return (i < N_DDR_CS_CONF) ? ddr_cs_conf[i].size : 0; }
-phys_size_t initdram (int board_type) -{ - phys_size_t dram_size = 0; - -#if defined(CONFIG_DDR_DLL) - /* - * This DLL-Override only used on TQM8540 and TQM8560 - */ - { - volatile ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); - int i, x; - - x = 10; - - /* - * Work around to stabilize DDR DLL - */ - gur->ddrdllcr = 0x81000000; - asm ("sync; isync; msync"); - udelay (200); - while (gur->ddrdllcr != 0x81000100) { - gur->devdisr = gur->devdisr | 0x00010000; - asm ("sync; isync; msync"); - for (i = 0; i < x; i++) - ; - gur->devdisr = gur->devdisr & 0xfff7ffff; - asm ("sync; isync; msync"); - x++; - } - } -#endif - - dram_size = fixed_sdram(); - - return dram_size; -} - #if defined(CONFIG_SYS_DRAM_TEST) int testdram (void) { diff --git a/board/tqc/tqm85xx/tlb.c b/board/tqc/tqm85xx/tlb.c index 75dd348..f9f8cc9 100644 --- a/board/tqc/tqm85xx/tlb.c +++ b/board/tqc/tqm85xx/tlb.c @@ -120,36 +120,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 6, BOOKE_PAGESZ_64M, 1), - -#if defined(CONFIG_TQM8548_AG) || defined (CONFIG_TQM8548_BE) - /* - * TLB 7+8: 2G DDR, cache enabled - * 0x00000000 2G DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 7, BOOKE_PAGESZ_1G, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x40000000, - MAS3_SX | MAS3_SW | MAS3_SR, 0, - 0, 8, BOOKE_PAGESZ_1G, 1), -#else - /* - * TLB 7+8: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 7, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), -#endif #ifdef CONFIG_PCIE1 /* * TLB 9: 16M Non-cacheable, guarded @@ -228,23 +198,6 @@ struct fsl_e_tlb_entry tlb_table[] = { SET_TLB_ENTRY (1, CONFIG_SYS_CCSRBAR, CONFIG_SYS_CCSRBAR_PHYS, MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, 0, 7, BOOKE_PAGESZ_64M, 1), - - /* - * TLB 8+9: 512M DDR, cache disabled (needed for memory test) - * 0x00000000 512M DDR System memory - * Without SPD EEPROM configured DDR, this must be setup manually. - * Make sure the TLB count at the top of this table is correct. - * Likely it needs to be increased by two for these entries. - */ - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE, CONFIG_SYS_DDR_SDRAM_BASE, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 8, BOOKE_PAGESZ_256M, 1), - - SET_TLB_ENTRY (1, CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - CONFIG_SYS_DDR_SDRAM_BASE + 0x10000000, - MAS3_SX | MAS3_SW | MAS3_SR, MAS2_I | MAS2_G, - 0, 9, BOOKE_PAGESZ_256M, 1), - #ifdef CONFIG_PCIE1 /* * TLB 10: 16M Non-cacheable, guarded diff --git a/board/xes/common/Makefile b/board/xes/common/Makefile index 7604f62..39d105f 100644 --- a/board/xes/common/Makefile +++ b/board/xes/common/Makefile @@ -33,8 +33,6 @@ COBJS-$(CONFIG_FSL_PCI_INIT) += fsl_8xxx_pci.o COBJS-$(CONFIG_MPC8572) += fsl_8xxx_clk.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_clk.o COBJS-$(CONFIG_P2020) += fsl_8xxx_clk.o -COBJS-$(CONFIG_FSL_DDR2) += fsl_8xxx_ddr.o -COBJS-$(CONFIG_FSL_DDR3) += fsl_8xxx_ddr.o COBJS-$(CONFIG_MPC85xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_MPC86xx) += fsl_8xxx_misc.o board.o COBJS-$(CONFIG_NAND_ACTL) += actl_nand.o diff --git a/board/xes/common/fsl_8xxx_ddr.c b/board/xes/common/fsl_8xxx_ddr.c deleted file mode 100644 index 81ee70d..0000000 --- a/board/xes/common/fsl_8xxx_ddr.c +++ /dev/null @@ -1,46 +0,0 @@ -/* - * Copyright 2008 Extreme Engineering Solutions, Inc. - * - * See file CREDITS for list of people who contributed to this - * project. - * - * This program is free software; you can redistribute it and/or - * modify it under the terms of the GNU General Public License as - * published by the Free Software Foundation; either version 2 of - * the License, or (at your option) any later version. - * - * This program is distributed in the hope that it will be useful, - * but WITHOUT ANY WARRANTY; without even the implied warranty of - * MERCHANTABILITY or FITNESS FOR A PARTICULAR PURPOSE. See the - * GNU General Public License for more details. - * - * You should have received a copy of the GNU General Public License - * along with this program; if not, write to the Free Software - * Foundation, Inc., 59 Temple Place, Suite 330, Boston, - * MA 02111-1307 USA - */ - -#include <common.h> -#include <asm/fsl_ddr_sdram.h> -#include <asm/mmu.h> - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) -extern void ddr_enable_ecc(unsigned int dram_size); -#endif - -phys_size_t initdram(int board_type) -{ - phys_size_t dram_size = fsl_ddr_sdram(); - -#ifdef CONFIG_MPC85xx - dram_size = setup_ddr_tlbs(dram_size / 0x100000); - dram_size *= 0x100000; -#endif - -#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) - /* Initialize and enable DDR ECC */ - ddr_enable_ecc(dram_size); -#endif - - return dram_size; -} diff --git a/board/xes/xpedite517x/xpedite517x.c b/board/xes/xpedite517x/xpedite517x.c index 0f7fa6c..572a908 100644 --- a/board/xes/xpedite517x/xpedite517x.c +++ b/board/xes/xpedite517x/xpedite517x.c @@ -22,6 +22,7 @@
#include <common.h> #include <asm/processor.h> +#include <asm/fsl_ddr_sdram.h> #include <asm/mmu.h> #include <asm/io.h> #include <fdt_support.h> @@ -71,6 +72,18 @@ int board_early_init_r(void) return 0; }
+phys_size_t initdram(int board_type) +{ + phys_size_t dram_size = fsl_ddr_sdram(); + +#if defined(CONFIG_DDR_ECC) && !defined(CONFIG_ECC_INIT_VIA_DDRCONTROLLER) + /* Initialize and enable DDR ECC */ + ddr_enable_ecc(dram_size); +#endif + + return dram_size; +} + #if defined(CONFIG_OF_BOARD_SETUP) void ft_board_setup(void *blob, bd_t *bd) { diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index 890d6d9..d8f43d7 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -147,6 +147,10 @@ * DDR Setup */ #define CONFIG_SYS_DDR_SDRAM_BASE 0x00000000 /* DDR is system memory */ +#if defined(CONFIG_TQM_BIGFLASH) || \ + (!defined(CONFIG_TQM8548_AG) && !defined(CONFIG_TQM8548_BE)) +#define CONFIG_DDR_TLB_WIMGE (MAS2_I | MAS2_G) +#endif #define CONFIG_SYS_SDRAM_BASE CONFIG_SYS_DDR_SDRAM_BASE #ifdef CONFIG_TQM8548_AG #define CONFIG_VERY_BIG_RAM
This config option is for an erratum workaround; rename it to be more clear. Also, drop it from config files don't need it and were undefining it.
Signed-off-by: Becky Bruce beckyb@kernel.crashing.org --- arch/powerpc/cpu/mpc85xx/cmd_errata.c | 3 +++ arch/powerpc/cpu/mpc85xx/cpu.c | 2 +- doc/README.mpc85xxads | 4 ++-- include/configs/MPC8536DS.h | 1 - include/configs/MPC8540EVAL.h | 2 +- include/configs/MPC8548CDS.h | 2 +- include/configs/MPC8572DS.h | 1 - include/configs/P1_P2_RDB.h | 1 - include/configs/PM854.h | 2 +- include/configs/PM856.h | 2 +- include/configs/SBC8540.h | 2 +- include/configs/TQM85xx.h | 2 +- include/configs/sbc8560.h | 2 +- include/configs/stxgp3.h | 2 +- include/configs/stxssa.h | 1 - 15 files changed, 14 insertions(+), 15 deletions(-)
diff --git a/arch/powerpc/cpu/mpc85xx/cmd_errata.c b/arch/powerpc/cpu/mpc85xx/cmd_errata.c index d73f3d7..2d32532 100644 --- a/arch/powerpc/cpu/mpc85xx/cmd_errata.c +++ b/arch/powerpc/cpu/mpc85xx/cmd_errata.c @@ -47,6 +47,9 @@ static int do_errata(cmd_tbl_t *cmdtp, int flag, int argc, char * const argv[]) #if defined(CONFIG_SYS_P4080_ERRATUM_CPU22) puts("Work-around for Erratum CPU22 enabled\n"); #endif +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) + puts("Work-around for DDR MSYNC_IN Erratum enabled\n"); +#endif return 0; }
diff --git a/arch/powerpc/cpu/mpc85xx/cpu.c b/arch/powerpc/cpu/mpc85xx/cpu.c index f242baf..f15daa3 100644 --- a/arch/powerpc/cpu/mpc85xx/cpu.c +++ b/arch/powerpc/cpu/mpc85xx/cpu.c @@ -295,7 +295,7 @@ phys_size_t initdram(int board_type)
puts("Initializing\n");
-#if defined(CONFIG_DDR_DLL) +#if defined(CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN) { ccsr_gur_t *gur = (void *)(CONFIG_SYS_MPC85xx_GUTS_ADDR); unsigned int x = 10; diff --git a/doc/README.mpc85xxads b/doc/README.mpc85xxads index 046f981..d059a97 100644 --- a/doc/README.mpc85xxads +++ b/doc/README.mpc85xxads @@ -144,8 +144,8 @@ Updated 13-July-2004 Jon Loeliger also manual config the DDR after undef this definition. CONFIG_DDR_ECC only for ECC DDR module - CONFIG_DDR_DLL DLL fix on some ADS boards needed for more - stability. + CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN DLL fix on some ADS boards needed + for more stability. CONFIG_HAS_FEC If an FEC is on chip, set to 1, else 0.
Other than the above definitions, the rest in the config files are diff --git a/include/configs/MPC8536DS.h b/include/configs/MPC8536DS.h index 850665a..774c59f 100644 --- a/include/configs/MPC8536DS.h +++ b/include/configs/MPC8536DS.h @@ -145,7 +145,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8540EVAL.h b/include/configs/MPC8540EVAL.h index a968949..073241b 100644 --- a/include/configs/MPC8540EVAL.h +++ b/include/configs/MPC8540EVAL.h @@ -122,7 +122,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ #undef CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ diff --git a/include/configs/MPC8548CDS.h b/include/configs/MPC8548CDS.h index b221a5c..e5ac3a9 100644 --- a/include/configs/MPC8548CDS.h +++ b/include/configs/MPC8548CDS.h @@ -89,7 +89,7 @@ extern unsigned long get_clock_freq(void); #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup*/ #define CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER /* DDR controller or DMA? */ #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/MPC8572DS.h b/include/configs/MPC8572DS.h index 692c811..1373f26 100644 --- a/include/configs/MPC8572DS.h +++ b/include/configs/MPC8572DS.h @@ -99,7 +99,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #define CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #define CONFIG_DDR_SPD -#undef CONFIG_DDR_DLL
#define CONFIG_ECC_INIT_VIA_DDRCONTROLLER #define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/P1_P2_RDB.h b/include/configs/P1_P2_RDB.h index 610f3ed..cf9702a 100644 --- a/include/configs/P1_P2_RDB.h +++ b/include/configs/P1_P2_RDB.h @@ -146,7 +146,6 @@ extern unsigned long get_board_sys_clk(unsigned long dummy); #define CONFIG_FSL_DDR2 #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ -#undef CONFIG_DDR_DLL
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
diff --git a/include/configs/PM854.h b/include/configs/PM854.h index 39283b2..559dcfa 100644 --- a/include/configs/PM854.h +++ b/include/configs/PM854.h @@ -96,7 +96,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
diff --git a/include/configs/PM856.h b/include/configs/PM856.h index dbce6c4..5727ec8 100644 --- a/include/configs/PM856.h +++ b/include/configs/PM856.h @@ -98,7 +98,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE #undef CONFIG_SPD_EEPROM /* Use SPD EEPROM for DDR setup */ #undef CONFIG_DDR_SPD -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_ECC /* only for ECC DDR module */ #define CONFIG_FSL_DMA /* use DMA to init DDR ECC */
diff --git a/include/configs/SBC8540.h b/include/configs/SBC8540.h index 7c1d0bd..df3a883 100644 --- a/include/configs/SBC8540.h +++ b/include/configs/SBC8540.h @@ -118,7 +118,7 @@ #undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/TQM85xx.h b/include/configs/TQM85xx.h index d8f43d7..1368a48 100644 --- a/include/configs/TQM85xx.h +++ b/include/configs/TQM85xx.h @@ -162,7 +162,7 @@
#if defined(CONFIG_TQM8540) || defined(CONFIG_TQM8560) /* TQM8540 & 8560 need DLL-override */ -#define CONFIG_DDR_DLL /* DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_DEFAULT_CL 25 /* CAS latency 2,5 */ #endif /* CONFIG_TQM8540 || CONFIG_TQM8560 */
diff --git a/include/configs/sbc8560.h b/include/configs/sbc8560.h index 65d8eba..c70c789 100644 --- a/include/configs/sbc8560.h +++ b/include/configs/sbc8560.h @@ -116,7 +116,7 @@ #undef CONFIG_DDR_SPD
#if defined(CONFIG_MPC85xx_REV1) - #define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #endif
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ diff --git a/include/configs/stxgp3.h b/include/configs/stxgp3.h index f4cd138..92fafa9 100644 --- a/include/configs/stxgp3.h +++ b/include/configs/stxgp3.h @@ -126,7 +126,7 @@ #undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#define CONFIG_DDR_DLL /* possible DLL fix needed */ +#define CONFIG_SYS_FSL_ERRATUM_DDR_MSYNC_IN /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef diff --git a/include/configs/stxssa.h b/include/configs/stxssa.h index 996120a..d5dd94f 100644 --- a/include/configs/stxssa.h +++ b/include/configs/stxssa.h @@ -135,7 +135,6 @@ #undef CONFIG_FSL_DDR_INTERACTIVE
#undef CONFIG_DDR_ECC /* only for ECC DDR module */ -#undef CONFIG_DDR_DLL /* possible DLL fix needed */ #define CONFIG_DDR_2T_TIMING /* Sets the 2T timing bit */
#define CONFIG_MEM_INIT_VALUE 0xDeadBeef
Hi Becky,
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{
- phys_size_t dram_size = 0;
- puts("Initializing\n");
Any chance we can remove the puts() above? "DRAM:" is always printed out directly before initdram is called, so I don't think the "Initializing" message adds much benefit and slightly dirties the output. For reference:
I2C: ready DRAM: Initializing DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC on) FLASH: Executed from FLASH1 FLASH: 256 MiB
vs
I2C: ready DRAM: DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC on) FLASH: Executed from FLASH1 FLASH: 256 MiB
Otherwise it looked good. I tested on the xpedite5170 that was a corner case, and the xpedite5370 (mpc8572-based).
Acked-by: Peter Tyser ptyser@xes-inc.com Tested-by: Peter Tyser ptyser@xes-inc.com
On Dec 2, 2010, at 8:26 PM, Peter Tyser wrote:
Hi Becky,
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{
- phys_size_t dram_size = 0;
- puts("Initializing\n");
Any chance we can remove the puts() above? "DRAM:" is always printed out directly before initdram is called, so I don't think the "Initializing" message adds much benefit and slightly dirties the output. For reference:
That's fine with me.... does anybody object to this? It's certainly easy to change this now.
-Becky
I2C: ready DRAM: Initializing DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC on) FLASH: Executed from FLASH1 FLASH: 256 MiB
vs
I2C: ready DRAM: DDR: 2 GiB (DDR2, 64-bit, CL=5, ECC on) FLASH: Executed from FLASH1 FLASH: 256 MiB
Otherwise it looked good. I tested on the xpedite5170 that was a corner case, and the xpedite5370 (mpc8572-based).
Acked-by: Peter Tyser ptyser@xes-inc.com Tested-by: Peter Tyser ptyser@xes-inc.com
On Fri, 2010-12-03 at 14:54 -0600, Becky Bruce wrote:
On Dec 2, 2010, at 8:26 PM, Peter Tyser wrote:
Hi Becky,
+/* Common ddr init for non-corenet fsl 85xx platforms */ +#ifndef CONFIG_FSL_CORENET +phys_size_t initdram(int board_type) +{
- phys_size_t dram_size = 0;
- puts("Initializing\n");
Any chance we can remove the puts() above? "DRAM:" is always printed out directly before initdram is called, so I don't think the "Initializing" message adds much benefit and slightly dirties the output. For reference:
That's fine with me.... does anybody object to this? It's certainly easy to change this now.
I just noticed it now, but I'd also be in favor of getting rid of the "DDR:" puts() at the end of initdram(). It doesn't add much value since the specific DDR type is already printed out in board_add_ram_info().
Best, Peter
On Thu, Dec 2, 2010 at 5:45 PM, Becky Bruce beckyb@kernel.crashing.org wrote:
This is for boards that use the SDRAM mode on the LBC but don't require any additional setup.
I'm merging all the initdram() calls into a single function for 85xx, and have to be able to distinguish between boards that require an sdram_init() function, and those that do not. We could have defined an empty sdram_init() but I hate doing that.
Would a weak function be a better way to do this?
On Dec 2, 2010, at 8:26 PM, Timur Tabi wrote:
On Thu, Dec 2, 2010 at 5:45 PM, Becky Bruce beckyb@kernel.crashing.org wrote:
This is for boards that use the SDRAM mode on the LBC but don't require any additional setup.
I'm merging all the initdram() calls into a single function for 85xx, and have to be able to distinguish between boards that require an sdram_init() function, and those that do not. We could have defined an empty sdram_init() but I hate doing that.
Would a weak function be a better way to do this?
Eeney meeney meiney mo..... If the peanut gallery prefers, I can go that way. I don't actually like either solution very much.
-B
On Dec 3, 2010, at 2:44 PM, Becky Bruce wrote:
On Dec 2, 2010, at 8:26 PM, Timur Tabi wrote:
On Thu, Dec 2, 2010 at 5:45 PM, Becky Bruce beckyb@kernel.crashing.org wrote:
This is for boards that use the SDRAM mode on the LBC but don't require any additional setup.
I'm merging all the initdram() calls into a single function for 85xx, and have to be able to distinguish between boards that require an sdram_init() function, and those that do not. We could have defined an empty sdram_init() but I hate doing that.
Would a weak function be a better way to do this?
Eeney meeney meiney mo..... If the peanut gallery prefers, I can go that way. I don't actually like either solution very much.
I'd prefer reduce the number of #defines
- k
participants (4)
-
Becky Bruce -
Kumar Gala -
Peter Tyser -
Timur Tabi