The following build warning is seen in tables.c:

warning: implicit declaration of function 'memalign'

Add the missing header file to fix it.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/lib/tables.c | 1 + 1 file changed, 1 insertion(+)

diff --git a/arch/x86/lib/tables.c b/arch/x86/lib/tables.c index a156f2c..1213a9c 100644 --- a/arch/x86/lib/tables.c +++ b/arch/x86/lib/tables.c @@ -5,6 +5,7 @@ */

#include <common.h> +#include <malloc.h> #include <asm/sfi.h> #include <asm/mpspec.h> #include <asm/smbios.h>

Reserve IRQ9 which is to be used as SCI interrupt number for ACPI in PIC mode.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/cpu/irq.c | 4 ++++ 1 file changed, 4 insertions(+)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index 2950783..ae90b0c 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -120,6 +120,10 @@ static int create_pirq_routing_table(struct udevice *dev)

priv->irq_mask = fdtdec_get_int(blob, node, "intel,pirq-mask", PIRQ_BITMAP); +#ifdef CONFIG_GENERATE_ACPI_TABLE + /* Reserve IRQ9 for SCI */ + priv->irq_mask &= ~(1 << 9); +#endif

if (priv->config == PIRQ_VIA_IBASE) { int ibase_off;

By default SCI is disabled after power on. ACTL is the register to enable SCI and route it to PIC/APIC. To support both ACPI in PIC mode and APIC mode, configure SCI to use IRQ9.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/cpu/irq.c | 25 ++++++++++++++++++++++ arch/x86/include/asm/irq.h | 4 ++++ doc/device-tree-bindings/misc/intel,irq-router.txt | 5 +++++ 3 files changed, 34 insertions(+)

diff --git a/arch/x86/cpu/irq.c b/arch/x86/cpu/irq.c index ae90b0c..487ac23 100644 --- a/arch/x86/cpu/irq.c +++ b/arch/x86/cpu/irq.c @@ -146,6 +146,9 @@ static int create_pirq_routing_table(struct udevice *dev) priv->ibase &= ~0xf; }

+ priv->actl_8bit = fdtdec_get_bool(blob, node, "intel,actl-8bit"); + priv->actl_addr = fdtdec_get_int(blob, node, "intel,actl-addr", 0); + cell = fdt_getprop(blob, node, "intel,pirq-routing", &len); if (!cell || len % sizeof(struct pirq_routing)) return -EINVAL; @@ -215,6 +218,24 @@ static int create_pirq_routing_table(struct udevice *dev) return 0; }

+#ifdef CONFIG_GENERATE_ACPI_TABLE +static void irq_enable_sci(struct udevice *dev) +{ + struct irq_router *priv = dev_get_priv(dev); + + if (priv->actl_8bit) { + /* Bit7 must be turned on to enable ACPI */ + dm_pci_write_config8(dev->parent, priv->actl_addr, 0x80); + } else { + /* Write 0 to enable SCI on IRQ9 */ + if (priv->config == PIRQ_VIA_PCI) + dm_pci_write_config32(dev->parent, priv->actl_addr, 0); + else + writel(0, priv->ibase + priv->actl_addr); + } +} +#endif + int irq_router_common_init(struct udevice *dev) { int ret; @@ -228,6 +249,10 @@ int irq_router_common_init(struct udevice *dev) pirq_route_irqs(dev, pirq_routing_table->slots, get_irq_slot_count(pirq_routing_table));

+#ifdef CONFIG_GENERATE_ACPI_TABLE + irq_enable_sci(dev); +#endif + return 0; }

diff --git a/arch/x86/include/asm/irq.h b/arch/x86/include/asm/irq.h index 5b9e673..ddb529e 100644 --- a/arch/x86/include/asm/irq.h +++ b/arch/x86/include/asm/irq.h @@ -34,6 +34,8 @@ enum pirq_config { * IRQ N is available to be routed * @lb_bdf: irq router's PCI bus/device/function number encoding * @ibase: IBASE register block base address + * @actl_8bit: ACTL register width is 8-bit (for ICH series chipset) + * @actl_addr: ACTL register offset */ struct irq_router { int config; @@ -41,6 +43,8 @@ struct irq_router { u16 irq_mask; u32 bdf; u32 ibase; + bool actl_8bit; + int actl_addr; };

struct pirq_routing { diff --git a/doc/device-tree-bindings/misc/intel,irq-router.txt b/doc/device-tree-bindings/misc/intel,irq-router.txt index e4d8ead..04ad346 100644 --- a/doc/device-tree-bindings/misc/intel,irq-router.txt +++ b/doc/device-tree-bindings/misc/intel,irq-router.txt @@ -14,6 +14,11 @@ Required properties : "ibase": IRQ routing is in the memory-mapped IBASE register block - intel,ibase-offset : IBASE register offset in the interrupt router's PCI configuration space, required only if intel,pirq-config = "ibase". +- intel,actl-8bit : If ACTL (ACPI control) register width is 8-bit, this must + be specified. The 8-bit ACTL register is seen on ICH series chipset, like + ICH9/Panther Point/etc. On Atom chipset it is a 32-bit register. +- intel,actl-addr : ACTL (ACPI control) register offset. ACTL can be either + in the interrupt router's PCI configuration space, or IBASE. - intel,pirq-link : Specifies the PIRQ link information with two cells. The first cell is the register offset that controls the first PIRQ link routing. The second cell is the total number of PIRQ links the router supports.

Currently when compiling U-Boot with ASL file, the build log says:

ASL board/intel/bayleybay/dsdt.c

This looks odd as ASL compiler's input is ASL file, not C file. Change the make rule to use $< instead.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index ad1d9b5..4f882f1 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -323,7 +323,7 @@ $(obj)/%.S: $(src)/%.ttf

# ACPI # --------------------------------------------------------------------------- -quiet_cmd_acpi_c_asl= ASL $@ +quiet_cmd_acpi_c_asl= ASL $< cmd_acpi_c_asl= \ $(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \ iasl -p $< -tc -va $<.tmp; \

It will be much easier if we split the whole dsdt.asl file into multiple smaller ASL parts and have access to U-Boot include files.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

scripts/Makefile.lib | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/scripts/Makefile.lib b/scripts/Makefile.lib index 85b5819..5f0b050 100644 --- a/scripts/Makefile.lib +++ b/scripts/Makefile.lib @@ -325,7 +325,7 @@ $(obj)/%.S: $(src)/%.ttf # --------------------------------------------------------------------------- quiet_cmd_acpi_c_asl= ASL $< cmd_acpi_c_asl= \ - $(CPP) -x assembler-with-cpp -P -o $<.tmp $<; \ + $(CPP) -x assembler-with-cpp -P $(UBOOTINCLUDE) -o $<.tmp $<; \ iasl -p $< -tc -va $<.tmp; \ mv $(patsubst %.asl,%.hex,$<) $@

- Remove #include <> header files. - Remove APM_CNT register defines, which should not be here as they are SMI related. - Remove MP_IRQ_ defines as they are duplicates of the same ones in asm/mpspec.h. - Remove ACTL register defines, which should not be here as they are chipset specific. - Remove functional fixed hardware defines, which are not used. - Remove dev_scope related defines, which are not used.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/include/asm/acpi_table.h | 68 --------------------------------------- 1 file changed, 68 deletions(-)

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index 9856fa6..e82752a 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -6,11 +6,6 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#include <common.h> -#include <malloc.h> -#include <asm/post.h> -#include <linux/string.h> - #define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ #define ACPI_TABLE_CREATOR "UBOOT " /* Must be 8 bytes long! */ #define OEM_ID "UBOOT " /* Must be 6 bytes long! */ @@ -19,42 +14,6 @@ #define OEM_REVISION 42 #define ASL_COMPILER_REVISION 42

-/* IO ports to generate SMIs */ -#define APM_CNT 0xb2 -#define APM_CNT_CST_CONTROL 0x85 -#define APM_CNT_PST_CONTROL 0x80 -#define APM_CNT_ACPI_DISABLE 0x1e -#define APM_CNT_ACPI_ENABLE 0xe1 -#define APM_CNT_MBI_UPDATE 0xeb -#define APM_CNT_GNVS_UPDATE 0xea -#define APM_CNT_FINALIZE 0xcb -#define APM_CNT_LEGACY 0xcc -#define APM_ST 0xb3 - -/* Multiple Processor Interrupts */ -#define MP_IRQ_POLARITY_DEFAULT 0x0 -#define MP_IRQ_POLARITY_HIGH 0x1 -#define MP_IRQ_POLARITY_LOW 0x3 -#define MP_IRQ_POLARITY_MASK 0x3 -#define MP_IRQ_TRIGGER_DEFAULT 0x0 -#define MP_IRQ_TRIGGER_EDGE 0x4 -#define MP_IRQ_TRIGGER_LEVEL 0xc -#define MP_IRQ_TRIGGER_MASK 0xc - -/* - * Interrupt assigned for SCI in order to - * create the ACPI MADT IRQ override entry - */ -#define ACTL 0x00 -#define SCIS_MASK 0x07 -#define SCIS_IRQ9 0x00 -#define SCIS_IRQ10 0x01 -#define SCIS_IRQ11 0x02 -#define SCIS_IRQ20 0x04 -#define SCIS_IRQ21 0x05 -#define SCIS_IRQ22 0x06 -#define SCIS_IRQ23 0x07 - #define ACPI_REV_ACPI_1_0 1 #define ACPI_REV_ACPI_2_0 1 #define ACPI_REV_ACPI_3_0 2 @@ -105,14 +64,6 @@ enum acpi_address_space_type { ACPI_ADDRESS_SPACE_FIXED = 0x7f /* Functional fixed hardware */ };

-/* functional fixed hardware */ -#define ACPI_FFIXEDHW_VENDOR_INTEL 1 /* Intel */ -#define ACPI_FFIXEDHW_CLASS_HLT 0 /* C1 Halt */ -#define ACPI_FFIXEDHW_CLASS_IO_HLT 1 /* C1 I/O then Halt */ -#define ACPI_FFIXEDHW_CLASS_MWAIT 2 /* MWAIT Native C-state */ -#define ACPI_FFIXEDHW_FLAG_HW_COORD 1 /* Hardware Coordination bit */ -#define ACPI_FFIXEDHW_FLAG_BM_STS 2 /* BM_STS avoidance bit */ - /* Access size definitions for Generic address structure */ enum acpi_address_space_size { ACPI_ACCESS_SIZE_UNDEFINED = 0, /* Undefined (legacy reasons) */ @@ -172,25 +123,6 @@ struct acpi_madt { u32 flags; /* Multiple APIC flags */ } acpi_madt_t;

-enum dev_scope_type { - SCOPE_PCI_ENDPOINT = 1, - SCOPE_PCI_SUB = 2, - SCOPE_IOAPIC = 3, - SCOPE_MSI_HPET = 4 -}; - -typedef struct dev_scope { - u8 type; - u8 length; - u8 reserved[2]; - u8 enumeration; - u8 start_bus; - struct { - u8 dev; - u8 fn; - } path[0]; -} __packed dev_scope_t; - /* MADT: APIC Structure Type*/ enum acpi_apic_types { LOCALAPIC = 0, /* Processor local APIC */

- Use "U-BOOT" and "U-BOOTBL" for the OEM ID and OEM table ID. - Do not typedef acpi_header_t, instead use struct acpi_table_hader. - Use a shorter name aslc_id and aslc-revision. - Change MCFG base address to use 32-bit value pairs (_l and _h). - Apply ACPI_APIC_ prefix to MADT APIC type macros and make their names to be more readable. - Apply __packed to struct acpi_madt_irqoverride and struct acpi_madt_lapic_nmi tables, which are not naturally aligned by the compiler. - Rename model to res1 as it is reserved after ACPI spec 1.0. - Apply ACPI_ prefix to the PM profile macros and change them to enum. - Add ospm_flags to FACS structure which is defined since ACPI 4.0.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/include/asm/acpi_table.h | 72 +++++++++++++++++++++------------------ arch/x86/lib/acpi_table.c | 71 ++++++++++++++++++++------------------ 2 files changed, 75 insertions(+), 68 deletions(-)

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index e82752a..418870e 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -6,10 +6,10 @@ * SPDX-License-Identifier: GPL-2.0+ */

-#define RSDP_SIG "RSD PTR " /* RSDT pointer signature */ -#define ACPI_TABLE_CREATOR "UBOOT " /* Must be 8 bytes long! */ -#define OEM_ID "UBOOT " /* Must be 6 bytes long! */ -#define ASLC "INTL" /* Must be 4 bytes long! */ +#define RSDP_SIG "RSD PTR " /* RSDP pointer signature */ +#define OEM_ID "U-BOOT" /* U-Boot */ +#define OEM_TABLE_ID "U-BOOTBL" /* U-Boot Table */ +#define ASLC_ID "INTL" /* Intel ASL Compiler */

#define OEM_REVISION 42 #define ASL_COMPILER_REVISION 42 @@ -74,7 +74,7 @@ enum acpi_address_space_size { };

/* Generic ACPI header, provided by (almost) all tables */ -typedef struct acpi_table_header { +struct acpi_table_header { char signature[4]; /* ACPI signature (4 ASCII characters) */ u32 length; /* Table length in bytes (incl. header) */ u8 revision; /* Table version (not ACPI version!) */ @@ -82,9 +82,9 @@ typedef struct acpi_table_header { char oem_id[6]; /* OEM identification */ char oem_table_id[8]; /* OEM table identification */ u32 oem_revision; /* OEM revision number */ - char asl_compiler_id[4]; /* ASL compiler vendor ID */ - u32 asl_compiler_revision; /* ASL compiler revision number */ -} acpi_header_t; + char aslc_id[4]; /* ASL compiler vendor ID */ + u32 aslc_revision; /* ASL compiler revision number */ +};

/* A maximum number of 32 ACPI tables ought to be enough for now */ #define MAX_ACPI_TABLES 32 @@ -108,8 +108,8 @@ struct acpi_mcfg { };

struct acpi_mcfg_mmconfig { - u32 base_address; - u32 base_reserved; + u32 base_address_l; + u32 base_address_h; u16 pci_segment_group_number; u8 start_bus_number; u8 end_bus_number; @@ -125,17 +125,17 @@ struct acpi_madt {

/* MADT: APIC Structure Type*/ enum acpi_apic_types { - LOCALAPIC = 0, /* Processor local APIC */ - IOAPIC, /* I/O APIC */ - IRQSOURCEOVERRIDE, /* Interrupt source override */ - NMITYPE, /* NMI source */ - LOCALNMITYPE, /* Local APIC NMI */ - LAPICADDRESSOVERRIDE, /* Local APIC address override */ - IOSAPIC, /* I/O SAPIC */ - LOCALSAPIC, /* Local SAPIC */ - PLATFORMIRQSOURCES, /* Platform interrupt sources */ - LOCALX2SAPIC, /* Processor local x2APIC */ - LOCALX2APICNMI, /* Local x2APIC NMI */ + ACPI_APIC_LAPIC = 0, /* Processor local APIC */ + ACPI_APIC_IOAPIC, /* I/O APIC */ + ACPI_APIC_IRQ_SRC_OVERRIDE, /* Interrupt source override */ + ACPI_APIC_NMI_SRC, /* NMI source */ + ACPI_APIC_LAPIC_NMI, /* Local APIC NMI */ + ACPI_APIC_LAPIC_ADDR_OVERRIDE, /* Local APIC address override */ + ACPI_APIC_IOSAPIC, /* I/O SAPIC */ + ACPI_APIC_LSAPIC, /* Local SAPIC */ + ACPI_APIC_PLATFORM_IRQ_SRC, /* Platform interrupt sources */ + ACPI_APIC_LX2APIC, /* Processor local x2APIC */ + ACPI_APIC_LX2APIC_NMI, /* Local x2APIC NMI */ };

/* MADT: Processor Local APIC Structure */ @@ -153,7 +153,7 @@ struct acpi_madt_lapic { /* bits 1-31: reserved */

/* MADT: Local APIC NMI Structure */ -struct acpi_madt_lapic_nmi { +struct __packed acpi_madt_lapic_nmi { u8 type; /* Type (4) */ u8 length; /* Length in bytes (6) */ u8 processor_id; /* ACPI processor ID */ @@ -172,7 +172,7 @@ struct acpi_madt_ioapic { };

/* MADT: Interrupt Source Override Structure */ -struct acpi_madt_irqoverride { +struct __packed acpi_madt_irqoverride { u8 type; /* Type (2) */ u8 length; /* Length in bytes (10) */ u8 bus; /* ISA (0) */ @@ -186,7 +186,7 @@ struct __packed acpi_fadt { struct acpi_table_header header; u32 firmware_ctrl; u32 dsdt; - u8 model; + u8 res1; u8 preferred_pm_profile; u16 sci_int; u32 smi_cmd; @@ -281,15 +281,17 @@ struct __packed acpi_fadt { #define ACPI_FADT_LEGACY_FREE 0x00

/* FADT Preferred Power Management Profile */ -#define PM_UNSPECIFIED 0 -#define PM_DESKTOP 1 -#define PM_MOBILE 2 -#define PM_WORKSTATION 3 -#define PM_ENTERPRISE_SERVER 4 -#define PM_SOHO_SERVER 5 -#define PM_APPLIANCE_PC 6 -#define PM_PERFORMANCE_SERVER 7 -#define PM_TABLET 8 /* ACPI 5.0 */ +enum acpi_pm_profile { + ACPI_PM_UNSPECIFIED = 0, + ACPI_PM_DESKTOP, + ACPI_PM_MOBILE, + ACPI_PM_WORKSTATION, + ACPI_PM_ENTERPRISE_SERVER, + ACPI_PM_SOHO_SERVER, + ACPI_PM_APPLIANCE_PC, + ACPI_PM_PERFORMANCE_SERVER, + ACPI_PM_TABLET +};

/* FACS (Firmware ACPI Control Structure) */ struct acpi_facs { @@ -302,7 +304,9 @@ struct acpi_facs { u32 x_firmware_waking_vector_l; /* X FW waking vector, low */ u32 x_firmware_waking_vector_h; /* X FW waking vector, high */ u8 version; /* ACPI 4.0: 2 */ - u8 resv[31]; /* FIXME: 4.0: ospm_flags */ + u8 res1[3]; + u32 ospm_flags; /* OSPM enabled flags */ + u8 res2[24]; };

/* FACS flags */ diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 0b1775c..75fa429 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -58,7 +58,8 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) rsdt->entry[i] = (u32)table;

/* Fix RSDT length or the kernel will assume invalid entries */ - rsdt->header.length = sizeof(acpi_header_t) + (sizeof(u32) * (i + 1)); + rsdt->header.length = sizeof(struct acpi_table_header) + + (sizeof(u32) * (i + 1));

/* Re-calculate checksum */ rsdt->header.checksum = 0; @@ -74,7 +75,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) xsdt->entry[i] = (u64)(u32)table;

/* Fix XSDT length */ - xsdt->header.length = sizeof(acpi_header_t) + + xsdt->header.length = sizeof(struct acpi_table_header) + (sizeof(u64) * (i + 1));

/* Re-calculate checksum */ @@ -87,7 +88,7 @@ static void acpi_add_table(struct acpi_rsdp *rsdp, void *table) static int acpi_create_madt_lapic(struct acpi_madt_lapic *lapic, u8 cpu, u8 apic) { - lapic->type = LOCALAPIC; /* Local APIC structure */ + lapic->type = ACPI_APIC_LAPIC; /* Local APIC structure */ lapic->length = sizeof(struct acpi_madt_lapic); lapic->flags = LOCAL_APIC_FLAG_ENABLED; /* Processor/LAPIC enabled */ lapic->processor_id = cpu; @@ -115,7 +116,7 @@ unsigned long acpi_create_madt_lapics(unsigned long current) int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, u32 gsi_base) { - ioapic->type = IOAPIC; + ioapic->type = ACPI_APIC_IOAPIC; ioapic->length = sizeof(struct acpi_madt_ioapic); ioapic->reserved = 0x00; ioapic->gsi_base = gsi_base; @@ -128,7 +129,7 @@ int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, u8 bus, u8 source, u32 gsirq, u16 flags) { - irqoverride->type = IRQSOURCEOVERRIDE; + irqoverride->type = ACPI_APIC_IRQ_SRC_OVERRIDE; irqoverride->length = sizeof(struct acpi_madt_irqoverride); irqoverride->bus = bus; irqoverride->source = source; @@ -141,7 +142,7 @@ int acpi_create_madt_irqoverride(struct acpi_madt_irqoverride *irqoverride, int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, u8 cpu, u16 flags, u8 lint) { - lapic_nmi->type = LOCALNMITYPE; + lapic_nmi->type = ACPI_APIC_LAPIC_NMI; lapic_nmi->length = sizeof(struct acpi_madt_lapic_nmi); lapic_nmi->flags = flags; lapic_nmi->processor_id = cpu; @@ -150,17 +151,18 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, return lapic_nmi->length; }

-static void fill_header(acpi_header_t *header, char *signature, int length) +static void fill_header(struct acpi_table_header *header, char *signature, + int length) { memcpy(header->signature, signature, length); memcpy(header->oem_id, OEM_ID, 6); - memcpy(header->oem_table_id, ACPI_TABLE_CREATOR, 8); - memcpy(header->asl_compiler_id, ASLC, 4); + memcpy(header->oem_table_id, OEM_TABLE_ID, 8); + memcpy(header->aslc_id, ASLC_ID, 4); }

static void acpi_create_madt(struct acpi_madt *madt) { - acpi_header_t *header = &(madt->header); + struct acpi_table_header *header = &(madt->header); unsigned long current = (unsigned long)madt + sizeof(struct acpi_madt);

memset((void *)madt, 0, sizeof(struct acpi_madt)); @@ -173,7 +175,7 @@ static void acpi_create_madt(struct acpi_madt *madt) header->revision = ACPI_REV_ACPI_2_0;

madt->lapic_addr = LAPIC_DEFAULT_BASE; - madt->flags = PCAT_COMPAT; + madt->flags = ACPI_MADT_PCAT_COMPAT;

current = acpi_fill_madt(current);

@@ -187,8 +189,8 @@ static int acpi_create_mcfg_mmconfig(struct acpi_mcfg_mmconfig *mmconfig, u32 base, u16 seg_nr, u8 start, u8 end) { memset(mmconfig, 0, sizeof(*mmconfig)); - mmconfig->base_address = base; - mmconfig->base_reserved = 0; + mmconfig->base_address_l = base; + mmconfig->base_address_h = 0; mmconfig->pci_segment_group_number = seg_nr; mmconfig->start_bus_number = start; mmconfig->end_bus_number = end; @@ -208,7 +210,7 @@ static unsigned long acpi_fill_mcfg(unsigned long current) /* MCFG is defined in the PCI Firmware Specification 3.0 */ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) { - acpi_header_t *header = &(mcfg->header); + struct acpi_table_header *header = &(mcfg->header); unsigned long current = (unsigned long)mcfg + sizeof(struct acpi_mcfg);

memset((void *)mcfg, 0, sizeof(struct acpi_mcfg)); @@ -244,7 +246,7 @@ static void acpi_create_facs(struct acpi_facs *facs)

static void acpi_write_rsdt(struct acpi_rsdt *rsdt) { - acpi_header_t *header = &(rsdt->header); + struct acpi_table_header *header = &(rsdt->header);

/* Fill out header fields */ fill_header(header, "RSDT", 4); @@ -262,7 +264,7 @@ static void acpi_write_rsdt(struct acpi_rsdt *rsdt)

static void acpi_write_xsdt(struct acpi_xsdt *xsdt) { - acpi_header_t *header = &(xsdt->header); + struct acpi_table_header *header = &(xsdt->header);

/* Fill out header fields */ fill_header(header, "XSDT", 4); @@ -309,12 +311,13 @@ static void acpi_write_rsdp(struct acpi_rsdp *rsdp, struct acpi_rsdt *rsdt, sizeof(struct acpi_rsdp)); }

-static void acpi_create_ssdt_generator(acpi_header_t *ssdt, +static void acpi_create_ssdt_generator(struct acpi_table_header *ssdt, const char *oem_table_id) { - unsigned long current = (unsigned long)ssdt + sizeof(acpi_header_t); + unsigned long current = (unsigned long)ssdt + + sizeof(struct acpi_table_header);

- memset((void *)ssdt, 0, sizeof(acpi_header_t)); + memset((void *)ssdt, 0, sizeof(struct acpi_table_header));

memcpy(&ssdt->signature, "SSDT", 4); /* Access size in ACPI 2.0c/3.0/4.0/5.0 */ @@ -322,9 +325,9 @@ static void acpi_create_ssdt_generator(acpi_header_t *ssdt, memcpy(&ssdt->oem_id, OEM_ID, 6); memcpy(&ssdt->oem_table_id, oem_table_id, 8); ssdt->oem_revision = OEM_REVISION; - memcpy(&ssdt->asl_compiler_id, ASLC, 4); - ssdt->asl_compiler_revision = ASL_COMPILER_REVISION; - ssdt->length = sizeof(acpi_header_t); + memcpy(&ssdt->aslc_id, ASLC_ID, 4); + ssdt->aslc_revision = ASL_COMPILER_REVISION; + ssdt->length = sizeof(struct acpi_table_header);

/* (Re)calculate length and checksum */ ssdt->length = current - (unsigned long)ssdt; @@ -342,11 +345,11 @@ u32 write_acpi_tables(u32 start) struct acpi_rsdt *rsdt; struct acpi_xsdt *xsdt; struct acpi_facs *facs; - acpi_header_t *dsdt; + struct acpi_table_header *dsdt; struct acpi_fadt *fadt; struct acpi_mcfg *mcfg; struct acpi_madt *madt; - acpi_header_t *ssdt; + struct acpi_table_header *ssdt;

current = start;

@@ -381,14 +384,14 @@ u32 write_acpi_tables(u32 start) acpi_create_facs(facs);

debug("ACPI: * DSDT\n"); - dsdt = (acpi_header_t *)current; - memcpy(dsdt, &AmlCode, sizeof(acpi_header_t)); - if (dsdt->length >= sizeof(acpi_header_t)) { - current += sizeof(acpi_header_t); + dsdt = (struct acpi_table_header *)current; + memcpy(dsdt, &AmlCode, sizeof(struct acpi_table_header)); + if (dsdt->length >= sizeof(struct acpi_table_header)) { + current += sizeof(struct acpi_table_header); memcpy((char *)current, - (char *)&AmlCode + sizeof(acpi_header_t), - dsdt->length - sizeof(acpi_header_t)); - current += dsdt->length - sizeof(acpi_header_t); + (char *)&AmlCode + sizeof(struct acpi_table_header), + dsdt->length - sizeof(struct acpi_table_header)); + current += dsdt->length - sizeof(struct acpi_table_header);

/* (Re)calculate length and checksum */ dsdt->length = current - (unsigned long)dsdt; @@ -424,9 +427,9 @@ u32 write_acpi_tables(u32 start) current = ALIGN(current, 16);

debug("ACPI: * SSDT\n"); - ssdt = (acpi_header_t *)current; - acpi_create_ssdt_generator(ssdt, ACPI_TABLE_CREATOR); - if (ssdt->length > sizeof(acpi_header_t)) { + ssdt = (struct acpi_table_header *)current; + acpi_create_ssdt_generator(ssdt, OEM_TABLE_ID); + if (ssdt->length > sizeof(struct acpi_table_header)) { current += ssdt->length; acpi_add_table(rsdp, ssdt); current = ALIGN(current, 16);

Rename fill_header() to acpi_fill_header() for consistency. Change its signature to remove the 'length' parameter and make it a public API.

Also remove the unnecessary include files, and improve the AmlCode[] comment a little bit.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/include/asm/acpi_table.h | 1 + arch/x86/lib/acpi_table.c | 22 ++++++++-------------- 2 files changed, 9 insertions(+), 14 deletions(-)

diff --git a/arch/x86/include/asm/acpi_table.h b/arch/x86/include/asm/acpi_table.h index c6688ea..5a829de 100644 --- a/arch/x86/include/asm/acpi_table.h +++ b/arch/x86/include/asm/acpi_table.h @@ -304,6 +304,7 @@ struct acpi_mcfg_mmconfig {

/* These can be used by the target port */

+void acpi_fill_header(struct acpi_table_header *header, char *signature); unsigned long acpi_create_madt_lapics(unsigned long current); int acpi_create_madt_ioapic(struct acpi_madt_ioapic *ioapic, u8 id, u32 addr, u32 gsi_base); diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 62fe39d..97d90f7 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -10,18 +10,13 @@ #include <cpu.h> #include <dm.h> #include <dm/uclass-internal.h> -#include <dm/lists.h> #include <asm/acpi_table.h> -#include <asm/cpu.h> -#include <asm/ioapic.h> #include <asm/lapic.h> #include <asm/tables.h> -#include <asm/pci.h>

/* - * IASL compiles the dsdt entries and - * writes the hex values to AmlCode array. - * CamelCase cannot be handled here. + * IASL compiles the dsdt entries and writes the hex values + * to a C array AmlCode[] (see dsdt.c). */ extern const unsigned char AmlCode[];

@@ -151,10 +146,9 @@ int acpi_create_madt_lapic_nmi(struct acpi_madt_lapic_nmi *lapic_nmi, return lapic_nmi->length; }

-static void fill_header(struct acpi_table_header *header, char *signature, - int length) +void acpi_fill_header(struct acpi_table_header *header, char *signature) { - memcpy(header->signature, signature, length); + memcpy(header->signature, signature, 4); memcpy(header->oem_id, OEM_ID, 6); memcpy(header->oem_table_id, OEM_TABLE_ID, 8); memcpy(header->aslc_id, ASLC_ID, 4); @@ -168,7 +162,7 @@ static void acpi_create_madt(struct acpi_madt *madt) memset((void *)madt, 0, sizeof(struct acpi_madt));

/* Fill out header fields */ - fill_header(header, "APIC", 4); + acpi_fill_header(header, "APIC"); header->length = sizeof(struct acpi_madt);

/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ @@ -216,7 +210,7 @@ static void acpi_create_mcfg(struct acpi_mcfg *mcfg) memset((void *)mcfg, 0, sizeof(struct acpi_mcfg));

/* Fill out header fields */ - fill_header(header, "MCFG", 4); + acpi_fill_header(header, "MCFG"); header->length = sizeof(struct acpi_mcfg);

/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ @@ -249,7 +243,7 @@ static void acpi_write_rsdt(struct acpi_rsdt *rsdt) struct acpi_table_header *header = &(rsdt->header);

/* Fill out header fields */ - fill_header(header, "RSDT", 4); + acpi_fill_header(header, "RSDT"); header->length = sizeof(struct acpi_rsdt);

/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */ @@ -267,7 +261,7 @@ static void acpi_write_xsdt(struct acpi_xsdt *xsdt) struct acpi_table_header *header = &(xsdt->header);

/* Fill out header fields */ - fill_header(header, "XSDT", 4); + acpi_fill_header(header, "XSDT"); header->length = sizeof(struct acpi_xsdt);

/* ACPI 1.0/2.0: 1, ACPI 3.0: 2, ACPI 4.0: 3 */

Per ACPI spec, the FACS table address must be aligned to a 64 byte boundary (Windows checks this, but Linux does not).

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

arch/x86/lib/acpi_table.c | 2 +- 1 file changed, 1 insertion(+), 1 deletion(-)

diff --git a/arch/x86/lib/acpi_table.c b/arch/x86/lib/acpi_table.c index 0e43452..9f2623a 100644 --- a/arch/x86/lib/acpi_table.c +++ b/arch/x86/lib/acpi_table.c @@ -338,7 +338,7 @@ u32 write_acpi_tables(u32 start) current = ALIGN(current, 16); xsdt = (struct acpi_xsdt *)current; current += sizeof(struct acpi_xsdt); - current = ALIGN(current, 16); + current = ALIGN(current, 64);

/* clear all table memory */ memset((void *)start, 0, current - start);

This adds basic BayTrail platform ASL files. They are intended to be included in dsdt.asl of any board that is based on this platform.

Note: ACPI mode support for GPIO/LPSS/SCC/LPE are not supported for now. They will be added in the future.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

.../include/asm/arch-baytrail/acpi/irq_helper.h | 111 +++++ .../include/asm/arch-baytrail/acpi/irqlinks.asl | 489 +++++++++++++++++++++ .../include/asm/arch-baytrail/acpi/irqroute.asl | 48 ++ arch/x86/include/asm/arch-baytrail/acpi/irqroute.h | 27 ++ arch/x86/include/asm/arch-baytrail/acpi/lpc.asl | 121 +++++ .../include/asm/arch-baytrail/acpi/platform.asl | 34 ++ .../include/asm/arch-baytrail/acpi/sleepstates.asl | 13 + .../asm/arch-baytrail/acpi/southcluster.asl | 211 +++++++++ arch/x86/include/asm/arch-baytrail/acpi/usb.asl | 34 ++ arch/x86/include/asm/arch-baytrail/acpi/xhci.asl | 31 ++ arch/x86/include/asm/arch-baytrail/device.h | 74 ++++ arch/x86/include/asm/arch-baytrail/iomap.h | 70 +++ arch/x86/include/asm/arch-baytrail/irq.h | 86 ++++ 13 files changed, 1349 insertions(+) create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/irqroute.h create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/lpc.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/platform.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/usb.asl create mode 100644 arch/x86/include/asm/arch-baytrail/acpi/xhci.asl create mode 100644 arch/x86/include/asm/arch-baytrail/device.h create mode 100644 arch/x86/include/asm/arch-baytrail/iomap.h create mode 100644 arch/x86/include/asm/arch-baytrail/irq.h

diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h new file mode 100644 index 0000000..2c3585a --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/irq_helper.h @@ -0,0 +1,111 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2014 Sage Electronics Engineering, LLC. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/irq_helper.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* + * This file intentionally gets included multiple times, to set pic and apic + * modes, so should not have guard statements added. + */ + +/* + * This file will use irqroute.asl and irqroute.h to generate the ACPI IRQ + * routing for the platform being compiled. + * + * This method uses #defines in irqroute.h along with the macros contained + * in this file to generate an IRQ routing for each PCI device in the system. + */ + +#undef PCI_DEV_PIRQ_ROUTES +#undef PCI_DEV_PIRQ_ROUTE +#undef ACPI_DEV_IRQ +#undef PCIE_BRIDGE_DEV +#undef RP_IRQ_ROUTES +#undef ROOTPORT_METHODS +#undef ROOTPORT_IRQ_ROUTES +#undef RP_METHOD + +#if defined(PIC_MODE) + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, _SB.PCI0.LPCB.LNK ## pin_name_, 0 } + +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## P, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +/* define as blank so ROOTPORT_METHODS only gets inserted once */ +#define ROOTPORT_METHODS(prefix_, dev_) + +#else /* defined(PIC_MODE) */ + +#define ACPI_DEV_IRQ(dev_, pin_, pin_name_) \ + Package() { ## dev_ ## ffff, pin_, 0, PIRQ ## pin_name_ ## _APIC_IRQ } + +#define RP_IRQ_ROUTES(prefix_, func_, a_, b_, c_, d_) \ +Name(prefix_ ## func_ ## A, Package() \ +{ \ + ACPI_DEV_IRQ(0x0000, 0, a_), \ + ACPI_DEV_IRQ(0x0000, 1, b_), \ + ACPI_DEV_IRQ(0x0000, 2, c_), \ + ACPI_DEV_IRQ(0x0000, 3, d_), \ +}) + +#define ROOTPORT_METHODS(prefix_, dev_) \ + RP_METHOD(prefix_, dev_, 0) \ + RP_METHOD(prefix_, dev_, 1) \ + RP_METHOD(prefix_, dev_, 2) \ + RP_METHOD(prefix_, dev_, 3) \ + RP_METHOD(prefix_, dev_, 4) \ + RP_METHOD(prefix_, dev_, 5) \ + RP_METHOD(prefix_, dev_, 6) \ + RP_METHOD(prefix_, dev_, 7) + +#endif /* defined(PIC_MODE) */ + +#define PCI_DEV_PIRQ_ROUTE(dev_, a_, b_, c_, d_) \ + ACPI_DEV_IRQ(dev_, 0, a_), \ + ACPI_DEV_IRQ(dev_, 1, b_), \ + ACPI_DEV_IRQ(dev_, 2, c_), \ + ACPI_DEV_IRQ(dev_, 3, d_) + +#define PCIE_BRIDGE_DEV(prefix_, dev_, a_, b_, c_, d_) \ + ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + ROOTPORT_METHODS(prefix_, dev_) + +#define ROOTPORT_IRQ_ROUTES(prefix_, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 0, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 1, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 2, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 3, d_, a_, b_, c_) \ + RP_IRQ_ROUTES(prefix_, 4, a_, b_, c_, d_) \ + RP_IRQ_ROUTES(prefix_, 5, b_, c_, d_, a_) \ + RP_IRQ_ROUTES(prefix_, 6, c_, d_, a_, b_) \ + RP_IRQ_ROUTES(prefix_, 7, d_, a_, b_, c_) + +#define RP_METHOD(prefix_, dev_, func_)\ +Device (prefix_ ## 0 ## func_) \ +{ \ + Name(_ADR, dev_ ## 000 ## func_) \ + Name(_PRW, Package() { 0, 0 }) \ + Method(_PRT) { \ + If (PICM) { \ + Return (prefix_ ## func_ ## A) \ + } Else { \ + Return (prefix_ ## func_ ## P) \ + } \ + } \ +} + +/* SoC specific PIRQ route configuration */ +#include "irqroute.h" diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl new file mode 100644 index 0000000..102e982 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/irqlinks.asl @@ -0,0 +1,489 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/irqlinks.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Scope () +{ + /* Intel Legacy Block */ + OperationRegion(ILBS, SystemMemory, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Field(ILBS, AnyAcc, NoLock, Preserve) { + Offset (0x8), + PRTA, 8, + PRTB, 8, + PRTC, 8, + PRTD, 8, + PRTE, 8, + PRTF, 8, + PRTG, 8, + PRTH, 8, + } +} + +Device (LNKA) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 1) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTA) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLA, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLA, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTA */ + ShiftLeft(1, And(PRTA, 0x0f), IRQ0) + + Return (RTLA) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTA) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTA, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKB) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 2) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTB) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLB, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLB, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTB */ + ShiftLeft(1, And(PRTB, 0x0f), IRQ0) + + Return (RTLB) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTB) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTB, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKC) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 3) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTC) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLC, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLC, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTC */ + ShiftLeft(1, And(PRTC, 0x0f), IRQ0) + + Return (RTLC) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTC) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTC, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKD) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 4) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTD) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLD, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLD, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTD */ + ShiftLeft(1, And(PRTD, 0x0f), IRQ0) + + Return (RTLD) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTD) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTD, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKE) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 5) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTE) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLE, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLE, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTE */ + ShiftLeft(1, And(PRTE, 0x0f), IRQ0) + + Return (RTLE) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTE) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTE, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKF) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 6) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTF) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLF, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLF, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTF */ + ShiftLeft(1, And(PRTF, 0x0f), IRQ0) + + Return (RTLF) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTF) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTF, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKG) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 7) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTG) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 10, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLG, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLG, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTG */ + ShiftLeft(1, And(PRTG, 0x0f), IRQ0) + + Return (RTLG) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTG) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTG, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} + +Device (LNKH) +{ + Name(_HID, EISAID("PNP0C0F")) + Name(_UID, 8) + + /* Disable method */ + Method(_DIS, 0, Serialized) + { + Store(0x80, PRTH) + } + + /* Possible Resource Settings for this Link */ + Name(_PRS, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) { 3, 4, 5, 6, 7, 11, 12, 14, 15 } + }) + + /* Current Resource Settings for this link */ + Method(_CRS, 0, Serialized) + { + Name(RTLH, ResourceTemplate() + { + IRQ(Level, ActiveLow, Shared) {} + }) + CreateWordField(RTLH, 1, IRQ0) + + /* Clear the WordField */ + Store(Zero, IRQ0) + + /* Set the bit from PRTH */ + ShiftLeft(1, And(PRTH, 0x0f), IRQ0) + + Return (RTLH) + } + + /* Set Resource Setting for this IRQ link */ + Method(_SRS, 1, Serialized) + { + CreateWordField(Arg0, 1, IRQ0) + + /* Which bit is set? */ + FindSetRightBit(IRQ0, Local0) + + Decrement(Local0) + Store(Local0, PRTH) + } + + /* Status */ + Method(_STA, 0, Serialized) + { + If (And(PRTH, 0x80)) { + Return (STA_DISABLED) + } Else { + Return (STA_INVISIBLE) + } + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl new file mode 100644 index 0000000..64d3820 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.asl @@ -0,0 +1,48 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/irqroute.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name(\PICM, 0) + +/* + * The _PIC method is called by the OS to choose between interrupt + * routing via the i8259 interrupt controller or the APIC. + * + * _PIC is called with a parameter of 0 for i8259 configuration and + * with a parameter of 1 for Local APIC/IOAPIC configuration. + */ +Method(_PIC, 1) +{ + /* Remember the OS' IRQ routing choice */ + Store(Arg0, PICM) +} + +/* PCI interrupt routing */ +Method(_PRT) { + If (PICM) { + Return (Package() { + #undef PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } Else { + Return (Package() { + #define PIC_MODE + #include "irq_helper.h" + PCI_DEV_PIRQ_ROUTES + }) + } + +} + +/* PCIe downstream ports interrupt routing */ +PCIE_BRIDGE_IRQ_ROUTES +#undef PIC_MODE +#include "irq_helper.h" +PCIE_BRIDGE_IRQ_ROUTES diff --git a/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h new file mode 100644 index 0000000..924660e --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/irqroute.h @@ -0,0 +1,27 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/arch/device.h> + +#define PCI_DEV_PIRQ_ROUTES \ + PCI_DEV_PIRQ_ROUTE(GFX_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(EMMC_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SDIO_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SD_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SATA_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(XHCI_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(LPE_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(MMC45_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO1_DEV, A, C, D, B), \ + PCI_DEV_PIRQ_ROUTE(TXE_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(HDA_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(PCIE_DEV, A, B, C, D), \ + PCI_DEV_PIRQ_ROUTE(EHCI_DEV, A, A, A, A), \ + PCI_DEV_PIRQ_ROUTE(SIO2_DEV, A, D, B, C), \ + PCI_DEV_PIRQ_ROUTE(PCU_DEV, A, B, C, D) + +#define PCIE_BRIDGE_IRQ_ROUTES \ + PCIE_BRIDGE_DEV(RP, PCIE_DEV, A, B, C, D) diff --git a/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl new file mode 100644 index 0000000..b375ee6 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/lpc.asl @@ -0,0 +1,121 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/lpc.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Intel LPC Bus Device - 0:1f.0 */ + +Device (LPCB) +{ + Name(_ADR, 0x001f0000) + + #include "irqlinks.asl" + + /* Firmware Hub */ + Device (FWH) + { + Name(_HID, EISAID("INT0800")) + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, 0xff000000, 0x01000000) + }) + } + + /* 8259 Interrupt Controller */ + Device (PIC) + { + Name(_HID, EISAID("PNP0000")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x20, 0x20, 0x01, 0x02) + IO(Decode16, 0x24, 0x24, 0x01, 0x02) + IO(Decode16, 0x28, 0x28, 0x01, 0x02) + IO(Decode16, 0x2c, 0x2c, 0x01, 0x02) + IO(Decode16, 0x30, 0x30, 0x01, 0x02) + IO(Decode16, 0x34, 0x34, 0x01, 0x02) + IO(Decode16, 0x38, 0x38, 0x01, 0x02) + IO(Decode16, 0x3c, 0x3c, 0x01, 0x02) + IO(Decode16, 0xa0, 0xa0, 0x01, 0x02) + IO(Decode16, 0xa4, 0xa4, 0x01, 0x02) + IO(Decode16, 0xa8, 0xa8, 0x01, 0x02) + IO(Decode16, 0xac, 0xac, 0x01, 0x02) + IO(Decode16, 0xb0, 0xb0, 0x01, 0x02) + IO(Decode16, 0xb4, 0xb4, 0x01, 0x02) + IO(Decode16, 0xb8, 0xb8, 0x01, 0x02) + IO(Decode16, 0xbc, 0xbc, 0x01, 0x02) + IO(Decode16, 0x4d0, 0x4d0, 0x01, 0x02) + IRQNoFlags () { 2 } + }) + } + + /* 8254 timer */ + Device (TIMR) + { + Name(_HID, EISAID("PNP0100")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x40, 0x40, 0x01, 0x04) + IO(Decode16, 0x50, 0x50, 0x10, 0x04) + IRQNoFlags() { 0 } + }) + } + + /* HPET */ + Device (HPET) + { + Name(_HID, EISAID("PNP0103")) + Name(_CID, 0x010CD041) + Name(_CRS, ResourceTemplate() + { + Memory32Fixed(ReadOnly, HPET_BASE_ADDRESS, HPET_BASE_SIZE) + }) + + Method(_STA, 0) + { + Return (STA_VISIBLE) + } + } + + /* Real Time Clock */ + Device (RTC) + { + Name(_HID, EISAID("PNP0B00")) + Name(_CRS, ResourceTemplate() + { + IO(Decode16, 0x70, 0x70, 1, 8) + /* + * Disable as Windows doesn't like it, and systems + * don't seem to use it + */ + /* IRQNoFlags() { 8 } */ + }) + } + + /* LPC device: Resource consumption */ + Device (LDRC) + { + Name(_HID, EISAID("PNP0C02")) + Name(_UID, 2) + + Name(RBUF, ResourceTemplate() + { + IO(Decode16, 0x61, 0x61, 0x1, 0x01) /* NMI Status */ + IO(Decode16, 0x63, 0x63, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x65, 0x65, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x67, 0x67, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0x80, 0x80, 0x1, 0x01) /* Port 80 Post */ + IO(Decode16, 0x92, 0x92, 0x1, 0x01) /* CPU Reserved */ + IO(Decode16, 0xb2, 0xb2, 0x1, 0x02) /* SWSMI */ + }) + + Method(_CRS, 0, NotSerialized) + { + Return (RBUF) + } + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/platform.asl b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl new file mode 100644 index 0000000..f6fa53b --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/platform.asl @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#include <asm/acpi/statdef.asl> +#include <asm/arch/iomap.h> +#include <asm/arch/irq.h> + +/* + * The _PTS method (Prepare To Sleep) is called before the OS is + * entering a sleep state. The sleep state number is passed in Arg0. + */ +Method(_PTS, 1) +{ +} + +/* The _WAK method is called on system wakeup */ +Method(_WAK, 1) +{ + Return (Package() {0, 0}) +} + +/* TODO: add CPU ASL support */ +/* #include "cpu.asl" */ + +Scope (_SB) +{ + #include "southcluster.asl" +} + +/* Chipset specific sleep states */ +#include "sleepstates.asl" diff --git a/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl new file mode 100644 index 0000000..eb5ae76 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/sleepstates.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/sleepstates.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Name(_S0, Package() {0x0, 0x0, 0x0, 0x0}) +Name(_S3, Package() {0x5, 0x0, 0x0, 0x0}) +Name(_S4, Package() {0x6, 0x0, 0x0, 0x0}) +Name(_S5, Package() {0x7, 0x0, 0x0, 0x0}) diff --git a/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl new file mode 100644 index 0000000..ab5c92e --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/southcluster.asl @@ -0,0 +1,211 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/southcluster.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +Device (PCI0) +{ + Name(_HID, EISAID("PNP0A08")) /* PCIe */ + Name(_CID, EISAID("PNP0A03")) /* PCI */ + + Name(_ADR, 0) + Name(_BBN, 0) + + Name(MCRS, ResourceTemplate() + { + /* Bus Numbers */ + WordBusNumber(ResourceProducer, MinFixed, MaxFixed, PosDecode, + 0x0000, 0x0000, 0x00ff, 0x0000, 0x0100, , , PB00) + + /* IO Region 0 */ + DWordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0000, 0x0cf7, 0x0000, 0x0cf8, , , PI00) + + /* PCI Config Space */ + Io(Decode16, 0x0cf8, 0x0cf8, 0x0001, 0x0008) + + /* IO Region 1 */ + DWordIO(ResourceProducer, MinFixed, MaxFixed, PosDecode, EntireRange, + 0x0000, 0x0d00, 0xffff, 0x0000, 0xf300, , , PI01) + + /* VGA memory (0xa0000-0xbffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000a0000, 0x000bffff, 0x00000000, + 0x00020000, , , ASEG) + + /* OPROM reserved (0xc0000-0xc3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c0000, 0x000c3fff, 0x00000000, + 0x00004000, , , OPR0) + + /* OPROM reserved (0xc4000-0xc7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c4000, 0x000c7fff, 0x00000000, + 0x00004000, , , OPR1) + + /* OPROM reserved (0xc8000-0xcbfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000c8000, 0x000cbfff, 0x00000000, + 0x00004000, , , OPR2) + + /* OPROM reserved (0xcc000-0xcffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000cc000, 0x000cffff, 0x00000000, + 0x00004000, , , OPR3) + + /* OPROM reserved (0xd0000-0xd3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d0000, 0x000d3fff, 0x00000000, + 0x00004000, , , OPR4) + + /* OPROM reserved (0xd4000-0xd7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d4000, 0x000d7fff, 0x00000000, + 0x00004000, , , OPR5) + + /* OPROM reserved (0xd8000-0xdbfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000d8000, 0x000dbfff, 0x00000000, + 0x00004000, , , OPR6) + + /* OPROM reserved (0xdc000-0xdffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000dc000, 0x000dffff, 0x00000000, + 0x00004000, , , OPR7) + + /* BIOS Extension (0xe0000-0xe3fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e0000, 0x000e3fff, 0x00000000, + 0x00004000, , , ESG0) + + /* BIOS Extension (0xe4000-0xe7fff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e4000, 0x000e7fff, 0x00000000, + 0x00004000, , , ESG1) + + /* BIOS Extension (0xe8000-0xebfff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000e8000, 0x000ebfff, 0x00000000, + 0x00004000, , , ESG2) + + /* BIOS Extension (0xec000-0xeffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000ec000, 0x000effff, 0x00000000, + 0x00004000, , , ESG3) + + /* System BIOS (0xf0000-0xfffff) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x000f0000, 0x000fffff, 0x00000000, + 0x00010000, , , FSEG) + + /* PCI Memory Region (Top of memory-CONFIG_MMCONF_BASE_ADDRESS) */ + DWordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, , , PMEM) + + /* High PCI Memory Region */ + QwordMemory(ResourceProducer, PosDecode, MinFixed, MaxFixed, + Cacheable, ReadWrite, + 0x00000000, 0x00000000, 0x00000000, 0x00000000, + 0x00000000, , , UMEM) + }) + + Method(_CRS, 0, Serialized) + { + /* Update PCI resource area */ + CreateDwordField(MCRS, ^PMEM._MIN, PMIN) + CreateDwordField(MCRS, ^PMEM._MAX, PMAX) + CreateDwordField(MCRS, ^PMEM._LEN, PLEN) + + /* + * Hardcode TOLM to 2GB for now as BayTrail FSP uses this value. + * + * TODO: for generic usage, read TOLM value from register, or + * from global NVS (not implemented by U-Boot yet). + */ + Store(0x80000000, PMIN) + Store(Subtract(MCFG_BASE_ADDRESS, 1), PMAX) + Add(Subtract(PMAX, PMIN), 1, PLEN) + + /* Update High PCI resource area */ + CreateQwordField(MCRS, ^UMEM._MIN, UMIN) + CreateQwordField(MCRS, ^UMEM._MAX, UMAX) + CreateQwordField(MCRS, ^UMEM._LEN, ULEN) + + /* Set base address to 48GB and allocate 16GB for PCI space */ + Store(0xc00000000, UMIN) + Store(0x400000000, ULEN) + Add(UMIN, Subtract(ULEN, 1), UMAX) + + Return (MCRS) + } + + /* Device Resource Consumption */ + Device (PDRC) + { + Name(_HID, EISAID("PNP0C02")) + Name(_UID, 1) + + Name(PDRS, ResourceTemplate() { + Memory32Fixed(ReadWrite, MCFG_BASE_ADDRESS, MCFG_BASE_SIZE) + Memory32Fixed(ReadWrite, ABORT_BASE_ADDRESS, ABORT_BASE_SIZE) + Memory32Fixed(ReadWrite, SPI_BASE_ADDRESS, SPI_BASE_SIZE) + Memory32Fixed(ReadWrite, PMC_BASE_ADDRESS, PMC_BASE_SIZE) + Memory32Fixed(ReadWrite, PUNIT_BASE_ADDRESS, PUNIT_BASE_SIZE) + Memory32Fixed(ReadWrite, ILB_BASE_ADDRESS, ILB_BASE_SIZE) + Memory32Fixed(ReadWrite, RCBA_BASE_ADDRESS, RCBA_BASE_SIZE) + Memory32Fixed(ReadWrite, MPHY_BASE_ADDRESS, MPHY_BASE_SIZE) + }) + + /* Current Resource Settings */ + Method(_CRS, 0, Serialized) + { + Return (PDRS) + } + } + + Method(_OSC, 4) + { + /* Check for proper GUID */ + If (LEqual(Arg0, ToUUID("33DB4D5B-1FF7-401C-9657-7441C03DD766"))) { + /* Let OS control everything */ + Return (Arg3) + } Else { + /* Unrecognized UUID */ + CreateDWordField(Arg3, 0, CDW1) + Or(CDW1, 4, CDW1) + Return (Arg3) + } + } + + /* LPC Bridge 0:1f.0 */ + #include "lpc.asl" + + /* USB EHCI 0:1d.0 */ + #include "usb.asl" + + /* USB XHCI 0:14.0 */ + #include "xhci.asl" + + /* IRQ routing for each PCI device */ + #include "irqroute.asl" +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/usb.asl b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl new file mode 100644 index 0000000..311f471 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/usb.asl @@ -0,0 +1,34 @@ +/* + * Copyright (C) 2007-2009 coresystems GmbH + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/usb.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* EHCI Controller 0:1d.0 */ + +Device (EHC1) +{ + Name(_ADR, 0x001d0000) + + /* Power Resources for Wake */ + Name(_PRW, Package() { 13, 4 }) + + /* Highest D state in S3 state */ + Name(_S3D, 2) + + /* Highest D state in S4 state */ + Name(_S4D, 2) + + Device (HUB7) + { + Name(_ADR, 0x00000000) + + Device(PRT1) { Name(_ADR, 1) } /* USB Port 0 */ + Device(PRT2) { Name(_ADR, 2) } /* USB Port 1 */ + Device(PRT3) { Name(_ADR, 3) } /* USB Port 2 */ + Device(PRT4) { Name(_ADR, 4) } /* USB Port 3 */ + } +} diff --git a/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl new file mode 100644 index 0000000..a5a4404 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/acpi/xhci.asl @@ -0,0 +1,31 @@ +/* + * Copyright (C) 2014 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/acpi/xhci.asl + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* XHCI Controller 0:14.0 */ + +Device (XHCI) +{ + Name(_ADR, 0x00140000) + + /* Power Resources for Wake */ + Name(_PRW, Package() { 13, 3 }) + + /* Highest D state in S3 state */ + Name(_S3D, 3) + + Device (RHUB) + { + Name(_ADR, 0x00000000) + + Device (PRT1) { Name(_ADR, 1) } /* USB Port 0 */ + Device (PRT2) { Name(_ADR, 2) } /* USB Port 1 */ + Device (PRT3) { Name(_ADR, 3) } /* USB Port 2 */ + Device (PRT4) { Name(_ADR, 4) } /* USB Port 3 */ + } +} diff --git a/arch/x86/include/asm/arch-baytrail/device.h b/arch/x86/include/asm/arch-baytrail/device.h new file mode 100644 index 0000000..798d35b --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/device.h @@ -0,0 +1,74 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/pci_devs.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _DEVICE_H_ +#define _DEVICE_H_ + +/* + * Internal PCI device numbers within the SoC. + * + * Note it must start with 0x_ prefix, as the device number macro will be + * included in the ACPI ASL files (see irq_helper.h and irq_route.h). + */ + +/* SoC transaction router */ +#define SOC_DEV 0x00 + +/* Graphics and Display */ +#define GFX_DEV 0x02 + +/* MIPI */ +#define MIPI_DEV 0x03 + +/* EMMC Port */ +#define EMMC_DEV 0x10 + +/* SDIO Port */ +#define SDIO_DEV 0x11 + +/* SD Port */ +#define SD_DEV 0x12 + +/* SATA */ +#define SATA_DEV 0x13 + +/* xHCI */ +#define XHCI_DEV 0x14 + +/* LPE Audio */ +#define LPE_DEV 0x15 + +/* OTG */ +#define OTG_DEV 0x16 + +/* MMC45 Port */ +#define MMC45_DEV 0x17 + +/* Serial IO 1 */ +#define SIO1_DEV 0x18 + +/* Trusted Execution Engine */ +#define TXE_DEV 0x1a + +/* HD Audio */ +#define HDA_DEV 0x1b + +/* PCIe Ports */ +#define PCIE_DEV 0x1c + +/* EHCI */ +#define EHCI_DEV 0x1d + +/* Serial IO 2 */ +#define SIO2_DEV 0x1e + +/* Platform Controller Unit */ +#define PCU_DEV 0x1f + +#endif /* _DEVICE_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/iomap.h b/arch/x86/include/asm/arch-baytrail/iomap.h new file mode 100644 index 0000000..62a9105 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/iomap.h @@ -0,0 +1,70 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/iomap.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BAYTRAIL_IOMAP_H_ +#define _BAYTRAIL_IOMAP_H_ + +/* Memory Mapped IO bases */ + +/* PCI Configuration Space */ +#define MCFG_BASE_ADDRESS CONFIG_PCIE_ECAM_BASE +#define MCFG_BASE_SIZE 0x10000000 + +/* Temporary Base Address */ +#define TEMP_BASE_ADDRESS 0xfd000000 + +/* Transactions in this range will abort */ +#define ABORT_BASE_ADDRESS 0xfeb00000 +#define ABORT_BASE_SIZE 0x00100000 + +/* High Performance Event Timer */ +#define HPET_BASE_ADDRESS 0xfed00000 +#define HPET_BASE_SIZE 0x400 + +/* SPI Bus */ +#define SPI_BASE_ADDRESS 0xfed01000 +#define SPI_BASE_SIZE 0x400 + +/* Power Management Controller */ +#define PMC_BASE_ADDRESS 0xfed03000 +#define PMC_BASE_SIZE 0x400 + +/* Power Management Unit */ +#define PUNIT_BASE_ADDRESS 0xfed05000 +#define PUNIT_BASE_SIZE 0x800 + +/* Intel Legacy Block */ +#define ILB_BASE_ADDRESS 0xfed08000 +#define ILB_BASE_SIZE 0x400 + +/* IO Memory */ +#define IO_BASE_ADDRESS 0xfed0c000 +#define IO_BASE_OFFSET_GPSCORE 0x0000 +#define IO_BASE_OFFSET_GPNCORE 0x1000 +#define IO_BASE_OFFSET_GPSSUS 0x2000 +#define IO_BASE_SIZE 0x4000 + +/* Root Complex Base Address */ +#define RCBA_BASE_ADDRESS 0xfed1c000 +#define RCBA_BASE_SIZE 0x400 + +/* MODPHY */ +#define MPHY_BASE_ADDRESS 0xfef00000 +#define MPHY_BASE_SIZE 0x100000 + +/* IO Port bases */ +#define ACPI_BASE_ADDRESS 0x0400 +#define ACPI_BASE_SIZE 0x80 + +#define GPIO_BASE_ADDRESS 0x0500 +#define GPIO_BASE_SIZE 0x100 + +#define SMBUS_BASE_ADDRESS 0xefa0 + +#endif /* _BAYTRAIL_IOMAP_H_ */ diff --git a/arch/x86/include/asm/arch-baytrail/irq.h b/arch/x86/include/asm/arch-baytrail/irq.h new file mode 100644 index 0000000..cd66f83 --- /dev/null +++ b/arch/x86/include/asm/arch-baytrail/irq.h @@ -0,0 +1,86 @@ +/* + * Copyright (C) 2013 Google Inc. + * Copyright (C) 2016 Bin Meng bmeng.cn@gmail.com + * + * Modified from coreboot src/soc/intel/baytrail/include/soc/irq.h + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +#ifndef _BAYTRAIL_IRQ_H_ +#define _BAYTRAIL_IRQ_H_ + +#define PIRQA_APIC_IRQ 16 +#define PIRQB_APIC_IRQ 17 +#define PIRQC_APIC_IRQ 18 +#define PIRQD_APIC_IRQ 19 +#define PIRQE_APIC_IRQ 20 +#define PIRQF_APIC_IRQ 21 +#define PIRQG_APIC_IRQ 22 +#define PIRQH_APIC_IRQ 23 + +/* The below IRQs are for when devices are in ACPI mode */ +#define LPE_DMA0_IRQ 24 +#define LPE_DMA1_IRQ 25 +#define LPE_SSP0_IRQ 26 +#define LPE_SSP1_IRQ 27 +#define LPE_SSP2_IRQ 28 +#define LPE_IPC2HOST_IRQ 29 +#define LPSS_I2C1_IRQ 32 +#define LPSS_I2C2_IRQ 33 +#define LPSS_I2C3_IRQ 34 +#define LPSS_I2C4_IRQ 35 +#define LPSS_I2C5_IRQ 36 +#define LPSS_I2C6_IRQ 37 +#define LPSS_I2C7_IRQ 38 +#define LPSS_HSUART1_IRQ 39 +#define LPSS_HSUART2_IRQ 40 +#define LPSS_SPI_IRQ 41 +#define LPSS_DMA1_IRQ 42 +#define LPSS_DMA2_IRQ 43 +#define SCC_EMMC_IRQ 44 +#define SCC_SDIO_IRQ 46 +#define SCC_SD_IRQ 47 +#define GPIO_NC_IRQ 48 +#define GPIO_SC_IRQ 49 +#define GPIO_SUS_IRQ 50 +/* GPIO direct / dedicated IRQs */ +#define GPIO_S0_DED_IRQ_0 51 +#define GPIO_S0_DED_IRQ_1 52 +#define GPIO_S0_DED_IRQ_2 53 +#define GPIO_S0_DED_IRQ_3 54 +#define GPIO_S0_DED_IRQ_4 55 +#define GPIO_S0_DED_IRQ_5 56 +#define GPIO_S0_DED_IRQ_6 57 +#define GPIO_S0_DED_IRQ_7 58 +#define GPIO_S0_DED_IRQ_8 59 +#define GPIO_S0_DED_IRQ_9 60 +#define GPIO_S0_DED_IRQ_10 61 +#define GPIO_S0_DED_IRQ_11 62 +#define GPIO_S0_DED_IRQ_12 63 +#define GPIO_S0_DED_IRQ_13 64 +#define GPIO_S0_DED_IRQ_14 65 +#define GPIO_S0_DED_IRQ_15 66 +#define GPIO_S5_DED_IRQ_0 67 +#define GPIO_S5_DED_IRQ_1 68 +#define GPIO_S5_DED_IRQ_2 69 +#define GPIO_S5_DED_IRQ_3 70 +#define GPIO_S5_DED_IRQ_4 71 +#define GPIO_S5_DED_IRQ_5 72 +#define GPIO_S5_DED_IRQ_6 73 +#define GPIO_S5_DED_IRQ_7 74 +#define GPIO_S5_DED_IRQ_8 75 +#define GPIO_S5_DED_IRQ_9 76 +#define GPIO_S5_DED_IRQ_10 77 +#define GPIO_S5_DED_IRQ_11 78 +#define GPIO_S5_DED_IRQ_12 79 +#define GPIO_S5_DED_IRQ_13 80 +#define GPIO_S5_DED_IRQ_14 81 +#define GPIO_S5_DED_IRQ_15 82 +/* DIRQs - Two levels of expansion to evaluate to numeric constants for ASL */ +#define _GPIO_S0_DED_IRQ(slot) GPIO_S0_DED_IRQ_##slot +#define _GPIO_S5_DED_IRQ(slot) GPIO_S5_DED_IRQ_##slot +#define GPIO_S0_DED_IRQ(slot) _GPIO_S0_DED_IRQ(slot) +#define GPIO_S5_DED_IRQ(slot) _GPIO_S5_DED_IRQ(slot) + +#endif /* _BAYTRAIL_IRQ_H_ */

Enable ACPI table generation by creating a DSDT table for all baytrail boards: conga-qeval20-qa3-e3845, bayleybay and minnowmax.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

board/congatec/conga-qeval20-qa3-e3845/Makefile | 1 + board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl | 13 +++++++++++++ board/congatec/conga-qeval20-qa3-e3845/dsdt.asl | 14 ++++++++++++++ board/intel/bayleybay/Makefile | 1 + board/intel/bayleybay/acpi/mainboard.asl | 11 +++++++++++ board/intel/bayleybay/dsdt.asl | 14 ++++++++++++++ board/intel/minnowmax/Makefile | 1 + board/intel/minnowmax/acpi/mainboard.asl | 11 +++++++++++ board/intel/minnowmax/dsdt.asl | 14 ++++++++++++++ configs/bayleybay_defconfig | 1 + configs/conga-qeval20-qa3-e3845_defconfig | 1 + configs/minnowmax_defconfig | 1 + 12 files changed, 83 insertions(+) create mode 100644 board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl create mode 100644 board/congatec/conga-qeval20-qa3-e3845/dsdt.asl create mode 100644 board/intel/bayleybay/acpi/mainboard.asl create mode 100644 board/intel/bayleybay/dsdt.asl create mode 100644 board/intel/minnowmax/acpi/mainboard.asl create mode 100644 board/intel/minnowmax/dsdt.asl

diff --git a/board/congatec/conga-qeval20-qa3-e3845/Makefile b/board/congatec/conga-qeval20-qa3-e3845/Makefile index 23b8748..b784510 100644 --- a/board/congatec/conga-qeval20-qa3-e3845/Makefile +++ b/board/congatec/conga-qeval20-qa3-e3845/Makefile @@ -5,3 +5,4 @@ #

obj-y += conga-qeval20-qa3.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl new file mode 100644 index 0000000..eace459 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/acpi/mainboard.asl @@ -0,0 +1,13 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} + +/* TODO: Need add Winbond SuperIO chipset W83627 ASL codes */ diff --git a/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/congatec/conga-qeval20-qa3-e3845/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intel/bayleybay/Makefile b/board/intel/bayleybay/Makefile index 88b5aad..52dda7d 100644 --- a/board/intel/bayleybay/Makefile +++ b/board/intel/bayleybay/Makefile @@ -5,3 +5,4 @@ #

obj-y += bayleybay.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/bayleybay/acpi/mainboard.asl b/board/intel/bayleybay/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/bayleybay/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/bayleybay/dsdt.asl b/board/intel/bayleybay/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/bayleybay/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/board/intel/minnowmax/Makefile b/board/intel/minnowmax/Makefile index 1a61432..73e5a8f 100644 --- a/board/intel/minnowmax/Makefile +++ b/board/intel/minnowmax/Makefile @@ -5,3 +5,4 @@ #

obj-y += minnowmax.o start.o +obj-$(CONFIG_GENERATE_ACPI_TABLE) += dsdt.o diff --git a/board/intel/minnowmax/acpi/mainboard.asl b/board/intel/minnowmax/acpi/mainboard.asl new file mode 100644 index 0000000..21785ea --- /dev/null +++ b/board/intel/minnowmax/acpi/mainboard.asl @@ -0,0 +1,11 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +/* Power Button */ +Device (PWRB) +{ + Name(_HID, EISAID("PNP0C0C")) +} diff --git a/board/intel/minnowmax/dsdt.asl b/board/intel/minnowmax/dsdt.asl new file mode 100644 index 0000000..6042011 --- /dev/null +++ b/board/intel/minnowmax/dsdt.asl @@ -0,0 +1,14 @@ +/* + * Copyright (C) 2016, Bin Meng bmeng.cn@gmail.com + * + * SPDX-License-Identifier: GPL-2.0+ + */ + +DefinitionBlock("dsdt.aml", "DSDT", 2, "U-BOOT", "U-BOOTBL", 0x00010000) +{ + /* platform specific */ + #include <asm/arch/acpi/platform.asl> + + /* board specific */ + #include "acpi/mainboard.asl" +} diff --git a/configs/bayleybay_defconfig b/configs/bayleybay_defconfig index dfafb0b..465394e 100644 --- a/configs/bayleybay_defconfig +++ b/configs/bayleybay_defconfig @@ -9,6 +9,7 @@ CONFIG_HAVE_VGA_BIOS=y CONFIG_VGA_BIOS_ADDR=0xfffa0000 CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y CONFIG_BOOTSTAGE=y CONFIG_BOOTSTAGE_REPORT=y diff --git a/configs/conga-qeval20-qa3-e3845_defconfig b/configs/conga-qeval20-qa3-e3845_defconfig index 24a927d..044045d 100644 --- a/configs/conga-qeval20-qa3-e3845_defconfig +++ b/configs/conga-qeval20-qa3-e3845_defconfig @@ -8,6 +8,7 @@ CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y diff --git a/configs/minnowmax_defconfig b/configs/minnowmax_defconfig index efb9c1e..cebd660 100644 --- a/configs/minnowmax_defconfig +++ b/configs/minnowmax_defconfig @@ -8,6 +8,7 @@ CONFIG_SMP=y CONFIG_HAVE_VGA_BIOS=y CONFIG_GENERATE_PIRQ_TABLE=y CONFIG_GENERATE_MP_TABLE=y +CONFIG_GENERATE_ACPI_TABLE=y CONFIG_FIT=y CONFIG_FIT_SIGNATURE=y CONFIG_BOOTSTAGE=y

Remove the kernel boot parameter acpi=off so that kernel can turn on ACPI support.

Signed-off-by: Bin Meng bmeng.cn@gmail.com ---

include/configs/x86-common.h | 9 +++++++-- 1 file changed, 7 insertions(+), 2 deletions(-)

diff --git a/include/configs/x86-common.h b/include/configs/x86-common.h index ea815c2..1e0f451 100644 --- a/include/configs/x86-common.h +++ b/include/configs/x86-common.h @@ -207,14 +207,19 @@ #define CONFIG_HOSTNAME x86 #define CONFIG_BOOTFILE "bzImage" #define CONFIG_LOADADDR 0x1000000 -#define CONFIG_RAMDISK_ADDR 0x4000000 +#define CONFIG_RAMDISK_ADDR 0x4000000 +#ifdef CONFIG_GENERATE_ACPI_TABLE +#define CONFIG_OTHBOOTARGS "othbootargs=\0" +#else +#define CONFIG_OTHBOOTARGS "othbootargs=acpi=off\0" +#endif

#define CONFIG_EXTRA_ENV_SETTINGS \ CONFIG_STD_DEVICES_SETTINGS \ "pciconfighost=1\0" \ "netdev=eth0\0" \ "consoledev=ttyS0\0" \ - "othbootargs=acpi=off\0" \ + CONFIG_OTHBOOTARGS \ "ramdiskaddr=0x4000000\0" \ "ramdiskfile=initramfs.gz\0"

Remove ACPI from the TODO list and add a new section to document current ACPI support in U-Boot.

Signed-off-by: Bin Meng bmeng.cn@gmail.com

---

doc/README.x86 | 36 +++++++++++++++++++++++++++++++++++- 1 file changed, 35 insertions(+), 1 deletion(-)

diff --git a/doc/README.x86 b/doc/README.x86 index a5dfb86..d74e6e4 100644 --- a/doc/README.x86 +++ b/doc/README.x86 @@ -957,12 +957,44 @@ transformations. Remember to add attribution to coreboot for new files added to U-Boot. This should go at the top of each file and list the coreboot filename where the code originated.

+ACPI Support Status +------------------- +Advanced Configuration and Power Interface (ACPI) [16] aims to establish +industry-standard interfaces enabling OS-directed configuration, power +management, and thermal management of mobile, desktop, and server platforms. + +Linux can boot without ACPI with "acpi=off" command line parameter, but +with ACPI the kernel gains the capabilities to handle power management. +For Windows, ACPI is a must-have firmware feature since Windows Vista. +CONFIG_GENERATE_ACPI_TABLE is the config option to turn on ACPI support in +U-Boot. This requires Intel ACPI compiler to be installed on your host to +compile ACPI DSDT table written in ASL format to AML format. You can get +the compiler via "apt-get install iasl" if you are on Ubuntu or download +the source from [17] to compile one by yourself. + +Current ACPI support in U-Boot is not complete. More features will be added +in the future. The status as of today is: + + * Support generating RSDT, XSDT, FACS, FADT, MADT, MCFG tables. + * Support one static DSDT table only, compiled by Intel ACPI compiler. + * Support S0/S5 only, no S3/S4 boot path support yet. + * No ACPI global NVS support (this can be optional, but we may need it in + the future to simplify ASL code logic when utilizing NVS variables). + * No dynamic AML bytecodes insertion at run-time (this is optional as we + can always describe the board in the static way). + * All ACPI interrupts are routed to SCI for OS to handle. No legacy SMI + implementation within U-Boot. + * Install Ubuntu from U-Boot plus SeaBIOS does not work. + * Install Windows 8.1/10 from U-Boot plus SeaBIOS does not work. + +So far ACPI is enabled on BayTrail based boards. Testing was done by booting +a pre-installed Ubuntu 14.04 from a SATA drive. Most devices seem to work +correctly and the board can respond a reboot/shutdown command from Ubuntu.

TODO List --------- - Audio - Chrome OS verified boot -- SMI and ACPI support, to provide platform info and facilities to Linux

References ---------- @@ -981,3 +1013,5 @@ References [13] http://events.linuxfoundation.org/sites/events/files/slides/elce-2014.pdf [14] http://www.seabios.org/SeaBIOS [15] doc/device-tree-bindings/misc/intel,irq-router.txt +[16] http://www.acpi.info +[17] https://www.acpica.org/downloads