Though nios2-generic board meant to be a template, it is helpful to be able to test on a real hardware. As the nios2 linux is developed and tested on a 3c120 FPGA based Golden Hardware Reference Design, it makes sense to rebase nios2-generic on this FPGA design.

Signed-off-by: Thomas Chou thomas@wytron.com.tw --- board/altera/nios2-generic/custom_fpga.h | 127 ++++++++++++++++-------------- include/configs/nios2-generic.h | 11 ++- 2 files changed, 78 insertions(+), 60 deletions(-)

diff --git a/board/altera/nios2-generic/custom_fpga.h b/board/altera/nios2-generic/custom_fpga.h index fd3ec9a..cf75d35 100644 --- a/board/altera/nios2-generic/custom_fpga.h +++ b/board/altera/nios2-generic/custom_fpga.h @@ -1,78 +1,89 @@ /* - * (C) Copyright 2010, Thomas Chou thomas@wytron.com.tw + * This header is generated by sopc2dts + * Sopc2dts is written by Walter Goossens waltergoossens@home.nl + * in cooperation with the nios2 community Nios2-dev@sopc.et.ntust.edu.tw * - * This program is free software; you can redistribute it and/or modify - * it under the terms of the GNU General Public License version 2 as - * published by the Free Software Foundation. - * - * This file is generated by sopc-create-config-files. + * SPDX-License-Identifier: GPL-2.0+ */ #ifndef _CUSTOM_FPGA_H_ #define _CUSTOM_FPGA_H_

-/* generated from std_1c20.sopc */ - -/* cpu.data_master is a altera_nios2 */ -#define CONFIG_SYS_CLK_FREQ 50000000 -#define CONFIG_SYS_RESET_ADDR 0x00000000 -#define CONFIG_SYS_EXCEPTION_ADDR 0x01000020 -#define CONFIG_SYS_ICACHE_SIZE 4096 -#define CONFIG_SYS_ICACHELINE_SIZE 32 -#define CONFIG_SYS_DCACHE_SIZE 2048 -#define CONFIG_SYS_DCACHELINE_SIZE 4 - -/* sdram.s1 is a altera_avalon_new_sdram_controller */ -#define CONFIG_SYS_SDRAM_BASE 0x01000000 -#define CONFIG_SYS_SDRAM_SIZE 0x01000000 - -/* uart1.s1 is a altera_avalon_uart */ -#define CONFIG_SYS_UART_BASE 0x82120840 -#define CONFIG_SYS_UART_FREQ 50000000 -#define CONFIG_SYS_UART_BAUD 115200 - -/* lan91c111.s1 is a altera_avalon_lan91c111 */ -#define CONFIG_SMC91111_BASE 0x82110300 -#define CONFIG_SMC91111 -#define CONFIG_SMC_USE_32_BIT - -/* epcs_controller.epcs_control_port is a altera_avalon_epcs_flash_controller */ -#define EPCS_CONTROLLER_REG_BASE 0x82100200 -#define CONFIG_SYS_ALTERA_SPI_LIST { EPCS_CONTROLLER_REG_BASE } -#define CONFIG_ALTERA_SPI -#define CONFIG_CMD_SPI -#define CONFIG_CMD_SF -#define CONFIG_SF_DEFAULT_SPEED 30000000 -#define CONFIG_SPI_FLASH -#define CONFIG_SPI_FLASH_STMICRO +/* generated from qsys_ghrd_3c120.sopcinfo */ + +/* Dumping slaves of cpu.data_master */ + +/* cpu.jtag_debug_module is a altera_nios2_qsys */ +#define CONFIG_SYS_CLK_FREQ 125000000 +#define CONFIG_SYS_DCACHE_SIZE 32768 +#define CONFIG_SYS_DCACHELINE_SIZE 32 +#define CONFIG_SYS_ICACHELINE_SIZE 32 +#define CONFIG_SYS_EXCEPTION_ADDR 0xd0000020 +#define CONFIG_SYS_ICACHE_SIZE 32768 +#define CONFIG_SYS_RESET_ADDR 0xc2800000 +#define IO_REGION_BASE 0xE0000000 + +/* pb_cpu_to_ddr2_bot.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_ddr2_bot.m0 */ + +/* ddr2_bot.s1 is a altmemddr2 */ +#define CONFIG_SYS_SDRAM_BASE 0xD0000000 +#define CONFIG_SYS_SDRAM_SIZE 0x08000000 + +/* pb_cpu_to_io.s0 is a altera_avalon_mm_bridge */ +/* Dumping slaves of pb_cpu_to_io.m0 */ + +/* timer_1ms.s1 is a altera_avalon_timer */ +#define CONFIG_SYS_TIMER_IRQ 11 +#define CONFIG_SYS_TIMER_FREQ 125000000 +#define CONFIG_SYS_TIMER_BASE 0xE8400000 + +/* sysid.control_slave is a altera_avalon_sysid_qsys */ +#define CONFIG_SYS_SYSID_BASE 0xE8004D40

/* jtag_uart.avalon_jtag_slave is a altera_avalon_jtag_uart */ -#define CONFIG_SYS_JTAG_UART_BASE 0x821208b0 +#define CONFIG_SYS_JTAG_UART_BASE 0xE8004D50 + +/* tse_mac.control_port is a triple_speed_ethernet */ +#define CONFIG_SYS_ALTERA_TSE_RX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_TX_BASE 0xE8004800 +#define CONFIG_SYS_ALTERA_TSE_SGDMA_RX_BASE 0xE8004400 +#define CONFIG_SYS_ALTERA_TSE_TX_FIFO 2048 +#define CONFIG_SYS_ALTERA_TSE_DESC_SIZE 0x00002000 +#define CONFIG_SYS_ALTERA_TSE_MAC_BASE 0xE8004000 +#define CONFIG_SYS_ALTERA_TSE_DESC_BASE 0xE8002000 +#define CONFIG_ALTERA_TSE +#define CONFIG_MII +#define CONFIG_CMD_MII +#define CONFIG_SYS_ALTERA_TSE_PHY_ADDR 18 +#define CONFIG_SYS_ALTERA_TSE_FLAGS 1 + +/* uart.s1 is a altera_avalon_uart */ +#define CONFIG_SYS_UART_BAUD 115200 +#define CONFIG_SYS_UART_BASE 0xE8004C80 +#define CONFIG_SYS_UART_FREQ 62500000 + +/* user_led_pio_8out.s1 is a altera_avalon_pio */ +#define USER_LED_PIO_8OUT_BASE 0xE8004CC0

-/* led_pio.s1 is a altera_avalon_pio */ -#define LED_PIO_BASE 0x82120870 -#define LED_PIO_WIDTH 8 -#define LED_PIO_RSTVAL 0x0 +/* user_dipsw_pio_8in.s1 is a altera_avalon_pio */ +#define USER_DIPSW_PIO_8IN_BASE 0xE8004CE0 +#define USER_DIPSW_PIO_8IN_IRQ 8

-/* high_res_timer.s1 is a altera_avalon_timer */ -#define CONFIG_SYS_TIMER_BASE 0x82120820 -#define CONFIG_SYS_TIMER_IRQ 3 -#define CONFIG_SYS_TIMER_FREQ 50000000 +/* user_pb_pio_4in.s1 is a altera_avalon_pio */ +#define USER_PB_PIO_4IN_BASE 0xE8004D00 +#define USER_PB_PIO_4IN_IRQ 9 + +/* cfi_flash_64m.uas is a altera_generic_tristate_controller */ +#define CFI_FLASH_64M_BASE 0xE0000000

/* ext_flash.s1 is a altera_avalon_cfi_flash */ -#define CONFIG_SYS_FLASH_BASE 0x80000000 +#define CONFIG_SYS_FLASH_BASE CFI_FLASH_64M_BASE #define CONFIG_FLASH_CFI_DRIVER #define CONFIG_SYS_CFI_FLASH_STATUS_POLL /* fix amd flash issue */ #define CONFIG_SYS_FLASH_CFI #define CONFIG_SYS_FLASH_USE_BUFFER_WRITE #define CONFIG_SYS_FLASH_PROTECTION #define CONFIG_SYS_MAX_FLASH_BANKS 1 -#define CONFIG_SYS_MAX_FLASH_SECT 1024 - -/* ext_ram.s1 is a altera_nios_dev_kit_stratix_edition_sram2 */ -#define CONFIG_SYS_SRAM_BASE 0x02000000 -#define CONFIG_SYS_SRAM_SIZE 0x00100000 - -/* sysid.control_slave is a altera_avalon_sysid */ -#define CONFIG_SYS_SYSID_BASE 0x821208b8 +#define CONFIG_SYS_MAX_FLASH_SECT 512

#endif /* _CUSTOM_FPGA_H_ */ diff --git a/include/configs/nios2-generic.h b/include/configs/nios2-generic.h index 51b1d00..6247bf1 100644 --- a/include/configs/nios2-generic.h +++ b/include/configs/nios2-generic.h @@ -22,7 +22,7 @@ /* * SERIAL */ -#define CONFIG_ALTERA_UART +#define CONFIG_ALTERA_JTAG_UART #if defined(CONFIG_ALTERA_JTAG_UART) # define CONFIG_SYS_NIOS_CONSOLE CONFIG_SYS_JTAG_UART_BASE #else @@ -56,6 +56,9 @@ #define CONFIG_BOARD_SPECIFIC_LED #define CONFIG_GPIO_LED /* Enable GPIO LED driver */ #define CONFIG_GPIO /* Enable GPIO driver */ +#define LED_PIO_BASE USER_LED_PIO_8OUT_BASE +#define LED_PIO_WIDTH 8 +#define LED_PIO_RSTVAL 0xff

#define STATUS_LED_BIT 0 /* Bit-0 on GPIO */ #define STATUS_LED_STATE 1 /* Blinking */ @@ -86,6 +89,10 @@ # define CONFIG_CMD_PING #endif

+#define CONFIG_OF_LIBFDT +#define CONFIG_OF_BOARD_SETUP +#define CONFIG_LMB + /* * ENVIRONMENT -- Put environment in sector CONFIG_SYS_MONITOR_LEN above * CONFIG_SYS_RESET_ADDR, since we assume the monitor is stored at the @@ -95,7 +102,7 @@ */ #define CONFIG_ENV_IS_IN_FLASH

-#define CONFIG_ENV_SIZE 0x10000 /* 64k, 1 sector */ +#define CONFIG_ENV_SIZE 0x20000 /* 128k, 1 sector */ #define CONFIG_ENV_OVERWRITE /* Serial change Ok */ #define CONFIG_ENV_ADDR ((CONFIG_SYS_RESET_ADDR + \ CONFIG_SYS_MONITOR_LEN) | \