[U-Boot] [PATCH 1/2] ARM: mx25: Print the silicon revison
Print the silicon revison during boot.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/arm926ejs/mx25/generic.c | 32 ++++++++++++++++++++++++++++- arch/arm/include/asm/arch-mx25/imx-regs.h | 4 +++ 2 files changed, 35 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index 76e4b5c..a4e8c14 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -105,12 +105,42 @@ ulong imx_get_perclk (int clk) return lldiv (fref, div); }
+ +u32 get_cpu_rev(void) +{ + u32 srev; + u32 system_rev = 0x25000; + + /* read SREV register from IIM module */ + struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE; + srev = readl(&iim->iim_srev); + + switch (srev) { + case 0x00: + system_rev |= CHIP_REV_1_0; + break; + case 0x01: + system_rev |= CHIP_REV_1_1; + break; + default: + system_rev |= CHIP_REV_UNKNOWN; + break; + } + + return system_rev; +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { char buf[32]; + u32 cpurev; + + cpurev = get_cpu_rev();
- printf ("CPU: Freescale i.MX25 at %s MHz\n\n", + printf("CPU: Freescale i.MX25 rev%d.%d at %s MHz\n\n", + (cpurev & 0x000F0) >> 4, + (cpurev & 0x0000F) >> 0, strmhz (buf, imx_get_armclk ())); return 0; } diff --git a/arch/arm/include/asm/arch-mx25/imx-regs.h b/arch/arm/include/asm/arch-mx25/imx-regs.h index 9e30f7c..92b58be 100644 --- a/arch/arm/include/asm/arch-mx25/imx-regs.h +++ b/arch/arm/include/asm/arch-mx25/imx-regs.h @@ -351,4 +351,8 @@ struct aips_regs { #define GPIO3_BASE_ADDR IMX_GPIO3_BASE #define GPIO4_BASE_ADDR IMX_GPIO4_BASE
+#define CHIP_REV_1_0 0x10 +#define CHIP_REV_1_1 0x11 +#define CHIP_REV_UNKNOWN 0xFF + #endif /* _IMX_REGS_H */
Print the source of reset during boot.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com --- arch/arm/cpu/arm926ejs/mx25/generic.c | 25 ++++++++++++++++++++++++- 1 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index a4e8c14..047e49d 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -130,6 +130,28 @@ u32 get_cpu_rev(void) return system_rev; }
+static char *get_reset_cause(void) +{ + /* read RCSR register from CCM module */ + struct ccm_regs *ccm = + (struct ccm_regs *)IMX_CCM_BASE; + + u32 cause = readl(&ccm->rcsr) & 0x0f; + + switch (cause) { + case 0x0000: + return "POR"; + case 0x0001: + return "RST"; + case 0x0002: + return "WDOG"; + case 0x0006: + return "JTAG"; + default: + return "unknown reset"; + } +} + #if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { @@ -138,10 +160,11 @@ int print_cpuinfo (void)
cpurev = get_cpu_rev();
- printf("CPU: Freescale i.MX25 rev%d.%d at %s MHz\n\n", + printf("CPU: Freescale i.MX25 rev%d.%d at %s MHz\n", (cpurev & 0x000F0) >> 4, (cpurev & 0x0000F) >> 0, strmhz (buf, imx_get_armclk ())); + printf("Reset cause: %s\n\n", get_reset_cause()); return 0; } #endif
On 08/30/2011 03:54 PM, Fabio Estevam wrote:
Print the source of reset during boot.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
arch/arm/cpu/arm926ejs/mx25/generic.c | 25 ++++++++++++++++++++++++- 1 files changed, 24 insertions(+), 1 deletions(-)
diff --git a/arch/arm/cpu/arm926ejs/mx25/generic.c b/arch/arm/cpu/arm926ejs/mx25/generic.c index a4e8c14..047e49d 100644 --- a/arch/arm/cpu/arm926ejs/mx25/generic.c +++ b/arch/arm/cpu/arm926ejs/mx25/generic.c @@ -130,6 +130,28 @@ u32 get_cpu_rev(void) return system_rev; }
+static char *get_reset_cause(void) +{
- /* read RCSR register from CCM module */
- struct ccm_regs *ccm =
(struct ccm_regs *)IMX_CCM_BASE;- u32 cause = readl(&ccm->rcsr) & 0x0f;
- switch (cause) {
- case 0x0000:
return "POR";- case 0x0001:
return "RST";- case 0x0002:
return "WDOG";- case 0x0006:
return "JTAG";- default:
return "unknown reset";- }
+}
Can you help me interpreting the manual ? I see in MX25 RM:
REST Reset status bits. Shows what caused the most recent reset to the system.Otherwise, the last signal that is released is honored. 0000 POR reset 0001 Reset In reset. xx10 WDOG reset x1x0 SOFT RESET 1xx0 JTAG SW RESET
The code for JTAG seems wrong, should be at 0x08. It sounds me odd that some bits are not fixed. According to the manual, we should check the single bits, becase for example a WDOG reset can be identified not only by 0x02, but also by 0x06, 0x0a, 0x0E..
Best regards, Stefano Babic
On 08/30/2011 03:54 PM, Fabio Estevam wrote:
Print the silicon revison during boot.
Signed-off-by: Fabio Estevam fabio.estevam@freescale.com
Hi Fabio,
+u32 get_cpu_rev(void) +{
- u32 srev;
- u32 system_rev = 0x25000;
- /* read SREV register from IIM module */
- struct iim_regs *iim = (struct iim_regs *)IMX_IIM_BASE;
- srev = readl(&iim->iim_srev);
- switch (srev) {
- case 0x00:
system_rev |= CHIP_REV_1_0;break;- case 0x01:
system_rev |= CHIP_REV_1_1;break;- default:
system_rev |= CHIP_REV_UNKNOWN;break;- }
- return system_rev;
+}
#if defined(CONFIG_DISPLAY_CPUINFO) int print_cpuinfo (void) { char buf[32];
- u32 cpurev;
- cpurev = get_cpu_rev();
- printf ("CPU: Freescale i.MX25 at %s MHz\n\n",
- printf("CPU: Freescale i.MX25 rev%d.%d at %s MHz\n\n",
(cpurev & 0x000F0) >> 4,(cpurev & 0x0000F) >> 0,
I see that we did different for other i.MX processor - if you check in the MX31 processor, we print the "unknown" string if the revision number does not match a known value instead of printing an arbitrary value as here. Can we stick with the same behavior ?
Best regards, Stefano Babic
participants (2)
-
Fabio Estevam -
Stefano Babic